/*
 * Scilab ( http://www.scilab.org/ ) - This file is part of Scilab
 * Copyright (C) 2008-2008 - INRIA - Bruno JOFRET
 * 
 * This file must be used under the terms of the CeCILL.
 * This source file is licensed as described in the file COPYING, which
 * you should have received as part of this distribution.  The terms
 * are also available at    
 * http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
 *
 */

/* THIS IS AN AUTOMATICALLY GENERATED FILE : DO NOT EDIT BY HAND. */

#ifndef __INT_INT16_H__
#define __INT_INT16_H__

#define s0int16u80(in)			sint16s(in)

#define d0int16u80(in)			dint16s(in)

#define s2int16u82(in,size,out)		sint16a(in, size[0]*size[1], out)

#define d2int16u82(in,size,out)		dint16a(in, size[0]*size[1], out)

#endif /* !__INT_INT8_H__ */