From b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b Mon Sep 17 00:00:00 2001 From: priyanka Date: Wed, 24 Jun 2015 15:03:17 +0530 Subject: initial commit / add all books --- 61/CH2/EX2.1/ex2_1.sce | 5 +++++ 61/CH2/EX2.10/ex2_10.jpg | Bin 0 -> 30967 bytes 61/CH2/EX2.10/ex2_10.sce | 26 ++++++++++++++++++++++++++ 61/CH2/EX2.11/ex2_11.jpg | Bin 0 -> 47929 bytes 61/CH2/EX2.11/ex2_11.sce | 29 +++++++++++++++++++++++++++++ 61/CH2/EX2.12/ex2_12.jpg | Bin 0 -> 36999 bytes 61/CH2/EX2.12/ex2_12.sce | 28 ++++++++++++++++++++++++++++ 61/CH2/EX2.13/ex2_13.jpg | Bin 0 -> 40971 bytes 61/CH2/EX2.13/ex2_13.sce | 15 +++++++++++++++ 61/CH2/EX2.2.a/ex2_2a.jpg | Bin 0 -> 23992 bytes 61/CH2/EX2.2.a/ex2_2a.sce | 25 +++++++++++++++++++++++++ 61/CH2/EX2.2.b/ex2_2b.JPG | Bin 0 -> 22398 bytes 61/CH2/EX2.2.b/ex2_2b.sce | 25 +++++++++++++++++++++++++ 61/CH2/EX2.3/ex2_3.sce | 7 +++++++ 61/CH2/EX2.4/ex2_4.sce | 5 +++++ 61/CH2/EX2.5/ex2_5.jpg | Bin 0 -> 55943 bytes 61/CH2/EX2.5/ex2_5.sce | 28 ++++++++++++++++++++++++++++ 61/CH2/EX2.6/ex2_6.sce | 10 ++++++++++ 61/CH2/EX2.7/ex2_7.sce | 14 ++++++++++++++ 61/CH2/EX2.8/ex2_8.sce | 13 +++++++++++++ 61/CH2/EX2.9/ex2_9.sce | 6 ++++++ 21 files changed, 236 insertions(+) create mode 100755 61/CH2/EX2.1/ex2_1.sce create mode 100755 61/CH2/EX2.10/ex2_10.jpg create mode 100755 61/CH2/EX2.10/ex2_10.sce create mode 100755 61/CH2/EX2.11/ex2_11.jpg create mode 100755 61/CH2/EX2.11/ex2_11.sce create mode 100755 61/CH2/EX2.12/ex2_12.jpg create mode 100755 61/CH2/EX2.12/ex2_12.sce create mode 100755 61/CH2/EX2.13/ex2_13.jpg create mode 100755 61/CH2/EX2.13/ex2_13.sce create mode 100755 61/CH2/EX2.2.a/ex2_2a.jpg create mode 100755 61/CH2/EX2.2.a/ex2_2a.sce create mode 100755 61/CH2/EX2.2.b/ex2_2b.JPG create mode 100755 61/CH2/EX2.2.b/ex2_2b.sce create mode 100755 61/CH2/EX2.3/ex2_3.sce create mode 100755 61/CH2/EX2.4/ex2_4.sce create mode 100755 61/CH2/EX2.5/ex2_5.jpg create mode 100755 61/CH2/EX2.5/ex2_5.sce create mode 100755 61/CH2/EX2.6/ex2_6.sce create mode 100755 61/CH2/EX2.7/ex2_7.sce create mode 100755 61/CH2/EX2.8/ex2_8.sce create mode 100755 61/CH2/EX2.9/ex2_9.sce (limited to '61/CH2') diff --git a/61/CH2/EX2.1/ex2_1.sce b/61/CH2/EX2.1/ex2_1.sce new file mode 100755 index 000000000..f6ec0052f --- /dev/null +++ b/61/CH2/EX2.1/ex2_1.sce @@ -0,0 +1,5 @@ +//Ex2.1 +//Average value of half wave rectifier +V_p=50; //Peak value is 50V +V_avg=V_p/%pi; +disp(V_avg,'average value of half wave rectifier in volts') \ No newline at end of file diff --git a/61/CH2/EX2.10/ex2_10.jpg b/61/CH2/EX2.10/ex2_10.jpg new file mode 100755 index 000000000..248d4f5c7 Binary files /dev/null and b/61/CH2/EX2.10/ex2_10.jpg differ diff --git a/61/CH2/EX2.10/ex2_10.sce b/61/CH2/EX2.10/ex2_10.sce new file mode 100755 index 000000000..031ba3f42 --- /dev/null +++ b/61/CH2/EX2.10/ex2_10.sce @@ -0,0 +1,26 @@ +//Ex2.10 +//let input wave be V_in=V_p_in*sin(2*%pi*f*t) +f=1; //Frequency is 1Hz +T=1/f; +R_1=100; //Resistances in ohms +R_L=1000; //Load +V_p_in=10; //Peak input voltage +V_th=0.7; //knee voltage of diode +clf(); +V_p_out=V_p_in*(R_L/(R_L+R_1)); //peak output voltage +disp(V_p_out,'peak output voltage in volts') +//let n be double the number of cycles of output shown in graph +for n=0:1:6 + t=T.*n/2:0.0005:T.*(n+1)/2 //time for each half cycle + V_in=V_p_in*sin(2*%pi*f.*t); + Vout=V_in*(R_L/(R_L+R_1)); + if modulo(n,2)==0 then //positive half, diode reverse biased + y=Vout; + else //negative half, diode forward biased + a=bool2s(Vout<-0.7); //puts zero to elements for which diode will conduct + b=bool2s(Vout>-0.7); + y=-V_th*a+b.*Vout; + end + plot(t,y) + end +xtitle('Negative limiter graph') \ No newline at end of file diff --git a/61/CH2/EX2.11/ex2_11.jpg b/61/CH2/EX2.11/ex2_11.jpg new file mode 100755 index 000000000..846545011 Binary files /dev/null and b/61/CH2/EX2.11/ex2_11.jpg differ diff --git a/61/CH2/EX2.11/ex2_11.sce b/61/CH2/EX2.11/ex2_11.sce new file mode 100755 index 000000000..285b959f3 --- /dev/null +++ b/61/CH2/EX2.11/ex2_11.sce @@ -0,0 +1,29 @@ +//Ex2.11 +//let input wave be V_in=V_p_in*sin(2*%pi*f*t) +f=1; //Frequency is 1Hz +T=1/f; +V_p_in=10; //Peak input voltage +V_th=0.7; //knee voltage of diode +clf(); +//let n be double the number of cycles of output shown in graph +for n=0:1:8 + t=T.*n/2:0.0005:T.*(n+1)/2 //time for each half cycle + V_in=V_p_in*sin(2*%pi*f.*t); + Vout=V_in; + if modulo(n,2)==0 then //positive half,D1 conducts till V_in=5.7V + a=bool2s(Vout<5.7); + b=bool2s(Vout>5.7); + y=a.*Vout+5.7*b; //output follows input till 5.7V then is constant at 5.7V + else //negative half, D2 conducts till V_in=-5.7V + a=bool2s(Vout<-5.7); + b=bool2s(Vout>-5.7); + y=-5.7*a+b.*Vout; //output follows input till -5.7V then stays constant at -5.7V + end + plot(t,y,'r') + + plot(t,V_in,'-.') + end + hl=legend(['output','input']); + xtitle('Positive and Negative diode limiter') + disp('max output voltage is 5.7V') + disp('min output voltage is -5.7V') \ No newline at end of file diff --git a/61/CH2/EX2.12/ex2_12.jpg b/61/CH2/EX2.12/ex2_12.jpg new file mode 100755 index 000000000..86e1b3983 Binary files /dev/null and b/61/CH2/EX2.12/ex2_12.jpg differ diff --git a/61/CH2/EX2.12/ex2_12.sce b/61/CH2/EX2.12/ex2_12.sce new file mode 100755 index 000000000..fdff6af05 --- /dev/null +++ b/61/CH2/EX2.12/ex2_12.sce @@ -0,0 +1,28 @@ +//Ex2.12 +//Positive diode limiter +//Let input wave be V_in=V_p_in*sin(2*%pi*f*t) +f=1; //let frequency be 1Hz +T=1/f; +V_p_in=18; //peak input voltage is 18V +V_supply=12; +R2=100; +R3=220; //resistances in ohms +V_bias=V_supply*(R3/(R2+R3)); +V=V_bias+0.7; //waveform clipped at V +clf(); +//let n be double the number of cycles of output wave shown in graph +for n=0:1:8 + t=n*T/2:0.0005:T.*(n+1)/2; + V_in=V_p_in*sin(2*%pi*f.*t); + Vout=V_in; + if modulo(n,2)==0 then //positive half, diode conucts till V + a=bool2s(VoutV); + y=a.*Vout+V*b; + else //negative half cycle, output follows input + y=Vout; + end + plot(t,y) +end +xtitle('Positive diode limiter graph') +disp(V,'diode limiting the voltage at this voltage') \ No newline at end of file diff --git a/61/CH2/EX2.13/ex2_13.jpg b/61/CH2/EX2.13/ex2_13.jpg new file mode 100755 index 000000000..d5ae8b1bf Binary files /dev/null and b/61/CH2/EX2.13/ex2_13.jpg differ diff --git a/61/CH2/EX2.13/ex2_13.sce b/61/CH2/EX2.13/ex2_13.sce new file mode 100755 index 000000000..27acca902 --- /dev/null +++ b/61/CH2/EX2.13/ex2_13.sce @@ -0,0 +1,15 @@ +//Ex2.13 +//Negative Clamping circuit +//let input voltage be V_in=V_p_in*sin(2*%pi*f*t) +f=1; //let frequency be 1Hz +T=1/f; +V_p_in=24; +V_DC=-(V_p_in-0.7); //DC level added to output +disp(V_DC,'V_DC in volts= ') +for n=0:1:8 + t=n*T/2:0.0005:T.*(n+1)/2; + V_in=V_p_in*sin(2*%pi*f.*t); + Vout=V_DC+V_in; + plot(t,Vout) +end +xtitle('Negative clipper graph') \ No newline at end of file diff --git a/61/CH2/EX2.2.a/ex2_2a.jpg b/61/CH2/EX2.2.a/ex2_2a.jpg new file mode 100755 index 000000000..73c34ff00 Binary files /dev/null and b/61/CH2/EX2.2.a/ex2_2a.jpg differ diff --git a/61/CH2/EX2.2.a/ex2_2a.sce b/61/CH2/EX2.2.a/ex2_2a.sce new file mode 100755 index 000000000..9e48e7e81 --- /dev/null +++ b/61/CH2/EX2.2.a/ex2_2a.sce @@ -0,0 +1,25 @@ +//Example-2.2(a) +//let V_in=5*sin(2*%pi*f.*t) be input wave ,hence frequency=1Hz +f=1; +V_p_in=5; +V_pout=V_p_in-0.7;; +disp(V_pout,'half wave rectifier output in volts') +t_d=(asin(0.7/V_p_in))/(2*%pi*f) +//t_d is the time till which diode will be reverse biased ie, till it reaches knee voltage +T=1/f; +clf(); +//let n be double the number of cycles of output shown in graph +for n=0:1:8 + t=T.*n/2:0.0005:T.*(n+1)/2 //time for each half cycle + if modulo(n,2)==0 then //positive half cycle, diode is forward biased + V_in=V_p_in*sin(2*%pi*f.*t) + Vout=V_in-0.7 //0.7 is knee voltage of diode + a=bool2s(Vout>0) //replace elements of Vout by 0 till input is 0.7 + y=a.*Vout + else //negative half cycle, diode is reverse biased + [p,q]=size(t); + y=zeros(p,q); + end + plot(t,y) +end +xtitle('half wave rectifier output') \ No newline at end of file diff --git a/61/CH2/EX2.2.b/ex2_2b.JPG b/61/CH2/EX2.2.b/ex2_2b.JPG new file mode 100755 index 000000000..905b4b7ff Binary files /dev/null and b/61/CH2/EX2.2.b/ex2_2b.JPG differ diff --git a/61/CH2/EX2.2.b/ex2_2b.sce b/61/CH2/EX2.2.b/ex2_2b.sce new file mode 100755 index 000000000..a62751546 --- /dev/null +++ b/61/CH2/EX2.2.b/ex2_2b.sce @@ -0,0 +1,25 @@ +//Example-2.2(b) +//let V_in=100*sin(2*%pi*f.*t) be input wave ,hence frequency=1Hz +f=1; +T=1/f; +V_p_in=100; +V_pout=(V_p_in-0.7); +disp(V_pout,'output of half wave rectifier in volts') +t_d=(asin(0.7/V_p_in))/(2*%pi*f) +//t_d is the time till which diode will be reverse biased ie, till it reaches knee voltage +clf(); +//let n be double the number of cycles of output shown in graph +for n=0:1:7 + t=T.*n/2:0.0005:T.*(n+1)/2 // time for each half cycle + if modulo(n,2)==0 then //positive half cycle + V_in=V_p_in*sin(2*%pi*f.*t) + Vout=V_in-0.7 //0.7 is knee voltage of diode + a=bool2s(Vout>0) //replace elements of Vout by 0 till input is 0.7 + y=a.*Vout + else //negative half cycle + [p,q]=size(t); + y=zeros(p,q); + end + plot(t,y) +end +xtitle('half wave rectifier output') \ No newline at end of file diff --git a/61/CH2/EX2.3/ex2_3.sce b/61/CH2/EX2.3/ex2_3.sce new file mode 100755 index 000000000..50fb497b9 --- /dev/null +++ b/61/CH2/EX2.3/ex2_3.sce @@ -0,0 +1,7 @@ +//Ex2.3 +V_p_in=156; //Peak input voltage +V_p_pri=156; //Peak voltage of primary of transformer +n=1/2; //Turn ratio is 2:1 +V_p_sec=n*V_p_pri; +V_p_out=(V_p_sec-0.7); +disp(V_p_out,'peak output voltage of half wave rectifier in volts') //Peak output voltage \ No newline at end of file diff --git a/61/CH2/EX2.4/ex2_4.sce b/61/CH2/EX2.4/ex2_4.sce new file mode 100755 index 000000000..1ad0cb0f6 --- /dev/null +++ b/61/CH2/EX2.4/ex2_4.sce @@ -0,0 +1,5 @@ +//Ex2.4 +//Average value of output of full wave rectifier +V_p=15; //Peak voltage +V_avg=(2*V_p)/%pi; +disp(V_avg,'Average value of output of full wave rectifier in volts') //Result \ No newline at end of file diff --git a/61/CH2/EX2.5/ex2_5.jpg b/61/CH2/EX2.5/ex2_5.jpg new file mode 100755 index 000000000..f225c8217 Binary files /dev/null and b/61/CH2/EX2.5/ex2_5.jpg differ diff --git a/61/CH2/EX2.5/ex2_5.sce b/61/CH2/EX2.5/ex2_5.sce new file mode 100755 index 000000000..46cd06042 --- /dev/null +++ b/61/CH2/EX2.5/ex2_5.sce @@ -0,0 +1,28 @@ +//Ex2.5 +//Assume frequency of input to be 1Hz +f=1; +T=1/f; +V_p_pri=100; //Peak voltage across primary winding +n=1/2; //tun ratio is 2:1 +V_p_sec=n*V_p_pri; +V_sec=V_p_sec/2; //voltage across each secondary is half the total voltage +clf(); +subplot(121) +xtitle('voltage across each secondary') +t=0:0.0005:2; +x=V_sec*sin(2*%pi*f.*t); +plot(t,x) +subplot(122) +xtitle('voltage across load') +//let n be double the number of cycles of output shown in graph +for n=0:1:4 + t=n.*T/2:0.0005:(n+1).*(T/2); +V_pout=V_sec-0.7; +V=V_pout*sin(2*%pi*f.*t) +a=bool2s(V*(-1)^n>0); +y=(-1)^n.*a.*V; +plot(t,y) +end +disp(V_pout,'full wave rectifier output voltage') +PIV=2*V_pout+0.7; +disp(PIV,'PIV in volts') diff --git a/61/CH2/EX2.6/ex2_6.sce b/61/CH2/EX2.6/ex2_6.sce new file mode 100755 index 000000000..08c581126 --- /dev/null +++ b/61/CH2/EX2.6/ex2_6.sce @@ -0,0 +1,10 @@ +//Ex-2.6 +V_rms=12; //rms secondary voltage +V_p_sec=sqrt(2)*V_rms; //peak secondary voltage +V_th=0.7; //knee voltage of diode +V_p_out=V_p_sec-2*V_th; //in one cycle, 2 diodes conduct +PIV=V_p_out+V_th; //applying KVL +disp('Peak output voltage in volts= '); +disp(V_p_out); +disp('PIV across each diode in volts= '); +disp(PIV) \ No newline at end of file diff --git a/61/CH2/EX2.7/ex2_7.sce b/61/CH2/EX2.7/ex2_7.sce new file mode 100755 index 000000000..e468b4f10 --- /dev/null +++ b/61/CH2/EX2.7/ex2_7.sce @@ -0,0 +1,14 @@ +//Ex2.7 +R_l=2200; //load resistance in Ohm +C=50*10^-6; //capacitance in Farad +V_rms=115; //rms of primary +V_p_pri=sqrt(2)*V_rms; //peak voltage across primary +n=0.1; //turn ratio is 10:1 +V_p_sec=n*V_p_pri; //primary voltage across secondary +V_p_rect=V_p_sec-1.4 //unfiltered peak rectified voltage +//we subtract 1.4 because in each cycle 2 diodes conduct & 2 do not +f=120; //frequency of full wave rectified voltage +V_r_pp=(1/(f*R_l*C))*V_p_rect; //peak to peak ripple voltage +V_DC=(1-(1/(2*f*R_l*C)))*V_p_rect; +r=V_r_pp/V_DC; +disp(r,'Ripple factor') \ No newline at end of file diff --git a/61/CH2/EX2.8/ex2_8.sce b/61/CH2/EX2.8/ex2_8.sce new file mode 100755 index 000000000..ccd94677f --- /dev/null +++ b/61/CH2/EX2.8/ex2_8.sce @@ -0,0 +1,13 @@ +//Ex2.8 +V_REF=1.25; //in volts +V_R1=V_REF; +R1=220; //in ohms +I_ADJ=50*10^-6 //in amperes +// MAX VALUE OF R2=5000 Ohms +//V_out=V_REF*(1+(R2/R1))+I_ADJ*R2 +R2_min=0; +V_out_min=V_REF*(1+(R2_min/R1))+I_ADJ*R2_min; +R2_max=5000; +V_out_max=V_REF*(1+(R2_max/R1))+I_ADJ*R2_max; +disp(V_out_min,'minimum output voltage in volts'); +disp(V_out_max,'maximum output voltage in volts'); \ No newline at end of file diff --git a/61/CH2/EX2.9/ex2_9.sce b/61/CH2/EX2.9/ex2_9.sce new file mode 100755 index 000000000..361e93fdf --- /dev/null +++ b/61/CH2/EX2.9/ex2_9.sce @@ -0,0 +1,6 @@ +//Ex2.9 +V_NL=5.18 //No load output voltage +V_FL=5.15 //Full load output voltage +load_reg=((V_NL-V_FL)/V_FL)*100 //In percentage +disp('load regulation percent= ') +disp(load_reg) \ No newline at end of file -- cgit