From b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b Mon Sep 17 00:00:00 2001
From: priyanka
Date: Wed, 24 Jun 2015 15:03:17 +0530
Subject: initial commit / add all books

---
 462/CH4/EX4.1.a.i/ex_4_1_a_i.pdf   | Bin 0 -> 92086 bytes
 462/CH4/EX4.1.a.i/ex_4_1_a_i.sce   |  41 +++++++++++++++++++++++++++++++++++++
 462/CH4/EX4.1.a.ii/ex_4_1_a_ii.pdf | Bin 0 -> 92142 bytes
 462/CH4/EX4.1.a.ii/ex_4_a_ii.sce   |  17 +++++++++++++++
 4 files changed, 58 insertions(+)
 create mode 100755 462/CH4/EX4.1.a.i/ex_4_1_a_i.pdf
 create mode 100755 462/CH4/EX4.1.a.i/ex_4_1_a_i.sce
 create mode 100755 462/CH4/EX4.1.a.ii/ex_4_1_a_ii.pdf
 create mode 100755 462/CH4/EX4.1.a.ii/ex_4_a_ii.sce

(limited to '462/CH4')

diff --git a/462/CH4/EX4.1.a.i/ex_4_1_a_i.pdf b/462/CH4/EX4.1.a.i/ex_4_1_a_i.pdf
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diff --git a/462/CH4/EX4.1.a.i/ex_4_1_a_i.sce b/462/CH4/EX4.1.a.i/ex_4_1_a_i.sce
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+//example 4.1(a)//
+clc
+//clears the screen//
+clear
+//clears already existing variables//
+disp('as given low level, V(o)=0.2V and high level, V(1)=5V')
+disp('case 1, when all the inputs are HIGH')
+//in this case both diodes will be conducting and transistor will be in saturation//
+a=0.7+0.7+0.8;
+//V(p)//
+b=5;
+//high level voltage in volts//
+c=5;
+//resistor in Kohms//
+d=0.8;
+//voltage between base and emitter in volts//
+e=(b-a)/c;
+//I(1)//
+f=d/c;
+//I(2)//
+i=e-f;
+//writing kirchoff's current law at the base of transistor//
+g=0.2;
+//voltage between collector and emitter in saturation(in volts)//
+h=2.2;
+//resistance of collector in Kohms//
+j=(b-g)/h;
+//collector current without load gate connected//
+disp('I(1) in mA:')
+disp(e)
+disp('I(2) in mA:')
+disp(f)
+disp('collector current(in mA):')
+disp(j)
+k=30;
+//h(FE)//
+s=k*i;
+if(s>j)
+disp('transistor is in saturation mode')
+disp('fan out is given by I(c)<=h(FE)I(B)')
+end
\ No newline at end of file
diff --git a/462/CH4/EX4.1.a.ii/ex_4_1_a_ii.pdf b/462/CH4/EX4.1.a.ii/ex_4_1_a_ii.pdf
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diff --git a/462/CH4/EX4.1.a.ii/ex_4_a_ii.sce b/462/CH4/EX4.1.a.ii/ex_4_a_ii.sce
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+//example 4.1.a(ii)//
+clc
+//clears the screen//
+clear
+//clears already existing variables//
+//for DTL NAND gate calculate fan out//
+disp('case II , if atleast one of the inputs is LOW')
+v=0.2+0.7;
+m=0.6+0.6+0.5;
+//min voltage for both diodes and transistor to be conducting//
+disp(v)
+disp('min voltage for both diodes and transistor to be conducting:')
+disp(m)
+if(v<m)
+disp('transistor is in cut off mode')
+disp('if the load gates are connected, the input diodes of the load gates are non conducting, which means the reverse saturation current of these diodes must be supplied through the collector resistor R(c), which will produce a voltage drop across R(c) and consequently the output voltage corresponding to HIGH state will be a little less than V(cc). The maximum current which can be supplied by the gate will depend upon V(OH). The fan out is determined on the basis of maximum current.')
+end
\ No newline at end of file
-- 
cgit