From b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b Mon Sep 17 00:00:00 2001
From: priyanka
Date: Wed, 24 Jun 2015 15:03:17 +0530
Subject: initial commit / add all books

---
 1964/CH12/EX12.17/ex12_17.sce | 8 ++++++++
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 create mode 100755 1964/CH12/EX12.17/ex12_17.sce

(limited to '1964/CH12/EX12.17')

diff --git a/1964/CH12/EX12.17/ex12_17.sce b/1964/CH12/EX12.17/ex12_17.sce
new file mode 100755
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+//Chapter-12, Example 12.17, Page 364
+//=============================================================================
+clc
+clear
+//During the negative half of the input signal,the diode conducts,and acts like a short circuit.Now,the output voltage,V0=0V.The capacitor is charged to 10V with polarities and it behaves like a battery.
+//During the positive half of the input signal,the diode does not conduct,and acts like an open circuit.Hence,the output voltage,V0=20V.This gives positively clamped voltage.
+mprintf("V0=10+10=20 V")
+//=================================END OF PROGRAM=======================================================================================================
-- 
cgit