From b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b Mon Sep 17 00:00:00 2001
From: priyanka
Date: Wed, 24 Jun 2015 15:03:17 +0530
Subject: initial commit / add all books

---
 1133/CH3/EX3.8/Example3_8.sce | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 1133/CH3/EX3.8/Example3_8.sce

(limited to '1133/CH3/EX3.8')

diff --git a/1133/CH3/EX3.8/Example3_8.sce b/1133/CH3/EX3.8/Example3_8.sce
new file mode 100755
index 000000000..8e1653294
--- /dev/null
+++ b/1133/CH3/EX3.8/Example3_8.sce
@@ -0,0 +1,21 @@
+//Example 3.8
+clc
+disp("Here, output voltage is sampled and fed in series with the input signal. Hence the topology is voltage series feedback.")
+disp("  The open loop voltage gain for one stage is given as,")
+disp("    Av = -gm*R_eq")
+req=(8*40*1000)/((40*1000)+(8*1000)+(8*40))  // in k-ohm
+format(5)
+disp(req,"  R_eq(in k-ohm) = r_d || R_d || (R_i1+R_2) =")
+av=-5*6.62
+format(6)
+disp(av,"  Av =")
+avm=-33.11^3
+disp(avm,"Av = Overall voltage gain = |A_vmid|^3 =")  // answer in textbook is wrong
+beta=50/(10^6)
+format(7)
+disp(beta,"  beta = Vf / Vo = -R_1 / R_g = -R_1 / R_1+R_2 =")
+d=1+((-5*10^-5)*-36306)
+format(6)
+disp(d,"  D = 1 + |Av|*beta =")
+avf=-36306/2.8153
+disp(avf,"  A_vf = Av / D =")
\ No newline at end of file
-- 
cgit