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-rwxr-xr-x275/CH3/EX3.3.73/Ch3_3_73.sce76
1 files changed, 38 insertions, 38 deletions
diff --git a/275/CH3/EX3.3.73/Ch3_3_73.sce b/275/CH3/EX3.3.73/Ch3_3_73.sce
index 1b299caa6..c2a961817 100755
--- a/275/CH3/EX3.3.73/Ch3_3_73.sce
+++ b/275/CH3/EX3.3.73/Ch3_3_73.sce
@@ -1,38 +1,38 @@
-clc
-disp("Example 3.73")
-printf("\n")
-disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")
-printf("Given\n")
-//given
-Vcc=18
-Vbe=0.7
-hFE=50
-R1=33*10^3
-R2=12*10^3
-Rc=1.2*10^3
-Re=10^3
-//thevenin voltage
-Vt=(Vcc*R2)/(R1+R2)
-//thevenin resistance
-Rt=(R1*R2)/(R1+R2)
-//base current
-Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)
-//collector current
-Icq=hFE*Ib
-//emitter current
-Ie=Ib+Icq
-//emitter voltage
-Ve=Ie*Re
-//collector to emitter voltage
-Vceq=Vcc-(Icq*Rc)-(Ie*Re)
-//collector voltage
-Vc=Vce+Ve
-//to draw DC load line
-Ic1=Vcc/(Rc+Re)
-Vce=[Vcc Vceq 0]
-Ic=[0 Icq Ic1]
-printf("Q(%f volt,%f ampere)\n",Vceq,Icq)
-plot2d(Vce, Ic)
-xlabel("Vce in volt")
-ylabel("Ic in ampere")
-xtitle("DC load line for base bias circuit")
+clc
+disp("Example 3.73")
+printf("\n")
+disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")
+printf("Given\n")
+//given
+Vcc=18
+Vbe=0.7
+hFE=50
+R1=33*10^3
+R2=12*10^3
+Rc=1.2*10^3
+Re=10^3
+//thevenin voltage
+Vt=(Vcc*R2)/(R1+R2)
+//thevenin resistance
+Rt=(R1*R2)/(R1+R2)
+//base current
+Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)
+//collector current
+Icq=hFE*Ib
+//emitter current
+Ie=Ib+Icq
+//emitter voltage
+Ve=Ie*Re
+//collector to emitter voltage
+Vceq=Vcc-(Icq*Rc)-(Ie*Re);
+Vce=[Vcc Vceq 0];
+//collector voltage
+Vc=Vce+Ve
+//to draw DC load line
+Ic1=Vcc/(Rc+Re)
+Ic=[0 Icq Ic1]
+printf("Q(%f volt,%f ampere)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce in volt")
+ylabel("Ic in ampere")
+xtitle("DC load line for base bias circuit") \ No newline at end of file