From 8fee690e428db1183e028dd8b832e06a367c89cc Mon Sep 17 00:00:00 2001
From: vishnueaswaran
Date: Fri, 19 Jul 2019 13:11:54 +0530
Subject: unknown changes!

---
 .../OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.cpp     | 0
 Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.h | 2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)
 mode change 100644 => 100755 Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.cpp
 mode change 100644 => 100755 Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.h

(limited to 'Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries')

diff --git a/Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.cpp b/Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.cpp
old mode 100644
new mode 100755
diff --git a/Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.h b/Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.h
old mode 100644
new mode 100755
index 2f2e7c5..33b0fb5
--- a/Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.h
+++ b/Resources/OpenPLCv2/firmware/ADC.test.arduino/one/libraries/vishnuADC.h
@@ -65,7 +65,7 @@ class ADS1118 {
         union Config configRegister;        ///< Config register
 
         //Bit constants
-		const long int SCLK       = 4000000;///< ADS1118 SCLK frequency: 4000000 Hz Maximum for ADS1018 (4Mhz)
+		const long int SCLK       = 1000000;///< ADS1118 SCLK frequency: 4000000 Hz Maximum for ADS1018 (4Mhz)
 		
 		// Used by "SS" bit
 		const uint8_t START_NOW   = 1;      ///< Start of conversion in single-shot mode
-- 
cgit