From b503d66fcc1e26be28b58cccf888e43f99d35ae2 Mon Sep 17 00:00:00 2001
From: Ambikeshwar
Date: Wed, 25 May 2016 14:20:23 +0530
Subject: Samples of VHDL code added for testing

---
 VHDL/inverter.vhdl | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 VHDL/inverter.vhdl

(limited to 'VHDL/inverter.vhdl')

diff --git a/VHDL/inverter.vhdl b/VHDL/inverter.vhdl
new file mode 100644
index 0000000..b9641fd
--- /dev/null
+++ b/VHDL/inverter.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+    port ( i: in std_logic_vector(0 downto 0);
+           o: out std_logic_vector(0 downto 0));
+end inverter;
+
+architecture inverter_beh of inverter is
+begin
+    o <= not i;
+end architecture;
+
+
-- 
cgit