From b503d66fcc1e26be28b58cccf888e43f99d35ae2 Mon Sep 17 00:00:00 2001
From: Ambikeshwar
Date: Wed, 25 May 2016 14:20:23 +0530
Subject: Samples of VHDL code added for testing

---
 VHDL/counter.vhdl | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 VHDL/counter.vhdl

(limited to 'VHDL/counter.vhdl')

diff --git a/VHDL/counter.vhdl b/VHDL/counter.vhdl
new file mode 100644
index 0000000..8d1d52e
--- /dev/null
+++ b/VHDL/counter.vhdl
@@ -0,0 +1,26 @@
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is 
+port(  clk:  in std_logic_vector(0 downto 0);
+  reset:  in std_logic_vector(0 downto 0);
+  count:  out std_logic_vector(3 downto 0)
+);
+end counter;
+
+architecture behav of counter is         
+  signal pre_count: unsigned(3 downto 0);
+  
+  begin
+    process(clk,reset)
+    begin
+      if reset = "1" then
+        pre_count <= "0000";
+      elsif (clk= "1" and clk'event) then
+          pre_count <= pre_count +1;
+      end if;	
+    end process; 
+ 
+    count <= std_logic_vector(pre_count);
+end behav;
-- 
cgit