From b503d66fcc1e26be28b58cccf888e43f99d35ae2 Mon Sep 17 00:00:00 2001
From: Ambikeshwar
Date: Wed, 25 May 2016 14:20:23 +0530
Subject: Samples of VHDL code added for testing

---
 VHDL/and_nghdl.vhdl | 15 +++++++++++++++
 VHDL/counter.vhdl   | 26 ++++++++++++++++++++++++++
 VHDL/d_ff.vhdl      | 19 +++++++++++++++++++
 VHDL/flipflop.vhdl  | 22 ++++++++++++++++++++++
 VHDL/inverter.vhdl  | 14 ++++++++++++++
 VHDL/myxor.vhdl     | 15 +++++++++++++++
 VHDL/or_nghdl.vhdl  | 15 +++++++++++++++
 7 files changed, 126 insertions(+)
 create mode 100644 VHDL/and_nghdl.vhdl
 create mode 100644 VHDL/counter.vhdl
 create mode 100644 VHDL/d_ff.vhdl
 create mode 100644 VHDL/flipflop.vhdl
 create mode 100644 VHDL/inverter.vhdl
 create mode 100644 VHDL/myxor.vhdl
 create mode 100644 VHDL/or_nghdl.vhdl

diff --git a/VHDL/and_nghdl.vhdl b/VHDL/and_nghdl.vhdl
new file mode 100644
index 0000000..3d48201
--- /dev/null
+++ b/VHDL/and_nghdl.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity and_nghdl is
+       port (e : in  std_logic_vector(0 downto 0); 
+             f : in  std_logic_vector(0 downto 0);
+             g : out std_logic_vector(0 downto 0)); 
+     end and_nghdl;
+     
+     architecture rtl of and_nghdl is
+     begin
+        
+        g <= e and f;
+        
+     end rtl;
diff --git a/VHDL/counter.vhdl b/VHDL/counter.vhdl
new file mode 100644
index 0000000..8d1d52e
--- /dev/null
+++ b/VHDL/counter.vhdl
@@ -0,0 +1,26 @@
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is 
+port(  clk:  in std_logic_vector(0 downto 0);
+  reset:  in std_logic_vector(0 downto 0);
+  count:  out std_logic_vector(3 downto 0)
+);
+end counter;
+
+architecture behav of counter is         
+  signal pre_count: unsigned(3 downto 0);
+  
+  begin
+    process(clk,reset)
+    begin
+      if reset = "1" then
+        pre_count <= "0000";
+      elsif (clk= "1" and clk'event) then
+          pre_count <= pre_count +1;
+      end if;	
+    end process; 
+ 
+    count <= std_logic_vector(pre_count);
+end behav;
diff --git a/VHDL/d_ff.vhdl b/VHDL/d_ff.vhdl
new file mode 100644
index 0000000..efc4177
--- /dev/null
+++ b/VHDL/d_ff.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee. std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity d_ff is
+PORT( D: in std_logic_vector(0 downto 0);
+CLOCK: in std_logic_vector(0 downto 0);
+Q: out std_logic_vector(0 downto 0));
+end d_ff;
+ 
+architecture behavioral of d_ff is
+begin
+process(CLOCK)
+begin
+if(CLOCK='1' and CLOCK'EVENT) then
+Q<=D;
+end if;
+end process;
+end behavioral;
diff --git a/VHDL/flipflop.vhdl b/VHDL/flipflop.vhdl
new file mode 100644
index 0000000..4140b76
--- /dev/null
+++ b/VHDL/flipflop.vhdl
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity flipflop is
+    Port ( CLK : in std_logic_vector(0 downto 0);
+	   RESET : in std_logic_vector(0 downto 0);
+           Dinp : in std_logic_vector(0 downto 0);
+           Dout : out std_logic_vector(0 downto 0));
+           
+end flipflop;
+architecture Behavioral of flipflop is
+begin
+            process (CLK,reset)
+            begin
+		if RESET = "1" then 
+			Dout <= "0";
+		elsif (CLK = "1" and CLK'event) then
+                        Dout <= Dinp;
+                end if;
+            end process;
+end Behavioral;
diff --git a/VHDL/inverter.vhdl b/VHDL/inverter.vhdl
new file mode 100644
index 0000000..b9641fd
--- /dev/null
+++ b/VHDL/inverter.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+    port ( i: in std_logic_vector(0 downto 0);
+           o: out std_logic_vector(0 downto 0));
+end inverter;
+
+architecture inverter_beh of inverter is
+begin
+    o <= not i;
+end architecture;
+
+
diff --git a/VHDL/myxor.vhdl b/VHDL/myxor.vhdl
new file mode 100644
index 0000000..b49f3ca
--- /dev/null
+++ b/VHDL/myxor.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity myxor is
+       port (a : in  std_logic_vector(0 downto 0); 
+             b : in  std_logic_vector(0 downto 0);
+             c : out std_logic_vector(0 downto 0)); 
+     end myxor;
+     
+     architecture rtl of myxor is
+     begin
+        
+        c <= a xor b;
+        
+     end rtl;
diff --git a/VHDL/or_nghdl.vhdl b/VHDL/or_nghdl.vhdl
new file mode 100644
index 0000000..92e36a8
--- /dev/null
+++ b/VHDL/or_nghdl.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity or_nghdl is
+       port (x : in  std_logic_vector(0 downto 0); 
+             y : in  std_logic_vector(0 downto 0);
+             z : out std_logic_vector(0 downto 0)); 
+     end or_nghdl;
+     
+     architecture rtl of or_nghdl is
+     begin
+        
+        z <= x or y;
+        
+     end rtl;
-- 
cgit