Eeschema

Eeschema is powerful schematic capture software distributed as part of KiCad and available under the following operating systems:

Regardless of the OS, all Eeschema files are 100% compatible from one OS to another.

Eeschema is an integrated application where all functions of drawing, control, layout, library management and access to the PCB design software are carried out within Eeschema itself.

Eeschema is intended to work with PcbNew, which is KiCad’s printed circuit design software. It can also export netlist files, which list all the electrical connections, for other packages.

Eeschema includes a component symbol editor, which can create and edit components and manage libraries. It also integrates the following additional but essential functions needed for modern schematic capture software:

Eeschema is limited only by the available memory. There is thus no real limitation to the number of components, component pins, connections, or sheets. In the case of multi-sheet diagrams, the representation is hierarchical.

Eeschema can use multi-sheet diagrams of these types:

You can reach the various commands by:

Here are the various possible command locations:

Here is the default hot key list:

All hot keys can be redefined by the user via the hotkey editor:

In Eeschema, the cursor moves over a grid, which can be displayed or hidden. The grid is always displayed in the library manager.

You can change the grid size via the pop-up menu or via the Preferences/Options menu.

The default grid size is 50 mil (0.050") or 1,27 millimeters.

This is the prefered grid to place components and wires in a schematic, and to place pins when designing a symbol in the Component Editor.

One can also work with a smaller grid from 25 mil to 10 mil. This is only intended for designing the component body or placing text and comments, not for placing pins and wires.

To change the zoom level:

The display units are in inches or millimeters. However, Eeschema always works internally in 0.001-inch (mil/thou) units.

The following information is displayed at the bottom right hand side of the window:

The relative coordinates can be reset to zero with the space bar. This is useful for making measurements between two points.

The top menu bar allows the opening and saving of schematics, program configuration, and viewing the documentation.

This toolbar gives access to the main functions of Eeschema.

If Eeschema is run in standalone mode, this is the available tool set:

If Eeschema is run from the project manager (KiCad), this is the available tool set:

Tools to initialize a project are not available, because these tools are in the Project Manager.

This toolbar contains tools to:

This toolbar manages the display options:

A right-click opens a contextual menu for the selected element. This contains:

Pop-up without selected element.

Editing of a label.

Editing a component.

Access to on-line help (this document) for an extensive tutorial about KiCad. Use “Copy Version Information” when submitting bug reports to identify your build and system.

The Sheet Settings icon, , allows you to define the sheet size and the contents of the title block.

Sheet numbering is automatically updated. You can set the date to today by pressing the left arrow button by "Issue Date", but it will not be automatically changed.

The Find icon, , can be used to access the search tool.

You can search for a reference, a value, or a text string in the current sheet or in the whole hierarchy. Once found, the cursor will be positioned on the found element in the relevant sub-sheet.

The Netlist icon, , opens the netlist generation tool.

The netlist file it creates describes all connections in the entire hierarchy.

In a multisheet hierarchy, any local label is visible only inside the sheet to which it belongs. Thus, the label TOTO of sheet 3 is different from the label TOTO of sheet 5 (if no connection has been intentionally introduced to connect them). This is due to the fact that the sheet name path is internally associated with the local label.

Note 1:

Label lengths have no limitations in Eeschema, but the software exploiting the generated netlist can be limited on this point.

Note 2:

Avoid spaces in the labels, because they will appear as separated words. It is not a limitation of Eeschema, but of many netlist formats, which often assume that a label has no spaces.

Option:

Default Format:

Check to select Pcbnew as the default format.

Other formats can also be generated:

External plugins can be launched to extend the netlist formats list (a PadsPcb Plugin was added here).

The icon gives access to the annotation tool. This tool performs an automatic naming of all components in the schematic.

For multi-part components (such as 7400 TTL which contains 4 gates), a multi-part suffix is also allocated (thus a 7400 TTL designated U3 will be divided into U3A, U3B, U3C and U3D).

You can unconditionally annotate all the components, or only the new components, i.e. those which were not previously annotated.

Scope

Annotation Order

Selects the order in which components will be numbered.

Annotation Choice

Selects the method by which numbers will be selected.

The icon gives access to the electrical rules check (ERC) tool.

This tool performs a design verification and is particularly useful to detect forgotten connections, and inconsistencies.

Once you have run the ERC, Eeschema places markers to highlight problems. The diagnosis can then be given by left clicking on the marker. An error file can also be generated.

The icon gives access to the bill of materials (BOM) generator. This menu allows the generation of a file listing of the components and/or hierarchical connections (global labels).

Eeschema’s BOM generator makes use of external plugins, generally in XSLT or Python form. Some are provided, and will be installed inside the KiCad program files directory.

A useful set of component properties to use for a BOM are:

For example:

A schematic can be represented by a single sheet, but, if big enough, it will require several sheets.

A schematic represented by several sheets is hierarchical, and all its sheets (each one represented by its own file) constitute an Eeschema project. The manipulation of hierarchical schematics will be described in the Hierarchical Schematics chapter.

A schematic designed with Eeschema is more than a simple graphic representation of an electronic device. It is normally the entry point of a development chain that allows for:

A schematic mainly consists of components, wires, labels, junctions, buses and power ports. For clarity in the schematic, you can place purely graphical elements like bus entries, comments, and polylines.

Components are added to the schematic from component libraries. After the schematic is made, a netlist is generated, which is later used to import the set of connections and footprints into PcbNew.

By default, Eeschema loads component symbols out of the libraries according to the set paths. This can cause a problem when loading a very old project: if the symbols in the library have changed since they were used in the project, the ones in the project would be automatically replaced with the new versions. The new versions might not line up correctly or might be oriented differently, leading to a broken schematic.

However, when a project is saved, a cache library is saved along with it. This allows the project to be distributed without the full libraries. If you load a project where symbols are present both in its cache and in the system libraries, Eeschema will scan the libraries for conflicts. Any conflicts found will be listed in the following dialog:

You can see in this example that the project originally used a diode with the cathode facing up, but the library now contains one with the cathode facing down. This change could ruin the project! Pressing OK here will cause the old symbol to be saved into a special “rescue” library, and all the components using that symbol will be renamed to avoid naming conflicts.

If you press Cancel, no rescues will be made, so Eeschema will load all the new components by default. Because no changes were made, you can still go back and run the rescue function again: choose "Rescue Cached Components" in the Tools menu to call up the dialog again.

If you would prefer not to see this dialog, you can press "Never Show Again". The default will be to do nothing and allow the new components to be loaded. This option can be changed back in the Component Libraries preferences.

A hierarchical representation is generally a good solution for projects bigger than a few sheets. If you want to manage this kind of project, it will be necessary to:

The complete schematic then consists in a main schematic sheet, called root sheet, and sub-sheets constituting the hierarchy. Moreover, a skillful subdividing of the design into separate sheets often improves on its readability.

From the root sheet, you must be able to find all sub-sheets. Hierarchical schematics management is very easy with Eeschema, thanks to an integrated "hierarchy navigator" accessible via the icon of the top toolbar.

There are two types of hierarchy that can exist simultaneously: the first one has just been evoked and is of general use. The second consists in creating components in the library that appear like traditional components in the schematic, but which actually correspond to a schematic which describes their internal structure.

This second type is used to develop integrated circuits, because in this case you have to use function libraries in the schematic you are drawing.

Eeschema currently doesn’t treat this second case.

A hierarchy can be:

Eeschema can deal with all these hierarchies.

The creation of a hierarchical schematic is easy, the whole hierarchy is handled starting from the root schematic, as if you had only one schematic.

The two important steps to understand are:

Navigation among sub-sheets It is very easy thanks to the navigator tool accessible via the button on the top toolbar.

Each sheet is reachable by clicking on its name. For quick access, right click on a sheet name, and choose to Enter Sheet.

You can quickly reach the root sheet, or a sub-sheet thanks to the tool of the right toolbar. After the navigation tool has been selected:

You have to:

Draw a rectangle defined by two diagonal points symbolizing the sub-sheet.

The size of this rectangle must allow you to place later particular labels, hierarchy pins, corresponding to the global labels (HLabels) in the sub-sheet.

These labels are similar to usual component pins. Select the tool .

Click to place the upper left corner of the rectangle. Click again to place the lower right corner, having a large enough rectangle.

You will then be prompted to type a file name and a sheet name for this sub-sheet (in order to reach the corresponding schematic, using the hierarchy navigator).

You must give at least a file name. If there is no sheet name, the file name will be used as sheet name (usual way to do that).

You will create here points of connection (hierarchy pins) for the symbol which has been just created.

These points of connection are similar to normal component pins, with however the possibility to connect a complete bus with only one point of connection.

There are two ways to do this:

The second solution is quite preferable.

Manual placement:

See below an example of the creation of the hierarchical pin called "CONNEXION".

You can define its graphical attributes, and size or later, by editing this pin sheet (Right click and select Edit in the PopUp menu).

Various pin symbols are available:

These pin symbols are only graphic enhancements, and have no other role.

Automatic placement:

All necessary pins can thus be placed quickly and without error. Their aspect is in accordance with corresponding global labels.

Each pin of the sheet symbol just created, must correspond to a label called hierarchical Label in the sub-sheet. Hierarchical labels are similar to labels, but they provide connections between sub-sheet and root sheet. The graphical representation of the two complementary labels (pin and HLabel) is similar. Hierarchical labels creation is made with the tool .

See below a root sheet example:

Notice pin VCC_PIC, connected to connector JP1.

Here are the corresponding connections in the sub-sheet :

You find again, the two corresponding hierarchical labels, providing connection between the two hierarchical sheets.

Here is an example. The same schematic is used twice (two instances). The two sheets share the same schematic because the file name is the same for the two sheets (“other_sheet.sch”). But the sheet names must be different.

You can create a project using many sheets, without creating connections between these sheets (flat hierarchy) if the next rules are respected:

Here is an example of a root sheet.

Here is the two pages, connected by global labels.

Here is the pic_programmer.sch.

Here is the pic_sockets.sch.

Look at global labels.

The automatic classification annotation tool allows you to automatically assign a designator to components in your schematic. For multi-parts components, assign a multi-part suffix to minimize the number of these packages. The automatic classification annotation tool is accessible via the icon . Here you find its main window.

Various possibilities are available:

The “Reset, but do not swap any annotated multi-unit parts” option keeps all existing associations between multi-unit parts. That is, if you have U2A and U2B, they may be reannotated to U1A and U1B respectively, but they will never be reannotated to U1A and U2A, nor to U2B and U2A. This is useful if you want to ensure that pin groupings are maintained, if you have already decided by yourself which subunits are best placed where.

The annotation order choice gives the method used to set the reference number inside each sheet of the hierarchy.

Except for particular cases, an automatic annotation applies to the whole project (all sheets) and to the new components, if you don’t want to modify previous annotations.

The Annotation Choice gives the method used to calculate reference Id:

The Electrical Rules Check (ERC) tool performs an automatic check of your schematic. The ERC checks for any errors in your sheet, such as unconnected pins, unconnected hierarchical symbols, shorted outputs, etc. Naturally, an automatic check is not infallible, and the software that makes it possible to detect all design errors is not yet 100% complete. Such a check is very useful, because it allows you to detect many oversights and small errors.

In fact all detected errors must be checked and then corrected before proceeding as normal. The quality of the ERC is directly related to the care taken in declaring electrical pin properties during library creation. ERC output is reported as "errors" or "warnings".

ERC can be started by clicking on the icon .

Warnings are placed on the schematic elements raising an ERC error (pins or labels).

You can also delete error markers from the dialog.

Here you can see four errors:

By right-clicking on a marker the pop-up menu allows you to access the ERC marker diagnostic window.

and when clicking on Marker Error Info you can get a description of the error.

It is common to have an error or a warning on power pins, even though all seems normal. See example above. This happens because, in most designs, the power is provided by connectors that are not power sources (like regulator output, which is declared as Power out).

The ERC thus won’t detect any Power out pin to control this wire and will declare them not driven by a power source.

To avoid this warning you have to place a "PWR_FLAG" on such a power port. Take a look at the following example:

The error marker will then disappear.

Most of the time, a PWR_FLAG must be connected to GND, because usually regulators have outputs declared as power out, but ground pins are never power out (the normal attribute is power in), so grounds never appear connected to a power source without a pwr_flag.

The Options panel allows you to configure connectivity rules to define electrical conditions for errors and warnings check.

Rules can be changed by clicking on the desired square of the matrix, causing it to cycle through the choices: normal, warning, error.

An ERC report file can be generated and saved by checking the option Write ERC report. The file extension for ERC report files is .erc. Here is an example of ERC report file.

A netlist is a file which describes electrical connections between components. In the netlist file you can find:

Different netlist formats exist. Sometimes the components list and the equi-potential list are two separate files. This netlist is fundamental in the use of schematic capture software, because the netlist is the link with other electronic CAD software, like:

Eeschema supports several netlist formats.

Select the tool to open the netlist creation dialog box.

Pcbnew selected

Spice selected

Using the different tabs you can select the desired format. In Spice format you can generate netlists with either equi-potential names (it is more legible) or net numbers (old Spice versions accept numbers only). By clicking the Netlist button, you will be asked for a netlist file name.

You can see below a schematic design using the PSPICE library:

Example of a PCBNEW netlist file:

In PSPICE format, the netlist is as follows:

For other netlist formats you can add netlist converters in the form of plugins. These converters are automatically launched by Eeschema. Chapter 14 gives some explanations and examples of converters.

A converter is a text file (xsl format) but one can use other languages like Python. When using the xsl format, a tool (xsltproc.exe or xsltproc) read the intermediate file created by Eeschema, and the converter file to create the output file. In this case, the converter file (a sheet style) is very small and very easy to write.

You can access both print and plot commands via the file menu.

The suported output formats are Postscript, PDF, SVG, DXF and HPGL. You can also directly print to your printer.

This command allows you to create PostScript files.

The file name is the sheet name with an extension .ps. You can disable the option "Plot border and title block". This is useful if you want to create a postscript file for encapsulation (format .eps) often used to insert a diagram in a word processing software. The message window displays the file names created.

Allows you to create plot files using the format PDF. The file name is the sheet name with an extension .pdf.

Allows you to create plot files using the vectored format SVG. The file name is the sheet name with an extension .svg.

Allows you to create plot files using the format DXF. The file name is the sheet name with an extension .dxf.

This command allows you to create an HPGL file. In this format you can define:

The plotter setup dialog window looks like the following:

The output file name will be the sheet name plus the extension .plt.

This command, available via the icon , allows you to visualize and generate design files for the standard printer.

The "Print sheet reference and title block" option enables or disables sheet references and title block.

The "Print in black and white" option sets printing in monochrome. This option is generally necessary if you use a black and white laser printer, because colors are printed into half-tones that are often not so readable.

A component is a schematic element which contains a graphical representation, electrical connections, and fields defining the component. Components used in a schematic are stored in component libraries. Eeschema provides a component library editing tool that allows you to create libraries, add, delete or transfer components between libraries, export components to files, and import components from files. The library editing tool provides a simple way to manage component library files.

A component library is composed of one or more components. Generally the components are logically grouped by function, type, and/or manufacturer.

A component is composed of:

Proper component designing requires:

The component library editor main window is shown below. It consists of three tool bars for quick access to common features and a component viewing/editing area. Not all commands are available on the tool bars but can be accessed using the menus.

The selection of the current library is possible via the which shows you all available libraries and allows you to select one. When a component is loaded or saved, it will be put in this library. The library name of component is the contents of its value field.

Graphical elements create the symbolic representation of a component and contain no electrical connection information. Their design is possible using the following tools:

The vertical toolbar on the right hand side of the main window allows you to place all of the graphical elements required to design a component’s symbolic representation.

Components can have two symbolic representations (a standard symbol and an alternate symbol often referred to as "DeMorgan") and/or have more than one unit per package (logic gates for example). Some components can have more than one unit per package each with different symbols and pin configurations.

Consider for instance a relay with two switches which can be designed as a component with three different units: a coil, switch 1, and switch 2. Designing a component with multiple units per package and/or alternate body styles is very flexible. A pin or a body symbol item can be common to all units or specific to a given unit or they can be common to both symbolic representation so are specific to a given symbol representation.

By default, pins are specific to each symbolic representation of each unit, because the pin number is specific to a unit, and the shape depends on the symbolic representation. When a pin is common to each unit or each symbolic representation, you need to create it only once for all units and all symbolic representations (this is usually the case for power pins). This is also the case for the body style graphic shapes and text, which may be common to each unit (but typically are specific to each symbolic representation).

You can click on the to create and insert a pin. The editing of all pin properties is done by double-clicking on the pin or right-clicking on the pin to open the pin context menu. Pins must be created carefully, because any error will have consequences on the PCB design. Any pin already placed can be edited, deleted, and/or moved.

All library components are defined with four default fields. The reference designator, value, footprint assignment, and documentation file link fields are created whenever a component is created or copied. Only the reference designator and value fields are required. For existing fields, you can use the context menu commands by right-clicking on the pin. Components defined in libraries are typically defined with these four default fields. Additional fields such as vendor, part number, unit cost, etc. can be added to library components but generally this is done in the schematic editor so the additional fields can be applied to all of the components in the schematic.

Power symbols are created the same way as normal components. It may be useful to place them in a dedicated library such as power.lib. Power symbols consist of a graphical symbol and a pin of the type "Power Invisible". Power port symbols are handled like any other component by the schematic capture software. Some precautions are essential. Below is an example of a power +5V symbol.

To create a power symbol, use the following steps:

An easier method to create a new power port symbol is to use another symbol as a model:

A component consist of the following elements

Two fields are to be initialized: reference and value. The name of the design associated with the component, and the name of the associated footprint, the other fields are the free fields, they can generally remain empty, and could be filled during schematic capture.

However, managing the documentation associated with any component facilitates the research, use and maintenance of libraries. The associated documentation consists of

Key words allow you to selectively search for a component according to various selection criteria. Comments and key words are displayed in various menus, and particularly when you select a component from the library.

The component also has an anchoring point. A rotation or a mirror is made relative to this anchor point and during a placement this point is used as a reference position. It is thus useful to position this anchor accurately.

A component can have aliases, i.e. equivalent names. This allows you to considerably reduce the number of components that need to be created (for example, a 74LS00 can have aliases such as 74000, 74HC00, 74HCT00…).

Finally, the components are distributed in libraries (classified by topics, or manufacturer) in order to facilitate their management.

The anchor is at the coordinates (0,0) and it is shown by the blue axes displayed on your screen.

The anchor can be repositioned by selecting the icon and clicking on the new desired anchor position. The drawing will be automatically re-centered on the new anchor point.

An alias is another name corresponding to the same component in the library. Components with similar pin-out and representation can then be represented by only one component, having several aliases (e.g. 7400 with alias 74LS00, 74HC00, 74LS37 ).

The use of aliases allows you to build complete libraries quickly. In addition these libraries, being much more compact, are easily loaded by KiCad.

To modify the list of aliases, you have to select the main editing window via the icon and select the alias folder.

You can thus add or remove the desired alias. The current alias cannot obviously be removed since it is edited.

To remove all aliases, you have firstly to select the root component. The first component in the alias list in the window of selection of the main toolbar.

The field editor is called via the icon .

There are four special fields (texts attached to the component), and configurable user fields

Special fields

To edit documentation information, it is necessary to call the main editing window of the component via the icon and to select the document folder.

Be sure to select the right alias, or the root component, because this documentation is the only characteristic which differs between aliases. The "Copy Doc" button allows you to copy the documentation information from the root component towards the currently edited alias.

You can easily compile a graphic symbols library file containing frequently used symbols. This can be used for the creation of components (triangles, the shape of AND, OR, Exclusive OR gates, etc.) for saving and subsequent re-use.

These files are stored by default in the library directory and have a .sym extension. The symbols are not gathered in libraries like the components because they are generally not so many.

Viewlib allows you to quickly examine the content of libraries. Viewlib is called by the tool or by the "place component" tool available from the right-hand side toolbar.

To examine the library content you need to select the wanted library from the list on the left-hand side. Available components will then appear in the second list which allow you to select a component.

The top tool bar in Viewlib is shown below.

The available commands are.

BOM files and netlist files can be converted from an Intermediate netlist file created by Eeschema.

This file uses XML syntax and is called the intermediate netlist. The intermediate netlist includes a large amount of data about your board and because of this, it can be used with post-processing to create a BOM or other reports.

Depending on the output (BOM or netlist), different subsets of the complete Intermediate Netlist file will be used in the post-processing.

By applying a post-processing filter to the Intermediate netlist file you can generate foreign netlist files as well as BOM files. Because this conversion is a text to text transformation, this post-processing filter can be written using Python, XSLT, or any other tool capable of taking XML as input.

XSLT itself is a an XML language very suitable for XML transformations. There is a free program called xsltproc that you can download and install. The xsltproc program can be used to read the Intermediate XML netlist input file, apply a style-sheet to transform the input, and save the results in an output file. Use of xsltproc requires a style-sheet file using XSLT conventions. The full conversion process is handled by Eeschema, after it is configured once to run xsltproc in a specific way.

The document that describes XSL Transformations (XSLT) is available here:

http://www.w3.org/TR/xslt

The command line format for python is something like:

python <script file name> <input filename> <output filename>

under Windows:

python *.exe f:/kicad/python/my_python_script.py "%I" "%O"

under Linux:

python /usr/local/kicad/python/my_python_script.py "%I" "%O"

Assuming python is installed on your PC.

This sample gives an idea of the netlist file format.

Refer to the page: http://xmlsoft.org/XSLT/xsltproc.html