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author | saurabhb17 | 2020-02-26 15:57:49 +0530 |
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committer | saurabhb17 | 2020-02-26 15:57:49 +0530 |
commit | aa35045840b78d3f48212db45da59a2e5c69b223 (patch) | |
tree | 6acee185a4dc19113fcbf0f9a3d6941085dedaf7 /pcbnew/scripting/examples | |
parent | 0db48f6533517ecebfd9f0693f89deca28408b76 (diff) | |
download | KiCad-eSim-aa35045840b78d3f48212db45da59a2e5c69b223.tar.gz KiCad-eSim-aa35045840b78d3f48212db45da59a2e5c69b223.tar.bz2 KiCad-eSim-aa35045840b78d3f48212db45da59a2e5c69b223.zip |
Added main execs
Diffstat (limited to 'pcbnew/scripting/examples')
-rwxr-xr-x | pcbnew/scripting/examples/createFPC40.py | 60 | ||||
-rwxr-xr-x | pcbnew/scripting/examples/createPcb.py | 48 | ||||
-rw-r--r-- | pcbnew/scripting/examples/hidePcbValuesShowReferences.py | 14 | ||||
-rwxr-xr-x | pcbnew/scripting/examples/listPcb.py | 66 | ||||
-rwxr-xr-x | pcbnew/scripting/examples/listPcbLibrary.py | 12 |
5 files changed, 200 insertions, 0 deletions
diff --git a/pcbnew/scripting/examples/createFPC40.py b/pcbnew/scripting/examples/createFPC40.py new file mode 100755 index 0000000..7c6568e --- /dev/null +++ b/pcbnew/scripting/examples/createFPC40.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python2.7 +from pcbnew import * + +size_025_160mm = wxSizeMM(0.25,1.6) +size_150_200mm = wxSizeMM(1.50,2.0) +pads = 40 + +# create a blank board +pcb = BOARD() + +pcb.m_NetClasses.GetDefault().SetClearance(FromMM(0.1)) + +# create a new module, it's parent is our previously created pcb +module = MODULE(pcb) +module.SetReference("FPC"+str(pads)) # give it a reference name +module.Reference().SetPos0(wxPointMM(-1,-1)) +pcb.Add(module) # add it to our pcb +m_pos = wxPointMM(50,50) +module.SetPosition(m_pos) + +# create a pad array and add it to the module + + +def smdRectPad(module,size,pos,name): + pad = D_PAD(module) + pad.SetSize(size) + pad.SetShape(PAD_RECT) + pad.SetAttribute(PAD_SMD) + pad.SetLayerMask(PAD_SMD_DEFAULT_LAYERS) + pad.SetPos0(pos) + pad.SetPadName(name) + return pad + +for n in range (0,pads): + pad = smdRectPad(module,size_025_160mm,wxPointMM(0.5*n,0),str(n+1)) + module.Add(pad) + + +pad_s0 = smdRectPad(module,size_150_200mm,wxPointMM(-1.6,1.3),"0") +pad_s1 = smdRectPad(module,size_150_200mm,wxPointMM((pads-1)*0.5+1.6,1.3),"0") +module.Add(pad_s0) +module.Add(pad_s1) + +e = EDGE_MODULE(module) +e.SetStart0(wxPointMM(-1,0)) +e.SetEnd0(wxPointMM(0,0)) +e.SetWidth(FromMM(0.2)) +e.SetLayer(EDGE_LAYER) +e.SetShape(S_SEGMENT) +module.Add(e) + +# save the PCB to disk +fpid = FPID("FPC"+str(pads)) #the name in library +module.SetFPID( fpid ) + +try: + FootprintLibCreate("fpc40.mod") +except: + pass # we try to create, but may be it exists already +FootprintSave("fpc40.mod",module) diff --git a/pcbnew/scripting/examples/createPcb.py b/pcbnew/scripting/examples/createPcb.py new file mode 100755 index 0000000..21c3803 --- /dev/null +++ b/pcbnew/scripting/examples/createPcb.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python2.7 +from pcbnew import * + +size_0_6mm = wxSizeMM(0.6,0.6) +size_1_0mm = wxSizeMM(1.0,1.0) + +# create a blank board +pcb = BOARD() + +pcb.m_NetClasses.GetDefault().SetClearance(FromMM(0.1)) + +# create a new module, it's parent is our previously created pcb +module = MODULE(pcb) +module.SetReference("M1") # give it a reference name +module.Reference().SetPos0(wxPointMM(-10,-10)) +pcb.Add(module) # add it to our pcb +m_pos = wxPointMM(50,50) +module.SetPosition(m_pos) + +# create a pad array and add it to the module +n = 1 +for y in range (0,10): + for x in range (0,10): + pad = D_PAD(module) + pad.SetDrillSize(size_0_6mm) + pad.SetSize(size_1_0mm) + pt = wxPointMM(1.27*x,1.27*y) + pad.SetPos0(pt); + #pad.SetPosition(pt) + pad.SetPadName(str(n)) + module.Add(pad) + n+=1 + + +# save the PCB to disk +pcb.Save("my2.kicad_pcb") +pcb.Save("my2.brd") + +pcb = LoadBoard("my2.kicad_pcb") + +print map( lambda x: x.GetReference() , list(pcb.GetModules())) + +for m in pcb.GetModules(): + for p in m.Pads(): + print p.GetPadName(), p.GetPosition(), p.GetOffset() + + +# pcb.GetDesignSettings() diff --git a/pcbnew/scripting/examples/hidePcbValuesShowReferences.py b/pcbnew/scripting/examples/hidePcbValuesShowReferences.py new file mode 100644 index 0000000..6b37842 --- /dev/null +++ b/pcbnew/scripting/examples/hidePcbValuesShowReferences.py @@ -0,0 +1,14 @@ +#!/usr/bin/env python +import sys +from pcbnew import * + +filename=sys.argv[1] + +pcb = LoadBoard(filename) + +for module in pcb.GetModules(): + print "* Module: %s"%module.GetReference() + module.Value().SetVisible(False) # set Value as Hidden + module.Reference().SetVisible(True) # set Reference as Visible + +pcb.Save("mod_"+filename) diff --git a/pcbnew/scripting/examples/listPcb.py b/pcbnew/scripting/examples/listPcb.py new file mode 100755 index 0000000..60ed093 --- /dev/null +++ b/pcbnew/scripting/examples/listPcb.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python +import sys +from pcbnew import * + +filename=sys.argv[1] + +pcb = LoadBoard(filename) + +ToUnits = ToMM +FromUnits = FromMM +#ToUnits=ToMils +#FromUnits=FromMils + +print "LISTING VIAS:" + +for item in pcb.GetTracks(): + if type(item) is VIA: + + pos = item.GetPosition() + drill = item.GetDrillValue() + width = item.GetWidth() + print " * Via: %s - %f/%f "%(ToUnits(pos),ToUnits(drill),ToUnits(width)) + + elif type(item) is TRACK: + + start = item.GetStart() + end = item.GetEnd() + width = item.GetWidth() + + print " * Track: %s to %s, width %f" % (ToUnits(start),ToUnits(end),ToUnits(width)) + + else: + print "Unknown type %s" % type(item) + +print "" +print "LIST DRAWINGS:" + +for item in pcb.GetDrawings(): + if type(item) is TEXTE_PCB: + print "* Text: '%s' at %s"%(item.GetText(), item.GetPosition()) + elif type(item) is DRAWSEGMENT: + print "* Drawing: %s"%item.GetShapeStr() # dir(item) + else: + print type(item) + +print "" +print "LIST MODULES:" + +for module in pcb.GetModules(): + print "* Module: %s at %s"%(module.GetReference(),ToUnits(module.GetPosition())) + +print "" +print "Ratsnest cnt:",len(pcb.GetFullRatsnest()) +print "track w cnt:",len(pcb.GetTrackWidthList()) +print "via s cnt:",len(pcb.GetViasDimensionsList()) + +print "" +print "LIST ZONES:", pcb.GetAreaCount() + +for idx in range(0, pcb.GetAreaCount()): + zone=pcb.GetArea(idx) + print "zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname() + +print "" +print "NetClasses:", pcb.GetNetClasses().GetCount(), + diff --git a/pcbnew/scripting/examples/listPcbLibrary.py b/pcbnew/scripting/examples/listPcbLibrary.py new file mode 100755 index 0000000..8262c17 --- /dev/null +++ b/pcbnew/scripting/examples/listPcbLibrary.py @@ -0,0 +1,12 @@ +#!/usr/bin/env python +from pcbnew import * + +lst = FootprintEnumerate("/usr/share/kicad/modules/sockets.mod") + +for name in lst: + m = FootprintLoad("/usr/share/kicad/modules/sockets.mod",name) + print name,"->",m.GetLibRef(), m.GetReference() + + for p in m.Pads(): + print "\t",p.GetPadName(),p.GetPosition(),p.GetPos0(), p.GetOffset() + |