EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:47:37 PM IST LIBS:power LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:special LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:analogSpice LIBS:analogXSpice LIBS:convergenceAidSpice LIBS:converterSpice LIBS:digitalSpice LIBS:digitalXSpice LIBS:linearSpice LIBS:measurementSpice LIBS:portSpice LIBS:sourcesSpice LIBS:RC-cache EELAYER 25 0 EELAYER END $Descr A4 11700 8267 encoding utf-8 Sheet 1 1 Title "" Date "15 may 2013" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr Wire Wire Line 4900 2050 5400 2050 Wire Wire Line 4900 2050 4900 2400 Connection ~ 5400 3050 Wire Wire Line 5400 2900 5400 3050 Wire Wire Line 5900 2050 6100 2050 Wire Wire Line 6100 3050 4900 3050 Wire Wire Line 6100 3050 6100 2600 Wire Wire Line 5550 3050 5550 3200 Connection ~ 5550 3050 Connection ~ 6100 2050 Wire Wire Line 4900 3050 4900 2600 Wire Wire Line 6100 2050 6100 2200 $Comp L CONN_2 P1 U 1 1 51868B92 P 4550 2500 F 0 "P1" V 4500 2500 40 0000 C CNN F 1 "CONN_2" V 4600 2500 40 0000 C CNN 1 4550 2500 -1 0 0 1 $EndComp $Comp L PWR_FLAG #FLG01 U 1 1 51863585 P 5400 2900 F 0 "#FLG01" H 5400 3170 30 0001 C CNN F 1 "PWR_FLAG" H 5400 3130 30 0000 C CNN 1 5400 2900 1 0 0 -1 $EndComp $Comp L GND #PWR02 U 1 1 5186344D P 5550 3200 F 0 "#PWR02" H 5550 3200 30 0001 C CNN F 1 "GND" H 5550 3130 30 0001 C CNN 1 5550 3200 1 0 0 -1 $EndComp $Comp L C C1 U 1 1 5186342E P 6100 2400 F 0 "C1" H 6150 2500 50 0000 L CNN F 1 "1u" H 6150 2300 50 0000 L CNN 1 6100 2400 1 0 0 -1 $EndComp $Comp L R R1 U 1 1 51863417 P 5650 2050 F 0 "R1" V 5730 2050 50 0000 C CNN F 1 "1k" V 5650 2050 50 0000 C CNN 1 5650 2050 0 1 1 0 $EndComp $EndSCHEMATC