From c632c1009c9e095135220c809d7c799841f160b3 Mon Sep 17 00:00:00 2001
From: Fahim
Date: Tue, 9 Sep 2014 16:11:17 +0530
Subject: Subject: Changing all content and name of directory and file to
 FreeEDA

Description: The content of file,name of directory and file has been
changed in the below format.

1. Oscad to FreeEDA
2. OSCAD to FreeEDA
3. oscad to freeeda
---
 OSCAD/Examples/bridgeRectifier/bridgeRectifier.sch | 203 ---------------------
 1 file changed, 203 deletions(-)
 delete mode 100644 OSCAD/Examples/bridgeRectifier/bridgeRectifier.sch

(limited to 'OSCAD/Examples/bridgeRectifier/bridgeRectifier.sch')

diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.sch b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.sch
deleted file mode 100644
index 8469355..0000000
--- a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.sch
+++ /dev/null
@@ -1,203 +0,0 @@
-EESchema Schematic File Version 2  date Monday 17 December 2012 12:01:58 PM IST
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:analogSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:linearSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:bridgeRectifier-cache
-EELAYER 25  0
-EELAYER END
-$Descr A4 11700 8267
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "9 dec 2012"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
-	6600 4000 4900 4000
-Wire Wire Line
-	6600 4000 6600 3550
-Connection ~ 6300 2600
-Wire Wire Line
-	6600 2950 6600 2600
-Wire Wire Line
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-Connection ~ 5150 3350
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-Connection ~ 5950 4000
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Connection ~ 5500 2600
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	5500 4000 5500 3800
-Wire Wire Line
-	6300 4000 6300 3500
-Connection ~ 5500 4000
-Wire Wire Line
-	4400 3750 4400 3950
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Connection ~ 5500 3350
-Wire Wire Line
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-Connection ~ 5650 4000
-Wire Wire Line
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-Wire Wire Line
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-$Comp
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-	0    1    1    0   
-$EndComp
-$Comp
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-P 4850 2450
-F 0 "U1" H 4700 2550 50  0000 C CNN
-F 1 "VPLOT8" H 5000 2550 50  0000 C CNN
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-	1    0    0    -1  
-$EndComp
-$Comp
-L PWR_FLAG #FLG01
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-F 0 "#FLG01" H 5950 3970 30  0001 C CNN
-F 1 "PWR_FLAG" H 5950 3930 30  0000 C CNN
-	1    5950 3700
-	1    0    0    -1  
-$EndComp
-$Comp
-L GND #PWR02
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-P 5650 4200
-F 0 "#PWR02" H 5650 4200 30  0001 C CNN
-F 1 "GND" H 5650 4130 30  0001 C CNN
-	1    5650 4200
-	1    0    0    -1  
-$EndComp
-$Comp
-L SINE V1
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-F 0 "V1" H 4200 3400 60  0000 C CNN
-F 1 "SINE" H 4200 3250 60  0000 C CNN
-F 2 "R1" H 4100 3300 60  0000 C CNN
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-$EndComp
-$Comp
-L R R1
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-F 1 "1000" V 6300 3250 50  0000 C CNN
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-$EndComp
-$Comp
-L DIODE D3
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-$Comp
-L DIODE D4
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-$Comp
-L DIODE D2
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-$EndComp
-$Comp
-L DIODE D1
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-$EndComp
-$EndSCHEMATC
-- 
cgit