diff options
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_3/example3.4')
10 files changed, 732 insertions, 0 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis new file mode 100644 index 0000000..73c8f09 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 4e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak new file mode 100644 index 0000000..1d8b498 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 04:09:27 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib new file mode 100644 index 0000000..f2704f3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:42:22 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak new file mode 100644 index 0000000..ca5b9de --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak @@ -0,0 +1,167 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 04:02:35 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example3.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 2550 5900 1050 +Wire Wire Line + 4400 4300 4400 3050 +Wire Wire Line + 5000 3800 5000 3250 +Wire Wire Line + 5000 2050 5000 1550 +Connection ~ 5000 5450 +Wire Wire Line + 4400 5450 5900 5450 +Wire Wire Line + 5900 1050 5000 1050 +Wire Wire Line + 4400 3050 4700 3050 +Wire Wire Line + 4400 5450 4400 5200 +Wire Wire Line + 5000 4950 5000 5750 +Connection ~ 5000 5600 +Connection ~ 5000 3450 +Wire Wire Line + 5000 2550 5000 2850 +Wire Wire Line + 5000 4300 5000 4450 +Wire Wire Line + 5900 5450 5900 3450 +$Comp +L IPLOT U2 +U 1 1 516BD643 +P 5000 4050 +F 0 "U2" H 4850 4150 50 0000 C CNN +F 1 "IPLOT" H 5150 4150 50 0000 C CNN + 1 5000 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516BD5F9 +P 5000 2300 +F 0 "U1" H 4850 2400 50 0000 C CNN +F 1 "IPLOT" H 5150 2400 50 0000 C CNN + 1 5000 2300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5166BF83 +P 5000 5600 +F 0 "#FLG01" H 5000 5695 30 0001 C CNN +F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN + 1 5000 5600 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166BF64 +P 5000 5750 +F 0 "#PWR02" H 5000 5750 30 0001 C CNN +F 1 "GND" H 5000 5680 30 0001 C CNN + 1 5000 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166BEE6 +P 4400 4750 +F 0 "v1" H 4200 4850 60 0000 C CNN +F 1 "4" H 4200 4700 60 0000 C CNN +F 2 "R1" H 4100 4750 60 0000 C CNN + 1 4400 4750 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5166BED7 +P 5900 3000 +F 0 "v2" H 5700 3100 60 0000 C CNN +F 1 "10V" H 5700 2950 60 0000 C CNN +F 2 "R1" H 5600 3000 60 0000 C CNN + 1 5900 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166BE96 +P 5000 4700 +F 0 "R2" V 5080 4700 50 0000 C CNN +F 1 "3300" V 5000 4700 50 0000 C CNN + 1 5000 4700 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166BE8E +P 5000 1300 +F 0 "R1" V 5080 1300 50 0000 C CNN +F 1 "4700" V 5000 1300 50 0000 C CNN + 1 5000 1300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166BE53 +P 4900 3050 +F 0 "Q1" H 4900 2900 50 0000 R CNN +F 1 "NPN" H 4900 3200 50 0000 R CNN + 1 4900 3050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir new file mode 100644 index 0000000..87e5f07 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 04:09:24 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 6 7 VPLOT8_1 +U2 7 3 IPLOT +U1 5 6 IPLOT +v1 2 0 4 +v2 4 0 10V +R2 3 0 3300 +R1 4 5 4700 +Q1 7 2 6 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt new file mode 100644 index 0000000..21ea9e6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 04:09:24 pm ist + +* Plotting option vplot8_1 +V_u2 7 3 0 +V_u1 5 6 0 +v1 2 0 4 +v2 4 0 10v +r2 3 0 3300 +r1 4 5 4700 +q1 6 2 7 npn + +.dc v1 0e-00 4e-00 5e-03 +.plot v(6) v(7) +.plot i(V_u2) +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out new file mode 100644 index 0000000..b00fc82 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out @@ -0,0 +1,21 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 04:09:24 pm ist + +* Plotting option vplot8_1 +V_u2 7 3 0 +V_u1 5 6 0 +v1 2 0 4 +v2 4 0 10v +r2 3 0 3300 +r1 4 5 4700 +q1 6 2 7 npn + +.dc v1 0e-00 4e-00 5e-03 + +* Control Statements +.control +run +plot v(6) v(7) +plot i(V_u2) +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro new file mode 100644 index 0000000..a38bf27 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro @@ -0,0 +1,84 @@ +update=Monday 15 April 2013 04:08:24 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj new file mode 100644 index 0000000..9978f31 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj @@ -0,0 +1 @@ +schematicFile example3.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch new file mode 100644 index 0000000..4138df7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch @@ -0,0 +1,186 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 04:09:27 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example3.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5000 2650 +$Comp +L VPLOT8_1 U3 +U 1 1 516BD8B9 +P 5300 2650 +F 0 "U3" H 5150 2750 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN + 1 5300 2650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516BD8AC +P 5300 3450 +F 0 "U3" H 5150 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN + 2 5300 3450 + 0 1 1 0 +$EndComp +Wire Wire Line + 5900 2550 5900 1050 +Wire Wire Line + 4400 4300 4400 3050 +Wire Wire Line + 5000 3800 5000 3250 +Wire Wire Line + 5000 2050 5000 1550 +Connection ~ 5000 5450 +Wire Wire Line + 4400 5450 5900 5450 +Wire Wire Line + 5900 1050 5000 1050 +Wire Wire Line + 4400 3050 4700 3050 +Wire Wire Line + 4400 5450 4400 5200 +Wire Wire Line + 5000 4950 5000 5750 +Connection ~ 5000 5600 +Connection ~ 5000 3450 +Wire Wire Line + 5000 2550 5000 2850 +Wire Wire Line + 5000 4300 5000 4450 +Wire Wire Line + 5900 5450 5900 3450 +$Comp +L IPLOT U2 +U 1 1 516BD643 +P 5000 4050 +F 0 "U2" H 4850 4150 50 0000 C CNN +F 1 "IPLOT" H 5150 4150 50 0000 C CNN + 1 5000 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516BD5F9 +P 5000 2300 +F 0 "U1" H 4850 2400 50 0000 C CNN +F 1 "IPLOT" H 5150 2400 50 0000 C CNN + 1 5000 2300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5166BF83 +P 5000 5600 +F 0 "#FLG01" H 5000 5695 30 0001 C CNN +F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN + 1 5000 5600 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166BF64 +P 5000 5750 +F 0 "#PWR02" H 5000 5750 30 0001 C CNN +F 1 "GND" H 5000 5680 30 0001 C CNN + 1 5000 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166BEE6 +P 4400 4750 +F 0 "v1" H 4200 4850 60 0000 C CNN +F 1 "4" H 4200 4700 60 0000 C CNN +F 2 "R1" H 4100 4750 60 0000 C CNN + 1 4400 4750 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5166BED7 +P 5900 3000 +F 0 "v2" H 5700 3100 60 0000 C CNN +F 1 "10V" H 5700 2950 60 0000 C CNN +F 2 "R1" H 5600 3000 60 0000 C CNN + 1 5900 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166BE96 +P 5000 4700 +F 0 "R2" V 5080 4700 50 0000 C CNN +F 1 "3300" V 5000 4700 50 0000 C CNN + 1 5000 4700 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166BE8E +P 5000 1300 +F 0 "R1" V 5080 1300 50 0000 C CNN +F 1 "4700" V 5000 1300 50 0000 C CNN + 1 5000 1300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166BE53 +P 4900 3050 +F 0 "Q1" H 4900 2900 50 0000 R CNN +F 1 "NPN" H 4900 3200 50 0000 R CNN + 1 4900 3050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC |