diff options
Diffstat (limited to 'OSCAD/Examples/nonInvertingAmplifier')
21 files changed, 1565 insertions, 0 deletions
diff --git a/OSCAD/Examples/nonInvertingAmplifier/analysis b/OSCAD/Examples/nonInvertingAmplifier/analysis new file mode 100644 index 0000000..888b3aa --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/analysis @@ -0,0 +1 @@ +.tran 100e-06 40e-03 0e-00 diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.bak b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.bak new file mode 100644 index 0000000..036ee3a --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:47:24 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.lib b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.lib new file mode 100644 index 0000000..8835104 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:47:58 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.bak b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.bak new file mode 100644 index 0000000..695fcbc --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.bak @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:47:24 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:nonInvertingAmplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4300 3300 +Wire Wire Line + 4300 3200 4300 3650 +Wire Wire Line + 5100 3300 5300 3300 +Wire Wire Line + 4600 3500 4600 3700 +Wire Wire Line + 5100 3500 5300 3500 +Connection ~ 6550 3400 +Wire Wire Line + 6300 3400 6850 3400 +Wire Wire Line + 6850 3100 6850 3650 +Connection ~ 6850 3400 +Connection ~ 4300 4650 +Wire Wire Line + 4300 4650 4600 4650 +Wire Wire Line + 4600 4650 4600 4400 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 6850 4150 6850 4400 +Wire Wire Line + 6050 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 3400 +Wire Wire Line + 5200 3500 5200 4050 +Wire Wire Line + 5200 4050 5550 4050 +Connection ~ 5200 3500 +Wire Wire Line + 4300 3300 4600 3300 +$Comp +L R R? +U 1 1 50D14DC5 +P 4850 3300 +F 0 "R?" V 4930 3300 50 0000 C CNN +F 1 "1000" V 4850 3300 50 0000 C CNN + 1 4850 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR01" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 4300 2900 +F 0 "U1" H 4150 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 4450 3000 50 0000 C CNN + 1 4300 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG02" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240CB +P 4600 3700 +F 0 "#PWR03" H 4600 3700 30 0001 C CNN +F 1 "GND" H 4600 3630 30 0001 C CNN + 1 4600 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR04" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 50824091 +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "SINE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4850 3500 +F 0 "R1" V 4930 3500 50 0000 C CNN +F 1 "1000" V 4850 3500 50 0000 C CNN + 1 4850 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir new file mode 100644 index 0000000..99dd1d0 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 19 December 2012 10:47:55 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R4 1 4 1000 +U1 4 3 VPLOT8_1 +X1 5 1 3 UA741 +v1 4 0 SINE +R3 3 0 10000 +R1 5 0 1000 +R2 3 5 2000 + +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.ckt b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.ckt new file mode 100644 index 0000000..1aac163 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 19 december 2012 10:47:55 am ist +.include ua741.sub + +r4 1 4 1000 +* Plotting option vplot8_1 +x1 5 1 3 ua741 +v1 4 0 sine(0 5 50 0 0) +r3 3 0 10000 +r1 5 0 1000 +r2 3 5 2000 + +.tran 100e-06 40e-03 0e-00 +.plot v(4) v(3) +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.out b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.out new file mode 100644 index 0000000..6417831 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 19 december 2012 10:47:55 am ist +.include ua741.sub + +r4 1 4 1000 +* Plotting option vplot8_1 +x1 5 1 3 ua741 +v1 4 0 sine(0 5 50 0 0) +r3 3 0 10000 +r1 5 0 1000 +r2 3 5 2000 + +.tran 100e-06 40e-03 0e-00 + +* Control Statements +.control +run +plot v(4) v(3) +.endc +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cmp b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cmp new file mode 100644 index 0000000..c3e04af --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cmp @@ -0,0 +1,38 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Saturday 20 October 2012 11:59:17 AM IST + +BeginCmp +TimeStamp = /50824062; +Reference = R1; +ValeurCmp = 1000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824045; +Reference = R2; +ValeurCmp = 2000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824073; +Reference = R3; +ValeurCmp = 10000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824091; +Reference = v1; +ValeurCmp = SINE; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /50823E96; +Reference = X1; +ValeurCmp = LM741; +IdModule = DIP-8__300; +EndCmp + +EndListe diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.net b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.net new file mode 100644 index 0000000..938591e --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.net @@ -0,0 +1,70 @@ +# EESchema Netlist Version 1.1 created Saturday 20 October 2012 12:03:26 PM IST +( + ( /50824595 $noname X1 UA741 {Lib=UA741} + ( 2 N-000004 ) + ( 3 GND ) + ( 6 N-000001 ) + ) + ( /50824091 R1 v1 SINE {Lib=SINE} + ( 1 N-000002 ) + ( 2 GND ) + ) + ( /50824073 $noname R3 10000 {Lib=R} + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /50824062 $noname R1 1000 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000002 ) + ) + ( /50824045 $noname R2 2000 {Lib=R} + ( 1 N-000001 ) + ( 2 N-000004 ) + ) +) +* +{ Allowed footprints by component: +$component X1 + DIP-8__300 +$endlist +$component v1 + 1_pin +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R2 1 + X1 6 + R3 1 +Net 2 "" "" + R1 2 + v1 1 +Net 3 "GND" "GND" + X1 3 + v1 2 + R3 2 +Net 4 "" "" + X1 2 + R1 1 + R2 2 +} +#End diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.pro b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.pro new file mode 100644 index 0000000..9f5d056 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:16:29 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.proj b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.proj new file mode 100644 index 0000000..c78c533 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.proj @@ -0,0 +1 @@ +schematicFile InvertingAmplifier.sch diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.sch b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.sch new file mode 100644 index 0000000..df340bb --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:47:58 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:nonInvertingAmplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4300 3300 +Wire Wire Line + 4300 3200 4300 3650 +Wire Wire Line + 5100 3300 5300 3300 +Wire Wire Line + 4600 3500 4600 3700 +Wire Wire Line + 5100 3500 5300 3500 +Connection ~ 6550 3400 +Wire Wire Line + 6300 3400 6850 3400 +Wire Wire Line + 6850 3100 6850 3650 +Connection ~ 6850 3400 +Connection ~ 4300 4650 +Wire Wire Line + 4300 4650 4600 4650 +Wire Wire Line + 4600 4650 4600 4400 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 6850 4150 6850 4400 +Wire Wire Line + 6050 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 3400 +Wire Wire Line + 5200 3500 5200 4050 +Wire Wire Line + 5200 4050 5550 4050 +Connection ~ 5200 3500 +Wire Wire Line + 4300 3300 4600 3300 +$Comp +L R R4 +U 1 1 50D14DC5 +P 4850 3300 +F 0 "R4" V 4930 3300 50 0000 C CNN +F 1 "1000" V 4850 3300 50 0000 C CNN + 1 4850 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR01" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 4300 2900 +F 0 "U1" H 4150 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 4450 3000 50 0000 C CNN + 1 4300 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG02" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240CB +P 4600 3700 +F 0 "#PWR03" H 4600 3700 30 0001 C CNN +F 1 "GND" H 4600 3630 30 0001 C CNN + 1 4600 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR04" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 50824091 +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "SINE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4850 3500 +F 0 "R1" V 4930 3500 50 0000 C CNN +F 1 "1000" V 4850 3500 50 0000 C CNN + 1 4850 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.bak b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.bak new file mode 100644 index 0000000..e2ece32 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.bak @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:17:01 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.lib b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.lib new file mode 100644 index 0000000..cbec3a5 --- /dev/null +++ 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L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.bak b/OSCAD/Examples/nonInvertingAmplifier/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.cir b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.ckt b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.out b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.pro b/OSCAD/Examples/nonInvertingAmplifier/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.sch b/OSCAD/Examples/nonInvertingAmplifier/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 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3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.sub b/OSCAD/Examples/nonInvertingAmplifier/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file |