diff options
Diffstat (limited to 'OSCAD/Examples/nodalExample_plot')
9 files changed, 577 insertions, 0 deletions
diff --git a/OSCAD/Examples/nodalExample_plot/analysis b/OSCAD/Examples/nodalExample_plot/analysis new file mode 100644 index 0000000..7dd51c6 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/analysis @@ -0,0 +1 @@ +.dc i1 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot-cache.lib b/OSCAD/Examples/nodalExample_plot/nodalExample_plot-cache.lib new file mode 100644 index 0000000..532ca7e --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 24 May 2013 02:15:51 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.bak b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.bak new file mode 100644 index 0000000..c19435c --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.bak @@ -0,0 +1,187 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 02:14:17 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:nodalExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6100 2850 6100 3250 +Connection ~ 5600 4000 +Wire Wire Line + 5600 3900 5600 4000 +Connection ~ 6100 4000 +Wire Wire Line + 6100 3750 6100 4000 +Wire Wire Line + 7850 3900 7850 4000 +Wire Wire Line + 7850 4000 4700 4000 +Wire Wire Line + 4700 4000 4700 3950 +Connection ~ 5250 3000 +Wire Wire Line + 5250 3300 5250 3000 +Wire Wire Line + 5850 3000 6350 3000 +Wire Wire Line + 4700 3050 4700 3000 +Wire Wire Line + 4700 3000 5350 3000 +Wire Wire Line + 6850 3000 7850 3000 +Wire Wire Line + 7100 3200 7100 3000 +Connection ~ 7100 3000 +Connection ~ 6100 3000 +Wire Wire Line + 7100 3700 7100 4000 +Connection ~ 7100 4000 +Wire Wire Line + 5250 3800 5250 4000 +Connection ~ 5250 4000 +Wire Wire Line + 5450 4100 5450 4000 +Connection ~ 5450 4000 +$Comp +L VPRINT1 U1 +U 1 1 506489B3 +P 6100 2550 +F 0 "U1" H 5950 2650 50 0000 C CNN +F 1 "VPRINT1" H 6250 2650 50 0000 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50641423 +P 5450 4100 +F 0 "#PWR01" H 5450 4100 30 0001 C CNN +F 1 "GND" H 5450 4030 30 0001 C CNN + 1 5450 4100 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 506413F9 +P 5600 3900 +F 0 "#FLG02" H 5600 4170 30 0001 C CNN +F 1 "PWR_FLAG" H 5600 4130 30 0000 C CNN + 1 5600 3900 + 1 0 0 -1 +$EndComp +$Comp +L DC i2 +U 1 1 50641279 +P 7850 3450 +F 0 "i2" H 7650 3550 60 0000 C CNN +F 1 "1" H 7650 3400 60 0000 C CNN +F 2 "R3" H 7550 3450 60 0000 C CNN + 1 7850 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50641261 +P 7100 3450 +F 0 "R5" V 7180 3450 50 0000 C CNN +F 1 "1" V 7100 3450 50 0000 C CNN + 1 7100 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50640DC3 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50640DAA +P 6600 3000 +F 0 "R4" V 6680 3000 50 0000 C CNN +F 1 "2" V 6600 3000 50 0000 C CNN + 1 6600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 50640DA8 +P 6100 3500 +F 0 "R3" V 6180 3500 50 0000 C CNN +F 1 "1" V 6100 3500 50 0000 C CNN + 1 6100 3500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50640DA0 +P 5250 3550 +F 0 "R1" V 5330 3550 50 0000 C CNN +F 1 "1" V 5250 3550 50 0000 C CNN + 1 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC i1 +U 1 1 5063F506 +P 4700 3500 +F 0 "i1" H 4500 3600 60 0000 C CNN +F 1 "1" H 4500 3450 60 0000 C CNN +F 2 "R3" H 4400 3500 60 0000 C CNN + 1 4700 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir new file mode 100644 index 0000000..f2dda85 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 24 May 2013 02:18:18 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 4 VPLOT8_1 +i2 1 0 1 +R5 1 0 1 +R2 4 3 1 +R4 1 4 2 +R3 4 0 1 +R1 3 0 1 +i1 3 0 1 + +.end diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.ckt b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.ckt new file mode 100644 index 0000000..219dd07 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:18:18 pm ist + +* Plotting option vplot8_1 +i2 1 0 1 +r5 1 0 1 +r2 4 3 1 +r4 1 4 2 +r3 4 0 1 +r1 3 0 1 +i1 3 0 1 + +.dc i1 0e-00 10e-00 1e-00 +.plot v(4) +.end diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.out b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.out new file mode 100644 index 0000000..a7809b6 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:18:18 pm ist + +* Plotting option vplot8_1 +i2 1 0 1 +r5 1 0 1 +r2 4 3 1 +r4 1 4 2 +r3 4 0 1 +r1 3 0 1 +i1 3 0 1 + +.dc i1 0e-00 10e-00 1e-00 + +* Control Statements +.control +run +plot v(4) +.endc +.end diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.pro b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.pro new file mode 100644 index 0000000..fb3c608 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.pro @@ -0,0 +1,74 @@ +update=Friday 24 May 2013 02:15:07 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.proj b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.proj new file mode 100644 index 0000000..0f13a25 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.proj @@ -0,0 +1 @@ +schematicFile nodalExample_plot.sch diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.sch b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.sch new file mode 100644 index 0000000..4ac9466 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.sch @@ -0,0 +1,186 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 02:15:51 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 1 1 519F28A8 +P 6100 2550 +F 0 "U1" H 5950 2650 50 0000 C CNN +F 1 "VPLOT8_1" H 6250 2650 50 0000 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2850 6100 3250 +Connection ~ 5600 4000 +Wire Wire Line + 5600 3900 5600 4000 +Connection ~ 6100 4000 +Wire Wire Line + 6100 3750 6100 4000 +Wire Wire Line + 7850 3900 7850 4000 +Wire Wire Line + 7850 4000 4700 4000 +Wire Wire Line + 4700 4000 4700 3950 +Connection ~ 5250 3000 +Wire Wire Line + 5250 3300 5250 3000 +Wire Wire Line + 5850 3000 6350 3000 +Wire Wire Line + 4700 3050 4700 3000 +Wire Wire Line + 4700 3000 5350 3000 +Wire Wire Line + 6850 3000 7850 3000 +Wire Wire Line + 7100 3200 7100 3000 +Connection ~ 7100 3000 +Connection ~ 6100 3000 +Wire Wire Line + 7100 3700 7100 4000 +Connection ~ 7100 4000 +Wire Wire Line + 5250 3800 5250 4000 +Connection ~ 5250 4000 +Wire Wire Line + 5450 4100 5450 4000 +Connection ~ 5450 4000 +$Comp +L GND #PWR1 +U 1 1 50641423 +P 5450 4100 +F 0 "#PWR1" H 5450 4100 30 0001 C CNN +F 1 "GND" H 5450 4030 30 0001 C CNN + 1 5450 4100 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 506413F9 +P 5600 3900 +F 0 "#FLG1" H 5600 4170 30 0001 C CNN +F 1 "PWR_FLAG" H 5600 4130 30 0000 C CNN + 1 5600 3900 + 1 0 0 -1 +$EndComp +$Comp +L DC i2 +U 1 1 50641279 +P 7850 3450 +F 0 "i2" H 7650 3550 60 0000 C CNN +F 1 "1" H 7650 3400 60 0000 C CNN +F 2 "R3" H 7550 3450 60 0000 C CNN + 1 7850 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50641261 +P 7100 3450 +F 0 "R5" V 7180 3450 50 0000 C CNN +F 1 "1" V 7100 3450 50 0000 C CNN + 1 7100 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50640DC3 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50640DAA +P 6600 3000 +F 0 "R4" V 6680 3000 50 0000 C CNN +F 1 "2" V 6600 3000 50 0000 C CNN + 1 6600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 50640DA8 +P 6100 3500 +F 0 "R3" V 6180 3500 50 0000 C CNN +F 1 "1" V 6100 3500 50 0000 C CNN + 1 6100 3500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50640DA0 +P 5250 3550 +F 0 "R1" V 5330 3550 50 0000 C CNN +F 1 "1" V 5250 3550 50 0000 C CNN + 1 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC i1 +U 1 1 5063F506 +P 4700 3500 +F 0 "i1" H 4500 3600 60 0000 C CNN +F 1 "1" H 4500 3450 60 0000 C CNN +F 2 "R3" H 4400 3500 60 0000 C CNN + 1 4700 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC |