13 files changed, 1228 insertions, 0 deletions
diff --git a/OSCAD/Examples/mixMode/analysis b/OSCAD/Examples/mixMode/analysis
new file mode 100644
index 0000000..bf5e632
--- /dev/null
+++ b/OSCAD/Examples/mixMode/analysis
@@ -0,0 +1 @@
+.tran  10e-09 1e-06 0e-00
diff --git a/OSCAD/Examples/mixMode/mixMode-cache.bak b/OSCAD/Examples/mixMode/mixMode-cache.bak
new file mode 100644
index 0000000..9e5fbb3
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode-cache.bak
@@ -0,0 +1,122 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:40:24 AM IST
+#encoding utf-8
+#
+# 74HCT04
+#
+DEF 74HCT04 U 0 30 Y Y 6 F N
+F0 "U" 150 100 40 H V C CNN
+F1 "74HCT04" 200 -100 40 H V C CNN
+ALIAS 74HC14 74HC04 74LS14
+DRAW
+P 4 0 0 0  -150 150  -150 -150  150 0  -150 150 N
+X GND 7 -50 -100 0 U 30 20 0 0 W N
+X VCC 14 -50 100 0 D 30 20 0 0 W N
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+X ~ 2 450 0 300 L 60 60 1 1 O I
+X ~ 3 -450 0 300 R 60 60 2 1 I
+X ~ 4 450 0 300 L 60 60 2 1 O I
+X ~ 5 -450 0 300 R 60 60 3 1 I
+X ~ 6 450 0 300 L 60 60 3 1 O I
+X ~ 8 450 0 300 L 60 60 4 1 O I
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+X ~ 10 450 0 300 L 60 60 5 1 O I
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+X ~ 12 450 0 300 L 60 60 6 1 O I
+X ~ 13 -450 0 300 R 60 60 6 1 I
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+X ~ 2 450 0 300 L 60 60 1 2 O
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+X ~ 4 450 0 300 L 60 60 2 2 O
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+X ~ 10 450 0 300 L 60 60 5 2 O
+X ~ 11 -450 0 300 R 60 60 5 2 I I
+X ~ 12 450 0 300 L 60 60 6 2 O
+X ~ 13 -450 0 300 R 60 60 6 2 I I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
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+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
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+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/mixMode/mixMode-cache.lib b/OSCAD/Examples/mixMode/mixMode-cache.lib
new file mode 100644
index 0000000..ab75e8e
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode-cache.lib
@@ -0,0 +1,122 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:41:04 AM IST
+#encoding utf-8
+#
+# 74HCT04
+#
+DEF 74HCT04 U 0 30 Y Y 6 F N
+F0 "U" 150 100 40 H V C CNN
+F1 "74HCT04" 200 -100 40 H V C CNN
+ALIAS 74HC14 74HC04 74LS14
+DRAW
+P 4 0 0 0  -150 150  -150 -150  150 0  -150 150 N
+X GND 7 -50 -100 0 U 30 20 0 0 W N
+X VCC 14 -50 100 0 D 30 20 0 0 W N
+X ~ 1 -450 0 300 R 60 60 1 1 I
+X ~ 2 450 0 300 L 60 60 1 1 O I
+X ~ 3 -450 0 300 R 60 60 2 1 I
+X ~ 4 450 0 300 L 60 60 2 1 O I
+X ~ 5 -450 0 300 R 60 60 3 1 I
+X ~ 6 450 0 300 L 60 60 3 1 O I
+X ~ 8 450 0 300 L 60 60 4 1 O I
+X ~ 9 -450 0 300 R 60 60 4 1 I
+X ~ 10 450 0 300 L 60 60 5 1 O I
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+X ~ 12 450 0 300 L 60 60 6 2 O
+X ~ 13 -450 0 300 R 60 60 6 2 I I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
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+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
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+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/mixMode/mixMode.bak b/OSCAD/Examples/mixMode/mixMode.bak
new file mode 100644
index 0000000..1f9d2dd
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.bak
@@ -0,0 +1,165 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:40:24 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:mixMode-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "17 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
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+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L VPLOT8_1 U1
+U 2 1 50CEB729
+P 7150 2900
+F 0 "U1" H 7000 3000 50  0000 C CNN
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+	2    7150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 50CEB722
+P 5600 2950
+F 0 "U1" H 5450 3050 50  0000 C CNN
+F 1 "VPLOT8_1" H 5750 3050 50  0000 C CNN
+	1    5600 2950
+	1    0    0    -1  
+$EndComp
+Connection ~ 5750 4400
+Wire Wire Line
+	5750 4400 5750 4300
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+	6850 3350 7350 3350
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+	6350 3000 6350 3250
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+	5350 4400 5350 4150
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+$Comp
+L PWR_FLAG #FLG01
+U 1 1 50653022
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+F 0 "#FLG01" H 6350 3270 30  0001 C CNN
+F 1 "PWR_FLAG" H 6350 3230 30  0000 C CNN
+	1    6350 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 50652FB6
+P 7350 3750
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+	1    7350 3750
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+$EndComp
+$Comp
+L 74HC04 U2
+U 1 1 505FDE5C
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+$EndComp
+$Comp
+L PWR_FLAG #FLG02
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+$Comp
+L R R1
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+$EndComp
+$Comp
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+$EndComp
+$Comp
+L PULSE v1
+U 1 1 505C9ECF
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diff --git a/OSCAD/Examples/mixMode/mixMode.brd b/OSCAD/Examples/mixMode/mixMode.brd
new file mode 100644
index 0000000..a68ce3f
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.brd
@@ -0,0 +1,400 @@
+PCBNEW-BOARD Version 1 date Friday 28 September 2012 10:42:25 AM IST
+
+# Created by Pcbnew(2011-05-25)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
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+Links 7
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+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "28 sep 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
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+Layer[15] Front signal
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+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
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+$EQUIPOT
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+$EQUIPOT
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+$NCLASS
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+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$SHAPE3D
+Na "device/douille_4mm(red).wrl"
+Sc 1.800000 1.800000 1.800000
+Of 0.590000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  2PIN_6mm
+$MODULE 1pin
+Po 50000 44000 0 15 00200000 5065317A ~~
+Li 1pin
+Cd module 1 pin (ou trou mecanique de percage)
+Kw DEV
+Sc 5065317A
+AR /505FD8A0
+Op 0 0 0
+T0 0 -1200 400 400 0 100 N V 21 N "U1"
+T1 0 1100 400 400 0 100 N I 21 N "ADC"
+DC 0 0 0 -900 150 21
+$PAD
+Sh "1" C 1600 1600 0 0 0
+Dr 1200 0 0
+At STD N 00E0FFFF
+Ne 5 "N-000006"
+Po 0 0
+$EndPAD
+$EndMODULE  1pin
+$MODULE 1pin
+Po 59500 43500 0 15 00200000 5065317C ~~
+Li 1pin
+Cd module 1 pin (ou trou mecanique de percage)
+Kw DEV
+Sc 5065317C
+AR /505FDC21
+Op 0 0 0
+T0 0 -1200 400 400 0 100 N V 21 N "U3"
+T1 0 1100 400 400 0 100 N I 21 N "DAC"
+DC 0 0 0 -900 150 21
+$PAD
+Sh "1" C 1600 1600 0 0 0
+Dr 1200 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000004"
+Po 0 0
+$EndPAD
+$EndMODULE  1pin
+$MODULE 1pin
+Po 41500 45500 0 15 00200000 5065317E ~~
+Li 1pin
+Cd module 1 pin (ou trou mecanique de percage)
+Kw DEV
+Sc 5065317E
+AR /5061678B
+Op 0 0 0
+T0 0 -1200 400 400 0 100 N V 21 N "U4"
+T1 0 1100 400 400 0 100 N I 21 N "VPLOT1"
+DC 0 0 0 -900 150 21
+$PAD
+Sh "1" C 1600 1600 0 0 0
+Dr 1200 0 0
+At STD N 00E0FFFF
+Ne 5 "N-000006"
+Po 0 0
+$EndPAD
+$EndMODULE  1pin
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/OSCAD/Examples/mixMode/mixMode.cir b/OSCAD/Examples/mixMode/mixMode.cir
new file mode 100644
index 0000000..3db9950
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.cir
@@ -0,0 +1,13 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:41:09 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  3 4 VPLOT8_1		
+R2  4 0 1000		
+U2  3 4 0 2 74HC04		
+R1  3 0 1000		
+v1  3 0 PULSE		
+
+.end
diff --git a/OSCAD/Examples/mixMode/mixMode.cir.ckt b/OSCAD/Examples/mixMode/mixMode.cir.ckt
new file mode 100644
index 0000000..590cf66
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.cir.ckt
@@ -0,0 +1,17 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:41:09 am ist
+
+* Plotting option vplot8_1
+r2  4 0 1000
+* 74hc04
+r1  3 0 1000
+v1  3 0 pulse(0 5 0 1e-8 1e-8 0.25e-6 0.5e-6)
+a1 [3] [3_in]  u2adc
+a2 3_in 4_out u2
+a3 [4_out] [4]  u2dac
+.model u2 d_inverter
+.model u2adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u2dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-09 1e-06 0e-00
+.plot v(3) v(4) 
+.end
diff --git a/OSCAD/Examples/mixMode/mixMode.cir.out b/OSCAD/Examples/mixMode/mixMode.cir.out
new file mode 100644
index 0000000..27f8a8c
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.cir.out
@@ -0,0 +1,22 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:41:09 am ist
+
+* Plotting option vplot8_1
+r2  4 0 1000
+* 74hc04
+r1  3 0 1000
+v1  3 0 pulse(0 5 0 1e-8 1e-8 0.25e-6 0.5e-6)
+a1 [3] [3_in]  u2adc
+a2 3_in 4_out u2
+a3 [4_out] [4]  u2dac
+.model u2 d_inverter
+.model u2adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u2dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-09 1e-06 0e-00
+
+* Control Statements 
+.control
+run
+plot v(3) v(4) 
+.endc
+.end
diff --git a/OSCAD/Examples/mixMode/mixMode.cmp b/OSCAD/Examples/mixMode/mixMode.cmp
new file mode 100644
index 0000000..8a56a56
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.cmp
@@ -0,0 +1,52 @@
+Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Friday 28 September 2012 10:41:02 AM IST
+
+BeginCmp
+TimeStamp = /505C9F25;
+Reference = R1;
+ValeurCmp = 1000;
+IdModule  = R1;
+EndCmp
+
+BeginCmp
+TimeStamp = /50652FB6;
+Reference = R2;
+ValeurCmp = R;
+IdModule  = R1;
+EndCmp
+
+BeginCmp
+TimeStamp = /505FD8A0;
+Reference = U1;
+ValeurCmp = ADC;
+IdModule  = 1pin;
+EndCmp
+
+BeginCmp
+TimeStamp = /505FDE5C;
+Reference = U2;
+ValeurCmp = 74HC04;
+IdModule  = DIP-14__300_ELL;
+EndCmp
+
+BeginCmp
+TimeStamp = /505FDC21;
+Reference = U3;
+ValeurCmp = DAC;
+IdModule  = 1pin;
+EndCmp
+
+BeginCmp
+TimeStamp = /5061678B;
+Reference = U4;
+ValeurCmp = VPLOT1;
+IdModule  = 1pin;
+EndCmp
+
+BeginCmp
+TimeStamp = /505C9ECF;
+Reference = v1;
+ValeurCmp = PULSE;
+IdModule  = 2PIN_6mm;
+EndCmp
+
+EndListe
diff --git a/OSCAD/Examples/mixMode/mixMode.net b/OSCAD/Examples/mixMode/mixMode.net
new file mode 100644
index 0000000..0175d5c
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.net
@@ -0,0 +1,77 @@
+# EESchema Netlist Version 1.1 created  Friday 28 September 2012 12:26:55 PM IST
+(
+ ( /50653344 $noname  U5 VPLOT1 {Lib=VPLOT1}
+  (    1 N-000005 )
+ )
+ ( /50652FB6 $noname  R2 1000 {Lib=R}
+  (    1 N-000005 )
+  (    2 GND )
+ )
+ ( /5061678B $noname  U4 VPLOT1 {Lib=VPLOT1}
+  (    1 N-000001 )
+ )
+ ( /505FDE5C $noname  U2 74HC04 {Lib=74HC04}
+  (    1 N-000006 )
+  (    2 N-000004 )
+  (    7 GND )
+  (   14 VCC )
+ )
+ ( /505FDC21 $noname  U3 DAC {Lib=DAC}
+  (    1 N-000004 )
+  (    2 N-000005 )
+ )
+ ( /505FD8A0 $noname  U1 ADC {Lib=ADC}
+  (    1 N-000001 )
+  (    2 N-000006 )
+ )
+ ( /505C9F25 $noname  R1 1000 {Lib=R}
+  (    1 N-000001 )
+  (    2 GND )
+ )
+ ( /505C9ECF $noname  v1 PULSE {Lib=PULSE}
+  (    1 N-000001 )
+  (    2 GND )
+ )
+)
+*
+{ Allowed footprints by component:
+$component R2
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component v1
+ 1_pin
+$endlist
+$endfootprintlist
+}
+{ Pin List by Nets
+Net 1 "" ""
+ U1 1
+ v1 1
+ R1 1
+ U4 1
+Net 2 "GND" "GND"
+ v1 2
+ R2 2
+ R1 2
+ U2 7
+Net 4 "" ""
+ U2 2
+ U3 1
+Net 5 "" ""
+ U3 2
+ U5 1
+ R2 1
+Net 6 "" ""
+ U1 2
+ U2 1
+}
+#End
diff --git a/OSCAD/Examples/mixMode/mixMode.pro b/OSCAD/Examples/mixMode/mixMode.pro
new file mode 100644
index 0000000..353cc12
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.pro
@@ -0,0 +1,71 @@
+update=Tuesday 30 October 2012 11:12:31 AM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/OSCAD/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=converterSpice
+LibName33=digitalSpice
+LibName34=linearSpice
+LibName35=measurementSpice
+LibName36=portSpice
+LibName37=sourcesSpice
diff --git a/OSCAD/Examples/mixMode/mixMode.proj b/OSCAD/Examples/mixMode/mixMode.proj
new file mode 100644
index 0000000..465ba2d
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.proj
@@ -0,0 +1 @@
+schematicFile mixMode.sch
diff --git a/OSCAD/Examples/mixMode/mixMode.sch b/OSCAD/Examples/mixMode/mixMode.sch
new file mode 100644
index 0000000..493dc4e
--- /dev/null
+++ b/OSCAD/Examples/mixMode/mixMode.sch
@@ -0,0 +1,165 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:41:04 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:mixMode-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "17 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L VPLOT8_1 U1
+U 2 1 50CEB729
+P 7150 2900
+F 0 "U1" H 7000 3000 50  0000 C CNN
+F 1 "VPLOT8_1" H 7300 3000 50  0000 C CNN
+	2    7150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 50CEB722
+P 5600 2950
+F 0 "U1" H 5450 3050 50  0000 C CNN
+F 1 "VPLOT8_1" H 5750 3050 50  0000 C CNN
+	1    5600 2950
+	1    0    0    -1  
+$EndComp
+Connection ~ 5750 4400
+Wire Wire Line
+	5750 4400 5750 4300
+Connection ~ 7150 3350
+Wire Wire Line
+	7150 3350 7150 3200
+Wire Wire Line
+	5950 3350 4800 3350
+Wire Wire Line
+	7350 4000 7350 4400
+Wire Wire Line
+	7350 4400 4800 4400
+Connection ~ 5600 3350
+Wire Wire Line
+	5600 3250 5600 3350
+Wire Wire Line
+	5350 3350 5350 3650
+Wire Wire Line
+	4800 4550 4800 4250
+Connection ~ 4800 4400
+Connection ~ 5350 3350
+Wire Wire Line
+	6850 3350 7350 3350
+Wire Wire Line
+	7350 3350 7350 3500
+Wire Wire Line
+	6350 3000 6350 3250
+Wire Wire Line
+	5350 4400 5350 4150
+Connection ~ 5350 4400
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 50653022
+P 6350 3000
+F 0 "#FLG01" H 6350 3270 30  0001 C CNN
+F 1 "PWR_FLAG" H 6350 3230 30  0000 C CNN
+	1    6350 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 50652FB6
+P 7350 3750
+F 0 "R2" V 7430 3750 50  0000 C CNN
+F 1 "1000" V 7350 3750 50  0000 C CNN
+	1    7350 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC04 U2
+U 1 1 505FDE5C
+P 6400 3350
+F 0 "U2" H 6550 3450 40  0000 C CNN
+F 1 "74HC04" H 6600 3250 40  0000 C CNN
+	1    6400 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 505CA177
+P 5750 4300
+F 0 "#FLG02" H 5750 4570 30  0001 C CNN
+F 1 "PWR_FLAG" H 5750 4530 30  0000 C CNN
+	1    5750 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 505C9F25
+P 5350 3900
+F 0 "R1" V 5430 3900 50  0000 C CNN
+F 1 "1000" V 5350 3900 50  0000 C CNN
+	1    5350 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 505C9EE8
+P 4800 4550
+F 0 "#PWR03" H 4800 4550 30  0001 C CNN
+F 1 "GND" H 4800 4480 30  0001 C CNN
+	1    4800 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v1
+U 1 1 505C9ECF
+P 4800 3800
+F 0 "v1" H 4600 3900 60  0000 C CNN
+F 1 "PULSE" H 4600 3750 60  0000 C CNN
+	1    4800 3800
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC