diff options
Diffstat (limited to 'OSCAD/Examples/frequencyDivider')
19 files changed, 2533 insertions, 0 deletions
diff --git a/OSCAD/Examples/frequencyDivider/analysis b/OSCAD/Examples/frequencyDivider/analysis new file mode 100644 index 0000000..1f89c69 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/analysis @@ -0,0 +1 @@ +.tran 50e-09 5e-06 0e-00 diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider-cache.bak b/OSCAD/Examples/frequencyDivider/frequencyDivider-cache.bak new file mode 100644 index 0000000..1434b97 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider-cache.bak @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 09:00:05 AM IST +#encoding utf-8 +# +# 74LS109 +# +DEF 74LS109 U 0 30 Y Y 2 F N +F0 "U" 0 100 60 H V C CNN +F1 "74LS109" 0 -100 60 H V C CNN +DRAW +S -350 -400 350 400 0 0 0 N +X GND 8 -250 -400 0 U 60 60 0 0 W N +X VCC 16 -250 400 0 U 60 60 0 0 W N +X Cd 1 0 -700 300 U 60 60 1 1 I I +X J 2 -650 250 300 R 60 60 1 1 I +X K 3 -650 -250 300 R 60 60 1 1 I I +X Cp 4 -650 0 300 R 60 60 1 1 I C +X Sd 5 0 700 300 D 60 60 1 1 I I +X Q 6 650 250 300 L 60 60 1 1 O +X ~Q 7 650 -250 300 L 60 60 1 1 O I +X ~Q 9 750 -250 400 L 60 60 2 1 I I +X Q 10 750 250 400 L 60 60 2 1 I +X Sd 11 0 800 400 D 60 60 2 1 I I +X Cp 12 -750 0 400 R 60 60 2 1 I C +X K 13 -750 -250 400 R 60 60 2 1 I I +X J 14 -750 250 400 R 60 60 2 1 I +X Cd 15 0 -800 400 U 60 60 2 1 I I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CP +# +DEF CP C 0 10 N N 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "CP" 50 -100 50 H V L CNN +ALIAS CAPAPOL +$FPLIST + CP* + SM* +$ENDFPLIST +DRAW +P 4 0 1 8 -100 50 -100 -50 100 -50 100 50 N +P 4 0 1 0 -50 50 -50 -20 50 -20 50 50 F +X ~ 1 0 200 150 D 40 40 1 1 P +X ~ 2 0 -200 150 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# IC +# +DEF IC U? 0 0 Y N 1 F N +F0 "U?" 0 270 30 H V C CNN +F1 "IC" 0 230 30 H V C CNN +DRAW +X ic 1 0 0 0 U 20 20 0 0 P +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 100 70 H V C CNN +F1 "LM555N" 0 -100 70 H V C CNN +DRAW +X GND 1 0 -400 0 U 60 60 0 0 W N +X VCC 8 0 400 0 D 60 60 0 0 W N +S -400 -400 400 400 0 1 0 N +X TR 2 -700 200 300 R 60 60 1 1 I +X Q 3 700 200 300 L 60 60 1 1 O +X R 4 -700 -300 300 R 60 60 1 1 I I +X CV 5 -700 -50 300 R 60 60 1 1 I +X THR 6 700 -200 300 L 60 60 1 1 I +X DIS 7 700 0 300 L 60 60 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider-cache.lib b/OSCAD/Examples/frequencyDivider/frequencyDivider-cache.lib new file mode 100644 index 0000000..497025f --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider-cache.lib @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 10:57:17 AM IST +#encoding utf-8 +# +# 74LS109 +# +DEF 74LS109 U 0 30 Y Y 2 F N +F0 "U" 0 100 60 H V C CNN +F1 "74LS109" 0 -100 60 H V C CNN +DRAW +S -350 -400 350 400 0 0 0 N +X GND 8 -250 -400 0 U 60 60 0 0 W N +X VCC 16 -250 400 0 U 60 60 0 0 W N +X Cd 1 0 -700 300 U 60 60 1 1 I I +X J 2 -650 250 300 R 60 60 1 1 I +X K 3 -650 -250 300 R 60 60 1 1 I I +X Cp 4 -650 0 300 R 60 60 1 1 I C +X Sd 5 0 700 300 D 60 60 1 1 I I +X Q 6 650 250 300 L 60 60 1 1 O +X ~Q 7 650 -250 300 L 60 60 1 1 O I +X ~Q 9 750 -250 400 L 60 60 2 1 I I +X Q 10 750 250 400 L 60 60 2 1 I +X Sd 11 0 800 400 D 60 60 2 1 I I +X Cp 12 -750 0 400 R 60 60 2 1 I C +X K 13 -750 -250 400 R 60 60 2 1 I I +X J 14 -750 250 400 R 60 60 2 1 I +X Cd 15 0 -800 400 U 60 60 2 1 I I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CP +# +DEF CP C 0 10 N N 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "CP" 50 -100 50 H V L CNN +ALIAS CAPAPOL +$FPLIST + CP* + SM* +$ENDFPLIST +DRAW +P 4 0 1 8 -100 50 -100 -50 100 -50 100 50 N +P 4 0 1 0 -50 50 -50 -20 50 -20 50 50 F +X ~ 1 0 200 150 D 40 40 1 1 P +X ~ 2 0 -200 150 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# IC +# +DEF IC U? 0 0 Y N 1 F N +F0 "U?" 0 270 30 H V C CNN +F1 "IC" 0 230 30 H V C CNN +DRAW +X ic 1 0 0 0 U 20 20 0 0 P +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 100 70 H V C CNN +F1 "LM555N" 0 -100 70 H V C CNN +DRAW +X GND 1 0 -400 0 U 60 60 0 0 W N +X VCC 8 0 400 0 D 60 60 0 0 W N +S -400 -400 400 400 0 1 0 N +X TR 2 -700 200 300 R 60 60 1 1 I +X Q 3 700 200 300 L 60 60 1 1 O +X R 4 -700 -300 300 R 60 60 1 1 I I +X CV 5 -700 -50 300 R 60 60 1 1 I +X THR 6 700 -200 300 L 60 60 1 1 I +X DIS 7 700 0 300 L 60 60 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.bak b/OSCAD/Examples/frequencyDivider/frequencyDivider.bak new file mode 100644 index 0000000..48303d3 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.bak @@ -0,0 +1,280 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 09:00:05 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:convergenceAidSpice +LIBS:frequencyDivider-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 2 1 50CE9193 +P 7700 3000 +F 0 "U1" H 7550 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 7850 3100 50 0000 C CNN + 2 7700 3000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CE918C +P 6300 3000 +F 0 "U1" H 6150 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 6450 3100 50 0000 C CNN + 1 6300 3000 + 1 0 0 -1 +$EndComp +Connection ~ 4650 4100 +Wire Wire Line + 4650 4100 4650 4050 +Connection ~ 6600 2850 +Wire Wire Line + 7050 4600 6600 4600 +Wire Wire Line + 6600 4600 6600 2850 +Connection ~ 6300 3350 +Wire Wire Line + 6300 3300 6300 3900 +Connection ~ 6100 3350 +Wire Wire Line + 6300 3900 6400 3900 +Wire Wire Line + 6300 3350 5900 3350 +Wire Wire Line + 6400 2850 6400 3650 +Wire Wire Line + 6100 4550 6100 4100 +Wire Wire Line + 3650 4700 4850 4700 +Wire Wire Line + 3650 4700 3650 4050 +Wire Wire Line + 3650 2700 4450 2700 +Wire Wire Line + 3650 2700 3650 3150 +Wire Wire Line + 5900 3550 6000 3550 +Wire Wire Line + 6000 3550 6000 3000 +Wire Wire Line + 6000 3000 4150 3000 +Wire Wire Line + 4150 3000 4150 3400 +Connection ~ 4000 3400 +Wire Wire Line + 4150 3400 4000 3400 +Wire Wire Line + 4000 4150 4000 4000 +Connection ~ 4200 4100 +Wire Wire Line + 4500 3350 4200 3350 +Wire Wire Line + 4200 3350 4200 4100 +Wire Wire Line + 4300 4400 5200 4400 +Connection ~ 5700 4550 +Wire Wire Line + 5700 4550 5700 4300 +Connection ~ 4850 4550 +Wire Wire Line + 4850 4700 4850 4550 +Connection ~ 5200 4550 +Connection ~ 5200 4400 +Wire Wire Line + 5200 4550 5200 3950 +Wire Wire Line + 5900 3750 5900 4100 +Wire Wire Line + 4450 2700 4450 2850 +Connection ~ 4450 2850 +Connection ~ 5200 2850 +Wire Wire Line + 5900 4550 5900 4800 +Connection ~ 5900 4550 +Connection ~ 4450 2700 +Wire Wire Line + 4500 3850 4400 3850 +Wire Wire Line + 4400 3850 4400 2850 +Connection ~ 4400 2850 +Wire Wire Line + 4300 4000 4300 3600 +Wire Wire Line + 4300 3600 4500 3600 +Wire Wire Line + 4000 3350 4000 3500 +Wire Wire Line + 5900 4100 4000 4100 +Connection ~ 4000 4100 +Wire Wire Line + 6100 3350 6100 3600 +Wire Wire Line + 4000 4550 6400 4550 +Wire Wire Line + 6400 4550 6400 4150 +Connection ~ 6100 4550 +Wire Wire Line + 5200 2850 5200 3150 +Wire Wire Line + 4000 2850 7050 2850 +Wire Wire Line + 7050 2850 7050 3200 +Connection ~ 6400 2850 +Wire Wire Line + 7700 3650 7700 3300 +$Comp +L IC U2 +U 1 1 50CE8F30 +P 4650 4050 +F 0 "U2" H 4650 4320 30 0000 C CNN +F 1 "IC" H 4650 4280 30 0000 C CNN + 1 4650 4050 + 1 0 0 -1 +$EndComp +NoConn ~ 7700 4150 +$Comp +L 74LS109 U3 +U 1 1 50C1C9BA +P 7050 3900 +F 0 "U3" H 7050 4000 60 0000 C CNN +F 1 "74LS109" H 7050 3800 60 0000 C CNN + 1 7050 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50A93D02 +P 5900 4800 +F 0 "#PWR01" H 5900 4800 30 0001 C CNN +F 1 "GND" H 5900 4730 30 0001 C CNN + 1 5900 4800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 50A93CC0 +P 5700 4300 +F 0 "#FLG02" H 5700 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5700 4530 30 0000 C CNN + 1 5700 4300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 50A93CB7 +P 5200 2850 +F 0 "#FLG03" H 5200 3120 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 3080 30 0000 C CNN + 1 5200 2850 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 50A93C56 +P 3650 3600 +F 0 "v1" H 3450 3700 60 0000 C CNN +F 1 "5" H 3450 3550 60 0000 C CNN +F 2 "R1" H 3350 3600 60 0000 C CNN + 1 3650 3600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A93BFE +P 6100 3850 +F 0 "R3" V 6180 3850 50 0000 C CNN +F 1 "1000" V 6100 3850 50 0000 C CNN + 1 6100 3850 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 50A93ACA +P 4300 4200 +F 0 "C2" H 4350 4300 50 0000 L CNN +F 1 "0.01e-6" H 4350 4100 50 0000 L CNN + 1 4300 4200 + 1 0 0 -1 +$EndComp +$Comp +L CP C1 +U 1 1 50A93893 +P 4000 4350 +F 0 "C1" H 4050 4450 50 0000 L CNN +F 1 "100e-12" H 4050 4250 50 0000 L CNN + 1 4000 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A93858 +P 4000 3750 +F 0 "R2" V 4080 3750 50 0000 C CNN +F 1 "10000" V 4000 3750 50 0000 C CNN + 1 4000 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A93852 +P 4000 3100 +F 0 "R1" V 4080 3100 50 0000 C CNN +F 1 "1000" V 4000 3100 50 0000 C CNN + 1 4000 3100 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X1 +U 1 1 50A937B9 +P 5200 3550 +F 0 "X1" H 5200 3650 70 0000 C CNN +F 1 "LM555N" H 5200 3450 70 0000 C CNN + 1 5200 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.cir b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir new file mode 100644 index 0000000..5989740 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:14 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 2 VPLOT8_1 +U2 5 IC +U3 3 3 0 6 3 2 1 0 3 74LS109 +v1 3 0 5 +R3 6 0 1000 +C2 7 0 0.01e-6 +C1 5 0 100e-12 +R2 8 5 10000 +R1 3 8 1000 +X1 0 5 6 3 7 5 8 3 LM555N + +.end diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.ckt b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.ckt new file mode 100644 index 0000000..293ca2e --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.ckt @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:14 am ist +.include lm555n.sub + +* Plotting option vplot8_1 +.ic v(5)=0 +* 74ls109 +v1 3 0 5 +r3 6 0 1000 +c2 7 0 0.01e-6 +c1 5 0 100e-12 +r2 8 5 10000 +r1 3 8 1000 +x1 0 5 6 3 7 5 8 3 lm555n +a1 [3 0 6 3 3] [3_in 0_in 6_in 3_in 3_in] u3adc +a2 3_in ~0_in 6_in ~3_in ~3_in 2_out 1_out u3 +a3 [2_out 1_out] [2 1] u3dac +.model u3 d_jkff +.model u3adc adc_bridge(in_low=0.8 in_high=2.0) +.model u3dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 50e-09 5e-06 0e-00 +.plot v(6) v(2) +.end diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.out b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.out new file mode 100644 index 0000000..97db1fc --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.out @@ -0,0 +1,28 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:14 am ist +.include lm555n.sub + +* Plotting option vplot8_1 +.ic v(5)=0 +* 74ls109 +v1 3 0 5 +r3 6 0 1000 +c2 7 0 0.01e-6 +c1 5 0 100e-12 +r2 8 5 10000 +r1 3 8 1000 +x1 0 5 6 3 7 5 8 3 lm555n +a1 [3 0 6 3 3] [3_in 0_in 6_in 3_in 3_in] u3adc +a2 3_in ~0_in 6_in ~3_in ~3_in 2_out 1_out u3 +a3 [2_out 1_out] [2 1] u3dac +.model u3 d_jkff +.model u3adc adc_bridge(in_low=0.8 in_high=2.0) +.model u3dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 50e-09 5e-06 0e-00 + +* Control Statements +.control +run +plot v(6) v(2) +.endc +.end diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.pro b/OSCAD/Examples/frequencyDivider/frequencyDivider.pro new file mode 100644 index 0000000..a4e7e69 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.pro @@ -0,0 +1,71 @@ +update=Monday 17 December 2012 08:48:56 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=special +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=analogSpice +LibName31=converterSpice +LibName32=digitalSpice +LibName33=linearSpice +LibName34=measurementSpice +LibName35=portSpice +LibName36=sourcesSpice +LibName37=convergenceAidSpice diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.proj b/OSCAD/Examples/frequencyDivider/frequencyDivider.proj new file mode 100644 index 0000000..0a193f0 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.proj @@ -0,0 +1 @@ +schematicFile IC555AstableMultivibrator.sch diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.sch b/OSCAD/Examples/frequencyDivider/frequencyDivider.sch new file mode 100644 index 0000000..3f76d3a --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.sch @@ -0,0 +1,280 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:57:17 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:convergenceAidSpice +LIBS:frequencyDivider-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 2 1 50CE9193 +P 7700 3000 +F 0 "U1" H 7550 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 7850 3100 50 0000 C CNN + 2 7700 3000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CE918C +P 6300 3000 +F 0 "U1" H 6150 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 6450 3100 50 0000 C CNN + 1 6300 3000 + 1 0 0 -1 +$EndComp +Connection ~ 4650 4100 +Wire Wire Line + 4650 4100 4650 4050 +Connection ~ 6600 2850 +Wire Wire Line + 7050 4600 6600 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+ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/lm555n-cache.lib b/OSCAD/Examples/frequencyDivider/lm555n-cache.lib new file mode 100644 index 0000000..1f8bfd1 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n-cache.lib @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 10:57:52 AM IST +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter" 100 100 40 H V C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +# D_SRLatch +# +DEF D_SRLatch U 0 40 Y Y 1 F N +F0 "U" -200 250 60 H V C CNN +F1 "D_SRLatch" 0 100 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X S 1 -600 150 300 R 50 50 1 1 I +X R 2 -600 -150 300 R 50 50 1 1 I +X Enable 3 -600 0 300 R 50 50 1 1 I +X Set 4 150 -500 300 U 50 50 1 1 I +X Reset 5 -150 -500 300 U 50 50 1 1 I +X Q 6 600 150 300 L 50 50 1 1 O +X ~Q 7 600 -150 300 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# DAC8 +# +DEF DAC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "DAC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 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O +X in 7 -300 0 150 R 25 25 7 1 I +X out 15 300 0 150 L 25 25 7 1 O +X in 8 -300 0 150 R 25 25 8 1 I +X out 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/lm555n.bak b/OSCAD/Examples/frequencyDivider/lm555n.bak new file mode 100644 index 0000000..92d1f7a --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.bak @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:48:46 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/lm555n.cir b/OSCAD/Examples/frequencyDivider/lm555n.cir new file mode 100644 index 0000000..9483a64 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.cir @@ -0,0 +1,25 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 21 D_INVERTER +U6 1 4 5 21 21 8 10 D_SRLATCH +E2 18 0 23 14 10000 +U4 19 20 11 12 LIMIT8 +U3 8 10 7 9 DAC8 +U2 11 12 6 4 1 5 ADC8 +U1 22 14 7 6 15 16 3 13 PORT +R8 9 2 1500 +Q1 22 2 3 QNOM +R7 18 20 25 +R6 17 19 25 +E1 17 0 16 15 10000 +R4 16 15 2E6 +R5 23 14 2E6 +R3 23 22 5000 +R2 15 23 5000 +R1 13 15 5000 + +.end diff --git a/OSCAD/Examples/frequencyDivider/lm555n.cir.ckt b/OSCAD/Examples/frequencyDivider/lm555n.cir.ckt new file mode 100644 index 0000000..90f04a3 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.cir.ckt @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/OSCAD/Examples/frequencyDivider/lm555n.cir.out b/OSCAD/Examples/frequencyDivider/lm555n.cir.out new file mode 100644 index 0000000..90f04a3 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.cir.out @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/OSCAD/Examples/frequencyDivider/lm555n.pro b/OSCAD/Examples/frequencyDivider/lm555n.pro new file mode 100644 index 0000000..09fa54e --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.pro @@ -0,0 +1,73 @@ +update=Monday 19 November 2012 04:56:38 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=analogXSpice +LibName33=converterSpice +LibName34=digitalSpice +LibName35=linearSpice +LibName36=measurementSpice +LibName37=portSpice +LibName38=sourcesSpice +LibName39=digitalXSpice diff --git a/OSCAD/Examples/frequencyDivider/lm555n.sch b/OSCAD/Examples/frequencyDivider/lm555n.sch new file mode 100644 index 0000000..fabbb66 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:57:52 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/lm555n.sub b/OSCAD/Examples/frequencyDivider/lm555n.sub new file mode 100644 index 0000000..254c530 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.sub @@ -0,0 +1,37 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.ends lm555n
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