1 files changed, 136 insertions, 0 deletions
diff --git a/OSCAD/Examples/RC/RC.bak b/OSCAD/Examples/RC/RC.bak
new file mode 100644
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+EESchema Schematic File Version 2  date Friday 24 May 2013 02:53:57 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:RC-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "24 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
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+Connection ~ 5900 2650
+$Comp
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+F 2 "R1" H 4350 3100 60  0000 C CNN
+	1    4650 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 5400 3550
+Wire Wire Line
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+Wire Wire Line
+	5900 3550 4650 3550
+Wire Wire Line
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+Wire Wire Line
+	5900 2650 5900 2900
+$Comp
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+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG1
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+F 1 "PWR_FLAG" H 5400 3780 30  0000 C CNN
+	1    5400 3550
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+$EndComp
+$Comp
+L GND #PWR1
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+F 1 "GND" H 5400 3730 30  0001 C CNN
+	1    5400 3800
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+$EndComp
+$Comp
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+$EndComp
+$Comp
+L R R1
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+$EndComp
+$Comp
+L C C1
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+$EndComp
+$EndSCHEMATC