11 files changed, 1072 insertions, 0 deletions

diff --git a/OSCAD/Examples/FlipFlops/FlipFlops-cache.bak b/OSCAD/Examples/FlipFlops/FlipFlops-cache.bak
new file mode 100644
index 0000000..71dbe1a
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops-cache.bak
@@ -0,0 +1,140 @@
+EESchema-LIBRARY Version 2.3  Date: Sunday 09 December 2012 04:03:52 PM IST
+#encoding utf-8
+#
+# 74LS74
+#
+DEF 74LS74 U 0 40 Y Y 2 F N
+F0 "U" 150 300 60 H V C CNN
+F1 "74LS74" 300 -295 60 H V C CNN
+ALIAS 74HC74
+DRAW
+X GND 7 -200 -250 0 U 30 30 0 0 W N
+X VCC 14 -200 250 0 D 30 30 0 0 W N
+S -300 250 300 -250 0 1 0 N
+X Cd 1 0 -550 300 U 60 60 1 1 I I
+X D 2 -600 200 300 R 60 60 1 1 I
+X Cp 3 -600 0 300 R 60 60 1 1 I C
+X Sd 4 0 550 300 D 60 60 1 1 I I
+X Q 5 600 200 300 L 60 60 1 1 O
+X ~Q 6 600 -200 300 L 60 60 1 1 O I
+X ~Q 8 600 -200 300 L 60 60 2 1 O I
+X Q 9 600 200 300 L 60 60 2 1 O
+X Sd 10 0 550 300 D 60 60 2 1 I I
+X Cp 11 -600 0 300 R 60 60 2 1 I C
+X D 12 -600 200 300 R 60 60 2 1 I
+X Cd 13 0 -550 300 U 60 60 2 1 I I
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pwl
+#
+DEF pwl v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pwl" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50
+A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50
+A -75 -700 750 919 880 0 1 0 N -100 50 -50 50
+A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50
+A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot1
+#
+DEF vplot1 U 0 40 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops-cache.lib b/OSCAD/Examples/FlipFlops/FlipFlops-cache.lib
new file mode 100644
index 0000000..dc46d4f
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3  Date: Sunday 09 December 2012 04:06:09 PM IST
+#encoding utf-8
+#
+# 74LS74
+#
+DEF 74LS74 U 0 40 Y Y 2 F N
+F0 "U" 150 300 60 H V C CNN
+F1 "74LS74" 300 -295 60 H V C CNN
+ALIAS 74HC74
+DRAW
+X GND 7 -200 -250 0 U 30 30 0 0 W N
+X VCC 14 -200 250 0 D 30 30 0 0 W N
+S -300 250 300 -250 0 1 0 N
+X Cd 1 0 -550 300 U 60 60 1 1 I I
+X D 2 -600 200 300 R 60 60 1 1 I
+X Cp 3 -600 0 300 R 60 60 1 1 I C
+X Sd 4 0 550 300 D 60 60 1 1 I I
+X Q 5 600 200 300 L 60 60 1 1 O
+X ~Q 6 600 -200 300 L 60 60 1 1 O I
+X ~Q 8 600 -200 300 L 60 60 2 1 O I
+X Q 9 600 200 300 L 60 60 2 1 O
+X Sd 10 0 550 300 D 60 60 2 1 I I
+X Cp 11 -600 0 300 R 60 60 2 1 I C
+X D 12 -600 200 300 R 60 60 2 1 I
+X Cd 13 0 -550 300 U 60 60 2 1 I I
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pwl
+#
+DEF pwl v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pwl" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50
+A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50
+A -75 -700 750 919 880 0 1 0 N -100 50 -50 50
+A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50
+A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.bak b/OSCAD/Examples/FlipFlops/FlipFlops.bak
new file mode 100644
index 0000000..e821e8b
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.bak
@@ -0,0 +1,303 @@
+EESchema Schematic File Version 2  date Sunday 09 December 2012 04:03:52 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:FlipFlops-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "9 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 2800 4400
+Wire Wire Line
+	2800 4400 2800 4050
+Wire Wire Line
+	6000 2900 6000 3400
+Wire Wire Line
+	3950 5200 3950 5450
+Wire Wire Line
+	3950 5450 4500 5450
+Wire Wire Line
+	2150 3200 4000 3200
+Connection ~ 6000 3400
+Connection ~ 2350 5300
+Wire Wire Line
+	2350 5300 2350 5150
+Connection ~ 6950 4550
+Wire Wire Line
+	5100 4550 5100 4150
+Connection ~ 9150 4550
+Wire Wire Line
+	5700 3400 6350 3400
+Connection ~ 5100 2050
+Wire Wire Line
+	6950 3050 6950 2050
+Wire Wire Line
+	4000 3200 4000 3400
+Wire Wire Line
+	4000 3400 4500 3400
+Connection ~ 2500 4400
+Connection ~ 2500 4100
+Wire Wire Line
+	2500 4250 2500 3950
+Wire Wire Line
+	2500 3200 2500 3450
+Wire Wire Line
+	2500 2950 2150 2950
+Wire Wire Line
+	2500 3050 2500 2750
+Connection ~ 2500 2950
+Wire Wire Line
+	2500 4100 2150 4100
+Wire Wire Line
+	2500 4400 2500 4550
+Wire Wire Line
+	2500 5450 2500 5050
+Connection ~ 2500 5300
+Connection ~ 2500 3200
+Wire Wire Line
+	4500 3600 4000 3600
+Wire Wire Line
+	4000 3600 4000 4400
+Wire Wire Line
+	5100 2050 5100 3050
+Wire Wire Line
+	6100 3600 6100 4400
+Wire Wire Line
+	6100 3600 6350 3600
+Connection ~ 4000 4400
+Wire Wire Line
+	6950 4150 6950 4550
+Wire Wire Line
+	4900 3200 4900 3350
+Wire Wire Line
+	2500 2050 2500 2250
+Connection ~ 2500 2050
+Wire Wire Line
+	6950 2050 2150 2050
+Wire Wire Line
+	6100 4400 2150 4400
+Wire Wire Line
+	3950 4700 3950 4550
+Wire Wire Line
+	3950 4550 6950 4550
+Connection ~ 4500 4550
+Connection ~ 5100 4550
+Wire Wire Line
+	3950 5300 2150 5300
+Connection ~ 3950 5300
+Wire Wire Line
+	2800 3200 2800 2850
+Connection ~ 2800 3200
+NoConn ~ 7550 3800
+NoConn ~ 7550 3400
+NoConn ~ 5700 3800
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 507305F9
+P 2350 5150
+F 0 "#FLG01" H 2350 5420 30  0001 C CNN
+F 1 "PWR_FLAG" H 2350 5380 30  0000 C CNN
+	1    2350 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 507305F3
+P 4900 3200
+F 0 "#FLG02" H 4900 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 4900 3430 30  0000 C CNN
+	1    4900 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT1 U4
+U 1 1 50730491
+P 2800 3750
+F 0 "U4" H 2650 3850 50  0000 C CNN
+F 1 "VPLOT1" H 2950 3850 50  0000 C CNN
+	1    2800 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT1 U3
+U 1 1 50730484
+P 2800 2550
+F 0 "U3" H 2650 2650 50  0000 C CNN
+F 1 "VPLOT1" H 2950 2650 50  0000 C CNN
+	1    2800 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT1 U2
+U 1 1 50730477
+P 6000 2600
+F 0 "U2" H 5850 2700 50  0000 C CNN
+F 1 "VPLOT1" H 6150 2700 50  0000 C CNN
+	1    6000 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 5073005A
+P 2500 5450
+F 0 "#PWR03" H 2500 5450 30  0001 C CNN
+F 1 "GND" H 2500 5380 30  0001 C CNN
+	1    2500 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 5073006C
+P 2500 3050
+F 0 "#PWR04" H 2500 3050 30  0001 C CNN
+F 1 "GND" H 2500 2980 30  0001 C CNN
+	1    2500 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR06
+U 1 1 50730061
+P 2500 4250
+F 0 "#PWR06" H 2500 4250 30  0001 C CNN
+F 1 "GND" H 2500 4180 30  0001 C CNN
+	1    2500 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 5072FFF1
+P 2500 3700
+F 0 "R2" V 2580 3700 50  0000 C CNN
+F 1 "1000" V 2500 3700 50  0000 C CNN
+	1    2500 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWL v2
+U 1 1 5072FFEC
+P 2150 3650
+F 0 "v2" H 1950 3750 60  0000 C CNN
+F 1 "PWL" H 1950 3600 60  0000 C CNN
+F 2 "R1" H 1850 3650 60  0000 C CNN
+	1    2150 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 5072FFBC
+P 2500 4800
+F 0 "R3" V 2580 4800 50  0000 C CNN
+F 1 "1000" V 2500 4800 50  0000 C CNN
+	1    2500 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v3
+U 1 1 5072FFAC
+P 2150 4850
+F 0 "v3" H 1950 4950 60  0000 C CNN
+F 1 "PULSE" H 1950 4800 60  0000 C CNN
+F 2 "R1" H 1850 4850 60  0000 C CNN
+	1    2150 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R4
+U 1 1 5072FF51
+P 3950 4950
+F 0 "R4" V 4030 4950 50  0000 C CNN
+F 1 "1000" V 3950 4950 50  0000 C CNN
+	1    3950 4950
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v4
+U 1 1 5072FF43
+P 4500 5000
+F 0 "v4" H 4300 5100 60  0000 C CNN
+F 1 "5" H 4300 4950 60  0000 C CNN
+F 2 "R1" H 4200 5000 60  0000 C CNN
+	1    4500 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v1
+U 1 1 5072FEED
+P 2150 2500
+F 0 "v1" H 1950 2600 60  0000 C CNN
+F 1 "5" H 1950 2450 60  0000 C CNN
+F 2 "R1" H 1850 2500 60  0000 C CNN
+	1    2150 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 5072FE04
+P 2500 2500
+F 0 "R1" V 2580 2500 50  0000 C CNN
+F 1 "1000" V 2500 2500 50  0000 C CNN
+	1    2500 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC74 U1
+U 2 1 50727541
+P 6950 3600
+F 0 "U1" H 7100 3900 60  0000 C CNN
+F 1 "74HC74" H 7250 3305 60  0000 C CNN
+	2    6950 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC74 U1
+U 1 1 507274E2
+P 5100 3600
+F 0 "U1" H 5250 3900 60  0000 C CNN
+F 1 "74HC74" H 5400 3305 60  0000 C CNN
+	1    5100 3600
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir b/OSCAD/Examples/FlipFlops/FlipFlops.cir
new file mode 100644
index 0000000..92a4982
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir
@@ -0,0 +1,18 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sunday 09 December 2012 04:06:26 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2  6 2 10 VPLOT8_1		
+R2  2 0 1000		
+v2  2 0 PWL		
+R3  6 0 1000		
+v3  6 0 PULSE		
+R4  1 0 1000		
+v4  1 0 5		
+v1  11 0 5		
+R1  11 0 1000		
+U1  1 2 6 11 10 3 0 5 4 11 6 10 1 7 74HC74		
+
+.end
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir.ckt b/OSCAD/Examples/FlipFlops/FlipFlops.cir.ckt
new file mode 100644
index 0000000..5f457bc
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir.ckt
@@ -0,0 +1,25 @@
+* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 04:06:26 pm ist
+
+* Plotting option vplot8_1
+r2  2 0 1000
+v2  2 0 pwl(0 0 2.6 0 2.60000000001 5 3 5 )
+r3  6 0 1000
+v3  6 0 pulse(0 5 0 0 0 0.5 1)
+r4  1 0 1000
+v4  1 0 5
+v1  11 0 5
+r1  11 0 1000
+* 74hc74
+a1 [2 6 11 1] [2_in 6_in 11_in 1_in] u1adc
+a2 2_in 6_in ~11_in ~1_in 10_out 3_out u1
+a3 [10_out 3_out] [10 3]  u1dac
+a4 [10 6 11 1] [10_in 6_in 11_in 1_in] u1adc
+a5 10_in 6_in ~11_in ~1_in 4_out 5_out u1
+a6 [4_out 5_out] [4 5]  u1dac
+.model u1 d_dff
+.model u1adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-03 4e-00 0e-00
+.plot v(6) v(2) v(10) 
+.end
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir.out b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out
new file mode 100644
index 0000000..9410f5b
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out
@@ -0,0 +1,30 @@
+* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 04:06:26 pm ist
+
+* Plotting option vplot8_1
+r2  2 0 1000
+v2  2 0 pwl(0 0 2.6 0 2.60000000001 5 3 5 )
+r3  6 0 1000
+v3  6 0 pulse(0 5 0 0 0 0.5 1)
+r4  1 0 1000
+v4  1 0 5
+v1  11 0 5
+r1  11 0 1000
+* 74hc74
+a1 [2 6 11 1] [2_in 6_in 11_in 1_in] u1adc
+a2 2_in 6_in ~11_in ~1_in 10_out 3_out u1
+a3 [10_out 3_out] [10 3]  u1dac
+a4 [10 6 11 1] [10_in 6_in 11_in 1_in] u1adc
+a5 10_in 6_in ~11_in ~1_in 4_out 5_out u1
+a6 [4_out 5_out] [4 5]  u1dac
+.model u1 d_dff
+.model u1adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-03 4e-00 0e-00
+
+* Control Statements 
+.control
+run
+plot v(6) v(2) v(10) 
+.endc
+.end
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir.out1 b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out1
new file mode 100644
index 0000000..c855d5e
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out1
@@ -0,0 +1,34 @@
+* eeschema netlist version 1.1 (spice format) creation date: tuesday 30 october 2012 07:12:51 pm ist
+
+* Plotting option vplot1
+* Plotting option vplot1
+* Plotting option vplot1
+r2  1 0 1000
+v2  1 0 pwl(0 0 2.6 0 2.6000000000001 5 3 5 )
+r3  4 0 1000
+v3  4 0 pulse(0 5 0 0 0 0.5 1)
+r4  9 0 1000
+v4  9 0 dc 5
+v1  10 0 dc 5
+r1  10 0 1000
+* 74hc74
+a1 [1 4 10 9] [1_in 4_in 10_in 9_in] u1adc
+a2 1_in 4_in ~10_in ~9_in 2_out 3_out u1
+a3 [2_out 3_out] [2 3]  u1dac
+a4 [2 4 10 9] [2_in 4_in 10_in 9_in] u1adc
+a5 2_in 4_in ~10_in ~9_in 6_out 7_out u1
+a6 [6_out 7_out] [6 7] dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+.model u1 d_dff
+.model u1adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-03 4e-00 0e-00
+
+* Control Statements 
+.control
+run
+plot v(4)
+plot v(1)
+plot v(2)
+.endc
+.end
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.pro b/OSCAD/Examples/FlipFlops/FlipFlops.pro
new file mode 100644
index 0000000..529955f
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.pro
@@ -0,0 +1,70 @@
+update=Monday 22 October 2012 05:17:18 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/OSCAD/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=cmos4000
+LibName8=adc-dac
+LibName9=memory
+LibName10=xilinx
+LibName11=special
+LibName12=microcontrollers
+LibName13=dsp
+LibName14=microchip
+LibName15=analog_switches
+LibName16=motorola
+LibName17=texas
+LibName18=intel
+LibName19=audio
+LibName20=interface
+LibName21=digital-audio
+LibName22=philips
+LibName23=display
+LibName24=cypress
+LibName25=siliconi
+LibName26=opto
+LibName27=atmel
+LibName28=contrib
+LibName29=valves
+LibName30=analogSpice
+LibName31=converterSpice
+LibName32=digitalSpice
+LibName33=linearSpice
+LibName34=measurementSpice
+LibName35=portSpice
+LibName36=sourcesSpice
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.proj b/OSCAD/Examples/FlipFlops/FlipFlops.proj
new file mode 100644
index 0000000..cc7b7c9
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.proj
@@ -0,0 +1 @@
+schematicFile FlipFlops.sch
diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.sch b/OSCAD/Examples/FlipFlops/FlipFlops.sch
new file mode 100644
index 0000000..d8fbb5e
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/FlipFlops.sch
@@ -0,0 +1,303 @@
+EESchema Schematic File Version 2  date Sunday 09 December 2012 04:06:09 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:FlipFlops-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "9 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L VPLOT8_1 U2
+U 3 1 50C4695B
+P 6000 2600
+F 0 "U2" H 5850 2700 50  0000 C CNN
+F 1 "VPLOT8_1" H 6150 2700 50  0000 C CNN
+	3    6000 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 2 1 50C46950
+P 2800 2550
+F 0 "U2" H 2650 2650 50  0000 C CNN
+F 1 "VPLOT8_1" H 2950 2650 50  0000 C CNN
+	2    2800 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 1 1 50C46944
+P 2800 3750
+F 0 "U2" H 2650 3850 50  0000 C CNN
+F 1 "VPLOT8_1" H 2950 3850 50  0000 C CNN
+	1    2800 3750
+	1    0    0    -1  
+$EndComp
+Connection ~ 2800 4400
+Wire Wire Line
+	2800 4400 2800 4050
+Wire Wire Line
+	6000 2900 6000 3400
+Wire Wire Line
+	3950 5200 3950 5450
+Wire Wire Line
+	3950 5450 4500 5450
+Wire Wire Line
+	2150 3200 4000 3200
+Connection ~ 6000 3400
+Connection ~ 2350 5300
+Wire Wire Line
+	2350 5300 2350 5150
+Connection ~ 6950 4550
+Wire Wire Line
+	5100 4550 5100 4150
+Connection ~ 9150 4550
+Wire Wire Line
+	5700 3400 6350 3400
+Connection ~ 5100 2050
+Wire Wire Line
+	6950 3050 6950 2050
+Wire Wire Line
+	4000 3200 4000 3400
+Wire Wire Line
+	4000 3400 4500 3400
+Connection ~ 2500 4400
+Connection ~ 2500 4100
+Wire Wire Line
+	2500 4250 2500 3950
+Wire Wire Line
+	2500 3200 2500 3450
+Wire Wire Line
+	2500 2950 2150 2950
+Wire Wire Line
+	2500 3050 2500 2750
+Connection ~ 2500 2950
+Wire Wire Line
+	2500 4100 2150 4100
+Wire Wire Line
+	2500 4400 2500 4550
+Wire Wire Line
+	2500 5450 2500 5050
+Connection ~ 2500 5300
+Connection ~ 2500 3200
+Wire Wire Line
+	4500 3600 4000 3600
+Wire Wire Line
+	4000 3600 4000 4400
+Wire Wire Line
+	5100 2050 5100 3050
+Wire Wire Line
+	6100 3600 6100 4400
+Wire Wire Line
+	6100 3600 6350 3600
+Connection ~ 4000 4400
+Wire Wire Line
+	6950 4150 6950 4550
+Wire Wire Line
+	4900 3200 4900 3350
+Wire Wire Line
+	2500 2050 2500 2250
+Connection ~ 2500 2050
+Wire Wire Line
+	6950 2050 2150 2050
+Wire Wire Line
+	6100 4400 2150 4400
+Wire Wire Line
+	3950 4700 3950 4550
+Wire Wire Line
+	3950 4550 6950 4550
+Connection ~ 4500 4550
+Connection ~ 5100 4550
+Wire Wire Line
+	3950 5300 2150 5300
+Connection ~ 3950 5300
+Wire Wire Line
+	2800 3200 2800 2850
+Connection ~ 2800 3200
+NoConn ~ 7550 3800
+NoConn ~ 7550 3400
+NoConn ~ 5700 3800
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 507305F9
+P 2350 5150
+F 0 "#FLG01" H 2350 5420 30  0001 C CNN
+F 1 "PWR_FLAG" H 2350 5380 30  0000 C CNN
+	1    2350 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 507305F3
+P 4900 3200
+F 0 "#FLG02" H 4900 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 4900 3430 30  0000 C CNN
+	1    4900 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 5073005A
+P 2500 5450
+F 0 "#PWR03" H 2500 5450 30  0001 C CNN
+F 1 "GND" H 2500 5380 30  0001 C CNN
+	1    2500 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 5073006C
+P 2500 3050
+F 0 "#PWR04" H 2500 3050 30  0001 C CNN
+F 1 "GND" H 2500 2980 30  0001 C CNN
+	1    2500 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR05
+U 1 1 50730061
+P 2500 4250
+F 0 "#PWR05" H 2500 4250 30  0001 C CNN
+F 1 "GND" H 2500 4180 30  0001 C CNN
+	1    2500 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 5072FFF1
+P 2500 3700
+F 0 "R2" V 2580 3700 50  0000 C CNN
+F 1 "1000" V 2500 3700 50  0000 C CNN
+	1    2500 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWL v2
+U 1 1 5072FFEC
+P 2150 3650
+F 0 "v2" H 1950 3750 60  0000 C CNN
+F 1 "PWL" H 1950 3600 60  0000 C CNN
+F 2 "R1" H 1850 3650 60  0000 C CNN
+	1    2150 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 5072FFBC
+P 2500 4800
+F 0 "R3" V 2580 4800 50  0000 C CNN
+F 1 "1000" V 2500 4800 50  0000 C CNN
+	1    2500 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v3
+U 1 1 5072FFAC
+P 2150 4850
+F 0 "v3" H 1950 4950 60  0000 C CNN
+F 1 "PULSE" H 1950 4800 60  0000 C CNN
+F 2 "R1" H 1850 4850 60  0000 C CNN
+	1    2150 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R4
+U 1 1 5072FF51
+P 3950 4950
+F 0 "R4" V 4030 4950 50  0000 C CNN
+F 1 "1000" V 3950 4950 50  0000 C CNN
+	1    3950 4950
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v4
+U 1 1 5072FF43
+P 4500 5000
+F 0 "v4" H 4300 5100 60  0000 C CNN
+F 1 "5" H 4300 4950 60  0000 C CNN
+F 2 "R1" H 4200 5000 60  0000 C CNN
+	1    4500 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v1
+U 1 1 5072FEED
+P 2150 2500
+F 0 "v1" H 1950 2600 60  0000 C CNN
+F 1 "5" H 1950 2450 60  0000 C CNN
+F 2 "R1" H 1850 2500 60  0000 C CNN
+	1    2150 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 5072FE04
+P 2500 2500
+F 0 "R1" V 2580 2500 50  0000 C CNN
+F 1 "1000" V 2500 2500 50  0000 C CNN
+	1    2500 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC74 U1
+U 2 1 50727541
+P 6950 3600
+F 0 "U1" H 7100 3900 60  0000 C CNN
+F 1 "74HC74" H 7250 3305 60  0000 C CNN
+	2    6950 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC74 U1
+U 1 1 507274E2
+P 5100 3600
+F 0 "U1" H 5250 3900 60  0000 C CNN
+F 1 "74HC74" H 5400 3305 60  0000 C CNN
+	1    5100 3600
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/FlipFlops/analysis b/OSCAD/Examples/FlipFlops/analysis
new file mode 100644
index 0000000..df1e38d
--- /dev/null
+++ b/OSCAD/Examples/FlipFlops/analysis
@@ -0,0 +1 @@
+.tran  10e-03 4e-00 0e-00