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| author | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
|---|---|---|
| committer | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
| commit | 8377256e7d90aa7ba1cb51f6164e99f81e2eb53c (patch) | |
| tree | 5afcc8e82d7f7d4f6fbff900520bd8f05eb343ca /OSCAD/Examples | |
| download | FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.gz FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.bz2 FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.zip | |
initial commit
Diffstat (limited to 'OSCAD/Examples')
752 files changed, 71204 insertions, 0 deletions
diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier-cache.bak b/OSCAD/Examples/BJT_amplifier/BJT_amplifier-cache.bak new file mode 100644 index 0000000..a2c3051 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier-cache.bak @@ -0,0 +1,133 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 04 June 2013 10:39:51 PM IST +#encoding utf-8 +# +# AC +# +DEF AC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier-cache.lib b/OSCAD/Examples/BJT_amplifier/BJT_amplifier-cache.lib new file mode 100644 index 0000000..b7e5592 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier-cache.lib @@ -0,0 +1,133 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 06 June 2013 05:14:30 PM IST +#encoding utf-8 +# +# AC +# +DEF AC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.bak b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.bak new file mode 100644 index 0000000..ad03361 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.bak @@ -0,0 +1,240 @@ +EESchema Schematic File Version 2 date Tuesday 04 June 2013 10:39:51 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:BJT_amplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "4 jun 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 7050 4450 +Wire Wire Line + 7600 4450 5100 4450 +Wire Wire Line + 7600 4450 7600 4050 +Wire Wire Line + 5100 4450 5100 4500 +Wire Wire Line + 5100 4500 3700 4500 +Connection ~ 6300 4450 +Connection ~ 6800 3300 +Wire Wire Line + 3800 3600 3700 3600 +Wire Wire Line + 7050 3950 7050 3300 +Wire Wire Line + 7050 3300 6700 3300 +Connection ~ 5100 3600 +Connection ~ 6100 3300 +Wire Wire Line + 6300 3300 5850 3300 +Wire Wire Line + 5850 3800 5850 3950 +Wire Wire Line + 5850 3300 5850 3400 +Wire Wire Line + 5100 3300 5100 3950 +Wire Wire Line + 5550 3600 4950 3600 +Wire Wire Line + 6300 4050 6300 3900 +Wire Wire Line + 6300 3900 5850 3900 +Connection ~ 5850 3900 +Connection ~ 5850 4450 +Wire Wire Line + 4550 3600 4300 3600 +Connection ~ 5100 4450 +Wire Wire Line + 5650 4450 5650 4850 +Connection ~ 5650 4450 +Wire Wire Line + 5100 2800 7600 2800 +Wire Wire Line + 7600 2800 7600 3150 +Connection ~ 6100 2800 +$Comp +L DC v1 +U 1 1 51A5D97E +P 7600 3600 +F 0 "v1" H 7400 3700 60 0000 C CNN +F 1 "DC" H 7400 3550 60 0000 C CNN +F 2 "R1" H 7300 3600 60 0000 C CNN + 1 7600 3600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 51A5D42D +P 6800 3000 +F 0 "U1" H 6650 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 6950 3100 50 0000 C CNN + 1 6800 3000 + 1 0 0 -1 +$EndComp +$Comp +L AC v2 +U 1 1 51A486A5 +P 3700 4050 +F 0 "v2" H 3500 4150 60 0000 C CNN +F 1 "AC" H 3500 4000 60 0000 C CNN +F 2 "R1" H 3400 4050 60 0000 C CNN + 1 3700 4050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51A48298 +P 5650 4450 +F 0 "#FLG01" H 5650 4720 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4680 30 0000 C CNN + 1 5650 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 51A47FCD +P 5650 4850 +F 0 "#PWR02" H 5650 4850 30 0001 C CNN +F 1 "GND" H 5650 4780 30 0001 C CNN + 1 5650 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51A47FBC +P 4050 3600 +F 0 "R1" V 4130 3600 50 0000 C CNN +F 1 "50" V 4050 3600 50 0000 C CNN + 1 4050 3600 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 51A47FAB +P 5100 3050 +F 0 "R2" V 5180 3050 50 0000 C CNN +F 1 "200k" V 5100 3050 50 0000 C CNN + 1 5100 3050 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 51A47FA0 +P 4750 3600 +F 0 "C1" H 4800 3700 50 0000 L CNN +F 1 "40u" H 4800 3500 50 0000 L CNN + 1 4750 3600 + 0 -1 -1 0 +$EndComp +$Comp +L R R3 +U 1 1 51A47F97 +P 5100 4200 +F 0 "R3" V 5180 4200 50 0000 C CNN +F 1 "50k" V 5100 4200 50 0000 C CNN + 1 5100 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 51A47F8B +P 7050 4200 +F 0 "R6" V 7130 4200 50 0000 C CNN +F 1 "1k" V 7050 4200 50 0000 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 51A47F80 +P 6300 4250 +F 0 "C2" H 6350 4350 50 0000 L CNN +F 1 "100u" H 6350 4150 50 0000 L CNN + 1 6300 4250 + -1 0 0 1 +$EndComp +$Comp +L C C3 +U 1 1 51A47F75 +P 6500 3300 +F 0 "C3" H 6550 3400 50 0000 L CNN +F 1 "40u" H 6550 3200 50 0000 L CNN + 1 6500 3300 + 0 1 1 0 +$EndComp +$Comp +L R R5 +U 1 1 51A47F5C +P 6100 3050 +F 0 "R5" V 6180 3050 50 0000 C CNN +F 1 "2k" V 6100 3050 50 0000 C CNN + 1 6100 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 51A47F50 +P 5850 4200 +F 0 "R4" V 5930 4200 50 0000 C CNN +F 1 "1.5k" V 5850 4200 50 0000 C CNN + 1 5850 4200 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 51A47F29 +P 5750 3600 +F 0 "Q1" H 5750 3450 50 0000 R CNN +F 1 "NPN" H 5750 3750 50 0000 R CNN + 1 5750 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir new file mode 100644 index 0000000..5000496 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir @@ -0,0 +1,21 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 29 May 2013 04:04:50 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 6 0 DC +U1 4 VPLOT8_1 +v2 2 0 AC +R1 3 2 50 +R2 6 8 200k +C1 3 8 40u +R3 8 0 50k +R6 4 0 1k +C2 0 5 100u +C3 4 7 40u +R5 6 7 2k +R4 5 0 1.5k +Q1 5 8 7 NPN + +.end diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir.ckt b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir.ckt new file mode 100644 index 0000000..281db0e --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir.ckt @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 29 may 2013 04:04:50 pm ist
+.include npn.lib
+
+v1 6 0 dc 10
+* Plotting option vplot8_1
+v2 2 0 ac 0.5
+r1 3 2 50
+r2 6 8 200k
+c1 3 8 40u
+r3 8 0 50k
+r6 4 0 1k
+c2 0 5 100u
+c3 4 7 40u
+r5 6 7 2k
+r4 5 0 1.5k
+q1 7 8 5 npn
+
+.ac dec 100 100Hz 10KHz
+.plot v(4)
+.end
diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir.out b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir.out new file mode 100644 index 0000000..13bbb55 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.cir.out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 29 may 2013 04:04:50 pm ist
+.include npn.lib
+
+v1 6 0 dc 10
+* Plotting option vplot8_1
+v2 2 0 ac 0.5
+r1 3 2 50
+r2 6 8 200k
+c1 3 8 40u
+r3 8 0 50k
+r6 4 0 1k
+c2 0 5 100u
+c3 4 7 40u
+r5 6 7 2k
+r4 5 0 1.5k
+q1 7 8 5 npn
+
+.ac dec 100 100Hz 10KHz
+
+* Control Statements
+.control
+run
+plot v(4)
+.endc
+.end
diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.pro b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.pro new file mode 100644 index 0000000..af68001 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.pro @@ -0,0 +1,74 @@ +update=Tuesday 28 May 2013 03:25:45 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.proj b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.proj new file mode 100644 index 0000000..79be1da --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.proj @@ -0,0 +1 @@ +schematicFile tp.sch diff --git a/OSCAD/Examples/BJT_amplifier/BJT_amplifier.sch b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.sch new file mode 100644 index 0000000..68e94c5 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/BJT_amplifier.sch @@ -0,0 +1,240 @@ +EESchema Schematic File Version 2 date Thursday 06 June 2013 05:14:30 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:BJT_amplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "6 jun 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 7050 4450 +Wire Wire Line + 7600 4450 5100 4450 +Wire Wire Line + 7600 4450 7600 4050 +Wire Wire Line + 5100 4450 5100 4500 +Wire Wire Line + 5100 4500 3700 4500 +Connection ~ 6300 4450 +Connection ~ 6800 3300 +Wire Wire Line + 3800 3600 3700 3600 +Wire Wire Line + 7050 3950 7050 3300 +Wire Wire Line + 7050 3300 6700 3300 +Connection ~ 5100 3600 +Connection ~ 6100 3300 +Wire Wire Line + 6300 3300 5850 3300 +Wire Wire Line + 5850 3800 5850 3950 +Wire Wire Line + 5850 3300 5850 3400 +Wire Wire Line + 5100 3300 5100 3950 +Wire Wire Line + 5550 3600 4950 3600 +Wire Wire Line + 6300 4050 6300 3900 +Wire Wire Line + 6300 3900 5850 3900 +Connection ~ 5850 3900 +Connection ~ 5850 4450 +Wire Wire Line + 4550 3600 4300 3600 +Connection ~ 5100 4450 +Wire Wire Line + 5650 4450 5650 4850 +Connection ~ 5650 4450 +Wire Wire Line + 5100 2800 7600 2800 +Wire Wire Line + 7600 2800 7600 3150 +Connection ~ 6100 2800 +$Comp +L DC v1 +U 1 1 51A5D97E +P 7600 3600 +F 0 "v1" H 7400 3700 60 0000 C CNN +F 1 "DC" H 7400 3550 60 0000 C CNN +F 2 "R1" H 7300 3600 60 0000 C CNN + 1 7600 3600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 51A5D42D +P 6800 3000 +F 0 "U1" H 6650 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 6950 3100 50 0000 C CNN + 1 6800 3000 + 1 0 0 -1 +$EndComp +$Comp +L AC v2 +U 1 1 51A486A5 +P 3700 4050 +F 0 "v2" H 3500 4150 60 0000 C CNN +F 1 "AC" H 3500 4000 60 0000 C CNN +F 2 "R1" H 3400 4050 60 0000 C CNN + 1 3700 4050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51A48298 +P 5650 4450 +F 0 "#FLG01" H 5650 4720 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4680 30 0000 C CNN + 1 5650 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 51A47FCD +P 5650 4850 +F 0 "#PWR02" H 5650 4850 30 0001 C CNN +F 1 "GND" H 5650 4780 30 0001 C CNN + 1 5650 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51A47FBC +P 4050 3600 +F 0 "R1" V 4130 3600 50 0000 C CNN +F 1 "50" V 4050 3600 50 0000 C CNN + 1 4050 3600 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 51A47FAB +P 5100 3050 +F 0 "R2" V 5180 3050 50 0000 C CNN +F 1 "200k" V 5100 3050 50 0000 C CNN + 1 5100 3050 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 51A47FA0 +P 4750 3600 +F 0 "C1" H 4800 3700 50 0000 L CNN +F 1 "40u" H 4800 3500 50 0000 L CNN + 1 4750 3600 + 0 -1 -1 0 +$EndComp +$Comp +L R R3 +U 1 1 51A47F97 +P 5100 4200 +F 0 "R3" V 5180 4200 50 0000 C CNN +F 1 "50k" V 5100 4200 50 0000 C CNN + 1 5100 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 51A47F8B +P 7050 4200 +F 0 "R6" V 7130 4200 50 0000 C CNN +F 1 "1k" V 7050 4200 50 0000 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 51A47F80 +P 6300 4250 +F 0 "C2" H 6350 4350 50 0000 L CNN +F 1 "100u" H 6350 4150 50 0000 L CNN + 1 6300 4250 + -1 0 0 1 +$EndComp +$Comp +L C C3 +U 1 1 51A47F75 +P 6500 3300 +F 0 "C3" H 6550 3400 50 0000 L CNN +F 1 "40u" H 6550 3200 50 0000 L CNN + 1 6500 3300 + 0 1 1 0 +$EndComp +$Comp +L R R5 +U 1 1 51A47F5C +P 6100 3050 +F 0 "R5" V 6180 3050 50 0000 C CNN +F 1 "2k" V 6100 3050 50 0000 C CNN + 1 6100 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 51A47F50 +P 5850 4200 +F 0 "R4" V 5930 4200 50 0000 C CNN +F 1 "1.5k" V 5850 4200 50 0000 C CNN + 1 5850 4200 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 51A47F29 +P 5750 3600 +F 0 "Q1" H 5750 3450 50 0000 R CNN +F 1 "NPN" H 5750 3750 50 0000 R CNN + 1 5750 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/BJT_amplifier/Untitled Document 1 b/OSCAD/Examples/BJT_amplifier/Untitled Document 1 new file mode 100644 index 0000000..efd848b --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/Untitled Document 1 @@ -0,0 +1,24 @@ +echo "Checking scilab ......................" +command -v scilab >/dev/null 2>&1 +RetVal=$? +if [ $RetVal -eq 0 ] +then + scilabPATH="/usr/bin/scilab" +......... +.......... +......... +..................... + +..................... + fi + else + if [ $linuxVersion = "x86_64" ] + then + echo -e " \e[1m Please download scilab 5.4.0 for 64 bits (Linux) from http://www.scilab.org/products/scilab/download \e[0m" + else + echo -e " \e1m' Please download scilab 5.4.0 for 32 bits (Linux) from http://www.scilab.org/products/scilab/download '\e[0m'" + fi + echo " And re-run install_OSCAD.sh " + exit 1 + fi +fi diff --git a/OSCAD/Examples/BJT_amplifier/analysis b/OSCAD/Examples/BJT_amplifier/analysis new file mode 100644 index 0000000..b49cde4 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/analysis @@ -0,0 +1,2 @@ + +.ac dec 100 100Hz 10KHz diff --git a/OSCAD/Examples/BJT_amplifier/npn.lib b/OSCAD/Examples/BJT_amplifier/npn.lib new file mode 100644 index 0000000..abc5bd0 --- /dev/null +++ b/OSCAD/Examples/BJT_amplifier/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 ++ Cje=4.493p Vjc=.75 Xtb=1.5 Rb=10 Rc=1 ++ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 ++ Ikf=66.78m Br=.7371 Mje=.2593 Mjc=.3085 Vaf=74.03 ++ Isc=0 Ise=6.734f Xtf=2 Vje=.75 Is=6.734f ++ Itf=.4 Eg=1.11 )
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vplot1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/BasicGates/BasicGates-cache.lib b/OSCAD/Examples/BasicGates/BasicGates-cache.lib new file mode 100644 index 0000000..90be75b --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates-cache.lib @@ -0,0 +1,331 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 08:37:05 AM IST +#encoding utf-8 +# +# 74HCT04 +# +DEF 74HCT04 U 0 30 Y Y 6 F N +F0 "U" 150 100 40 H V C CNN +F1 "74HCT04" 200 -100 40 H V C CNN +ALIAS 74HC14 74HC04 74LS14 +DRAW +P 4 0 0 0 -150 150 -150 -150 150 0 -150 150 N +X GND 7 -50 -100 0 U 30 20 0 0 W N +X VCC 14 -50 100 0 D 30 20 0 0 W N +X ~ 1 -450 0 300 R 60 60 1 1 I +X ~ 2 450 0 300 L 60 60 1 1 O I +X ~ 3 -450 0 300 R 60 60 2 1 I +X ~ 4 450 0 300 L 60 60 2 1 O I +X ~ 5 -450 0 300 R 60 60 3 1 I +X ~ 6 450 0 300 L 60 60 3 1 O I +X ~ 8 450 0 300 L 60 60 4 1 O I +X ~ 9 -450 0 300 R 60 60 4 1 I +X ~ 10 450 0 300 L 60 60 5 1 O I +X ~ 11 -450 0 300 R 60 60 5 1 I +X ~ 12 450 0 300 L 60 60 6 1 O I +X ~ 13 -450 0 300 R 60 60 6 1 I +X ~ 1 -450 0 300 R 60 60 1 2 I I +X ~ 2 450 0 300 L 60 60 1 2 O +X ~ 3 -450 0 300 R 60 60 2 2 I I +X ~ 4 450 0 300 L 60 60 2 2 O +X ~ 5 -450 0 300 R 60 60 3 2 I I +X ~ 6 450 0 300 L 60 60 3 2 O +X ~ 8 450 0 300 L 60 60 4 2 O +X ~ 9 -450 0 300 R 60 60 4 2 I I +X ~ 10 450 0 300 L 60 60 5 2 O +X ~ 11 -450 0 300 R 60 60 5 2 I I +X ~ 12 450 0 300 L 60 60 6 2 O +X ~ 13 -450 0 300 R 60 60 6 2 I I +ENDDRAW +ENDDEF +# +# 74LS00 +# +DEF 74LS00 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS00" 0 -100 60 H V C CNN +ALIAS 74LS37 7400 74HCT00 74HC00 +$FPLIST + 14DIP300* + SO14* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A 100 0 200 -899 899 0 1 0 N 100 -200 100 200 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O I +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O I +X ~ 8 600 0 300 L 60 60 3 1 O I +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O I +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -465 0 259 504 -504 0 2 0 N -300 200 -300 -200 +A -11 143 343 -881 -246 0 2 0 N 0 -200 300 0 +A -10 -141 340 244 883 0 2 0 N 300 0 0 200 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O +X ~ 8 600 0 300 L 60 60 3 2 O +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS02 +# +DEF 74LS02 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS02" 50 -50 60 H V C CNN +ALIAS 74HC02 74HCT02 7402 74LS28 +$FPLIST + SO14* + 14DIP* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A -470 0 262 496 -496 0 1 8 N -300 200 -300 -200 +A -1 -127 327 898 228 0 1 8 N 0 200 300 0 +A -1 128 327 -230 -898 0 1 8 N 300 0 0 -200 +P 2 0 1 8 -300 -200 0 -200 N +P 2 0 1 8 -300 200 0 200 N +X ~ 1 600 0 300 L 60 60 1 1 O I +X ~ 2 -600 100 370 R 60 60 1 1 I +X ~ 3 -600 -100 370 R 60 60 1 1 I +X ~ 4 600 0 300 L 60 60 2 1 O I +X ~ 5 -600 100 370 R 60 60 2 1 I +X ~ 6 -600 -100 370 R 60 60 2 1 I +X ~ 8 -600 100 370 R 60 60 3 1 I +X ~ 9 -600 -100 370 R 60 60 3 1 I +X ~ 10 600 0 300 L 60 60 3 1 O I +X ~ 11 -600 100 370 R 60 60 4 1 I +X ~ 12 -600 -100 370 R 60 60 4 1 I +X ~ 13 600 0 300 L 60 60 4 1 O I +A 100 0 200 896 -896 0 2 8 N 101 200 101 -199 +P 4 0 2 8 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 600 0 300 L 60 60 1 2 O +X ~ 2 -600 100 300 R 60 60 1 2 I I +X ~ 3 -600 -100 300 R 60 60 1 2 I I +X ~ 4 600 0 300 L 60 60 2 2 O +X ~ 5 -600 100 300 R 60 60 2 2 I I +X ~ 6 -600 -100 300 R 60 60 2 2 I I +X ~ 8 -600 100 300 R 60 60 3 2 I I +X ~ 9 -600 -100 300 R 60 60 3 2 I I +X ~ 10 600 0 300 L 60 60 3 2 O +X ~ 11 -600 100 300 R 60 60 4 2 I I +X ~ 12 -600 -100 300 R 60 60 4 2 I I +X ~ 13 600 0 300 L 60 60 4 2 O +ENDDRAW +ENDDEF +# +# 74LS08 +# +DEF 74LS08 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS08" 0 -50 60 H V C CNN +ALIAS 74LS09 +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 U 40 40 0 0 W N +A 100 0 200 896 -896 0 1 0 N 101 200 101 -199 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O +X ~ 8 600 0 300 L 60 60 3 1 O +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198 +A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 2 0 N 2 200 300 0 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O I +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O I +X ~ 8 600 0 300 L 60 60 3 2 O I +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O I +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS32 +# +DEF 74LS32 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS32" 0 -50 60 H V C CNN +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 U 40 40 0 0 W N +A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198 +A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 1 0 N 2 200 300 0 +P 2 0 1 0 -300 -200 0 -200 N +P 2 0 1 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 1 I +X ~ 2 -600 -100 370 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O +X ~ 4 -600 100 370 R 60 60 2 1 I +X ~ 5 -600 -100 370 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O +X ~ 8 600 0 300 L 60 60 3 1 O +X ~ 9 -600 100 370 R 60 60 3 1 I +X ~ 10 -600 -100 370 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O +X ~ 12 -600 100 370 R 60 60 4 1 I +X ~ 13 -600 -100 370 R 60 60 4 1 I +A 100 0 200 896 -896 0 2 0 N 101 200 101 -199 +P 4 0 2 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 2 I I +X ~ 2 -600 -100 300 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O I +X ~ 4 -600 100 300 R 60 60 2 2 I I +X ~ 5 -600 -100 300 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O I +X ~ 8 600 0 300 L 60 60 3 2 O I +X ~ 9 -600 100 300 R 60 60 3 2 I I +X ~ 10 -600 -100 300 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O I +X ~ 12 -600 100 300 R 60 60 4 2 I I +X ~ 13 -600 -100 300 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS86 +# +DEF 74LS86 U 0 30 Y N 4 F N +F0 "U" 50 50 50 H V C CNN +F1 "74LS86" 50 -50 40 H V C CNN +ALIAS 74HC86 +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198 +A -396 -2 281 457 -451 0 1 0 N -200 199 -198 -200 +A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 1 0 N 2 200 300 0 +P 2 0 1 0 -200 -200 0 -200 N +P 2 0 1 0 -200 200 0 200 N +X IN1 1 -600 100 370 R 60 60 1 1 I +X IN2 2 -600 -100 370 R 60 60 1 1 I +X OUT 3 600 0 300 L 60 60 1 1 O +X IN1 4 -600 100 370 R 60 60 2 1 I +X IN2 5 -600 -100 370 R 60 60 2 1 I +X OUT 6 600 0 300 L 60 60 2 1 O +X OUT 8 600 0 300 L 60 60 3 1 O +X IN1 9 -600 100 370 R 60 60 3 1 I +X IN2 10 -600 -100 370 R 60 60 3 1 I +X OUT 11 600 0 300 L 60 60 4 1 O +X IN1 12 -600 100 370 R 60 60 4 1 I +X IN2 13 -600 -100 370 R 60 60 4 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/BasicGates/BasicGates.bak b/OSCAD/Examples/BasicGates/BasicGates.bak new file mode 100644 index 0000000..b0c177c --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.bak @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 date Sunday 09 December 2012 08:00:09 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:BasicGates-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "30 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 9700 3000 +Wire Wire Line + 9700 3000 9700 2800 +Wire Wire Line + 9900 3100 9900 3000 +Wire Wire Line + 9900 3000 9100 3000 +Wire Wire Line + 1700 3800 3750 3800 +Wire Wire Line + 7900 3100 7850 3100 +Wire Wire Line + 7850 3100 7850 3400 +Wire Wire Line + 7850 3400 7750 3400 +Connection ~ 5300 2300 +Wire Wire Line + 5300 2300 5300 3300 +Wire Wire Line + 5300 3300 5500 3300 +Wire Wire Line + 5100 3500 5500 3500 +Wire Wire Line + 7900 2900 7350 2900 +Wire Wire Line + 7350 2900 7350 2400 +Wire Wire Line + 7350 2400 7000 2400 +Connection ~ 3750 2200 +Wire Wire Line + 3900 3400 3750 3400 +Wire Wire Line + 3750 3400 3750 2200 +Wire Wire Line + 3850 2200 3650 2200 +Wire Wire Line + 3650 2200 3650 1700 +Connection ~ 2400 1700 +Wire Wire Line + 2400 1700 2400 1550 +Connection ~ 2250 1700 +Connection ~ 2000 2900 +Wire Wire Line + 2000 2900 2000 2700 +Wire Wire Line + 2250 3800 2250 4150 +Wire Wire Line + 1700 3800 1700 3950 +Wire Wire Line + 2250 2500 2250 2900 +Wire Wire Line + 2250 2900 1750 2900 +Connection ~ 1700 5050 +Wire Wire Line + 1700 5050 2250 5050 +Wire Wire Line + 2250 5050 2250 4650 +Wire Wire Line + 1700 4850 1700 5200 +Wire Wire Line + 1750 1800 1750 1700 +Wire Wire Line + 2250 1700 2250 2000 +Wire Wire Line + 1750 3150 1750 2700 +Connection ~ 1750 2900 +Connection ~ 2250 3800 +Wire Wire Line + 2400 3800 2400 3600 +Connection ~ 2400 3800 +Wire Wire Line + 3900 3600 3750 3600 +Wire Wire Line + 3750 3600 3750 3800 +Wire Wire Line + 3500 3800 3500 2400 +Wire Wire Line + 3500 2400 3850 2400 +Connection ~ 3500 3800 +Wire Wire Line + 5050 2300 5800 2300 +Wire Wire Line + 6200 2200 6200 1900 +Wire Wire Line + 5800 2500 5200 2500 +Wire Wire Line + 5200 2500 5200 3500 +Connection ~ 5200 3500 +Wire Wire Line + 6700 3400 6850 3400 +Wire Wire Line + 1750 1700 3650 1700 +Wire Wire Line + 9900 3600 9900 3900 +Text Notes 9150 2850 0 60 ~ 0 +~A.B +Text Notes 9050 2850 0 60 ~ 0 ++ +Text Notes 8900 2850 0 60 ~ 0 +A.B +Text Notes 8000 2300 0 60 ~ 0 +~B +Text Notes 7900 2300 0 60 ~ 0 ++ +Text Notes 7750 2300 0 60 ~ 0 +=~A +Text Notes 7900 3650 0 60 ~ 0 +=A+B +Text Notes 7850 3500 0 60 ~ 0 +A.B+A+B +Text Notes 6450 3600 0 60 ~ 0 +~((A.B)+(A+B)) +Text Notes 7100 2300 0 60 ~ 0 +~((A.B).(A+B)) +$Comp +L 74HC86 U12 +U 1 1 507253B2 +P 8500 3000 +F 0 "U12" H 8550 3050 50 0000 C CNN +F 1 "74HC86" H 8550 2950 40 0000 C CNN + 1 8500 3000 + 1 0 0 -1 +$EndComp +Text Notes 5150 3650 0 60 ~ 0 +A+B +Text Notes 5100 2250 0 60 ~ 0 +A.B +Text Notes 3600 3950 0 60 ~ 0 +B +Text Notes 3500 1650 0 60 ~ 0 +A +$Comp +L 74LS32 U8 +U 1 1 50725446 +P 4500 3500 +F 0 "U8" H 4500 3550 60 0000 C CNN +F 1 "74LS32" H 4500 3450 60 0000 C CNN + 1 4500 3500 + 1 0 0 -1 +$EndComp +$Comp +L 74LS08 U7 +U 1 1 50725428 +P 4450 2300 +F 0 "U7" H 4450 2350 60 0000 C CNN +F 1 "74LS08" H 4450 2250 60 0000 C CNN + 1 4450 2300 + 1 0 0 -1 +$EndComp +$Comp +L 74HC02 U9 +U 1 1 50725415 +P 6100 3400 +F 0 "U9" H 6100 3450 60 0000 C CNN +F 1 "74HC02" H 6150 3350 60 0000 C CNN + 1 6100 3400 + 1 0 0 -1 +$EndComp +$Comp +L 74HC04 U11 +U 1 1 507253DF +P 7300 3400 +F 0 "U11" H 7450 3500 40 0000 C CNN +F 1 "74HC04" H 7500 3300 40 0000 C CNN + 1 7300 3400 + 1 0 0 -1 +$EndComp +$Comp +L 7400 U10 +U 1 1 5072539F +P 6400 2400 +F 0 "U10" H 6400 2450 60 0000 C CNN +F 1 "7400" H 6400 2300 60 0000 C CNN + 1 6400 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5072534B +P 9900 3900 +F 0 "#PWR01" H 9900 3900 30 0001 C CNN +F 1 "GND" H 9900 3830 30 0001 C CNN + 1 9900 3900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U1 +U 1 1 50725278 +P 2400 1250 +F 0 "U1" H 2250 1350 50 0000 C CNN +F 1 "VPLOT1" H 2550 1350 50 0000 C CNN + 1 2400 1250 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 507251F2 +P 2000 2700 +F 0 "#FLG02" H 2000 2970 30 0001 C CNN +F 1 "PWR_FLAG" H 2000 2930 30 0000 C CNN + 1 2000 2700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 507251E5 +P 1750 3150 +F 0 "#PWR03" H 1750 3150 30 0001 C CNN +F 1 "GND" H 1750 3080 30 0001 C CNN + 1 1750 3150 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 507251A7 +P 2250 2250 +F 0 "R3" V 2330 2250 50 0000 C CNN +F 1 "1000" V 2250 2250 50 0000 C CNN + 1 2250 2250 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v2 +U 1 1 50725192 +P 1750 2250 +F 0 "v2" H 1550 2350 60 0000 C CNN +F 1 "PULSE" H 1550 2200 60 0000 C CNN + 1 1750 2250 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U5 +U 1 1 50653344 +P 9700 2500 +F 0 "U5" H 9550 2600 50 0000 C CNN +F 1 "VPLOT1" H 9850 2600 50 0000 C CNN + 1 9700 2500 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 50653022 +P 6200 1900 +F 0 "#FLG04" H 6200 2170 30 0001 C CNN +F 1 "PWR_FLAG" H 6200 2130 30 0000 C CNN + 1 6200 1900 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 9900 3350 +F 0 "R2" V 9980 3350 50 0000 C CNN +F 1 "1000" V 9900 3350 50 0000 C CNN + 1 9900 3350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U2 +U 1 1 5061678B +P 2400 3300 +F 0 "U2" H 2250 3400 50 0000 C CNN +F 1 "VPLOT1" H 2550 3400 50 0000 C CNN + 1 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 2250 4400 +F 0 "R1" V 2330 4400 50 0000 C CNN +F 1 "1000" V 2250 4400 50 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 505C9EE8 +P 1700 5200 +F 0 "#PWR05" H 1700 5200 30 0001 C CNN +F 1 "GND" H 1700 5130 30 0001 C CNN + 1 1700 5200 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 505C9ECF +P 1700 4400 +F 0 "v1" H 1500 4500 60 0000 C CNN +F 1 "PULSE" H 1500 4350 60 0000 C CNN + 1 1700 4400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/BasicGates/BasicGates.cir b/OSCAD/Examples/BasicGates/BasicGates.cir new file mode 100644 index 0000000..839fbc6 --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.cir @@ -0,0 +1,20 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Sunday 09 December 2012 08:37:15 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 8 4 9 VPLOT8_1 +U12 5 6 9 0 3 74HC86 +U8 8 4 10 0 3 74LS32 +U7 8 4 2 0 3 74LS08 +U9 7 2 10 0 3 74HC02 +U11 7 6 0 3 74HC04 +U10 2 10 5 0 3 7400 +R3 8 0 1000 +v2 8 0 PULSE +R2 9 0 1000 +R1 4 0 1000 +v1 4 0 PULSE + +.end diff --git a/OSCAD/Examples/BasicGates/BasicGates.cir.ckt b/OSCAD/Examples/BasicGates/BasicGates.cir.ckt new file mode 100644 index 0000000..857c283 --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.cir.ckt @@ -0,0 +1,59 @@ +* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 08:37:15 am ist + +* Plotting option vplot8_1 +* 74hc86 +* 74ls32 +* 74ls08 +* 74hc02 +* 74hc04 +* 7400 +r3 8 0 1000 +v2 8 0 pulse(0 5 0 0 0 0.25e-6 0.5e-6) +r2 9 0 1000 +r1 4 0 1000 +v1 4 0 pulse(0 5 0 0 0 0.125e-6 0.5e-6) +a1 [5] [5_in] u12adc +a2 [6] [6_in] u12adc +a3 [5_in 6_in] 9_out u12 +a4 [9_out] [9] u12dac +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a5 [8] [8_in] u8adc +a6 [4] [4_in] u8adc +a7 [8_in 4_in] 10_out u8 +a8 [10_out] [10] u8dac +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a9 [8] [8_in] u7adc +a10 [4] [4_in] u7adc +a11 [8_in 4_in] 2_out u7 +a12 [2_out] [2] u7dac +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a13 [2] [2_in] u9adc +a14 [10] [10_in] u9adc +a15 [2_in 10_in] 7_out u9 +a16 [7_out] [7] u9dac +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a17 [7] [7_in] u11adc +a18 7_in 6_out u11 +a19 [6_out] [6] u11dac +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a20 [2] [2_in] u10adc +a21 [10] [10_in] u10adc +a22 [2_in 10_in] 5_out u10 +a23 [5_out] [5] u10dac +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 +.plot .v(8) .v(4) .v(9) . +.end diff --git a/OSCAD/Examples/BasicGates/BasicGates.cir.out b/OSCAD/Examples/BasicGates/BasicGates.cir.out new file mode 100644 index 0000000..4e7ccde --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.cir.out @@ -0,0 +1,64 @@ +* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 08:37:15 am ist + +* Plotting option vplot8_1 +* 74hc86 +* 74ls32 +* 74ls08 +* 74hc02 +* 74hc04 +* 7400 +r3 8 0 1000 +v2 8 0 pulse(0 5 0 0 0 0.25e-6 0.5e-6) +r2 9 0 1000 +r1 4 0 1000 +v1 4 0 pulse(0 5 0 0 0 0.125e-6 0.5e-6) +a1 [5] [5_in] u12adc +a2 [6] [6_in] u12adc +a3 [5_in 6_in] 9_out u12 +a4 [9_out] [9] u12dac +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a5 [8] [8_in] u8adc +a6 [4] [4_in] u8adc +a7 [8_in 4_in] 10_out u8 +a8 [10_out] [10] u8dac +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a9 [8] [8_in] u7adc +a10 [4] [4_in] u7adc +a11 [8_in 4_in] 2_out u7 +a12 [2_out] [2] u7dac +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a13 [2] [2_in] u9adc +a14 [10] [10_in] u9adc +a15 [2_in 10_in] 7_out u9 +a16 [7_out] [7] u9dac +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a17 [7] [7_in] u11adc +a18 7_in 6_out u11 +a19 [6_out] [6] u11dac +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a20 [2] [2_in] u10adc +a21 [10] [10_in] u10adc +a22 [2_in 10_in] 5_out u10 +a23 [5_out] [5] u10dac +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 + +* Control Statements +.control +run +plot v(8) v(4) v(9) +.endc +.end diff --git a/OSCAD/Examples/BasicGates/BasicGates.cmp b/OSCAD/Examples/BasicGates/BasicGates.cmp new file mode 100644 index 0000000..70877a7 --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.cmp @@ -0,0 +1,101 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 05:06:15 PM IST + +BeginCmp +TimeStamp = /505C9F25; +Reference = R1; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50652FB6; +Reference = R2; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /507251A7; +Reference = R3; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /505FD8A0; +Reference = U3; +ValeurCmp = ADC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /505FDC21; +Reference = U4; +ValeurCmp = DAC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725212; +Reference = U6; +ValeurCmp = ADC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725428; +Reference = U7; +ValeurCmp = 74LS08; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725446; +Reference = U8; +ValeurCmp = 74LS32; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725415; +Reference = U9; +ValeurCmp = 74HC02; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /5072539F; +Reference = U10; +ValeurCmp = 7400; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /507253DF; +Reference = U11; +ValeurCmp = 74HC04; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /507253B2; +Reference = U12; +ValeurCmp = 74HC86; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /505C9ECF; +Reference = v1; +ValeurCmp = PULSE; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725192; +Reference = v2; +ValeurCmp = PULSE; +IdModule = ; +EndCmp + +EndListe diff --git a/OSCAD/Examples/BasicGates/BasicGates.net b/OSCAD/Examples/BasicGates/BasicGates.net new file mode 100644 index 0000000..e5b57d3 --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.net @@ -0,0 +1,112 @@ +# EESchema Netlist Version 1.1 created Monday 22 October 2012 05:06:15 PM IST +( + ( /505C9F25 R3 R1 1000 + ( 1 N-000006 ) + ( 2 GND ) + ) + ( /50652FB6 R3 R2 1000 + ( 1 N-000007 ) + ( 2 GND ) + ) + ( /507251A7 R3 R3 1000 + ( 1 N-000009 ) + ( 2 GND ) + ) + ( /505FD8A0 $noname$ U3 ADC + ( 1 N-000006 ) + ( 2 N-000005 ) + ) + ( /505FDC21 $noname$ U4 DAC + ( 1 N-000008 ) + ( 2 N-000007 ) + ) + ( /50725212 $noname$ U6 ADC + ( 1 N-000009 ) + ( 2 N-000011 ) + ) + ( /50725428 $noname$ U7 74LS08 + ( 1 N-000011 ) + ( 2 N-000005 ) + ( 3 N-000003 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /50725446 $noname$ U8 74LS32 + ( 1 N-000011 ) + ( 2 N-000005 ) + ( 3 N-000013 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /50725415 $noname$ U9 74HC02 + ( 1 N-000004 ) + ( 2 N-000003 ) + ( 3 N-000013 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /5072539F $noname$ U10 7400 + ( 1 N-000003 ) + ( 2 N-000013 ) + ( 3 N-000010 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /507253DF $noname$ U11 74HC04 + ( 1 N-000004 ) + ( 2 N-000012 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /507253B2 $noname$ U12 74HC86 + ( 1 N-000010 ) + ( 2 N-000012 ) + ( 3 N-000008 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /505C9ECF $noname$ v1 PULSE + ( 1 N-000006 ) + ( 2 GND ) + ) + ( /50725192 $noname$ v2 PULSE + ( 1 N-000009 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component U9 + SO14* + 14DIP* +$endlist +$component U10 + 14DIP300* + SO14* +$endlist +$component v1 + 1_pin +$endlist +$component v2 + 1_pin +$endlist +$endfootprintlist +} diff --git a/OSCAD/Examples/BasicGates/BasicGates.pro b/OSCAD/Examples/BasicGates/BasicGates.pro new file mode 100644 index 0000000..067b52d --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.pro @@ -0,0 +1,71 @@ +update=Monday 22 October 2012 05:04:10 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/BasicGates/BasicGates.proj b/OSCAD/Examples/BasicGates/BasicGates.proj new file mode 100644 index 0000000..f8a0441 --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.proj @@ -0,0 +1 @@ +schematicFile BasicGates.sch diff --git a/OSCAD/Examples/BasicGates/BasicGates.sch b/OSCAD/Examples/BasicGates/BasicGates.sch new file mode 100644 index 0000000..050f6d4 --- /dev/null +++ b/OSCAD/Examples/BasicGates/BasicGates.sch @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 date Sunday 09 December 2012 08:37:05 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:BasicGates-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 3 1 50C3FFE2 +P 9700 2500 +F 0 "U1" H 9550 2600 50 0000 C CNN +F 1 "VPLOT8_1" H 9850 2600 50 0000 C CNN + 3 9700 2500 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50C3FFDB +P 2400 3300 +F 0 "U1" H 2250 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3400 50 0000 C CNN + 2 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50C3FFD3 +P 2400 1250 +F 0 "U1" H 2250 1350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 1350 50 0000 C CNN + 1 2400 1250 + 1 0 0 -1 +$EndComp +Connection ~ 9700 3000 +Wire Wire Line + 9700 3000 9700 2800 +Wire Wire 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1 "PULSE" H 1550 2200 60 0000 C CNN + 1 1750 2250 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 50653022 +P 6200 1900 +F 0 "#FLG04" H 6200 2170 30 0001 C CNN +F 1 "PWR_FLAG" H 6200 2130 30 0000 C CNN + 1 6200 1900 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 9900 3350 +F 0 "R2" V 9980 3350 50 0000 C CNN +F 1 "1000" V 9900 3350 50 0000 C CNN + 1 9900 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 2250 4400 +F 0 "R1" V 2330 4400 50 0000 C CNN +F 1 "1000" V 2250 4400 50 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 505C9EE8 +P 1700 5200 +F 0 "#PWR05" H 1700 5200 30 0001 C CNN +F 1 "GND" H 1700 5130 30 0001 C CNN + 1 1700 5200 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 505C9ECF +P 1700 4400 +F 0 "v1" H 1500 4500 60 0000 C CNN +F 1 "PULSE" H 1500 4350 60 0000 C CNN + 1 1700 4400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/BasicGates/analysis b/OSCAD/Examples/BasicGates/analysis new file mode 100644 index 0000000..bf5e632 --- /dev/null +++ b/OSCAD/Examples/BasicGates/analysis @@ -0,0 +1 @@ +.tran 10e-09 1e-06 0e-00 diff --git a/OSCAD/Examples/FlipFlops/FlipFlops-cache.bak b/OSCAD/Examples/FlipFlops/FlipFlops-cache.bak new file mode 100644 index 0000000..71dbe1a --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops-cache.bak @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 04:03:52 PM IST +#encoding utf-8 +# +# 74LS74 +# +DEF 74LS74 U 0 40 Y Y 2 F N +F0 "U" 150 300 60 H V C CNN +F1 "74LS74" 300 -295 60 H V C CNN +ALIAS 74HC74 +DRAW +X GND 7 -200 -250 0 U 30 30 0 0 W N +X VCC 14 -200 250 0 D 30 30 0 0 W N +S -300 250 300 -250 0 1 0 N +X Cd 1 0 -550 300 U 60 60 1 1 I I +X D 2 -600 200 300 R 60 60 1 1 I +X Cp 3 -600 0 300 R 60 60 1 1 I C +X Sd 4 0 550 300 D 60 60 1 1 I I +X Q 5 600 200 300 L 60 60 1 1 O +X ~Q 6 600 -200 300 L 60 60 1 1 O I +X ~Q 8 600 -200 300 L 60 60 2 1 O I +X Q 9 600 200 300 L 60 60 2 1 O +X Sd 10 0 550 300 D 60 60 2 1 I I +X Cp 11 -600 0 300 R 60 60 2 1 I C +X D 12 -600 200 300 R 60 60 2 1 I +X Cd 13 0 -550 300 U 60 60 2 1 I I +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pwl +# +DEF pwl v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pwl" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50 +A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50 +A -75 -700 750 919 880 0 1 0 N -100 50 -50 50 +A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50 +A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot1 +# +DEF vplot1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/FlipFlops/FlipFlops-cache.lib b/OSCAD/Examples/FlipFlops/FlipFlops-cache.lib new file mode 100644 index 0000000..dc46d4f --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 04:06:09 PM IST +#encoding utf-8 +# +# 74LS74 +# +DEF 74LS74 U 0 40 Y Y 2 F N +F0 "U" 150 300 60 H V C CNN +F1 "74LS74" 300 -295 60 H V C CNN +ALIAS 74HC74 +DRAW +X GND 7 -200 -250 0 U 30 30 0 0 W N +X VCC 14 -200 250 0 D 30 30 0 0 W N +S -300 250 300 -250 0 1 0 N +X Cd 1 0 -550 300 U 60 60 1 1 I I +X D 2 -600 200 300 R 60 60 1 1 I +X Cp 3 -600 0 300 R 60 60 1 1 I C +X Sd 4 0 550 300 D 60 60 1 1 I I +X Q 5 600 200 300 L 60 60 1 1 O +X ~Q 6 600 -200 300 L 60 60 1 1 O I +X ~Q 8 600 -200 300 L 60 60 2 1 O I +X Q 9 600 200 300 L 60 60 2 1 O +X Sd 10 0 550 300 D 60 60 2 1 I I +X Cp 11 -600 0 300 R 60 60 2 1 I C +X D 12 -600 200 300 R 60 60 2 1 I +X Cd 13 0 -550 300 U 60 60 2 1 I I +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pwl +# +DEF pwl v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pwl" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50 +A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50 +A -75 -700 750 919 880 0 1 0 N -100 50 -50 50 +A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50 +A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.bak b/OSCAD/Examples/FlipFlops/FlipFlops.bak new file mode 100644 index 0000000..e821e8b --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.bak @@ -0,0 +1,303 @@ +EESchema Schematic File Version 2 date Sunday 09 December 2012 04:03:52 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:FlipFlops-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 2800 4400 +Wire Wire Line + 2800 4400 2800 4050 +Wire Wire Line + 6000 2900 6000 3400 +Wire Wire Line + 3950 5200 3950 5450 +Wire Wire Line + 3950 5450 4500 5450 +Wire Wire Line + 2150 3200 4000 3200 +Connection ~ 6000 3400 +Connection ~ 2350 5300 +Wire Wire Line + 2350 5300 2350 5150 +Connection ~ 6950 4550 +Wire Wire Line + 5100 4550 5100 4150 +Connection ~ 9150 4550 +Wire Wire Line + 5700 3400 6350 3400 +Connection ~ 5100 2050 +Wire Wire Line + 6950 3050 6950 2050 +Wire Wire Line + 4000 3200 4000 3400 +Wire Wire Line + 4000 3400 4500 3400 +Connection ~ 2500 4400 +Connection ~ 2500 4100 +Wire Wire Line + 2500 4250 2500 3950 +Wire Wire Line + 2500 3200 2500 3450 +Wire Wire Line + 2500 2950 2150 2950 +Wire Wire Line + 2500 3050 2500 2750 +Connection ~ 2500 2950 +Wire Wire Line + 2500 4100 2150 4100 +Wire Wire Line + 2500 4400 2500 4550 +Wire Wire Line + 2500 5450 2500 5050 +Connection ~ 2500 5300 +Connection ~ 2500 3200 +Wire Wire Line + 4500 3600 4000 3600 +Wire Wire Line + 4000 3600 4000 4400 +Wire Wire Line + 5100 2050 5100 3050 +Wire Wire Line + 6100 3600 6100 4400 +Wire Wire Line + 6100 3600 6350 3600 +Connection ~ 4000 4400 +Wire Wire Line + 6950 4150 6950 4550 +Wire Wire Line + 4900 3200 4900 3350 +Wire Wire Line + 2500 2050 2500 2250 +Connection ~ 2500 2050 +Wire Wire Line + 6950 2050 2150 2050 +Wire Wire Line + 6100 4400 2150 4400 +Wire Wire Line + 3950 4700 3950 4550 +Wire Wire Line + 3950 4550 6950 4550 +Connection ~ 4500 4550 +Connection ~ 5100 4550 +Wire Wire Line + 3950 5300 2150 5300 +Connection ~ 3950 5300 +Wire Wire Line + 2800 3200 2800 2850 +Connection ~ 2800 3200 +NoConn ~ 7550 3800 +NoConn ~ 7550 3400 +NoConn ~ 5700 3800 +$Comp +L PWR_FLAG #FLG01 +U 1 1 507305F9 +P 2350 5150 +F 0 "#FLG01" H 2350 5420 30 0001 C CNN +F 1 "PWR_FLAG" H 2350 5380 30 0000 C CNN + 1 2350 5150 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 507305F3 +P 4900 3200 +F 0 "#FLG02" H 4900 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 4900 3430 30 0000 C CNN + 1 4900 3200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U4 +U 1 1 50730491 +P 2800 3750 +F 0 "U4" H 2650 3850 50 0000 C CNN +F 1 "VPLOT1" H 2950 3850 50 0000 C CNN + 1 2800 3750 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U3 +U 1 1 50730484 +P 2800 2550 +F 0 "U3" H 2650 2650 50 0000 C CNN +F 1 "VPLOT1" H 2950 2650 50 0000 C CNN + 1 2800 2550 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U2 +U 1 1 50730477 +P 6000 2600 +F 0 "U2" H 5850 2700 50 0000 C CNN +F 1 "VPLOT1" H 6150 2700 50 0000 C CNN + 1 6000 2600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5073005A +P 2500 5450 +F 0 "#PWR03" H 2500 5450 30 0001 C CNN +F 1 "GND" H 2500 5380 30 0001 C CNN + 1 2500 5450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 5073006C +P 2500 3050 +F 0 "#PWR04" H 2500 3050 30 0001 C CNN +F 1 "GND" H 2500 2980 30 0001 C CNN + 1 2500 3050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 50730061 +P 2500 4250 +F 0 "#PWR06" H 2500 4250 30 0001 C CNN +F 1 "GND" H 2500 4180 30 0001 C CNN + 1 2500 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5072FFF1 +P 2500 3700 +F 0 "R2" V 2580 3700 50 0000 C CNN +F 1 "1000" V 2500 3700 50 0000 C CNN + 1 2500 3700 + 1 0 0 -1 +$EndComp +$Comp +L PWL v2 +U 1 1 5072FFEC +P 2150 3650 +F 0 "v2" H 1950 3750 60 0000 C CNN +F 1 "PWL" H 1950 3600 60 0000 C CNN +F 2 "R1" H 1850 3650 60 0000 C CNN + 1 2150 3650 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5072FFBC +P 2500 4800 +F 0 "R3" V 2580 4800 50 0000 C CNN +F 1 "1000" V 2500 4800 50 0000 C CNN + 1 2500 4800 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v3 +U 1 1 5072FFAC +P 2150 4850 +F 0 "v3" H 1950 4950 60 0000 C CNN +F 1 "PULSE" H 1950 4800 60 0000 C CNN +F 2 "R1" H 1850 4850 60 0000 C CNN + 1 2150 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5072FF51 +P 3950 4950 +F 0 "R4" V 4030 4950 50 0000 C CNN +F 1 "1000" V 3950 4950 50 0000 C CNN + 1 3950 4950 + 1 0 0 -1 +$EndComp +$Comp +L DC v4 +U 1 1 5072FF43 +P 4500 5000 +F 0 "v4" H 4300 5100 60 0000 C CNN +F 1 "5" H 4300 4950 60 0000 C CNN +F 2 "R1" H 4200 5000 60 0000 C CNN + 1 4500 5000 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5072FEED +P 2150 2500 +F 0 "v1" H 1950 2600 60 0000 C CNN +F 1 "5" H 1950 2450 60 0000 C CNN +F 2 "R1" H 1850 2500 60 0000 C CNN + 1 2150 2500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5072FE04 +P 2500 2500 +F 0 "R1" V 2580 2500 50 0000 C CNN +F 1 "1000" V 2500 2500 50 0000 C CNN + 1 2500 2500 + 1 0 0 -1 +$EndComp +$Comp +L 74HC74 U1 +U 2 1 50727541 +P 6950 3600 +F 0 "U1" H 7100 3900 60 0000 C CNN +F 1 "74HC74" H 7250 3305 60 0000 C CNN + 2 6950 3600 + 1 0 0 -1 +$EndComp +$Comp +L 74HC74 U1 +U 1 1 507274E2 +P 5100 3600 +F 0 "U1" H 5250 3900 60 0000 C CNN +F 1 "74HC74" H 5400 3305 60 0000 C CNN + 1 5100 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir b/OSCAD/Examples/FlipFlops/FlipFlops.cir new file mode 100644 index 0000000..92a4982 --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Sunday 09 December 2012 04:06:26 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 6 2 10 VPLOT8_1 +R2 2 0 1000 +v2 2 0 PWL +R3 6 0 1000 +v3 6 0 PULSE +R4 1 0 1000 +v4 1 0 5 +v1 11 0 5 +R1 11 0 1000 +U1 1 2 6 11 10 3 0 5 4 11 6 10 1 7 74HC74 + +.end diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir.ckt b/OSCAD/Examples/FlipFlops/FlipFlops.cir.ckt new file mode 100644 index 0000000..5f457bc --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir.ckt @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 04:06:26 pm ist + +* Plotting option vplot8_1 +r2 2 0 1000 +v2 2 0 pwl(0 0 2.6 0 2.60000000001 5 3 5 ) +r3 6 0 1000 +v3 6 0 pulse(0 5 0 0 0 0.5 1) +r4 1 0 1000 +v4 1 0 5 +v1 11 0 5 +r1 11 0 1000 +* 74hc74 +a1 [2 6 11 1] [2_in 6_in 11_in 1_in] u1adc +a2 2_in 6_in ~11_in ~1_in 10_out 3_out u1 +a3 [10_out 3_out] [10 3] u1dac +a4 [10 6 11 1] [10_in 6_in 11_in 1_in] u1adc +a5 10_in 6_in ~11_in ~1_in 4_out 5_out u1 +a6 [4_out 5_out] [4 5] u1dac +.model u1 d_dff +.model u1adc adc_bridge(in_low=0.8 in_high=2.0) +.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-03 4e-00 0e-00 +.plot v(6) v(2) v(10) +.end diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir.out b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out new file mode 100644 index 0000000..9410f5b --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out @@ -0,0 +1,30 @@ +* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 04:06:26 pm ist + +* Plotting option vplot8_1 +r2 2 0 1000 +v2 2 0 pwl(0 0 2.6 0 2.60000000001 5 3 5 ) +r3 6 0 1000 +v3 6 0 pulse(0 5 0 0 0 0.5 1) +r4 1 0 1000 +v4 1 0 5 +v1 11 0 5 +r1 11 0 1000 +* 74hc74 +a1 [2 6 11 1] [2_in 6_in 11_in 1_in] u1adc +a2 2_in 6_in ~11_in ~1_in 10_out 3_out u1 +a3 [10_out 3_out] [10 3] u1dac +a4 [10 6 11 1] [10_in 6_in 11_in 1_in] u1adc +a5 10_in 6_in ~11_in ~1_in 4_out 5_out u1 +a6 [4_out 5_out] [4 5] u1dac +.model u1 d_dff +.model u1adc adc_bridge(in_low=0.8 in_high=2.0) +.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-03 4e-00 0e-00 + +* Control Statements +.control +run +plot v(6) v(2) v(10) +.endc +.end diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.cir.out1 b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out1 new file mode 100644 index 0000000..c855d5e --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.cir.out1 @@ -0,0 +1,34 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 30 october 2012 07:12:51 pm ist + +* Plotting option vplot1 +* Plotting option vplot1 +* Plotting option vplot1 +r2 1 0 1000 +v2 1 0 pwl(0 0 2.6 0 2.6000000000001 5 3 5 ) +r3 4 0 1000 +v3 4 0 pulse(0 5 0 0 0 0.5 1) +r4 9 0 1000 +v4 9 0 dc 5 +v1 10 0 dc 5 +r1 10 0 1000 +* 74hc74 +a1 [1 4 10 9] [1_in 4_in 10_in 9_in] u1adc +a2 1_in 4_in ~10_in ~9_in 2_out 3_out u1 +a3 [2_out 3_out] [2 3] u1dac +a4 [2 4 10 9] [2_in 4_in 10_in 9_in] u1adc +a5 2_in 4_in ~10_in ~9_in 6_out 7_out u1 +a6 [6_out 7_out] [6 7] dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u1 d_dff +.model u1adc adc_bridge(in_low=0.8 in_high=2.0) +.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-03 4e-00 0e-00 + +* Control Statements +.control +run +plot v(4) +plot v(1) +plot v(2) +.endc +.end diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.pro b/OSCAD/Examples/FlipFlops/FlipFlops.pro new file mode 100644 index 0000000..529955f --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.pro @@ -0,0 +1,70 @@ +update=Monday 22 October 2012 05:17:18 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=special +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=analogSpice +LibName31=converterSpice +LibName32=digitalSpice +LibName33=linearSpice +LibName34=measurementSpice +LibName35=portSpice +LibName36=sourcesSpice diff --git a/OSCAD/Examples/FlipFlops/FlipFlops.proj b/OSCAD/Examples/FlipFlops/FlipFlops.proj new file mode 100644 index 0000000..cc7b7c9 --- /dev/null +++ b/OSCAD/Examples/FlipFlops/FlipFlops.proj @@ -0,0 +1 @@ +schematicFile FlipFlops.sch diff --git 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I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator-cache.lib b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator-cache.lib new file mode 100644 index 0000000..65c560c --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 02 April 2013 02:52:17 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CP +# +DEF CP C 0 10 N N 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "CP" 50 -100 50 H V L CNN +ALIAS CAPAPOL +$FPLIST + CP* + SM* +$ENDFPLIST +DRAW +P 4 0 1 8 -100 50 -100 -50 100 -50 100 50 N +P 4 0 1 0 -50 50 -50 -20 50 -20 50 50 F +X ~ 1 0 200 150 D 40 40 1 1 P +X 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40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.bak b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.bak new file mode 100644 index 0000000..93f021b --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.bak @@ -0,0 +1,252 @@ +EESchema Schematic File Version 2 date Monday 10 December 2012 10:40:22 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice 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+Connection ~ 3750 4100 +$Comp +L VPLOT8_1 U1 +U 2 1 50C4B392 +P 6300 2850 +F 0 "U1" H 6150 2950 50 0000 C CNN +F 1 "VPLOT8_1" H 6450 2950 50 0000 C CNN + 2 6300 2850 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50C4B386 +P 3750 3700 +F 0 "U1" H 3600 3800 50 0000 C CNN +F 1 "VPLOT8_1" H 3900 3800 50 0000 C CNN + 1 3750 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50A93D02 +P 5900 4800 +F 0 "#PWR01" H 5900 4800 30 0001 C CNN +F 1 "GND" H 5900 4730 30 0001 C CNN + 1 5900 4800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 50A93CC0 +P 5700 4300 +F 0 "#FLG02" H 5700 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5700 4530 30 0000 C CNN + 1 5700 4300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 50A93CB7 +P 5200 2650 +F 0 "#FLG03" H 5200 2920 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 2880 30 0000 C CNN + 1 5200 2650 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 50A93C56 +P 2650 3600 +F 0 "v1" H 2450 3700 60 0000 C CNN +F 1 "5" H 2450 3550 60 0000 C CNN +F 2 "R1" H 2350 3600 60 0000 C CNN + 1 2650 3600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A93BFE +P 6300 3800 +F 0 "R3" V 6380 3800 50 0000 C CNN +F 1 "1000" V 6300 3800 50 0000 C CNN + 1 6300 3800 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 50A93ACA +P 4150 4200 +F 0 "C2" H 4200 4300 50 0000 L CNN +F 1 "0.01e-6" H 4200 4100 50 0000 L CNN + 1 4150 4200 + 1 0 0 -1 +$EndComp +$Comp +L CP C1 +U 1 1 50A93893 +P 3500 4350 +F 0 "C1" H 3550 4450 50 0000 L CNN +F 1 "100e-12" H 3550 4250 50 0000 L CNN + 1 3500 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A93858 +P 3500 3750 +F 0 "R2" V 3580 3750 50 0000 C CNN +F 1 "10000" V 3500 3750 50 0000 C CNN + 1 3500 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A93852 +P 3500 3100 +F 0 "R1" V 3580 3100 50 0000 C CNN +F 1 "1000" V 3500 3100 50 0000 C CNN + 1 3500 3100 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X1 +U 1 1 50A937B9 +P 5200 3550 +F 0 "X1" H 5200 3650 70 0000 C CNN +F 1 "LM555N" H 5200 3450 70 0000 C CNN + 1 5200 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.brd b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.brd new file mode 100644 index 0000000..fce068e --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.brd @@ -0,0 +1,84 @@ +PCBNEW-BOARD Version 1 date Tuesday 02 April 2013 02:48:05 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 0 +NoConn 0 +Di 0 0 117000 82670 +Ndraw 0 +Ntrack 0 +Nzone 0 +BoardThickness 630 +Nmodule 0 +Nnets 1 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "2 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +$EndNCLASS +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir new file mode 100644 index 0000000..b1689e6 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 06 June 2013 11:44:39 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 4 IC +U1 4 5 VPLOT8_1 +v1 3 0 5 +R3 5 0 1000 +C2 2 0 0.01e-6 +C1 4 0 100e-12 +R2 6 4 10000 +R1 3 6 1000 +X1 0 4 5 3 2 4 6 3 LM555N + +.end diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir.ckt b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir.ckt new file mode 100644 index 0000000..58dd7f4 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir.ckt @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 06 june 2013 11:44:39 pm ist +.include lm555n.sub + +.ic v(3)=0 + +.ic v(4)=0 +* Plotting option vplot8_1 +v1 3 0 5 +r3 5 0 1000 +c2 2 0 0.01e-6 +c1 4 0 100e-12 +r2 6 4 10000 +r1 3 6 1000 +x1 0 4 5 3 2 4 6 3 lm555n + +.tran 50e-09 5e-06 0e-00 +.plot v(4) v(5) +.end diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir.out b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir.out new file mode 100644 index 0000000..06e4c85 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.cir.out @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 06 june 2013 11:44:39 pm ist +.include lm555n.sub + +.ic v(3)=0 + +.ic v(4)=0 +* Plotting option vplot8_1 +v1 3 0 5 +r3 5 0 1000 +c2 2 0 0.01e-6 +c1 4 0 100e-12 +r2 6 4 10000 +r1 3 6 1000 +x1 0 4 5 3 2 4 6 3 lm555n + +.tran 50e-09 5e-06 0e-00 + +* Control Statements +.control +run +plot v(4) v(5) +.endc +.end diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.net b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.net new file mode 100644 index 0000000..ed060b3 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.net @@ -0,0 +1,110 @@ +# EESchema Netlist Version 1.1 created Tuesday 02 April 2013 02:47:19 PM IST +( + ( /50C55B25 $noname U2 IC {Lib=IC} + ( 1 N-000004 ) + ) + ( /50C4B392 $noname U1 VPLOT8_1 {Lib=VPLOT8_1} + ( 1 N-000004 ) + ( 2 N-000005 ) + ) + ( /50A93C56 R1 v1 5 {Lib=DC} + ( 1 VCC ) + ( 2 GND ) + ) + ( /50A93BFE $noname R3 1000 {Lib=R} + ( 1 N-000005 ) + ( 2 GND ) + ) + ( /50A93ACA $noname C2 0.01e-6 {Lib=C} + ( 1 N-000002 ) + ( 2 GND ) + ) + ( /50A93893 $noname C1 100e-12 {Lib=CP} + ( 1 N-000004 ) + ( 2 GND ) + ) + ( /50A93858 $noname R2 10000 {Lib=R} + ( 1 N-000006 ) + ( 2 N-000004 ) + ) + ( /50A93852 $noname R1 1000 {Lib=R} + ( 1 VCC ) + ( 2 N-000006 ) + ) + ( /50A937B9 $noname X1 LM555N {Lib=LM555N} + ( 1 GND ) + ( 2 N-000004 ) + ( 3 N-000005 ) + ( 4 VCC ) + ( 5 N-000002 ) + ( 6 N-000004 ) + ( 7 N-000006 ) + ( 8 VCC ) + ) +) +* +{ Allowed footprints by component: +$component v1 + 1_pin +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C2 + SM* + C? + C1-1 +$endlist +$component C1 + CP* + SM* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "GND" "GND" + C1 2 + C2 2 + X1 1 + R3 2 + v1 2 +Net 2 "" "" + X1 5 + C2 1 +Net 3 "VCC" "VCC" + X1 4 + R1 1 + X1 8 + v1 1 +Net 4 "" "" + U2 1 + U1 1 + C1 1 + X1 6 + R2 2 + X1 2 +Net 5 "" "" + R3 1 + U1 2 + X1 3 +Net 6 "" "" + X1 7 + R1 2 + R2 1 +} +#End diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.pro b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.pro new file mode 100644 index 0000000..8fb611c --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.pro @@ -0,0 +1,71 @@ +update=Monday 10 December 2012 09:07:41 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=special +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=analogSpice +LibName31=converterSpice +LibName32=digitalSpice +LibName33=linearSpice +LibName34=measurementSpice +LibName35=portSpice +LibName36=sourcesSpice +LibName37=convergenceAidSpice diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.proj b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.proj new file mode 100644 index 0000000..0a193f0 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.proj @@ -0,0 +1 @@ +schematicFile IC555AstableMultivibrator.sch diff --git a/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.sch b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.sch new file mode 100644 index 0000000..9d4e53b --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/IC555AstableMultivibrator.sch @@ -0,0 +1,244 @@ +EESchema Schematic File Version 2 date Tuesday 02 April 2013 02:52:17 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:IC555AstableMultivibrator-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "2 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L IC U2 +U 1 1 50C55B25 +P 4450 4050 +F 0 "U2" H 4450 4320 30 0000 C CNN +F 1 "IC" H 4450 4280 30 0000 C CNN + 1 4450 4050 + 1 0 0 -1 +$EndComp +Connection ~ 4450 4100 +Wire Wire Line + 4450 4050 4450 4100 +Connection ~ 6300 3350 +Wire Wire Line + 6300 3150 6300 3550 +Connection ~ 5700 4550 +Wire Wire Line + 5700 4550 5700 4300 +Wire Wire Line + 2650 4050 2650 4700 +Wire Wire Line + 2650 4700 4850 4700 +Connection ~ 4850 4550 +Wire Wire Line + 4850 4700 4850 4550 +Connection ~ 5200 4550 +Wire Wire Line + 3500 4550 6300 4550 +Wire Wire Line + 6300 4550 6300 4050 +Connection ~ 5200 4400 +Wire Wire Line + 4150 4400 5200 4400 +Connection ~ 4250 2850 +Wire Wire Line + 4250 2850 4250 3850 +Wire Wire Line + 4250 3850 4500 3850 +Wire Wire Line + 5900 3550 6100 3550 +Wire Wire Line + 6100 3550 6100 3000 +Wire Wire Line + 6100 3000 3750 3000 +Wire Wire Line + 3750 3000 3750 3450 +Connection ~ 3500 3450 +Wire Wire Line + 3750 3450 3500 3450 +Connection ~ 3500 4100 +Wire Wire Line + 3950 4100 3950 3350 +Wire Wire Line + 3950 3350 4500 3350 +Wire Wire Line + 3500 4150 3500 4000 +Wire Wire Line + 3500 3500 3500 3350 +Wire Wire Line + 5200 4550 5200 3950 +Wire Wire Line + 5900 3750 5900 4100 +Wire Wire Line + 5900 4100 3500 4100 +Connection ~ 3950 4100 +Wire Wire Line + 5200 2850 3500 2850 +Wire Wire Line + 4150 4000 4150 3600 +Wire Wire Line + 4150 3600 4500 3600 +Wire Wire Line + 6300 3350 5900 3350 +Wire Wire Line + 4450 2850 4450 2700 +Connection ~ 4450 2850 +Wire Wire Line + 4450 2700 2650 2700 +Wire Wire Line + 2650 2700 2650 3150 +Wire Wire Line + 5200 2650 5200 3150 +Connection ~ 5200 2850 +Wire Wire Line + 5900 4550 5900 4800 +Connection ~ 5900 4550 +Wire Wire Line + 3750 4100 3750 4000 +Connection ~ 3750 4100 +$Comp +L VPLOT8_1 U1 +U 2 1 50C4B392 +P 6300 2850 +F 0 "U1" H 6150 2950 50 0000 C CNN +F 1 "VPLOT8_1" H 6450 2950 50 0000 C CNN + 2 6300 2850 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50C4B386 +P 3750 3700 +F 0 "U1" H 3600 3800 50 0000 C CNN +F 1 "VPLOT8_1" H 3900 3800 50 0000 C CNN + 1 3750 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50A93D02 +P 5900 4800 +F 0 "#PWR01" H 5900 4800 30 0001 C CNN +F 1 "GND" H 5900 4730 30 0001 C CNN + 1 5900 4800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 50A93CC0 +P 5700 4300 +F 0 "#FLG02" H 5700 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5700 4530 30 0000 C CNN + 1 5700 4300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 50A93CB7 +P 5200 2650 +F 0 "#FLG03" H 5200 2920 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 2880 30 0000 C CNN + 1 5200 2650 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 50A93C56 +P 2650 3600 +F 0 "v1" H 2450 3700 60 0000 C CNN +F 1 "5" H 2450 3550 60 0000 C CNN +F 2 "R1" H 2350 3600 60 0000 C CNN + 1 2650 3600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A93BFE +P 6300 3800 +F 0 "R3" V 6380 3800 50 0000 C CNN +F 1 "1000" V 6300 3800 50 0000 C CNN + 1 6300 3800 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 50A93ACA +P 4150 4200 +F 0 "C2" H 4200 4300 50 0000 L CNN +F 1 "0.01e-6" H 4200 4100 50 0000 L CNN + 1 4150 4200 + 1 0 0 -1 +$EndComp +$Comp +L CP C1 +U 1 1 50A93893 +P 3500 4350 +F 0 "C1" H 3550 4450 50 0000 L CNN +F 1 "100e-12" H 3550 4250 50 0000 L CNN + 1 3500 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A93858 +P 3500 3750 +F 0 "R2" V 3580 3750 50 0000 C CNN +F 1 "10000" V 3500 3750 50 0000 C CNN + 1 3500 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A93852 +P 3500 3100 +F 0 "R1" V 3580 3100 50 0000 C CNN +F 1 "1000" V 3500 3100 50 0000 C CNN + 1 3500 3100 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X1 +U 1 1 50A937B9 +P 5200 3550 +F 0 "X1" H 5200 3650 70 0000 C CNN +F 1 "LM555N" H 5200 3450 70 0000 C CNN + 1 5200 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/IC555AstableMultivibrator/analysis b/OSCAD/Examples/IC555AstableMultivibrator/analysis new file mode 100644 index 0000000..a715127 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/analysis @@ -0,0 +1,2 @@ +.tran 50e-09 5e-06 0e-00 +.ic v(3)=0 diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n-cache.bak b/OSCAD/Examples/IC555AstableMultivibrator/lm555n-cache.bak new file mode 100644 index 0000000..29460f2 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n-cache.bak @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:00:30 AM IST +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter" 100 100 40 H V C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +# D_SRLatch +# +DEF D_SRLatch U 0 40 Y Y 1 F N +F0 "U" -200 250 60 H V C CNN +F1 "D_SRLatch" 0 100 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X S 1 -600 150 300 R 50 50 1 1 I +X R 2 -600 -150 300 R 50 50 1 1 I +X Enable 3 -600 0 300 R 50 50 1 1 I +X Set 4 150 -500 300 U 50 50 1 1 I +X Reset 5 -150 -500 300 U 50 50 1 1 I +X Q 6 600 150 300 L 50 50 1 1 O +X ~Q 7 600 -150 300 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# DAC8 +# +DEF DAC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "DAC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# LIMIT8 +# +DEF LIMIT8 U 0 40 Y Y 8 F N +F0 "U" 0 100 30 H V C CNN +F1 "LIMIT8" 0 0 30 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in 1 -300 0 150 R 25 25 1 1 I +X out 9 300 0 150 L 25 25 1 1 O +X in 2 -300 0 150 R 25 25 2 1 I +X out 10 300 0 150 L 25 25 2 1 O +X in 3 -300 0 150 R 25 25 3 1 I +X out 11 300 0 150 L 25 25 3 1 O +X in 4 -300 0 150 R 25 25 4 1 I +X out 12 300 0 150 L 25 25 4 1 O +X in 5 -300 0 150 R 25 25 5 1 I +X out 13 300 0 150 L 25 25 5 1 O +X in 6 -300 0 150 R 25 25 6 1 I +X out 14 300 0 150 L 25 25 6 1 O +X in 7 -300 0 150 R 25 25 7 1 I +X out 15 300 0 150 L 25 25 7 1 O +X in 8 -300 0 150 R 25 25 8 1 I +X out 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n-cache.lib b/OSCAD/Examples/IC555AstableMultivibrator/lm555n-cache.lib new file mode 100644 index 0000000..421c114 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n-cache.lib @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:00:43 AM IST +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter" 100 100 40 H V C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +# D_SRLatch +# +DEF D_SRLatch U 0 40 Y Y 1 F N +F0 "U" -200 250 60 H V C CNN +F1 "D_SRLatch" 0 100 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X S 1 -600 150 300 R 50 50 1 1 I +X R 2 -600 -150 300 R 50 50 1 1 I +X Enable 3 -600 0 300 R 50 50 1 1 I +X Set 4 150 -500 300 U 50 50 1 1 I +X Reset 5 -150 -500 300 U 50 50 1 1 I +X Q 6 600 150 300 L 50 50 1 1 O +X ~Q 7 600 -150 300 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# DAC8 +# +DEF DAC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "DAC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# LIMIT8 +# +DEF LIMIT8 U 0 40 Y Y 8 F N +F0 "U" 0 100 30 H V C CNN +F1 "LIMIT8" 0 0 30 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in 1 -300 0 150 R 25 25 1 1 I +X out 9 300 0 150 L 25 25 1 1 O +X in 2 -300 0 150 R 25 25 2 1 I +X out 10 300 0 150 L 25 25 2 1 O +X in 3 -300 0 150 R 25 25 3 1 I +X out 11 300 0 150 L 25 25 3 1 O +X in 4 -300 0 150 R 25 25 4 1 I +X out 12 300 0 150 L 25 25 4 1 O +X in 5 -300 0 150 R 25 25 5 1 I +X out 13 300 0 150 L 25 25 5 1 O +X in 6 -300 0 150 R 25 25 6 1 I +X out 14 300 0 150 L 25 25 6 1 O +X in 7 -300 0 150 R 25 25 7 1 I +X out 15 300 0 150 L 25 25 7 1 O +X in 8 -300 0 150 R 25 25 8 1 I +X out 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.bak b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.bak new file mode 100644 index 0000000..6b8426e --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.bak @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:00:30 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir new file mode 100644 index 0000000..144b715 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir @@ -0,0 +1,25 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:00:36 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 21 D_INVERTER +U6 1 4 5 21 21 8 10 D_SRLATCH +E2 18 0 23 14 10000 +U4 19 20 11 12 LIMIT8 +U3 8 10 7 9 DAC8 +U2 11 12 6 4 1 5 ADC8 +U1 22 14 7 6 15 16 3 13 PORT +R8 9 2 1500 +Q1 22 2 3 QNOM +R7 18 20 25 +R6 17 19 25 +E1 17 0 16 15 10000 +R4 16 15 2E6 +R5 23 14 2E6 +R3 23 22 5000 +R2 15 23 5000 +R1 13 15 5000 + +.end diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir.ckt b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir.ckt new file mode 100644 index 0000000..f45920f --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir.ckt @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir.out b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir.out new file mode 100644 index 0000000..f45920f --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.cir.out @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.pro b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.pro new file mode 100644 index 0000000..09fa54e --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.pro @@ -0,0 +1,73 @@ +update=Monday 19 November 2012 04:56:38 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=analogXSpice +LibName33=converterSpice +LibName34=digitalSpice +LibName35=linearSpice +LibName36=measurementSpice +LibName37=portSpice +LibName38=sourcesSpice +LibName39=digitalXSpice diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.sch b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.sch new file mode 100644 index 0000000..417063b --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:00:43 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 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4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/IC555AstableMultivibrator/lm555n.sub b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.sub new file mode 100644 index 0000000..beeefc4 --- /dev/null +++ b/OSCAD/Examples/IC555AstableMultivibrator/lm555n.sub @@ -0,0 +1,37 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.ends lm555n
\ No newline at end of file diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier-cache.bak b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier-cache.bak new file mode 100644 index 0000000..0c195d8 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:09:30 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier-cache.lib b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier-cache.lib new file mode 100644 index 0000000..fbea033 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:36:39 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.bak b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.bak new file mode 100644 index 0000000..54b3539 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.bak @@ -0,0 +1,194 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:09:30 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:InvertingAmplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4300 3550 +Wire Wire Line + 4300 3550 3400 3550 +Wire Wire Line + 3400 3550 3400 3100 +Wire Wire Line + 6550 3400 6550 4050 +Wire Wire Line + 6550 4050 6050 4050 +Wire Wire Line + 6850 4150 6850 4400 +Connection ~ 5150 3500 +Wire Wire Line + 5550 4050 5150 4050 +Wire Wire Line + 5150 4050 5150 3500 +Wire Wire Line + 4300 3400 4300 3300 +Wire Wire Line + 4300 3300 5300 3300 +Wire Wire Line + 4400 3500 4300 3500 +Wire Wire Line + 4300 3500 4300 3650 +Wire Wire Line + 4900 3500 5300 3500 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 4600 4400 4600 4650 +Wire Wire Line + 4600 4650 4300 4650 +Connection ~ 4300 4650 +Connection ~ 6850 3400 +Wire Wire Line + 6850 3100 6850 3650 +Wire Wire Line + 6300 3400 6850 3400 +Connection ~ 6550 3400 +$Comp +L GND #PWR01 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR01" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 3400 2800 +F 0 "U1" H 3250 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 3550 2900 50 0000 C CNN + 1 3400 2800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG02" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240CB +P 4300 3400 +F 0 "#PWR03" H 4300 3400 30 0001 C CNN +F 1 "GND" H 4300 3330 30 0001 C CNN + 1 4300 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR04" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 50824091 +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "SINE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4650 3500 +F 0 "R1" V 4730 3500 50 0000 C CNN +F 1 "1000" V 4650 3500 50 0000 C CNN + 1 4650 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir new file mode 100644 index 0000000..f995c1d --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir @@ -0,0 +1,14 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 19 December 2012 10:36:45 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 3 4 VPLOT8_1 +X1 2 0 4 UA741 +v1 3 0 SINE +R3 4 0 10000 +R1 2 3 1000 +R2 4 2 2000 + +.end diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir.ckt b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir.ckt new file mode 100644 index 0000000..543e15f --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 19 december 2012 10:36:45 am ist +.include ua741.sub + +* Plotting option vplot8_1 +x1 2 0 4 ua741 +v1 3 0 sine(0 5 50 0 0) +r3 4 0 10000 +r1 2 3 1000 +r2 4 2 2000 + +.tran 100e-06 40e-03 0e-00 +.plot v(3) v(4) +.end diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir.out b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir.out new file mode 100644 index 0000000..e67a64a --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 19 december 2012 10:36:45 am ist +.include ua741.sub + +* Plotting option vplot8_1 +x1 2 0 4 ua741 +v1 3 0 sine(0 5 50 0 0) +r3 4 0 10000 +r1 2 3 1000 +r2 4 2 2000 + +.tran 100e-06 40e-03 0e-00 + +* Control Statements +.control +run +plot v(3) v(4) +.endc +.end diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cmp b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cmp new file mode 100644 index 0000000..c3e04af --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.cmp @@ -0,0 +1,38 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Saturday 20 October 2012 11:59:17 AM IST + +BeginCmp +TimeStamp = /50824062; +Reference = R1; +ValeurCmp = 1000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824045; +Reference = R2; +ValeurCmp = 2000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824073; +Reference = R3; +ValeurCmp = 10000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824091; +Reference = v1; +ValeurCmp = SINE; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /50823E96; +Reference = X1; +ValeurCmp = LM741; +IdModule = DIP-8__300; +EndCmp + +EndListe diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.net b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.net new file mode 100644 index 0000000..938591e --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.net @@ -0,0 +1,70 @@ +# EESchema Netlist Version 1.1 created Saturday 20 October 2012 12:03:26 PM IST +( + ( /50824595 $noname X1 UA741 {Lib=UA741} + ( 2 N-000004 ) + ( 3 GND ) + ( 6 N-000001 ) + ) + ( /50824091 R1 v1 SINE {Lib=SINE} + ( 1 N-000002 ) + ( 2 GND ) + ) + ( /50824073 $noname R3 10000 {Lib=R} + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /50824062 $noname R1 1000 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000002 ) + ) + ( /50824045 $noname R2 2000 {Lib=R} + ( 1 N-000001 ) + ( 2 N-000004 ) + ) +) +* +{ Allowed footprints by component: +$component X1 + DIP-8__300 +$endlist +$component v1 + 1_pin +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R2 1 + X1 6 + R3 1 +Net 2 "" "" + R1 2 + v1 1 +Net 3 "GND" "GND" + X1 3 + v1 2 + R3 2 +Net 4 "" "" + X1 2 + R1 1 + R2 2 +} +#End diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.pro b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.pro new file mode 100644 index 0000000..9f5d056 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:16:29 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.proj b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.proj new file mode 100644 index 0000000..c78c533 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.proj @@ -0,0 +1 @@ +schematicFile InvertingAmplifier.sch diff --git a/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.sch b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.sch new file mode 100644 index 0000000..9b6032d --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/InvertingAmplifier.sch @@ -0,0 +1,194 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:36:39 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:InvertingAmplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4300 3550 +Wire Wire Line + 4300 3550 3400 3550 +Wire Wire Line + 3400 3550 3400 3100 +Wire Wire Line + 6550 3400 6550 4050 +Wire Wire Line + 6550 4050 6050 4050 +Wire Wire Line + 6850 4150 6850 4400 +Connection ~ 5150 3500 +Wire Wire Line + 5550 4050 5150 4050 +Wire Wire Line + 5150 4050 5150 3500 +Wire Wire Line + 4300 3400 4300 3300 +Wire Wire Line + 4300 3300 5300 3300 +Wire Wire Line + 4400 3500 4300 3500 +Wire Wire Line + 4300 3500 4300 3650 +Wire Wire Line + 4900 3500 5300 3500 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 4600 4400 4600 4650 +Wire Wire Line + 4600 4650 4300 4650 +Connection ~ 4300 4650 +Connection ~ 6850 3400 +Wire Wire Line + 6850 3100 6850 3650 +Wire Wire Line + 6300 3400 6850 3400 +Connection ~ 6550 3400 +$Comp +L GND #PWR01 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR01" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 3400 2800 +F 0 "U1" H 3250 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 3550 2900 50 0000 C CNN + 1 3400 2800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG02" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240CB +P 4300 3400 +F 0 "#PWR03" H 4300 3400 30 0001 C CNN +F 1 "GND" H 4300 3330 30 0001 C CNN + 1 4300 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR04" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 50824091 +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "SINE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4650 3500 +F 0 "R1" V 4730 3500 50 0000 C CNN +F 1 "1000" V 4650 3500 50 0000 C CNN + 1 4650 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/InvertingAmplifier/analysis b/OSCAD/Examples/InvertingAmplifier/analysis new file mode 100644 index 0000000..888b3aa --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/analysis @@ -0,0 +1 @@ +.tran 100e-06 40e-03 0e-00 diff --git a/OSCAD/Examples/InvertingAmplifier/ua741-cache.bak b/OSCAD/Examples/InvertingAmplifier/ua741-cache.bak new file mode 100644 index 0000000..e2ece32 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741-cache.bak @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:17:01 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/InvertingAmplifier/ua741-cache.lib b/OSCAD/Examples/InvertingAmplifier/ua741-cache.lib new file mode 100644 index 0000000..cbec3a5 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:15:16 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/InvertingAmplifier/ua741.bak b/OSCAD/Examples/InvertingAmplifier/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice 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CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/InvertingAmplifier/ua741.cir b/OSCAD/Examples/InvertingAmplifier/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/InvertingAmplifier/ua741.cir.ckt b/OSCAD/Examples/InvertingAmplifier/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/InvertingAmplifier/ua741.cir.out b/OSCAD/Examples/InvertingAmplifier/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/InvertingAmplifier/ua741.pro b/OSCAD/Examples/InvertingAmplifier/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/InvertingAmplifier/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 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\ No newline at end of file diff --git a/OSCAD/Examples/RC/RC-cache.bak b/OSCAD/Examples/RC/RC-cache.bak new file mode 100644 index 0000000..65af569 --- /dev/null +++ b/OSCAD/Examples/RC/RC-cache.bak @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 24 May 2013 02:53:57 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/RC/RC-cache.lib b/OSCAD/Examples/RC/RC-cache.lib new file mode 100644 index 0000000..e808d27 --- /dev/null +++ b/OSCAD/Examples/RC/RC-cache.lib @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 24 May 2013 02:54:22 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/RC/RC.bak b/OSCAD/Examples/RC/RC.bak new file mode 100644 index 0000000..4b41a9e --- /dev/null +++ b/OSCAD/Examples/RC/RC.bak @@ -0,0 +1,136 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 02:53:57 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:RC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4650 2650 +Connection ~ 5900 2650 +$Comp +L SINE v1 +U 1 1 519F2A93 +P 4650 3100 +F 0 "v1" H 4450 3200 60 0000 C CNN +F 1 "SINE" H 4450 3050 60 0000 C CNN +F 2 "R1" H 4350 3100 60 0000 C CNN + 1 4650 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 3300 5900 3550 +Wire Wire Line + 5600 2650 5900 2650 +Connection ~ 5400 3550 +Wire Wire Line + 5400 3550 5400 3800 +Wire Wire Line + 5900 3550 4650 3550 +Wire Wire Line + 4650 2650 5100 2650 +Wire Wire Line + 5900 2650 5900 2900 +$Comp +L VPLOT8_1 U1 +U 2 1 519F22B7 +P 5900 2350 +F 0 "U1" H 5750 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 6050 2450 50 0000 C CNN + 2 5900 2350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 519F229B +P 5400 3550 +F 0 "#FLG1" H 5400 3820 30 0001 C CNN +F 1 "PWR_FLAG" H 5400 3780 30 0000 C CNN + 1 5400 3550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 519F2294 +P 5400 3800 +F 0 "#PWR1" H 5400 3800 30 0001 C CNN +F 1 "GND" H 5400 3730 30 0001 C CNN + 1 5400 3800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 519F228E +P 4650 2350 +F 0 "U1" H 4500 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 4800 2450 50 0000 C CNN + 1 4650 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 519F2283 +P 5350 2650 +F 0 "R1" V 5430 2650 50 0000 C CNN +F 1 "1k" V 5350 2650 50 0000 C CNN + 1 5350 2650 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 519F227E +P 5900 3100 +F 0 "C1" H 5950 3200 50 0000 L CNN +F 1 "1u" H 5950 3000 50 0000 L CNN + 1 5900 3100 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/RC/RC.cir b/OSCAD/Examples/RC/RC.cir new file mode 100644 index 0000000..17738ac --- /dev/null +++ b/OSCAD/Examples/RC/RC.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 24 May 2013 02:23:51 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 1 0 SINE +U1 1 3 VPLOT8_1 +R1 3 1 1k +C1 0 3 1u + +.end diff --git a/OSCAD/Examples/RC/RC.cir.ckt b/OSCAD/Examples/RC/RC.cir.ckt new file mode 100644 index 0000000..7a8138f --- /dev/null +++ b/OSCAD/Examples/RC/RC.cir.ckt @@ -0,0 +1,10 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:23:51 pm ist
+
+v1 1 0 sine(0 5 300 0 0)
+* Plotting option vplot8_1
+r1 3 1 1k
+c1 0 3 1u
+
+.tran 5e-03 30e-03 0e-00
+.plot v(1) v(3)
+.end
diff --git a/OSCAD/Examples/RC/RC.cir.out b/OSCAD/Examples/RC/RC.cir.out new file mode 100644 index 0000000..01e68ad --- /dev/null +++ b/OSCAD/Examples/RC/RC.cir.out @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:23:51 pm ist
+
+v1 1 0 sine(0 5 300 0 0)
+* Plotting option vplot8_1
+r1 3 1 1k
+c1 0 3 1u
+
+.tran 5e-03 30e-03 0e-00
+
+* Control Statements
+.control
+run
+plot v(1) v(3)
+.endc
+.end
diff --git a/OSCAD/Examples/RC/RC.pro b/OSCAD/Examples/RC/RC.pro new file mode 100644 index 0000000..cfb5fa1 --- /dev/null +++ b/OSCAD/Examples/RC/RC.pro @@ -0,0 +1,74 @@ +update=Friday 24 May 2013 02:22:07 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/RC/RC.proj b/OSCAD/Examples/RC/RC.proj new file mode 100644 index 0000000..396e6d0 --- /dev/null +++ b/OSCAD/Examples/RC/RC.proj @@ -0,0 +1 @@ +schematicFile RC.sch diff --git a/OSCAD/Examples/RC/RC.sch b/OSCAD/Examples/RC/RC.sch new file mode 100644 index 0000000..6afd4fa --- /dev/null +++ b/OSCAD/Examples/RC/RC.sch @@ -0,0 +1,137 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 02:54:22 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:RC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5200 3550 +Connection ~ 4650 2650 +Connection ~ 5900 2650 +$Comp +L SINE v1 +U 1 1 519F2A93 +P 4650 3100 +F 0 "v1" H 4450 3200 60 0000 C CNN +F 1 "SINE" H 4450 3050 60 0000 C CNN +F 2 "R1" H 4350 3100 60 0000 C CNN + 1 4650 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 3300 5900 3550 +Wire Wire Line + 5600 2650 5900 2650 +Connection ~ 5400 3550 +Wire Wire Line + 5400 3550 5400 3800 +Wire Wire Line + 5900 3550 4650 3550 +Wire Wire Line + 4650 2650 5100 2650 +Wire Wire Line + 5900 2650 5900 2900 +$Comp +L VPLOT8_1 U1 +U 2 1 519F22B7 +P 5900 2350 +F 0 "U1" H 5750 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 6050 2450 50 0000 C CNN + 2 5900 2350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 519F229B +P 5200 3550 +F 0 "#FLG1" H 5200 3820 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 3780 30 0000 C CNN + 1 5200 3550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 519F2294 +P 5400 3800 +F 0 "#PWR1" H 5400 3800 30 0001 C CNN +F 1 "GND" H 5400 3730 30 0001 C CNN + 1 5400 3800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 519F228E +P 4650 2350 +F 0 "U1" H 4500 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 4800 2450 50 0000 C CNN + 1 4650 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 519F2283 +P 5350 2650 +F 0 "R1" V 5430 2650 50 0000 C CNN +F 1 "1k" V 5350 2650 50 0000 C CNN + 1 5350 2650 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 519F227E +P 5900 3100 +F 0 "C1" H 5950 3200 50 0000 L CNN +F 1 "1u" H 5950 3000 50 0000 L CNN + 1 5900 3100 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/RC/analysis b/OSCAD/Examples/RC/analysis new file mode 100644 index 0000000..4d26811 --- /dev/null +++ b/OSCAD/Examples/RC/analysis @@ -0,0 +1 @@ +.tran 5e-03 30e-03 0e-00
diff --git a/OSCAD/Examples/RC_ac/RC_ac-cache.bak b/OSCAD/Examples/RC_ac/RC_ac-cache.bak new file mode 100644 index 0000000..8073555 --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac-cache.bak @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 24 May 2013 01:55:44 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/RC_ac/RC_ac-cache.lib b/OSCAD/Examples/RC_ac/RC_ac-cache.lib new file mode 100644 index 0000000..0dca988 --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac-cache.lib @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 24 May 2013 01:59:22 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/RC_ac/RC_ac.bak b/OSCAD/Examples/RC_ac/RC_ac.bak new file mode 100644 index 0000000..037cb21 --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.bak @@ -0,0 +1,136 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 01:55:44 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:RC_ac-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 3300 5900 3550 +Wire Wire Line + 5600 2650 5900 2650 +Connection ~ 4900 2650 +Connection ~ 5750 2650 +Connection ~ 5400 3550 +Wire Wire Line + 5400 3550 5400 3800 +Wire Wire Line + 5900 3550 4650 3550 +Wire Wire Line + 4650 2650 5100 2650 +Wire Wire Line + 5900 2650 5900 2900 +$Comp +L VPLOT8_1 U1 +U 2 1 519F22B7 +P 5750 2350 +F 0 "U1" H 5600 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 2450 50 0000 C CNN + 2 5750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 519F229B +P 5400 3550 +F 0 "#FLG01" H 5400 3820 30 0001 C CNN +F 1 "PWR_FLAG" H 5400 3780 30 0000 C CNN + 1 5400 3550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 519F2294 +P 5400 3800 +F 0 "#PWR02" H 5400 3800 30 0001 C CNN +F 1 "GND" H 5400 3730 30 0001 C CNN + 1 5400 3800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 519F228E +P 4900 2350 +F 0 "U1" H 4750 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 5050 2450 50 0000 C CNN + 1 4900 2350 + 1 0 0 -1 +$EndComp +$Comp +L AC v1 +U 1 1 519F2287 +P 4650 3100 +F 0 "v1" H 4450 3200 60 0000 C CNN +F 1 "AC" H 4450 3050 60 0000 C CNN +F 2 "R1" H 4350 3100 60 0000 C CNN + 1 4650 3100 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 519F2283 +P 5350 2650 +F 0 "R1" V 5430 2650 50 0000 C CNN +F 1 "R" V 5350 2650 50 0000 C CNN + 1 5350 2650 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 519F227E +P 5900 3100 +F 0 "C1" H 5950 3200 50 0000 L CNN +F 1 "C" H 5950 3000 50 0000 L CNN + 1 5900 3100 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/RC_ac/RC_ac.cir b/OSCAD/Examples/RC_ac/RC_ac.cir new file mode 100644 index 0000000..5393d72 --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 24 May 2013 01:58:56 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 1 3 VPLOT8_1 +v1 1 0 AC +R1 3 1 1k +C1 0 3 1u + +.end diff --git a/OSCAD/Examples/RC_ac/RC_ac.cir.ckt b/OSCAD/Examples/RC_ac/RC_ac.cir.ckt new file mode 100644 index 0000000..8cbaa41 --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.cir.ckt @@ -0,0 +1,10 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 01:58:56 pm ist
+
+* Plotting option vplot8_1
+v1 1 0 ac 2
+r1 3 1 1k
+c1 0 3 1u
+
+.ac lin 10 1Hz 10Meg
+.plot v(1) v(3)
+.end
diff --git a/OSCAD/Examples/RC_ac/RC_ac.cir.out b/OSCAD/Examples/RC_ac/RC_ac.cir.out new file mode 100644 index 0000000..ad45dbf --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.cir.out @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 01:58:56 pm ist
+
+* Plotting option vplot8_1
+v1 1 0 ac 2
+r1 3 1 1k
+c1 0 3 1u
+
+.ac lin 10 1Hz 10Meg
+
+* Control Statements
+.control
+run
+plot v(1) v(3)
+.endc
+.end
diff --git a/OSCAD/Examples/RC_ac/RC_ac.pro b/OSCAD/Examples/RC_ac/RC_ac.pro new file mode 100644 index 0000000..270d2dd --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.pro @@ -0,0 +1,74 @@ +update=Friday 24 May 2013 01:49:03 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/RC_ac/RC_ac.proj b/OSCAD/Examples/RC_ac/RC_ac.proj new file mode 100644 index 0000000..3b990b8 --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.proj @@ -0,0 +1 @@ +schematicFile RC_ac.sch diff --git a/OSCAD/Examples/RC_ac/RC_ac.sch b/OSCAD/Examples/RC_ac/RC_ac.sch new file mode 100644 index 0000000..8d14d8e --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.sch @@ -0,0 +1,136 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 01:59:22 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:RC_ac-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 3300 5900 3550 +Wire Wire Line + 5600 2650 5900 2650 +Connection ~ 4900 2650 +Connection ~ 5750 2650 +Connection ~ 5400 3550 +Wire Wire Line + 5400 3550 5400 3800 +Wire Wire Line + 5900 3550 4650 3550 +Wire Wire Line + 4650 2650 5100 2650 +Wire Wire Line + 5900 2650 5900 2900 +$Comp +L VPLOT8_1 U1 +U 2 1 519F22B7 +P 5750 2350 +F 0 "U1" H 5600 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 2450 50 0000 C CNN + 2 5750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 519F229B +P 5400 3550 +F 0 "#FLG01" H 5400 3820 30 0001 C CNN +F 1 "PWR_FLAG" H 5400 3780 30 0000 C CNN + 1 5400 3550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 519F2294 +P 5400 3800 +F 0 "#PWR02" H 5400 3800 30 0001 C CNN +F 1 "GND" H 5400 3730 30 0001 C CNN + 1 5400 3800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 519F228E +P 4900 2350 +F 0 "U1" H 4750 2450 50 0000 C CNN +F 1 "VPLOT8_1" H 5050 2450 50 0000 C CNN + 1 4900 2350 + 1 0 0 -1 +$EndComp +$Comp +L AC v1 +U 1 1 519F2287 +P 4650 3100 +F 0 "v1" H 4450 3200 60 0000 C CNN +F 1 "AC" H 4450 3050 60 0000 C CNN +F 2 "R1" H 4350 3100 60 0000 C CNN + 1 4650 3100 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 519F2283 +P 5350 2650 +F 0 "R1" V 5430 2650 50 0000 C CNN +F 1 "1k" V 5350 2650 50 0000 C CNN + 1 5350 2650 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 519F227E +P 5900 3100 +F 0 "C1" H 5950 3200 50 0000 L CNN +F 1 "1u" H 5950 3000 50 0000 L CNN + 1 5900 3100 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/RC_ac/analysis b/OSCAD/Examples/RC_ac/analysis new file mode 100644 index 0000000..2f4e6f2 --- /dev/null +++ b/OSCAD/Examples/RC_ac/analysis @@ -0,0 +1,2 @@ + +.ac lin 10 1Hz 10Meg diff --git a/OSCAD/Examples/RC_pcb/$savepcb.000 b/OSCAD/Examples/RC_pcb/$savepcb.000 new file mode 100644 index 0000000..8c07ce1 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/$savepcb.000 @@ -0,0 +1,203 @@ +PCBNEW-BOARD Version 1 date Thursday 16 May 2013 12:19:27 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 3 +NoConn 3 +Di -1875 -1494 1875 721 +Ndraw 0 +Ntrack 0 +Nzone 0 +BoardThickness 630 +Nmodule 3 +Nnets 4 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "16 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 315 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000001" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 315 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000001" +AddNet "N-000003" +$EndNCLASS +$MODULE SIL-2 +Po 0 0 0 15 00200000 51947CAE ~~ +Li SIL-2 +Cd Connecteurs 2 pins +Kw CONN DEV +Sc 51947CAE +AR /51868B92 +Op 0 0 0 +T0 0 -1000 681 428 0 107 N V 21 N "P1" +T1 0 -1000 600 400 0 100 N I 21 N "CONN_2" +DS -1000 500 -1000 -500 120 21 +DS -1000 -500 1000 -500 120 21 +DS 1000 -500 1000 500 120 21 +DS 1000 500 -1000 500 120 21 +$PAD +Sh "1" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 500 0 +$EndPAD +$EndMODULE SIL-2 +$MODULE R3 +Po 0 0 0 15 00200000 51947CAF ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 51947CAF +AR /51863417 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R1" +T1 0 0 550 500 0 80 N I 21 N "1k" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE C1 +Po 0 0 0 15 3F92C496 51947CB0 ~~ +Li C1 +Cd Condensateur e = 1 pas +Kw C +Sc 51947CB0 +AR /5186342E +Op 0 0 0 +T0 100 -900 400 400 0 80 N V 21 N "C1" +T1 0 -900 400 400 0 80 N I 21 N "1u" +DS -980 -500 1000 -500 120 21 +DS 1000 -500 1000 500 120 21 +DS 1000 500 -1000 500 120 21 +DS -1000 500 -1000 -500 120 21 +DS -1000 -250 -750 -500 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/capa_1_pas.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE C1 +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/RC_pcb/$savepcb.brd b/OSCAD/Examples/RC_pcb/$savepcb.brd new file mode 100644 index 0000000..22858c3 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/$savepcb.brd @@ -0,0 +1,203 @@ +PCBNEW-BOARD Version 1 date Thursday 16 May 2013 12:56:45 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 3 +NoConn 3 +Di -1875 -1494 1875 721 +Ndraw 0 +Ntrack 0 +Nzone 0 +BoardThickness 630 +Nmodule 3 +Nnets 4 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "16 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 315 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000001" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 315 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000001" +AddNet "N-000003" +$EndNCLASS +$MODULE SIL-2 +Po 0 0 0 15 00200000 51947CAE ~~ +Li SIL-2 +Cd Connecteurs 2 pins +Kw CONN DEV +Sc 51947CAE +AR /51868B92 +Op 0 0 0 +T0 0 -1000 681 428 0 107 N V 21 N "P1" +T1 0 -1000 600 400 0 100 N I 21 N "CONN_2" +DS -1000 500 -1000 -500 120 21 +DS -1000 -500 1000 -500 120 21 +DS 1000 -500 1000 500 120 21 +DS 1000 500 -1000 500 120 21 +$PAD +Sh "1" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 500 0 +$EndPAD +$EndMODULE SIL-2 +$MODULE R3 +Po 0 0 0 15 00200000 51947CAF ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 51947CAF +AR /51863417 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R1" +T1 0 0 550 500 0 80 N I 21 N "1k" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE C1 +Po 0 0 0 15 3F92C496 51947CB0 ~~ +Li C1 +Cd Condensateur e = 1 pas +Kw C +Sc 51947CB0 +AR /5186342E +Op 0 0 0 +T0 100 -900 400 400 0 80 N V 21 N "C1" +T1 0 -900 400 400 0 80 N I 21 N "1u" +DS -980 -500 1000 -500 120 21 +DS 1000 -500 1000 500 120 21 +DS 1000 500 -1000 500 120 21 +DS -1000 500 -1000 -500 120 21 +DS -1000 -250 -750 -500 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/capa_1_pas.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE C1 +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/RC_pcb/RC-SilkS_Back.gbo b/OSCAD/Examples/RC_pcb/RC-SilkS_Back.gbo new file mode 100644 index 0000000..9f1f35b --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC-SilkS_Back.gbo @@ -0,0 +1,12 @@ +G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST* +G01* +G70* +G90* +%MOIN*% +G04 Gerber Fmt 3.4, Leading zero omitted, Abs format* +%FSLAX34Y34*% +G04 APERTURE LIST* +%ADD10C,0.006000*% +G04 APERTURE END LIST* +G54D10* +M02* diff --git a/OSCAD/Examples/RC_pcb/RC-SilkS_Front.gto b/OSCAD/Examples/RC_pcb/RC-SilkS_Front.gto new file mode 100644 index 0000000..95cd1a3 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC-SilkS_Front.gto @@ -0,0 +1,113 @@ +G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST* +G01* +G70* +G90* +%MOIN*% +G04 Gerber Fmt 3.4, Leading zero omitted, Abs format* +%FSLAX34Y34*% +G04 APERTURE LIST* +%ADD10C,0.006000*% +%ADD11C,0.012000*% +%ADD12C,0.010700*% +%ADD13C,0.008000*% +G04 APERTURE END LIST* +G54D10* +G54D11* +X61500Y-38000D02* +X60500Y-38000D01* +X60500Y-38000D02* +X60500Y-36000D01* +X60500Y-36000D02* +X61500Y-36000D01* +X61500Y-36000D02* +X61500Y-38000D01* +X57000Y-35500D02* +X57200Y-35500D01* +X60000Y-35500D02* +X59800Y-35500D01* +X59800Y-35500D02* +X59800Y-35100D01* +X59800Y-35100D02* +X57200Y-35100D01* +X57200Y-35100D02* +X57200Y-35900D01* +X57200Y-35900D02* +X59800Y-35900D01* +X59800Y-35900D02* +X59800Y-35500D01* +X57200Y-35300D02* +X57400Y-35100D01* +X56520Y-37000D02* +X58500Y-37000D01* +X58500Y-37000D02* +X58500Y-38000D01* +X58500Y-38000D02* +X56500Y-38000D01* +X56500Y-38000D02* +X56500Y-37000D01* +X56500Y-37250D02* +X56750Y-37000D01* +G54D12* +X60275Y-37316D02* +X59594Y-37316D01* +X59594Y-37153D01* +X59627Y-37112D01* +X59659Y-37092D01* +X59724Y-37072D01* +X59821Y-37072D01* +X59886Y-37092D01* +X59918Y-37112D01* +X59951Y-37153D01* +X59951Y-37316D01* +X60275Y-36664D02* +X60275Y-36908D01* +X60275Y-36786D02* +X59594Y-36786D01* +X59691Y-36827D01* +X59756Y-36868D01* +X59789Y-36908D01* +G54D13* +X58417Y-35723D02* +X58250Y-35461D01* +X58131Y-35723D02* +X58131Y-35173D01* +X58322Y-35173D01* +X58369Y-35199D01* +X58393Y-35225D01* +X58417Y-35277D01* +X58417Y-35356D01* +X58393Y-35408D01* +X58369Y-35435D01* +X58322Y-35461D01* +X58131Y-35461D01* +X58893Y-35723D02* +X58607Y-35723D01* +X58750Y-35723D02* +X58750Y-35173D01* +X58702Y-35251D01* +X58655Y-35304D01* +X58607Y-35330D01* +X57534Y-36724D02* +X57515Y-36743D01* +X57458Y-36762D01* +X57420Y-36762D01* +X57362Y-36743D01* +X57324Y-36705D01* +X57305Y-36667D01* +X57286Y-36590D01* +X57286Y-36533D01* +X57305Y-36457D01* +X57324Y-36419D01* +X57362Y-36381D01* +X57420Y-36362D01* +X57458Y-36362D01* +X57515Y-36381D01* +X57534Y-36400D01* +X57915Y-36762D02* +X57686Y-36762D01* +X57800Y-36762D02* +X57800Y-36362D01* +X57762Y-36419D01* +X57724Y-36457D01* +X57686Y-36476D01* +M02* diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-Back.gbl b/OSCAD/Examples/RC_pcb/RC_pcb-Back.gbl new file mode 100644 index 0000000..020cb57 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb-Back.gbl @@ -0,0 +1,30 @@ +G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST* +G01* +G70* +G90* +%MOIN*% +G04 Gerber Fmt 3.4, Leading zero omitted, Abs format* +%FSLAX34Y34*% +G04 APERTURE LIST* +%ADD10C,0.006000*% +%ADD11R,0.055000X0.055000*% +%ADD12C,0.055000*% +%ADD13C,0.031500*% +G04 APERTURE END LIST* +G54D10* +G54D11* +X61000Y-37500D03* +G54D12* +X61000Y-36500D03* +X57000Y-35500D03* +X60000Y-35500D03* +X57000Y-37500D03* +X58000Y-37500D03* +G54D13* +X58000Y-37500D02* +X61000Y-37500D01* +X57000Y-35500D02* +X57000Y-37500D01* +X60000Y-35500D02* +X61000Y-36500D01* +M02* diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-Front.gtl b/OSCAD/Examples/RC_pcb/RC_pcb-Front.gtl new file mode 100644 index 0000000..3f06326 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb-Front.gtl @@ -0,0 +1,22 @@ +G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST* +G01* +G70* +G90* +%MOIN*% +G04 Gerber Fmt 3.4, Leading zero omitted, Abs format* +%FSLAX34Y34*% +G04 APERTURE LIST* +%ADD10C,0.006000*% +%ADD11R,0.055000X0.055000*% +%ADD12C,0.055000*% +G04 APERTURE END LIST* +G54D10* +G54D11* +X61000Y-37500D03* +G54D12* +X61000Y-36500D03* +X57000Y-35500D03* +X60000Y-35500D03* +X57000Y-37500D03* +X58000Y-37500D03* +M02* diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-cache.bak b/OSCAD/Examples/RC_pcb/RC_pcb-cache.bak new file mode 100644 index 0000000..3b20495 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb-cache.bak @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 12:09:45 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CONN_2 +# +DEF CONN_2 P 0 40 Y N 1 F N +F0 "P" -50 0 40 V V C CNN +F1 "CONN_2" 50 0 40 V V C CNN +DRAW +S -100 150 100 -150 0 1 0 N +X P1 1 -350 100 250 R 60 60 1 1 P I +X PM 2 -350 -100 250 R 60 60 1 1 P I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-cache.lib b/OSCAD/Examples/RC_pcb/RC_pcb-cache.lib new file mode 100644 index 0000000..a8a529e --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:47:37 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CONN_2 +# +DEF CONN_2 P 0 40 Y N 1 F N +F0 "P" -50 0 40 V V C CNN +F1 "CONN_2" 50 0 40 V V C CNN +DRAW +S -100 150 100 -150 0 1 0 N +X P1 1 -350 100 250 R 60 60 1 1 P I +X PM 2 -350 -100 250 R 60 60 1 1 P I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.bak b/OSCAD/Examples/RC_pcb/RC_pcb.bak new file mode 100644 index 0000000..7ad2473 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.bak @@ -0,0 +1,125 @@ +EESchema Schematic File Version 2 date Tuesday 14 May 2013 12:09:45 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:RC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6100 2200 6100 2050 +Wire Wire Line + 4900 2600 4900 3050 +Connection ~ 6100 2050 +Connection ~ 5550 3050 +Wire Wire Line + 5550 3050 5550 3200 +Wire Wire Line + 6100 2600 6100 3050 +Wire Wire Line + 6100 3050 4900 3050 +Wire Wire Line + 5400 2050 5400 2000 +Wire Wire Line + 5400 2000 4900 2000 +Wire Wire Line + 6100 2050 5900 2050 +Wire Wire Line + 5400 2900 5400 3050 +Connection ~ 5400 3050 +Wire Wire Line + 4900 2000 4900 2400 +$Comp +L CONN_2 P1 +U 1 1 51868B92 +P 4550 2500 +F 0 "P1" V 4500 2500 40 0000 C CNN +F 1 "CONN_2" V 4600 2500 40 0000 C CNN + 1 4550 2500 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51863585 +P 5400 2900 +F 0 "#FLG01" H 5400 3170 30 0001 C CNN +F 1 "PWR_FLAG" H 5400 3130 30 0000 C CNN + 1 5400 2900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5186344D +P 5550 3200 +F 0 "#PWR02" H 5550 3200 30 0001 C CNN +F 1 "GND" H 5550 3130 30 0001 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 5186342E +P 6100 2400 +F 0 "C1" H 6150 2500 50 0000 L CNN +F 1 "1u" H 6150 2300 50 0000 L CNN + 1 6100 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51863417 +P 5650 2050 +F 0 "R1" V 5730 2050 50 0000 C CNN +F 1 "1k" V 5650 2050 50 0000 C CNN + 1 5650 2050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.brd b/OSCAD/Examples/RC_pcb/RC_pcb.brd new file mode 100644 index 0000000..335c0b9 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.brd @@ -0,0 +1,225 @@ +PCBNEW-BOARD Version 1 date Sunday 05 May 2013 10:20:45 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 3 +NoConn 0 +Di 55424 33924 63076 39076 +Ndraw 4 +Ntrack 3 +Nzone 0 +BoardThickness 630 +Nmodule 3 +Nnets 4 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "5 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 315 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000001" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 315 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000001" +AddNet "N-000003" +$EndNCLASS +$MODULE SIL-2 +Po 61000 37000 900 15 00200000 51868CE1 ~~ +Li SIL-2 +Cd Connecteurs 2 pins +Kw CONN DEV +Sc 51868CE1 +AR /51868B92 +Op 0 0 0 +T0 0 -1000 681 428 900 107 N V 21 N "P1" +T1 0 -1000 600 400 900 100 N I 21 N "CONN_2" +DS -1000 500 -1000 -500 120 21 +DS -1000 -500 1000 -500 120 21 +DS 1000 -500 1000 500 120 21 +DS 1000 500 -1000 500 120 21 +$PAD +Sh "1" R 550 550 0 0 900 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 900 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 500 0 +$EndPAD +$EndMODULE SIL-2 +$MODULE R3 +Po 58500 35500 0 15 00200000 51868CE2 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 51868CE2 +AR /51863417 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R1" +T1 0 0 550 500 0 80 N I 21 N "1k" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE C1 +Po 57500 37500 0 15 3F92C496 51868CE3 ~~ +Li C1 +Cd Condensateur e = 1 pas +Kw C +Sc 51868CE3 +AR /5186342E +Op 0 0 0 +T0 100 -900 400 400 0 80 N V 21 N "C1" +T1 0 -900 400 400 0 80 N I 21 N "1u" +DS -980 -500 1000 -500 120 21 +DS 1000 -500 1000 500 120 21 +DS 1000 500 -1000 500 120 21 +DS -1000 500 -1000 -500 120 21 +DS -1000 -250 -750 -500 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/capa_1_pas.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE C1 +$DRAWSEGMENT +Po 0 55500 39000 55500 34000 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 63000 39000 55500 39000 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 63000 34000 63000 39000 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 55500 34000 63000 34000 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$TRACK +Po 0 58000 37500 61000 37500 315 -1 +De 0 0 1 0 C00000 +Po 0 57000 35500 57000 37500 315 -1 +De 0 0 2 0 C00000 +Po 0 60000 35500 61000 36500 315 -1 +De 0 0 3 0 C00000 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.cir.ckt.sol b/OSCAD/Examples/RC_pcb/RC_pcb.cir.ckt.sol new file mode 100644 index 0000000..29b1351 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.cir.ckt.sol @@ -0,0 +1,6 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +V 1 0 0.0000000000 0.0000000000 +C 3 0 0.0000000000 0.0000000000 +I 0 3 -0.0000000000 0.0000000000 +R 3 1 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.cmp b/OSCAD/Examples/RC_pcb/RC_pcb.cmp new file mode 100644 index 0000000..14cc046 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.cmp @@ -0,0 +1,24 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Thursday 16 May 2013 01:22:40 AM IST + +BeginCmp +TimeStamp = /5186342E; +Reference = C1; +ValeurCmp = 1u; +IdModule = C1; +EndCmp + +BeginCmp +TimeStamp = /51868B92; +Reference = P1; +ValeurCmp = CONN_2; +IdModule = SIL-2; +EndCmp + +BeginCmp +TimeStamp = /51863417; +Reference = R1; +ValeurCmp = 1k; +IdModule = R3; +EndCmp + +EndListe diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.net b/OSCAD/Examples/RC_pcb/RC_pcb.net new file mode 100644 index 0000000..1cda301 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.net @@ -0,0 +1,30 @@ +# EESchema Netlist Version 1.1 created Thursday 16 May 2013 01:22:40 AM IST +( + ( /5186342E C1 C1 1u + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /51868B92 SIL-2 P1 CONN_2 + ( 1 GND ) + ( 2 N-000003 ) + ) + ( /51863417 R3 R1 1k + ( 1 N-000001 ) + ( 2 N-000003 ) + ) +) +* +{ Allowed footprints by component: +$component C1 + SM* + C? + C1-1 +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.pro b/OSCAD/Examples/RC_pcb/RC_pcb.pro new file mode 100644 index 0000000..952e2e1 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.pro @@ -0,0 +1,74 @@ +update=Monday 13 May 2013 07:10:16 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/rakhi/OSCAD/library/analogSpice +LibName32=/home/rakhi/OSCAD/library/analogXSpice +LibName33=/home/rakhi/OSCAD/library/convergenceAidSpice +LibName34=/home/rakhi/OSCAD/library/converterSpice +LibName35=/home/rakhi/OSCAD/library/digitalSpice +LibName36=/home/rakhi/OSCAD/library/digitalXSpice +LibName37=/home/rakhi/OSCAD/library/linearSpice +LibName38=/home/rakhi/OSCAD/library/measurementSpice +LibName39=/home/rakhi/OSCAD/library/portSpice +LibName40=/home/rakhi/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.proj b/OSCAD/Examples/RC_pcb/RC_pcb.proj new file mode 100644 index 0000000..396e6d0 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.proj @@ -0,0 +1 @@ +schematicFile RC.sch diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.sch b/OSCAD/Examples/RC_pcb/RC_pcb.sch new file mode 100644 index 0000000..8661fb3 --- /dev/null +++ b/OSCAD/Examples/RC_pcb/RC_pcb.sch @@ -0,0 +1,123 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:47:37 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:RC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4900 2050 5400 2050 +Wire Wire Line + 4900 2050 4900 2400 +Connection ~ 5400 3050 +Wire Wire Line + 5400 2900 5400 3050 +Wire Wire Line + 5900 2050 6100 2050 +Wire Wire Line + 6100 3050 4900 3050 +Wire Wire Line + 6100 3050 6100 2600 +Wire Wire Line + 5550 3050 5550 3200 +Connection ~ 5550 3050 +Connection ~ 6100 2050 +Wire Wire Line + 4900 3050 4900 2600 +Wire Wire Line + 6100 2050 6100 2200 +$Comp +L CONN_2 P1 +U 1 1 51868B92 +P 4550 2500 +F 0 "P1" V 4500 2500 40 0000 C CNN +F 1 "CONN_2" V 4600 2500 40 0000 C CNN + 1 4550 2500 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51863585 +P 5400 2900 +F 0 "#FLG01" H 5400 3170 30 0001 C CNN +F 1 "PWR_FLAG" H 5400 3130 30 0000 C CNN + 1 5400 2900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5186344D +P 5550 3200 +F 0 "#PWR02" H 5550 3200 30 0001 C CNN +F 1 "GND" H 5550 3130 30 0001 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 5186342E +P 6100 2400 +F 0 "C1" H 6150 2500 50 0000 L CNN +F 1 "1u" H 6150 2300 50 0000 L CNN + 1 6100 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51863417 +P 5650 2050 +F 0 "R1" V 5730 2050 50 0000 C CNN +F 1 "1k" V 5650 2050 50 0000 C CNN + 1 5650 2050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/bridgeRectifier/$savepcb.000 b/OSCAD/Examples/bridgeRectifier/$savepcb.000 new file mode 100644 index 0000000..5b76389 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/$savepcb.000 @@ -0,0 +1,366 @@ +PCBNEW-BOARD Version 1 date Thursday 04 October 2012 12:22:20 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 8 +NoConn 2 +Di 39125 25379 49041 30735 +Ndraw 0 +Ntrack 13 +Nzone 0 +BoardThickness 630 +Nmodule 6 +Nnets 5 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "4 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000002" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000002" +AddNet "N-000003" +AddNet "N-000004" +$EndNCLASS +$MODULE R3 +Po 46500 30000 1800 15 00200000 506D2FD9 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 506D2FD9 +AR /506BDD54 +Op 0 A 0 +T0 0 0 550 500 1800 80 N V 21 N "R1" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R1 +Po 41500 30000 1800 15 00200000 506D2FDA ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 506D2FDA +AR /506BDD71 +Op A A 0 +T0 -400 1000 550 500 1800 80 N V 21 N "V1" +T1 -450 1000 550 500 1800 80 N I 21 N "SINE" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE D3 +Po 46500 28000 0 15 00200000 506D2FDB ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDB +AR /506BDD23 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D1" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 46500 26000 0 15 00200000 506D2FDD ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDD +AR /506BDD29 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D2" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 41000 28000 0 15 00200000 506D2FDF ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDF +AR /506BDD38 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D3" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 41000 26000 0 15 00200000 506D31A5 ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D31A5 +AR /506BDD2F +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D4" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$TRACK +Po 0 39500 28000 39500 26000 80 -1 +De 0 0 1 0 C00000 +Po 0 42500 26000 45000 26000 80 -1 +De 0 0 2 0 C00000 +Po 0 42500 28000 45000 28000 80 -1 +De 0 0 3 0 C00000 +Po 0 42000 30000 42500 30000 80 -1 +De 0 0 3 0 400000 +Po 0 43000 28500 42500 28000 80 -1 +De 0 0 3 0 800000 +Po 0 43000 29500 43000 28500 80 -1 +De 0 0 3 0 0 +Po 0 42500 30000 43000 29500 80 -1 +De 0 0 3 0 0 +Po 0 49000 27000 49000 29000 80 -1 +De 0 0 4 0 0 +Po 0 49000 29000 48000 30000 80 -1 +De 0 0 4 0 800000 +Po 0 48000 26000 48500 26000 80 -1 +De 0 0 4 0 400000 +Po 0 49000 27000 48000 28000 80 -1 +De 0 0 4 0 800000 +Po 0 49000 26500 49000 27000 80 -1 +De 0 0 4 0 0 +Po 0 48500 26000 49000 26500 80 -1 +De 0 0 4 0 0 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/bridgeRectifier/$savepcb.brd b/OSCAD/Examples/bridgeRectifier/$savepcb.brd new file mode 100644 index 0000000..309f60a --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/$savepcb.brd @@ -0,0 +1,374 @@ +PCBNEW-BOARD Version 1 date Wednesday 21 November 2012 12:10:28 AM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 8 +NoConn 0 +Di 39125 25379 48489 31041 +Ndraw 0 +Ntrack 17 +Nzone 0 +BoardThickness 630 +Nmodule 6 +Nnets 5 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "20 nov 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 38500 31500 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000002" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000002" +AddNet "N-000003" +AddNet "N-000004" +$EndNCLASS +$MODULE R3 +Po 46500 30000 1800 15 00200000 506D2FD9 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 506D2FD9 +AR /506BDD54 +Op 0 A 0 +T0 0 0 550 500 1800 80 N V 21 N "R1" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R1 +Po 41500 30000 1800 15 00200000 506D2FDA ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 506D2FDA +AR /506BDD71 +Op A A 0 +T0 -400 1000 550 500 1800 80 N V 21 N "V1" +T1 -450 1000 550 500 1800 80 N I 21 N "SINE" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE D3 +Po 46500 28000 0 15 00200000 506D2FDB ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDB +AR /506BDD23 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D1" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 46500 26000 0 15 00200000 506D2FDD ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDD +AR /506BDD29 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D2" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 41000 28000 0 15 00200000 506D2FDF ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDF +AR /506BDD38 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D3" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 41000 26000 0 15 00200000 506D31A5 F~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D31A5 +AR /506BDD2F +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D4" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$TRACK +Po 0 39500 28000 39500 26000 80 -1 +De 0 0 1 0 C00000 +Po 0 45000 30000 44000 30000 80 -1 +De 0 0 1 0 400000 +Po 0 44000 30000 43000 31000 80 -1 +De 0 0 1 0 0 +Po 0 43000 31000 40500 31000 80 -1 +De 0 0 1 0 0 +Po 0 40500 31000 39500 30000 80 -1 +De 0 0 1 0 0 +Po 0 39500 30000 39500 28000 80 -1 +De 0 0 1 0 800000 +Po 0 41000 30000 41000 27000 80 -1 +De 0 0 2 0 400000 +Po 0 42000 26000 42500 26000 80 -1 +De 0 0 2 0 800000 +Po 0 41000 27000 42000 26000 80 -1 +De 0 0 2 0 0 +Po 0 42500 26000 45000 26000 80 -1 +De 0 0 2 0 C00000 +Po 0 42500 28000 45000 28000 80 -1 +De 0 0 3 0 C00000 +Po 0 42000 30000 42500 30000 80 -1 +De 0 0 3 0 400000 +Po 0 43000 28500 42500 28000 80 -1 +De 0 0 3 0 800000 +Po 0 43000 29500 43000 28500 80 -1 +De 0 0 3 0 0 +Po 0 42500 30000 43000 29500 80 -1 +De 0 0 3 0 0 +Po 0 48000 28000 48000 30000 80 -1 +De 0 0 4 0 C00000 +Po 0 48000 26000 48000 28000 80 -1 +De 0 0 4 0 C00000 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/bridgeRectifier/1n4007.lib b/OSCAD/Examples/bridgeRectifier/1n4007.lib new file mode 100644 index 0000000..7de0312 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/1n4007.lib @@ -0,0 +1,3 @@ +.model 1n4007 D( CJO=1E-11 AF=1 EG=1.05743 IS=7.02767e-09 RS=0.0341512 ++ M=0.5 N=1.80803 BV=1000 FC=0.5 XTI=5 ++ TT=1E-07 VJ=0.7 IBV=5e-08 KF=0 )
\ No newline at end of file diff --git a/OSCAD/Examples/bridgeRectifier/analysis b/OSCAD/Examples/bridgeRectifier/analysis new file mode 100644 index 0000000..888b3aa --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/analysis @@ -0,0 +1 @@ +.tran 100e-06 40e-03 0e-00 diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier-cache.bak b/OSCAD/Examples/bridgeRectifier/bridgeRectifier-cache.bak new file mode 100644 index 0000000..0103c9f --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier-cache.bak @@ -0,0 +1,106 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 10:56:29 AM IST +#encoding utf-8 +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier-cache.lib b/OSCAD/Examples/bridgeRectifier/bridgeRectifier-cache.lib new file mode 100644 index 0000000..0e9344f --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier-cache.lib @@ -0,0 +1,106 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 12:01:58 PM IST +#encoding utf-8 +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.bak b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.bak new file mode 100644 index 0000000..542665c --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.bak @@ -0,0 +1,203 @@ +EESchema Schematic File Version 2 date Sunday 09 December 2012 10:56:29 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:bridgeRectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6600 4000 4900 4000 +Wire Wire Line + 6600 4000 6600 3550 +Connection ~ 6300 2600 +Wire Wire Line + 6600 2950 6600 2600 +Wire Wire Line + 6600 2600 4900 2600 +Connection ~ 5150 3350 +Wire Wire Line + 5150 2450 5150 3350 +Connection ~ 5950 4000 +Wire Wire Line + 5950 4000 5950 3700 +Connection ~ 4900 3200 +Wire Wire Line + 4900 3200 4650 3200 +Wire Wire Line + 4650 3200 4650 2650 +Wire Wire Line + 4650 2650 4400 2650 +Wire Wire Line + 4400 2650 4400 2850 +Connection ~ 5500 2600 +Wire Wire Line + 5500 3150 5500 3400 +Wire Wire Line + 4900 3400 4900 3150 +Wire Wire Line + 4900 2600 4900 2750 +Wire Wire Line + 5500 2600 5500 2750 +Wire Wire Line + 4900 4000 4900 3800 +Wire Wire Line + 5500 4000 5500 3800 +Wire Wire Line + 6300 4000 6300 3500 +Connection ~ 5500 4000 +Wire Wire Line + 4400 3750 4400 3950 +Wire Wire Line + 4400 3950 4650 3950 +Wire Wire Line + 4650 3950 4650 3350 +Wire Wire Line + 4650 3350 5500 3350 +Connection ~ 5500 3350 +Wire Wire Line + 5650 4000 5650 4200 +Connection ~ 5650 4000 +Wire Wire Line + 6300 2600 6300 3000 +Wire Wire Line + 4550 2450 4550 2650 +Connection ~ 4550 2650 +Connection ~ 6300 4000 +$Comp +L VPLOT8 U1 +U 2 1 50C41A9A +P 6600 3250 +F 0 "U1" H 6450 3350 50 0000 C CNN +F 1 "VPLOT8" H 6750 3350 50 0000 C CNN + 2 6600 3250 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8 U1 +U 1 1 50C41A90 +P 4850 2450 +F 0 "U1" H 4700 2550 50 0000 C CNN +F 1 "VPLOT8" H 5000 2550 50 0000 C CNN + 1 4850 2450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 506BDF52 +P 5950 3700 +F 0 "#FLG01" H 5950 3970 30 0001 C CNN +F 1 "PWR_FLAG" H 5950 3930 30 0000 C CNN + 1 5950 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 506BDF42 +P 5650 4200 +F 0 "#PWR02" H 5650 4200 30 0001 C CNN +F 1 "GND" H 5650 4130 30 0001 C CNN + 1 5650 4200 + 1 0 0 -1 +$EndComp +$Comp +L SINE V1 +U 1 1 506BDD71 +P 4400 3300 +F 0 "V1" H 4200 3400 60 0000 C CNN +F 1 "SINE" H 4200 3250 60 0000 C CNN +F 2 "R1" H 4100 3300 60 0000 C CNN + 1 4400 3300 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 506BDD54 +P 6300 3250 +F 0 "R1" V 6380 3250 50 0000 C CNN +F 1 "1000" V 6300 3250 50 0000 C CNN + 1 6300 3250 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D3 +U 1 1 506BDD38 +P 4900 3600 +F 0 "D3" H 4900 3700 40 0000 C CNN +F 1 "1n4007" H 4900 3500 40 0000 C CNN + 1 4900 3600 + 0 -1 -1 0 +$EndComp +$Comp +L DIODE D4 +U 1 1 506BDD2F +P 5500 3600 +F 0 "D4" H 5500 3700 40 0000 C CNN +F 1 "1n4007" H 5500 3500 40 0000 C CNN + 1 5500 3600 + 0 -1 -1 0 +$EndComp +$Comp +L DIODE D2 +U 1 1 506BDD29 +P 5500 2950 +F 0 "D2" H 5500 3050 40 0000 C CNN +F 1 "1n4007" H 5500 2850 40 0000 C CNN + 1 5500 2950 + 0 -1 -1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 506BDD23 +P 4900 2950 +F 0 "D1" H 4900 3050 40 0000 C CNN +F 1 "1n4007" H 4900 2850 40 0000 C CNN + 1 4900 2950 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.brd b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.brd new file mode 100644 index 0000000..1f56fcf --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.brd @@ -0,0 +1,374 @@ +PCBNEW-BOARD Version 1 date Thursday 04 October 2012 12:24:14 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 8 +NoConn 0 +Di 39125 25379 48489 31041 +Ndraw 0 +Ntrack 17 +Nzone 0 +BoardThickness 630 +Nmodule 6 +Nnets 5 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "4 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000002" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000002" +AddNet "N-000003" +AddNet "N-000004" +$EndNCLASS +$MODULE R3 +Po 46500 30000 1800 15 00200000 506D2FD9 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 506D2FD9 +AR /506BDD54 +Op 0 A 0 +T0 0 0 550 500 1800 80 N V 21 N "R1" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R1 +Po 41500 30000 1800 15 00200000 506D2FDA ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 506D2FDA +AR /506BDD71 +Op A A 0 +T0 -400 1000 550 500 1800 80 N V 21 N "V1" +T1 -450 1000 550 500 1800 80 N I 21 N "SINE" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE D3 +Po 46500 28000 0 15 00200000 506D2FDB ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDB +AR /506BDD23 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D1" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 46500 26000 0 15 00200000 506D2FDD ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDD +AR /506BDD29 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D2" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$SHAPE3D +Na "discret/diode.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE D3 +$MODULE D3 +Po 41000 28000 0 15 00200000 506D2FDF ~~ +Li D3 +Cd Diode 3 pas +Kw DIODE DEV +Sc 506D2FDF +AR /506BDD38 +Op 0 0 0 +T0 0 0 400 400 0 80 N V 21 N "D3" +T1 0 0 400 400 0 80 N I 21 N "DIODE" +DS 1500 0 1200 0 120 21 +DS 1200 0 1200 -400 120 21 +DS 1200 -400 -1200 -400 120 21 +DS -1200 -400 -1200 0 120 21 +DS -1200 0 -1500 0 120 21 +DS -1200 0 -1200 400 120 21 +DS -1200 400 1200 400 120 21 +DS 1200 400 1200 0 120 21 +DS 1000 -400 1000 400 120 21 +DS 900 400 900 -400 120 21 +$PAD +Sh "2" R 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po -1500 0 +$EndPAD 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0 45000 30000 44000 30000 80 -1 +De 0 0 1 0 400000 +Po 0 39500 30000 39500 28000 80 -1 +De 0 0 1 0 800000 +Po 0 40500 31000 39500 30000 80 -1 +De 0 0 1 0 0 +Po 0 43000 31000 40500 31000 80 -1 +De 0 0 1 0 0 +Po 0 44000 30000 43000 31000 80 -1 +De 0 0 1 0 0 +Po 0 39500 28000 39500 26000 80 -1 +De 0 0 1 0 C00000 +Po 0 41000 30000 41000 27000 80 -1 +De 0 0 2 0 400000 +Po 0 42000 26000 42500 26000 80 -1 +De 0 0 2 0 800000 +Po 0 41000 27000 42000 26000 80 -1 +De 0 0 2 0 0 +Po 0 42500 26000 45000 26000 80 -1 +De 0 0 2 0 C00000 +Po 0 42500 28000 45000 28000 80 -1 +De 0 0 3 0 C00000 +Po 0 42000 30000 42500 30000 80 -1 +De 0 0 3 0 400000 +Po 0 43000 28500 42500 28000 80 -1 +De 0 0 3 0 800000 +Po 0 43000 29500 43000 28500 80 -1 +De 0 0 3 0 0 +Po 0 42500 30000 43000 29500 80 -1 +De 0 0 3 0 0 +Po 0 48000 28000 48000 30000 80 -1 +De 0 0 4 0 C00000 +Po 0 48000 26000 48000 28000 80 -1 +De 0 0 4 0 C00000 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir new file mode 100644 index 0000000..4eab418 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 12:01:55 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 3 4 1 0 VPLOT8 +V1 3 1 SINE +R1 4 0 1000 +D3 0 3 1n4007 +D4 0 1 1n4007 +D2 1 4 1n4007 +D1 3 4 1n4007 + +.end diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.ckt b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.ckt new file mode 100644 index 0000000..ceab340 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 12:01:55 pm ist
+.include 1n4007.lib
+
+v1 3 1 sine(0 4 50 0 0)
+r1 4 0 1000
+d3 0 3 1n4007
+d4 0 1 1n4007
+d2 1 4 1n4007
+d1 3 4 1n4007
+
+.tran 100e-06 40e-03 0e-00
+.plot v(3)-v(1) v(4)
+.end
diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.ckt.sol b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.ckt.sol new file mode 100644 index 0000000..d25e686 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.ckt.sol @@ -0,0 +1,8 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +V 3 1 0.0000000000 0.0000000000 +R 4 0 0.0000000000 0.0000000000 +D 0 3 -0.0000000000 0.0000000000 +D 0 1 -0.0000000000 0.0000000000 +D 1 4 0.0000000000 0.0000000000 +D 3 4 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.out b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.out new file mode 100644 index 0000000..b3aade9 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 12:01:55 pm ist
+.include 1n4007.lib
+
+v1 3 1 sine(0 4 50 0 0)
+r1 4 0 1000
+d3 0 3 1n4007
+d4 0 1 1n4007
+d2 1 4 1n4007
+d1 3 4 1n4007
+
+.tran 100e-06 40e-03 0e-00
+
+* Control Statements
+.control
+run
+plot v(3)-v(1) v(4)
+.endc
+.end
diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cmp b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cmp new file mode 100644 index 0000000..2420597 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.cmp @@ -0,0 +1,45 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 04:28:50 PM IST + +BeginCmp +TimeStamp = /506BDD23; +Reference = D1; +ValeurCmp = 1n4007; +IdModule = D3; +EndCmp + +BeginCmp +TimeStamp = /506BDD29; +Reference = D2; +ValeurCmp = 1n4007; +IdModule = D3; +EndCmp + +BeginCmp +TimeStamp = /506BDD38; +Reference = D3; +ValeurCmp = 1n4007; +IdModule = D3; +EndCmp + +BeginCmp +TimeStamp = /506BDD2F; +Reference = D4; +ValeurCmp = 1n4007; +IdModule = D3; +EndCmp + +BeginCmp +TimeStamp = /506BDD54; +Reference = R1; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /506BDD71; +Reference = V1; +ValeurCmp = SINE; +IdModule = R1; +EndCmp + +EndListe diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst new file mode 100644 index 0000000..a966a95 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst @@ -0,0 +1,25 @@ +eeschema (2011-05-25)-stable >> Creation date: Monday 15 October 2012 02:40:18 PM IST + +#Cmp ( order = Reference ) +| D1 DIODE +| D2 DIODE +| D3 DIODE +| D4 DIODE +| R1 1000 +| U1 VPLOT1 +| U2 VPLOT +| V1 SINE +#End Cmp + +#Cmp ( order = Value ) +| 1000 R1 +| DIODE D1 +| DIODE D2 +| DIODE D3 +| DIODE D4 +| SINE V1 +| VPLOT U2 +| VPLOT1 U1 +#End Cmp + +#End List diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.net b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.net new file mode 100644 index 0000000..94b1097 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.net @@ -0,0 +1,56 @@ +# EESchema Netlist Version 1.1 created Monday 22 October 2012 04:28:50 PM IST +( + ( /506BDD23 D3 D1 1n4007 + ( 1 N-000003 ) + ( 2 N-000004 ) + ) + ( /506BDD29 D3 D2 1n4007 + ( 1 N-000001 ) + ( 2 N-000004 ) + ) + ( /506BDD38 D3 D3 1n4007 + ( 1 GND ) + ( 2 N-000003 ) + ) + ( /506BDD2F D3 D4 1n4007 + ( 1 GND ) + ( 2 N-000001 ) + ) + ( /506BDD54 R3 R1 1000 + ( 1 N-000004 ) + ( 2 GND ) + ) + ( /506BDD71 R1 V1 SINE + ( 1 N-000003 ) + ( 2 N-000001 ) + ) +) +* +{ Allowed footprints by component: +$component D1 + D? + S* +$endlist +$component D2 + D? + S* +$endlist +$component D3 + D? + S* +$endlist +$component D4 + D? + S* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component V1 + 1_pin +$endlist +$endfootprintlist +} diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.pdf b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.pdf Binary files differnew file mode 100644 index 0000000..4500c18 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.pdf diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.pro b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.pro new file mode 100644 index 0000000..64e6524 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.pro @@ -0,0 +1,71 @@ +update=Monday 22 October 2012 04:25:50 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.proj b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.proj new file mode 100644 index 0000000..1937538 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.proj @@ -0,0 +1 @@ +schematicFile bridgeRectifier.sch diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.ps b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.ps new file mode 100644 index 0000000..2df6517 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.ps @@ -0,0 +1,2726 @@ +%!PS-Adobe-3.0 +%%Creator: EESchema-PS +%%CreationDate: Mon Oct 15 14:45:06 2012 +%%Title: bridgeRectifier.ps +%%Pages: 1 +%%PageOrder: Ascend +%%BoundingBox: 0 0 596 843 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Jones +%Copyright: Copyright (c) 1997, 2009 American Mathematical Society +%Copyright: (<http://www.ams.org>), with Reserved Font Name CMR6. +% This Font Software is licensed under the SIL Open Font License, Version 1.1. +% This license is in the accompanying file OFL.txt, and is also +% available with a FAQ at: http://scripts.sil.org/OFL. +%%EndComments +FontDirectory/CMR6 known{/CMR6 findfont dup/UniqueID known{dup +/UniqueID get 5000789 eq exch/FontType get 1 eq and}{pop false}ifelse +{save true}{false}ifelse}{false}ifelse +11 dict begin +/FontType 1 def +/FontMatrix [0.001 0 0 0.001 0 0 ]readonly def +/FontName /CMR6 def +/FontBBox {-20 -250 1193 750 }readonly def +/UniqueID 5000789 def +/PaintType 0 def +/FontInfo 9 dict dup begin +/version (003.002) readonly def +/Notice (Copyright \050c\051 1997, 2009 American Mathematical Society \050<http://www.ams.org>\051, with Reserved Font Name CMR6.) readonly def +/FullName (CMR6) readonly def +/FamilyName (Computer Modern) readonly def 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a/OSCAD/Examples/bridgeRectifier/diode_Dref.pstex_t b/OSCAD/Examples/bridgeRectifier/diode_Dref.pstex_t new file mode 100644 index 0000000..65c5d99 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/diode_Dref.pstex_t @@ -0,0 +1,19 @@ +\begin{picture}(0,0)% +\includegraphics{diode_Dref.pstex}% +\end{picture}% +\setlength{\unitlength}{3947sp}% +% +\begingroup\makeatletter\ifx\SetFigFont\undefined% +\gdef\SetFigFont#1#2#3#4#5{% + \reset@font\fontsize{#1}{#2pt}% + \fontfamily{#3}\fontseries{#4}\fontshape{#5}% + \selectfont}% +\fi\endgroup% +\begin{picture}(2435,1374)(1939,-1648) +\put(2251,-661){\makebox(0,0)[lb]{\smash{{\SetFigFont{12}{14.4}{\rmdefault}{\mddefault}{\updefault}{\color[rgb]{0,0,0}$D_{dnumber}$}% +}}}} +\put(3076,-961){\makebox(0,0)[lb]{\smash{{\SetFigFont{12}{14.4}{\rmdefault}{\mddefault}{\updefault}{\color[rgb]{0,0,0}$R_{D_{dnumber}}$}% +}}}} +\put(4351,-886){\makebox(0,0)[lb]{\smash{{\SetFigFont{12}{14.4}{\rmdefault}{\mddefault}{\updefault}{\color[rgb]{0,0,0}$I_{D_{dnumber}}$}% +}}}} +\end{picture}% diff --git a/OSCAD/Examples/bridgeRectifier/latfont b/OSCAD/Examples/bridgeRectifier/latfont new file mode 100644 index 0000000..90e1eb3 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/latfont @@ -0,0 +1,8 @@ +echo {\\input{$*.pstex_t}} >& dummy_font.tex +cat latfont1.tex dummy_font.tex latfont2.tex >& dummy_fig.tex +latex dummy_fig.tex +dvips -E -o dummy_fig.eps dummy_fig.dvi +mv dummy_fig.eps $*.eps +rm dummy_fig.* +rm -rf dummy_font.tex +evince $1.eps & diff --git a/OSCAD/Examples/bridgeRectifier/latfont1.tex b/OSCAD/Examples/bridgeRectifier/latfont1.tex new file mode 100644 index 0000000..e6301a4 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/latfont1.tex @@ -0,0 +1,20 @@ +\documentclass[12pt]{book} +\textwidth 6.5in +\textheight 9.0in +\topmargin 0.0in +\oddsidemargin 0.2in +\evensidemargin 0.2in +\textfloatsep 0.6cm +\abovecaptionskip 0.1cm +\usepackage[dvips]{graphicx} +\usepackage{makeidx} +\usepackage{epsfig} +\usepackage{color} +\setlength{\textwidth}{50cm} +\setlength{\textheight}{50cm} +\begin{document} +\pagestyle{empty} + +\begin{center} +%\resizebox{!}{5cm}{\input{cap_trns.pstex_t}} + diff --git a/OSCAD/Examples/bridgeRectifier/latfont2.tex b/OSCAD/Examples/bridgeRectifier/latfont2.tex new file mode 100644 index 0000000..3f4cd92 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/latfont2.tex @@ -0,0 +1,2 @@ +\end{center} +\end{document}
\ No newline at end of file diff --git a/OSCAD/Examples/bridgeRectifierFilter/1n4007.lib b/OSCAD/Examples/bridgeRectifierFilter/1n4007.lib new file mode 100644 index 0000000..e95f7ea --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/1n4007.lib @@ -0,0 +1,3 @@ +.model 1n4007 D( VJ=0.7 CJO=1E-11 RS=0.0341512 IS=7.02767e-09 AF=1 ++ M=0.5 N=1.80803 BV=1000 FC=0.5 IBV=5e-08 ++ TT=1E-07 EG=1.05743 XTI=5 KF=0 )
\ No newline at end of file diff --git a/OSCAD/Examples/bridgeRectifierFilter/analysis b/OSCAD/Examples/bridgeRectifierFilter/analysis new file mode 100644 index 0000000..888b3aa --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/analysis @@ -0,0 +1 @@ +.tran 100e-06 40e-03 0e-00 diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter-cache.bak b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter-cache.bak new file mode 100644 index 0000000..0708079 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter-cache.bak @@ -0,0 +1,121 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 20 November 2012 11:18:10 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot +# +DEF vplot U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -400 0 300 R 50 50 1 1 O +X - 2 400 0 300 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# vplot1 +# +DEF vplot1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter-cache.lib b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter-cache.lib new file mode 100644 index 0000000..c2529f8 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter-cache.lib @@ -0,0 +1,121 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 03:22:19 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot +# +DEF vplot U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 2 300 0 200 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot1 +# +DEF vplot1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.bak b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.bak new file mode 100644 index 0000000..acc6cf8 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.bak @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 date Tuesday 20 November 2012 11:18:10 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:bridgeRectifierFilter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 nov 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3750 4400 0 80 Italic 0 +Bridge Rectifier with Capacitor Filter +Wire Wire Line + 5850 2900 5850 2850 +Wire Wire Line + 3700 2950 3700 2650 +Connection ~ 5350 4100 +Wire Wire Line + 5350 4100 5350 3900 +Connection ~ 5850 2900 +Connection ~ 5650 2900 +Wire Wire Line + 6200 3300 6200 2900 +Wire Wire Line + 6200 2900 4250 2900 +Connection ~ 3700 2950 +Connection ~ 4250 3400 +Wire Wire Line + 4250 3400 3850 3400 +Wire Wire Line + 3850 3400 3850 2950 +Wire Wire Line + 3850 2950 3400 2950 +Wire Wire Line + 3400 2950 3400 3000 +Connection ~ 4850 2900 +Wire Wire Line + 5650 2900 5650 3300 +Wire Wire Line + 4250 3700 4250 3300 +Wire Wire Line + 4850 3700 4850 3300 +Wire Wire Line + 5650 4100 5650 3800 +Connection ~ 4850 4100 +Wire Wire Line + 3400 3900 3400 4000 +Wire Wire Line + 3400 4000 3850 4000 +Wire Wire Line + 3850 4000 3850 3600 +Wire Wire Line + 3850 3600 4850 3600 +Connection ~ 4850 3600 +Connection ~ 4500 3600 +Wire Wire Line + 4250 4100 6200 4100 +Wire Wire Line + 6200 4100 6200 3700 +Connection ~ 5650 4100 +Connection ~ 5200 4100 +Wire Wire Line + 5200 4100 5200 4200 +Wire Wire Line + 4500 3600 4500 2650 +$Comp +L PWR_FLAG #FLG01 +U 1 1 50852DDA +P 5350 3900 +F 0 "#FLG01" H 5350 4170 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4130 30 0000 C CNN + 1 5350 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5070FDD5 +P 5200 4200 +F 0 "#PWR02" H 5200 4200 30 0001 C CNN +F 1 "GND" H 5200 4130 30 0001 C CNN + 1 5200 4200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT1 U2 +U 1 1 5070F9F8 +P 5850 2550 +F 0 "U2" H 5700 2650 50 0000 C CNN +F 1 "VPLOT1" H 6000 2650 50 0000 C CNN + 1 5850 2550 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT U1 +U 1 1 5070F9E6 +P 4100 2650 +F 0 "U1" H 3950 2750 50 0000 C CNN +F 1 "VPLOT" H 4250 2750 50 0000 C CNN + 1 4100 2650 + 1 0 0 -1 +$EndComp +$Comp +L SINE V1 +U 1 1 5070F9A6 +P 3400 3450 +F 0 "V1" H 3200 3550 60 0000 C CNN +F 1 "SINE" H 3200 3400 60 0000 C CNN +F 2 "R1" H 3100 3450 60 0000 C CNN + 1 3400 3450 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 5070F977 +P 6200 3500 +F 0 "C1" H 6250 3600 50 0000 L CNN +F 1 "1e-06" H 6250 3400 50 0000 L CNN + 1 6200 3500 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D4 +U 1 1 5070F878 +P 4850 3900 +F 0 "D4" H 4850 4000 40 0000 C CNN +F 1 "1n4007" H 4850 3800 40 0000 C CNN + 1 4850 3900 + 0 -1 -1 0 +$EndComp +$Comp +L DIODE D2 +U 1 1 5070F85B +P 4850 3100 +F 0 "D2" H 4850 3200 40 0000 C CNN +F 1 "1n4007" H 4850 3000 40 0000 C CNN + 1 4850 3100 + 0 -1 -1 0 +$EndComp +$Comp +L DIODE D3 +U 1 1 5070F84B +P 4250 3900 +F 0 "D3" H 4250 4000 40 0000 C CNN +F 1 "1n4007" H 4250 3800 40 0000 C CNN + 1 4250 3900 + 0 -1 -1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 5070F83D +P 4250 3100 +F 0 "D1" H 4250 3200 40 0000 C CNN +F 1 "1n4007" H 4250 3000 40 0000 C CNN + 1 4250 3100 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 5070F82C +P 5650 3550 +F 0 "R1" V 5730 3550 50 0000 C CNN +F 1 "100000" V 5650 3550 50 0000 C CNN + 1 5650 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir new file mode 100644 index 0000000..4597fee --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Sunday 09 December 2012 03:22:39 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 3 VPLOT1 +U1 4 1 VPLOT +V1 4 1 SINE +C1 3 0 1e-06 +D4 0 1 1n4007 +D2 1 3 1n4007 +D3 0 4 1n4007 +D1 4 3 1n4007 +R1 3 0 100000 + +.end diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.ckt b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.ckt new file mode 100644 index 0000000..f6731c0 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 03:22:39 pm ist +.include 1n4007.lib + +* Plotting option vplot1 +* Plotting option vplot +v1 4 1 sine(0 5 50 0 0) +c1 3 0 1e-06 +d4 0 1 1n4007 +d2 1 3 1n4007 +d3 0 4 1n4007 +d1 4 3 1n4007 +r1 3 0 100000 + +.tran 100e-06 40e-03 0e-00 +.plot v(3) +.plot v(4)-v(1) +.end diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.ckt.sol b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.ckt.sol new file mode 100644 index 0000000..6403344 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.ckt.sol @@ -0,0 +1,10 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +V 4 1 0.0000000000 0.0000000000 +C 3 0 0.0000000000 0.0000000000 +I 0 3 -0.0000000000 0.0000000000 +D 0 1 -0.0000000000 0.0000000000 +D 1 3 0.0000000000 0.0000000000 +D 0 4 -0.0000000000 0.0000000000 +D 4 3 0.0000000000 0.0000000000 +R 3 0 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.out b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.out new file mode 100644 index 0000000..f4a26cd --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 03:22:39 pm ist +.include 1n4007.lib + +* Plotting option vplot1 +* Plotting option vplot +v1 4 1 sine(0 5 50 0 0) +c1 3 0 1e-06 +d4 0 1 1n4007 +d2 1 3 1n4007 +d3 0 4 1n4007 +d1 4 3 1n4007 +r1 3 0 100000 + +.tran 100e-06 40e-03 0e-00 + +* Control Statements +.control +run +plot v(3) +plot v(4)-v(1) +.endc +.end diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.net b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.net new file mode 100644 index 0000000..5ff5b10 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.net @@ -0,0 +1,96 @@ +# EESchema Netlist Version 1.1 created Tuesday 02 April 2013 03:03:04 PM IST +( + ( /5070F9F8 $noname U2 VPLOT1 {Lib=VPLOT1} + ( 1 N-000003 ) + ) + ( /5070F9E6 $noname U1 VPLOT {Lib=VPLOT} + ( 1 N-000004 ) + ( 2 N-000001 ) + ) + ( /5070F9A6 R1 V1 SINE {Lib=SINE} + ( 1 N-000004 ) + ( 2 N-000001 ) + ) + ( /5070F977 $noname C1 1e-06 {Lib=C} + ( 1 N-000003 ) + ( 2 GND ) + ) + ( /5070F878 $noname D4 1n4007 {Lib=DIODE} + ( 1 GND ) + ( 2 N-000001 ) + ) + ( /5070F85B $noname D2 1n4007 {Lib=DIODE} + ( 1 N-000001 ) + ( 2 N-000003 ) + ) + ( /5070F84B $noname D3 1n4007 {Lib=DIODE} + ( 1 GND ) + ( 2 N-000004 ) + ) + ( /5070F83D $noname D1 1n4007 {Lib=DIODE} + ( 1 N-000004 ) + ( 2 N-000003 ) + ) + ( /5070F82C $noname R1 100000 {Lib=R} + ( 1 N-000003 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component V1 + 1_pin +$endlist +$component C1 + SM* + C? + C1-1 +$endlist +$component D4 + D? + S* +$endlist +$component D2 + D? + S* +$endlist +$component D3 + D? + S* +$endlist +$component D1 + D? + S* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + V1 2 + D2 1 + D4 2 + U1 2 +Net 2 "GND" "GND" + R1 2 + D3 1 + D4 1 + C1 2 +Net 3 "" "" + C1 1 + U2 1 + D2 2 + D1 2 + R1 1 +Net 4 "" "" + V1 1 + D3 2 + D1 1 + U1 1 +} +#End diff --git a/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.pro b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.pro new file mode 100644 index 0000000..50c35d1 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifierFilter/bridgeRectifierFilter.pro @@ -0,0 +1,71 @@ +update=Monday 22 October 2012 04:57:56 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice 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-300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.bak b/OSCAD/Examples/frequencyDivider/frequencyDivider.bak new file mode 100644 index 0000000..48303d3 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.bak @@ -0,0 +1,280 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 09:00:05 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:convergenceAidSpice +LIBS:frequencyDivider-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 2 1 50CE9193 +P 7700 3000 +F 0 "U1" H 7550 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 7850 3100 50 0000 C CNN + 2 7700 3000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CE918C +P 6300 3000 +F 0 "U1" H 6150 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 6450 3100 50 0000 C CNN + 1 6300 3000 + 1 0 0 -1 +$EndComp +Connection ~ 4650 4100 +Wire Wire Line + 4650 4100 4650 4050 +Connection ~ 6600 2850 +Wire Wire Line + 7050 4600 6600 4600 +Wire Wire Line + 6600 4600 6600 2850 +Connection ~ 6300 3350 +Wire Wire Line + 6300 3300 6300 3900 +Connection ~ 6100 3350 +Wire Wire Line + 6300 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0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50A93D02 +P 5900 4800 +F 0 "#PWR01" H 5900 4800 30 0001 C CNN +F 1 "GND" H 5900 4730 30 0001 C CNN + 1 5900 4800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 50A93CC0 +P 5700 4300 +F 0 "#FLG02" H 5700 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5700 4530 30 0000 C CNN + 1 5700 4300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 50A93CB7 +P 5200 2850 +F 0 "#FLG03" H 5200 3120 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 3080 30 0000 C CNN + 1 5200 2850 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 50A93C56 +P 3650 3600 +F 0 "v1" H 3450 3700 60 0000 C CNN +F 1 "5" H 3450 3550 60 0000 C CNN +F 2 "R1" H 3350 3600 60 0000 C CNN + 1 3650 3600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A93BFE +P 6100 3850 +F 0 "R3" V 6180 3850 50 0000 C CNN +F 1 "1000" V 6100 3850 50 0000 C CNN + 1 6100 3850 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 50A93ACA +P 4300 4200 +F 0 "C2" H 4350 4300 50 0000 L CNN +F 1 "0.01e-6" H 4350 4100 50 0000 L CNN + 1 4300 4200 + 1 0 0 -1 +$EndComp +$Comp +L CP C1 +U 1 1 50A93893 +P 4000 4350 +F 0 "C1" H 4050 4450 50 0000 L CNN +F 1 "100e-12" H 4050 4250 50 0000 L CNN + 1 4000 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A93858 +P 4000 3750 +F 0 "R2" V 4080 3750 50 0000 C CNN +F 1 "10000" V 4000 3750 50 0000 C CNN + 1 4000 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A93852 +P 4000 3100 +F 0 "R1" V 4080 3100 50 0000 C CNN +F 1 "1000" V 4000 3100 50 0000 C CNN + 1 4000 3100 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X1 +U 1 1 50A937B9 +P 5200 3550 +F 0 "X1" H 5200 3650 70 0000 C CNN +F 1 "LM555N" H 5200 3450 70 0000 C CNN + 1 5200 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.cir b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir new file mode 100644 index 0000000..5989740 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:14 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 2 VPLOT8_1 +U2 5 IC +U3 3 3 0 6 3 2 1 0 3 74LS109 +v1 3 0 5 +R3 6 0 1000 +C2 7 0 0.01e-6 +C1 5 0 100e-12 +R2 8 5 10000 +R1 3 8 1000 +X1 0 5 6 3 7 5 8 3 LM555N + +.end diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.ckt b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.ckt new file mode 100644 index 0000000..293ca2e --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.ckt @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:14 am ist +.include lm555n.sub + +* Plotting option vplot8_1 +.ic v(5)=0 +* 74ls109 +v1 3 0 5 +r3 6 0 1000 +c2 7 0 0.01e-6 +c1 5 0 100e-12 +r2 8 5 10000 +r1 3 8 1000 +x1 0 5 6 3 7 5 8 3 lm555n +a1 [3 0 6 3 3] [3_in 0_in 6_in 3_in 3_in] u3adc +a2 3_in ~0_in 6_in ~3_in ~3_in 2_out 1_out u3 +a3 [2_out 1_out] [2 1] u3dac +.model u3 d_jkff +.model u3adc adc_bridge(in_low=0.8 in_high=2.0) +.model u3dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 50e-09 5e-06 0e-00 +.plot v(6) v(2) +.end diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.out b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.out new file mode 100644 index 0000000..97db1fc --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.cir.out @@ -0,0 +1,28 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:14 am ist +.include lm555n.sub + +* Plotting option vplot8_1 +.ic v(5)=0 +* 74ls109 +v1 3 0 5 +r3 6 0 1000 +c2 7 0 0.01e-6 +c1 5 0 100e-12 +r2 8 5 10000 +r1 3 8 1000 +x1 0 5 6 3 7 5 8 3 lm555n +a1 [3 0 6 3 3] [3_in 0_in 6_in 3_in 3_in] u3adc +a2 3_in ~0_in 6_in ~3_in ~3_in 2_out 1_out u3 +a3 [2_out 1_out] [2 1] u3dac +.model u3 d_jkff +.model u3adc adc_bridge(in_low=0.8 in_high=2.0) +.model u3dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 50e-09 5e-06 0e-00 + +* Control Statements +.control +run +plot v(6) v(2) +.endc +.end diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.pro b/OSCAD/Examples/frequencyDivider/frequencyDivider.pro new file mode 100644 index 0000000..a4e7e69 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.pro @@ -0,0 +1,71 @@ +update=Monday 17 December 2012 08:48:56 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=special +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=analogSpice +LibName31=converterSpice +LibName32=digitalSpice +LibName33=linearSpice +LibName34=measurementSpice +LibName35=portSpice +LibName36=sourcesSpice +LibName37=convergenceAidSpice diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.proj b/OSCAD/Examples/frequencyDivider/frequencyDivider.proj new file mode 100644 index 0000000..0a193f0 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.proj @@ -0,0 +1 @@ +schematicFile IC555AstableMultivibrator.sch diff --git a/OSCAD/Examples/frequencyDivider/frequencyDivider.sch b/OSCAD/Examples/frequencyDivider/frequencyDivider.sch new file mode 100644 index 0000000..3f76d3a --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/frequencyDivider.sch @@ -0,0 +1,280 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:57:17 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:convergenceAidSpice +LIBS:frequencyDivider-cache +EELAYER 25 0 +EELAYER END +$Descr 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5700 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5700 4530 30 0000 C CNN + 1 5700 4300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 50A93CB7 +P 5200 2850 +F 0 "#FLG03" H 5200 3120 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 3080 30 0000 C CNN + 1 5200 2850 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 50A93C56 +P 3650 3600 +F 0 "v1" H 3450 3700 60 0000 C CNN +F 1 "5" H 3450 3550 60 0000 C CNN +F 2 "R1" H 3350 3600 60 0000 C CNN + 1 3650 3600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A93BFE +P 6100 3850 +F 0 "R3" V 6180 3850 50 0000 C CNN +F 1 "1000" V 6100 3850 50 0000 C CNN + 1 6100 3850 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 50A93ACA +P 4300 4200 +F 0 "C2" H 4350 4300 50 0000 L CNN +F 1 "0.01e-6" H 4350 4100 50 0000 L CNN + 1 4300 4200 + 1 0 0 -1 +$EndComp +$Comp +L CP C1 +U 1 1 50A93893 +P 4000 4350 +F 0 "C1" H 4050 4450 50 0000 L CNN +F 1 "100e-12" H 4050 4250 50 0000 L CNN + 1 4000 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A93858 +P 4000 3750 +F 0 "R2" V 4080 3750 50 0000 C CNN +F 1 "10000" V 4000 3750 50 0000 C CNN + 1 4000 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A93852 +P 4000 3100 +F 0 "R1" V 4080 3100 50 0000 C CNN +F 1 "1000" V 4000 3100 50 0000 C CNN + 1 4000 3100 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X1 +U 1 1 50A937B9 +P 5200 3550 +F 0 "X1" H 5200 3650 70 0000 C CNN +F 1 "LM555N" H 5200 3450 70 0000 C CNN + 1 5200 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/lm555n-cache.bak b/OSCAD/Examples/frequencyDivider/lm555n-cache.bak new file mode 100644 index 0000000..2cfdb3a --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n-cache.bak @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 10:48:46 AM IST +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 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1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/lm555n-cache.lib b/OSCAD/Examples/frequencyDivider/lm555n-cache.lib new file mode 100644 index 0000000..1f8bfd1 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n-cache.lib @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 10:57:52 AM IST +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter" 100 100 40 H V C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +# D_SRLatch +# +DEF D_SRLatch U 0 40 Y Y 1 F N +F0 "U" -200 250 60 H V C CNN +F1 "D_SRLatch" 0 100 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X S 1 -600 150 300 R 50 50 1 1 I +X R 2 -600 -150 300 R 50 50 1 1 I +X Enable 3 -600 0 300 R 50 50 1 1 I +X Set 4 150 -500 300 U 50 50 1 1 I +X Reset 5 -150 -500 300 U 50 50 1 1 I +X Q 6 600 150 300 L 50 50 1 1 O +X ~Q 7 600 -150 300 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# DAC8 +# +DEF DAC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "DAC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# LIMIT8 +# +DEF LIMIT8 U 0 40 Y Y 8 F N +F0 "U" 0 100 30 H V C CNN +F1 "LIMIT8" 0 0 30 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in 1 -300 0 150 R 25 25 1 1 I +X out 9 300 0 150 L 25 25 1 1 O +X in 2 -300 0 150 R 25 25 2 1 I +X out 10 300 0 150 L 25 25 2 1 O +X in 3 -300 0 150 R 25 25 3 1 I +X out 11 300 0 150 L 25 25 3 1 O +X in 4 -300 0 150 R 25 25 4 1 I +X out 12 300 0 150 L 25 25 4 1 O +X in 5 -300 0 150 R 25 25 5 1 I +X out 13 300 0 150 L 25 25 5 1 O +X in 6 -300 0 150 R 25 25 6 1 I +X out 14 300 0 150 L 25 25 6 1 O +X in 7 -300 0 150 R 25 25 7 1 I +X out 15 300 0 150 L 25 25 7 1 O +X in 8 -300 0 150 R 25 25 8 1 I +X out 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/frequencyDivider/lm555n.bak b/OSCAD/Examples/frequencyDivider/lm555n.bak new file mode 100644 index 0000000..92d1f7a --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.bak @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:48:46 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 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2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/lm555n.cir b/OSCAD/Examples/frequencyDivider/lm555n.cir new file mode 100644 index 0000000..9483a64 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.cir @@ -0,0 +1,25 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 21 D_INVERTER +U6 1 4 5 21 21 8 10 D_SRLATCH +E2 18 0 23 14 10000 +U4 19 20 11 12 LIMIT8 +U3 8 10 7 9 DAC8 +U2 11 12 6 4 1 5 ADC8 +U1 22 14 7 6 15 16 3 13 PORT +R8 9 2 1500 +Q1 22 2 3 QNOM +R7 18 20 25 +R6 17 19 25 +E1 17 0 16 15 10000 +R4 16 15 2E6 +R5 23 14 2E6 +R3 23 22 5000 +R2 15 23 5000 +R1 13 15 5000 + +.end diff --git a/OSCAD/Examples/frequencyDivider/lm555n.cir.ckt b/OSCAD/Examples/frequencyDivider/lm555n.cir.ckt new file mode 100644 index 0000000..90f04a3 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.cir.ckt @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/OSCAD/Examples/frequencyDivider/lm555n.cir.out b/OSCAD/Examples/frequencyDivider/lm555n.cir.out new file mode 100644 index 0000000..90f04a3 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.cir.out @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/OSCAD/Examples/frequencyDivider/lm555n.pro b/OSCAD/Examples/frequencyDivider/lm555n.pro new file mode 100644 index 0000000..09fa54e --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.pro @@ -0,0 +1,73 @@ +update=Monday 19 November 2012 04:56:38 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=analogXSpice +LibName33=converterSpice +LibName34=digitalSpice +LibName35=linearSpice +LibName36=measurementSpice +LibName37=portSpice +LibName38=sourcesSpice +LibName39=digitalXSpice diff --git a/OSCAD/Examples/frequencyDivider/lm555n.sch b/OSCAD/Examples/frequencyDivider/lm555n.sch new file mode 100644 index 0000000..fabbb66 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:57:52 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice 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4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/frequencyDivider/lm555n.sub b/OSCAD/Examples/frequencyDivider/lm555n.sub new file mode 100644 index 0000000..254c530 --- /dev/null +++ b/OSCAD/Examples/frequencyDivider/lm555n.sub @@ -0,0 +1,37 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.ends lm555n
\ No newline at end of file diff --git a/OSCAD/Examples/linear1/analysis b/OSCAD/Examples/linear1/analysis new file mode 100644 index 0000000..162ad08 --- /dev/null +++ b/OSCAD/Examples/linear1/analysis @@ -0,0 +1 @@ +.op
\ No newline at end of file diff --git a/OSCAD/Examples/linear1/linear1-cache.bak b/OSCAD/Examples/linear1/linear1-cache.bak new file mode 100644 index 0000000..b2b47b7 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1-cache.bak @@ -0,0 +1,106 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:21:41 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/linear1/linear1-cache.lib b/OSCAD/Examples/linear1/linear1-cache.lib new file mode 100644 index 0000000..55c3d03 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1-cache.lib @@ -0,0 +1,106 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:24:11 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/linear1/linear1.bak b/OSCAD/Examples/linear1/linear1.bak new file mode 100644 index 0000000..2be3d0e --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.bak @@ -0,0 +1,233 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:21:41 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:linear1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6100 2500 5650 2500 +Wire Wire Line + 5650 2500 5650 2900 +Connection ~ 5650 2900 +Wire Wire Line + 5350 2900 5750 2900 +Connection ~ 6850 3800 +Wire Wire Line + 6850 3800 6850 3600 +Connection ~ 7300 2900 +Wire Wire Line + 7300 3000 7300 2500 +Connection ~ 6400 3800 +Wire Wire Line + 6400 3500 6400 3800 +Connection ~ 5500 3800 +Wire Wire Line + 7300 3500 7300 3800 +Wire Wire Line + 7300 3800 3750 3800 +Connection ~ 4600 2900 +Wire Wire Line + 4600 3000 4600 2900 +Connection ~ 6400 2900 +Wire Wire Line + 6550 2900 6250 2900 +Wire Wire Line + 4750 2900 4450 2900 +Wire Wire Line + 3750 2900 3950 2900 +Wire Wire Line + 6400 2900 6400 3000 +Wire Wire Line + 7300 2900 7050 2900 +Wire Wire Line + 4600 3500 4600 3800 +Connection ~ 4600 3800 +Wire Wire Line + 5800 3800 5800 4000 +Connection ~ 5800 3800 +Wire Wire Line + 7300 2500 6700 2500 +Wire Wire Line + 7300 2750 7700 2750 +Connection ~ 7300 2750 +$Comp +L VPRINT1 U1 +U 1 1 506964BE +P 7700 2450 +F 0 "U1" H 7550 2550 50 0001 C CNN +F 1 "VPRINT1" H 7850 2550 50 0000 C CNN + 1 7700 2450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50695F5E +P 6850 3600 +F 0 "#FLG01" H 6850 3870 30 0001 C CNN +F 1 "PWR_FLAG" H 6850 3830 30 0000 C CNN + 1 6850 3600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50695EE6 +P 5800 4000 +F 0 "#PWR02" H 5800 4000 30 0001 C CNN +F 1 "GND" H 5800 3930 30 0001 C CNN + 1 5800 4000 + 1 0 0 -1 +$EndComp +Text Label 6100 3800 0 60 ~ 0 +c +Text Label 6350 2750 0 60 ~ 0 +c +Text Label 6450 2750 0 60 ~ 0 +b +Text Label 6550 2900 0 60 ~ 0 +b +Text Label 5100 3150 0 60 ~ 0 +b +Text Label 5000 3150 0 60 ~ 0 +a +Text Label 7150 2900 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50695730 +P 5050 2950 +F 0 "E1" H 4850 3050 50 0000 C CNN +F 1 "0.5" H 4850 2900 50 0000 C CNN + 1 5050 2950 + 1 0 0 -1 +$EndComp +$Comp +L DC I1 +U 1 1 506956A6 +P 5500 3350 +F 0 "I1" H 5300 3450 60 0000 C CNN +F 1 "1" H 5300 3300 60 0000 C CNN +F 2 "R1" H 5200 3350 60 0000 C CNN + 1 5500 3350 + -1 0 0 1 +$EndComp +$Comp +L DC V1 +U 1 1 50695694 +P 3750 3350 +F 0 "V1" H 3550 3450 60 0000 C CNN +F 1 "1" H 3550 3300 60 0000 C CNN +F 2 "R1" H 3450 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +$Comp +L VCCS G1 +U 1 1 5069566A +P 6400 2550 +F 0 "G1" H 6200 2650 50 0000 C CNN +F 1 "0.5" H 6200 2500 50 0000 C CNN + 1 6400 2550 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 506955DC +P 7300 3250 +F 0 "R6" V 7380 3250 50 0000 C CNN +F 1 "1" V 7300 3250 50 0000 C CNN + 1 7300 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 506955D8 +P 6400 3250 +F 0 "R3" V 6480 3250 50 0000 C CNN +F 1 "1" V 6400 3250 50 0000 C CNN + 1 6400 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 506955D1 +P 6800 2900 +F 0 "R5" V 6880 2900 50 0000 C CNN +F 1 "0.5" V 6800 2900 50 0000 C CNN + 1 6800 2900 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 506955CC +P 6000 2900 +F 0 "R4" V 6080 2900 50 0000 C CNN +F 1 "1" V 6000 2900 50 0000 C CNN + 1 6000 2900 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 506955C7 +P 4600 3250 +F 0 "R2" V 4680 3250 50 0000 C CNN +F 1 "1" V 4600 3250 50 0000 C CNN + 1 4600 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 506955C2 +P 4200 2900 +F 0 "R1" V 4280 2900 50 0000 C CNN +F 1 "1" V 4200 2900 50 0000 C CNN + 1 4200 2900 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/linear1/linear1.brd b/OSCAD/Examples/linear1/linear1.brd new file mode 100644 index 0000000..a04a203 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.brd @@ -0,0 +1,84 @@ +PCBNEW-BOARD Version 1 date Thursday 04 October 2012 03:56:07 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 0 +NoConn 0 +Di 0 0 117000 82670 +Ndraw 0 +Ntrack 0 +Nzone 0 +BoardThickness 630 +Nmodule 0 +Nnets 1 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "4 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +$EndNCLASS +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/linear1/linear1.cir b/OSCAD/Examples/linear1/linear1.cir new file mode 100644 index 0000000..349f95a --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.cir @@ -0,0 +1,19 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:24:34 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 1 VPRINT1 +E1 4 6 1 2 0.5 +I1 0 6 1 +V1 3 0 1 +G1 6 1 0 2 0.5 +R6 1 0 1 +R3 2 0 1 +R5 1 2 0.5 +R4 2 6 1 +R2 4 0 1 +R1 4 3 1 + +.end diff --git a/OSCAD/Examples/linear1/linear1.cir.ckt b/OSCAD/Examples/linear1/linear1.cir.ckt new file mode 100644 index 0000000..6738a45 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:24:34 am ist + +* Printing option vprint1 +e1 4 6 1 2 0.5 +i1 0 6 1 +v1 3 0 1 +g1 6 1 0 2 0.5 +r6 1 0 1 +r3 2 0 1 +r5 1 2 0.5 +r4 2 6 1 +r2 4 0 1 +r1 4 3 1 + +.op +.print v(1) +.end diff --git a/OSCAD/Examples/linear1/linear1.cir.ckt.sol b/OSCAD/Examples/linear1/linear1.cir.ckt.sol new file mode 100644 index 0000000..5727235 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.cir.ckt.sol @@ -0,0 +1,14 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +E 4 6 0.0000000000 0.0000000000 +I 1 2 0.0000000000 0.0000000000 +I 0 6 -0.0000000000 0.0000000000 +V 3 0 0.0000000000 0.0000000000 +G 6 1 0.0000000000 -0.0000000000 +I 0 2 -0.0000000000 0.0000000000 +R 1 0 0.0000000000 0.0000000000 +R 2 0 0.0000000000 0.0000000000 +R 1 2 0.0000000000 0.0000000000 +R 2 6 0.0000000000 0.0000000000 +R 4 0 0.0000000000 0.0000000000 +R 4 3 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/linear1/linear1.cir.out b/OSCAD/Examples/linear1/linear1.cir.out new file mode 100644 index 0000000..b996360 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:24:34 am ist + +* Printing option vprint1 +e1 4 6 1 2 0.5 +i1 0 6 1 +v1 3 0 1 +g1 6 1 0 2 0.5 +r6 1 0 1 +r3 2 0 1 +r5 1 2 0.5 +r4 2 6 1 +r2 4 0 1 +r1 4 3 1 + +.op + +* Control Statements +.control +run +print v(1) +.endc +.end diff --git a/OSCAD/Examples/linear1/linear1.cmp b/OSCAD/Examples/linear1/linear1.cmp new file mode 100644 index 0000000..84671d7 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.cmp @@ -0,0 +1,73 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 04:10:55 PM IST + +BeginCmp +TimeStamp = /50695730; +Reference = E1; +ValeurCmp = 0.5; +IdModule = bornier4; +EndCmp + +BeginCmp +TimeStamp = /5069566A; +Reference = G1; +ValeurCmp = 0.5; +IdModule = bornier4; +EndCmp + +BeginCmp +TimeStamp = /506956A6; +Reference = I1; +ValeurCmp = DC; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /506955C2; +Reference = R1; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /506955C7; +Reference = R2; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /506955D8; +Reference = R3; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /506955CC; +Reference = R4; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /506955D1; +Reference = R5; +ValeurCmp = 0.5; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /506955DC; +Reference = R6; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50695694; +Reference = V1; +ValeurCmp = DC; +IdModule = R1; +EndCmp + +EndListe diff --git a/OSCAD/Examples/linear1/linear1.net b/OSCAD/Examples/linear1/linear1.net new file mode 100644 index 0000000..c615a65 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.net @@ -0,0 +1,99 @@ +# EESchema Netlist Version 1.1 created Monday 22 October 2012 04:10:55 PM IST +( + ( /50695730 bornier4 E1 0.5 + ( 1 N-000005 ) + ( 2 N-000006 ) + ( 3 /a ) + ( 4 /b ) + ) + ( /5069566A bornier4 G1 0.5 + ( 1 N-000006 ) + ( 2 /a ) + ( 3 GND ) + ( 4 /b ) + ) + ( /506956A6 R1 I1 DC + ( 1 GND ) + ( 2 N-000006 ) + ) + ( /506955C2 R3 R1 1 + ( 1 N-000005 ) + ( 2 N-000004 ) + ) + ( /506955C7 R3 R2 1 + ( 1 N-000005 ) + ( 2 GND ) + ) + ( /506955D8 R3 R3 1 + ( 1 /b ) + ( 2 GND ) + ) + ( /506955CC R3 R4 1 + ( 1 /b ) + ( 2 N-000006 ) + ) + ( /506955D1 R3 R5 0.5 + ( 1 /a ) + ( 2 /b ) + ) + ( /506955DC R3 R6 1 + ( 1 /a ) + ( 2 GND ) + ) + ( /50695694 R1 V1 DC + ( 1 N-000004 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component E1 + 1_pin +$endlist +$component G1 + 1_pin +$endlist +$component I1 + 1_pin +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R4 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R5 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R6 + R? + SM0603 + SM0805 + R?-* +$endlist +$component V1 + 1_pin +$endlist +$endfootprintlist +} diff --git a/OSCAD/Examples/linear1/linear1.pro b/OSCAD/Examples/linear1/linear1.pro new file mode 100644 index 0000000..0a485f9 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.pro @@ -0,0 +1,71 @@ +update=Monday 22 October 2012 04:08:41 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/linear1/linear1.proj b/OSCAD/Examples/linear1/linear1.proj new file mode 100644 index 0000000..e532113 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.proj @@ -0,0 +1 @@ +schematicFile linear1.sch diff --git a/OSCAD/Examples/linear1/linear1.sch b/OSCAD/Examples/linear1/linear1.sch new file mode 100644 index 0000000..452dbd0 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.sch @@ -0,0 +1,234 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:24:11 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:linear1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5500 2900 +Wire Wire Line + 5350 2900 5750 2900 +Connection ~ 7300 2750 +Wire Wire Line + 7300 2750 7700 2750 +Wire Wire Line + 6700 2500 7300 2500 +Connection ~ 5800 3800 +Wire Wire Line + 5800 3800 5800 4000 +Connection ~ 4600 3800 +Wire Wire Line + 4600 3500 4600 3800 +Wire Wire Line + 7300 2900 7050 2900 +Wire Wire Line + 6400 2900 6400 3000 +Wire Wire Line + 3750 2900 3950 2900 +Wire Wire Line + 4750 2900 4450 2900 +Wire Wire Line + 6550 2900 6250 2900 +Connection ~ 6400 2900 +Wire Wire Line + 4600 3000 4600 2900 +Connection ~ 4600 2900 +Wire Wire Line + 3750 3800 7300 3800 +Wire Wire Line + 7300 3800 7300 3500 +Connection ~ 5500 3800 +Wire Wire Line + 6400 3500 6400 3800 +Connection ~ 6400 3800 +Wire Wire Line + 7300 2500 7300 3000 +Connection ~ 7300 2900 +Wire Wire Line + 6850 3800 6850 3600 +Connection ~ 6850 3800 +Connection ~ 5650 2900 +Wire Wire Line + 5650 2900 5650 2500 +Wire Wire Line + 5650 2500 6100 2500 +$Comp +L VPRINT1 U1 +U 1 1 506964BE +P 7700 2450 +F 0 "U1" H 7550 2550 50 0001 C CNN +F 1 "VPRINT1" H 7850 2550 50 0000 C CNN + 1 7700 2450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50695F5E +P 6850 3600 +F 0 "#FLG01" H 6850 3870 30 0001 C CNN +F 1 "PWR_FLAG" H 6850 3830 30 0000 C CNN + 1 6850 3600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50695EE6 +P 5800 4000 +F 0 "#PWR02" H 5800 4000 30 0001 C CNN +F 1 "GND" H 5800 3930 30 0001 C CNN + 1 5800 4000 + 1 0 0 -1 +$EndComp +Text Label 6100 3800 0 60 ~ 0 +c +Text Label 6350 2750 0 60 ~ 0 +c +Text Label 6450 2750 0 60 ~ 0 +b +Text Label 6550 2900 0 60 ~ 0 +b +Text Label 5100 3150 0 60 ~ 0 +b +Text Label 5000 3150 0 60 ~ 0 +a +Text Label 7150 2900 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50695730 +P 5050 2950 +F 0 "E1" H 4850 3050 50 0000 C CNN +F 1 "0.5" H 4850 2900 50 0000 C CNN + 1 5050 2950 + 1 0 0 -1 +$EndComp +$Comp +L DC I1 +U 1 1 506956A6 +P 5500 3350 +F 0 "I1" H 5300 3450 60 0000 C CNN +F 1 "1" H 5300 3300 60 0000 C CNN +F 2 "R1" H 5200 3350 60 0000 C CNN + 1 5500 3350 + -1 0 0 1 +$EndComp +$Comp +L DC V1 +U 1 1 50695694 +P 3750 3350 +F 0 "V1" H 3550 3450 60 0000 C CNN +F 1 "1" H 3550 3300 60 0000 C CNN +F 2 "R1" H 3450 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +$Comp +L VCCS G1 +U 1 1 5069566A +P 6400 2550 +F 0 "G1" H 6200 2650 50 0000 C CNN +F 1 "0.5" H 6200 2500 50 0000 C CNN + 1 6400 2550 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 506955DC +P 7300 3250 +F 0 "R6" V 7380 3250 50 0000 C CNN +F 1 "1" V 7300 3250 50 0000 C CNN + 1 7300 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 506955D8 +P 6400 3250 +F 0 "R3" V 6480 3250 50 0000 C CNN +F 1 "1" V 6400 3250 50 0000 C CNN + 1 6400 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 506955D1 +P 6800 2900 +F 0 "R5" V 6880 2900 50 0000 C CNN +F 1 "0.5" V 6800 2900 50 0000 C CNN + 1 6800 2900 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 506955CC +P 6000 2900 +F 0 "R4" V 6080 2900 50 0000 C CNN +F 1 "1" V 6000 2900 50 0000 C CNN + 1 6000 2900 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 506955C7 +P 4600 3250 +F 0 "R2" V 4680 3250 50 0000 C CNN +F 1 "1" V 4600 3250 50 0000 C CNN + 1 4600 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 506955C2 +P 4200 2900 +F 0 "R1" V 4280 2900 50 0000 C CNN +F 1 "1" V 4200 2900 50 0000 C CNN + 1 4200 2900 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/linear2/analysis b/OSCAD/Examples/linear2/analysis new file mode 100644 index 0000000..162ad08 --- /dev/null +++ b/OSCAD/Examples/linear2/analysis @@ -0,0 +1 @@ +.op
\ No newline at end of file diff --git a/OSCAD/Examples/linear2/linear2-cache.bak b/OSCAD/Examples/linear2/linear2-cache.bak new file mode 100644 index 0000000..df2206b --- /dev/null +++ b/OSCAD/Examples/linear2/linear2-cache.bak @@ -0,0 +1,89 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:32:27 AM IST +#encoding utf-8 +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" -200 100 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/linear2/linear2-cache.lib b/OSCAD/Examples/linear2/linear2-cache.lib new file mode 100644 index 0000000..79f9376 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2-cache.lib @@ -0,0 +1,89 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:32:49 AM IST +#encoding utf-8 +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" -200 100 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/linear2/linear2.bak b/OSCAD/Examples/linear2/linear2.bak new file mode 100644 index 0000000..e9d9386 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.bak @@ -0,0 +1,181 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:32:27 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:linear2-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6450 4000 +Wire Wire Line + 6450 4000 6450 3800 +Connection ~ 6750 3000 +Wire Wire Line + 6750 3000 6750 2850 +Connection ~ 6000 4000 +Wire Wire Line + 6000 3800 6000 4000 +Connection ~ 5300 3000 +Wire Wire Line + 5300 3300 5300 3000 +Wire Wire Line + 6850 3800 6850 4000 +Wire Wire Line + 6850 4000 4800 4000 +Wire Wire Line + 4800 4000 4800 3950 +Wire Wire Line + 5850 3000 6100 3000 +Wire Wire Line + 4800 3050 4800 3000 +Wire Wire Line + 4800 3000 5350 3000 +Wire Wire Line + 6600 3000 6850 3000 +Wire Wire Line + 6850 3000 6850 3200 +Wire Wire Line + 5300 3800 5300 4000 +Connection ~ 5300 4000 +Wire Wire Line + 6000 3000 6000 3150 +Connection ~ 6000 3000 +Wire Wire Line + 5600 4000 5600 4150 +Connection ~ 5600 4000 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5069EA51 +P 6450 3800 +F 0 "#FLG01" H 6450 4070 30 0001 C CNN +F 1 "PWR_FLAG" H 6450 4030 30 0000 C CNN + 1 6450 3800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5069EA30 +P 5600 4150 +F 0 "#PWR02" H 5600 4150 30 0001 C CNN +F 1 "GND" H 5600 4080 30 0001 C CNN + 1 5600 4150 + 1 0 0 -1 +$EndComp +$Comp +L VPRINT1 U1 +U 1 1 5069E9D3 +P 6750 2550 +F 0 "U1" H 6600 2650 50 0001 C CNN +F 1 "VPRINT1" H 6900 2650 50 0000 C CNN + 1 6750 2550 + 1 0 0 -1 +$EndComp +Text Label 6600 3550 0 60 ~ 0 +b +Text Label 6600 3450 0 60 ~ 0 +a +Text Label 6000 3300 0 60 ~ 0 +b +Text Label 6000 3150 0 60 ~ 0 +a +$Comp +L R R4 +U 1 1 5069E7B0 +P 6350 3000 +F 0 "R4" V 6430 3000 50 0000 C CNN +F 1 "0.1" V 6350 3000 50 0000 C CNN + 1 6350 3000 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 5069E7AC +P 5300 3550 +F 0 "R1" V 5380 3550 50 0000 C CNN +F 1 "0.2" V 5300 3550 50 0000 C CNN + 1 5300 3550 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5069E7A9 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "0.1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 5069E7A6 +P 6000 3550 +F 0 "R3" V 6080 3550 50 0000 C CNN +F 1 "0.2" V 6000 3550 50 0000 C CNN + 1 6000 3550 + 1 0 0 -1 +$EndComp +$Comp +L CCVS H1 +U 1 1 5069E78C +P 6800 3500 +F 0 "H1" H 6600 3600 50 0000 C CNN +F 1 "2" H 6600 3450 50 0000 C CNN + 1 6800 3500 + 0 1 1 0 +$EndComp +$Comp +L DC I1 +U 1 1 5069E6DB +P 4800 3500 +F 0 "I1" H 4600 3600 60 0000 C CNN +F 1 "1" H 4600 3450 60 0000 C CNN +F 2 "R1" H 4500 3500 60 0000 C CNN + 1 4800 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/linear2/linear2.brd b/OSCAD/Examples/linear2/linear2.brd new file mode 100644 index 0000000..ab9dee7 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.brd @@ -0,0 +1,398 @@ +PCBNEW-BOARD Version 1 date Tuesday 02 October 2012 12:48:38 AM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 9 +NoConn 0 +Di 48825 32959 59875 43721 +Ndraw 0 +Ntrack 25 +Nzone 0 +BoardThickness 630 +Nmodule 6 +Nnets 6 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "1 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "/a" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "/b" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 5 "N-000005" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "/a" +AddNet "/b" +AddNet "GND" +AddNet "N-000004" +AddNet "N-000005" +$EndNCLASS +$MODULE R3 +Po 58000 34500 0 15 00200000 5069EAF6 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5069EAF6 +AR /5069E7AC +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R1" +T1 0 0 550 500 0 80 N I 21 N "0.2" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 58000 39500 0 15 00200000 5069EAF8 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5069EAF8 +AR /5069E7A9 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R2" +T1 0 0 550 500 0 80 N I 21 N "0.1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "/a" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 58000 37000 0 15 00200000 5069EAFA ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5069EAFA +AR /5069E7A6 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R3" +T1 0 0 550 500 0 80 N I 21 N "0.2" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "/b" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 58000 42500 0 15 00200000 5069EAFC ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5069EAFC +AR /5069E7B0 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R4" +T1 0 0 550 500 0 80 N I 21 N "0.1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 5 "N-000005" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "/a" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R1 +Po 52000 34000 0 15 00200000 5069EAFD ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 5069EAFD +AR /5069E6DB +Op A A 0 +T0 -400 1000 550 500 0 80 N V 21 N "I1" +T1 -450 1000 550 500 0 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE bornier4 +Po 52000 39500 900 15 3EC0ED29 5069EAFE ~~ +Li bornier4 +Cd Bornier d'alimentation 4 pins +Kw DEV +Sc 5069EAFE +AR /5069E78C +Op 0 0 0 +T0 0 -2500 1030 629 900 120 N V 21 N "H1" +T1 0 2000 600 600 900 120 N V 21 N "2" +DS -4000 -1500 -4000 1500 120 21 +DS 4000 1500 4000 -1500 120 21 +DS 4000 1000 -4000 1000 120 21 +DS -4000 -1500 4000 -1500 120 21 +DS -4000 1500 4000 1500 120 21 +$PAD +Sh "2" C 1500 1500 0 0 900 +Dr 600 0 0 +At STD N 00E0FFFF +Ne 3 "GND" +Po -1000 0 +$EndPAD +$PAD +Sh "3" C 1500 1500 0 0 900 +Dr 600 0 0 +At STD N 00E0FFFF +Ne 1 "/a" +Po 1000 0 +$EndPAD +$PAD +Sh "1" R 1500 1500 0 0 900 +Dr 600 0 0 +At STD N 00E0FFFF +Ne 5 "N-000005" +Po -3000 0 +$EndPAD +$PAD +Sh "4" C 1500 1500 0 0 900 +Dr 600 0 0 +At STD N 00E0FFFF +Ne 2 "/b" +Po 3000 0 +$EndPAD +$SHAPE3D +Na "device/bornier_4.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE bornier4 +$TRACK +Po 0 56500 39500 58000 39500 80 -1 +De 0 0 1 0 400000 +Po 0 59500 41000 59500 42500 80 -1 +De 0 0 1 0 800000 +Po 0 58000 39500 59500 41000 80 -1 +De 0 0 1 0 0 +Po 0 52000 38500 55500 38500 80 -1 +De 0 0 1 0 400000 +Po 0 55500 38500 56500 39500 80 -1 +De 0 0 1 0 800000 +Po 0 52000 36500 56000 36500 80 -1 +De 0 0 2 0 400000 +Po 0 56000 36500 56500 37000 80 -1 +De 0 0 2 0 800000 +Po 0 52000 40500 50500 39000 80 -1 +De 0 0 3 0 400000 +Po 0 52500 33500 52500 34000 80 -1 +De 0 0 3 0 800000 +Po 0 52000 33000 52500 33500 80 -1 +De 0 0 3 0 0 +Po 0 51000 33000 52000 33000 80 -1 +De 0 0 3 0 0 +Po 0 50500 33500 51000 33000 80 -1 +De 0 0 3 0 0 +Po 0 50500 39000 50500 33500 80 -1 +De 0 0 3 0 0 +Po 0 59500 34500 59500 37000 80 -1 +De 0 0 3 0 C00000 +Po 0 52500 34000 55000 34000 80 -1 +De 0 0 3 0 400000 +Po 0 58500 33500 59500 34500 80 -1 +De 0 0 3 0 800000 +Po 0 55500 33500 58500 33500 80 -1 +De 0 0 3 0 0 +Po 0 55000 34000 55500 33500 80 -1 +De 0 0 3 0 0 +Po 0 56500 34500 57500 34500 80 -1 +De 0 0 4 0 400000 +Po 0 58500 38500 59500 39500 80 -1 +De 0 0 4 0 800000 +Po 0 58500 35500 58500 38500 80 -1 +De 0 0 4 0 0 +Po 0 57500 34500 58500 35500 80 -1 +De 0 0 4 0 0 +Po 0 51500 34000 52000 34500 80 -1 +De 0 0 4 0 400000 +Po 0 52000 34500 56500 34500 80 -1 +De 0 0 4 0 800000 +Po 0 52000 42500 56500 42500 80 -1 +De 0 0 5 0 C00000 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/linear2/linear2.cir b/OSCAD/Examples/linear2/linear2.cir new file mode 100644 index 0000000..f3a43b2 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:32:43 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 5 VPRINT1 +R4 5 2 0.1 +R1 4 0 0.2 +R2 2 4 0.1 +R3 3 0 0.2 +H1 5 0 2 3 2 +I1 4 0 1 + +.end diff --git a/OSCAD/Examples/linear2/linear2.cir.ckt b/OSCAD/Examples/linear2/linear2.cir.ckt new file mode 100644 index 0000000..04d0eb4 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:32:43 am ist
+
+* Printing option vprint1
+r4 5 2 0.1
+r1 4 0 0.2
+r2 2 4 0.1
+r3 3 0 0.2
+* h1
+i1 4 0 1
+Vh1 2 3 0
+h1 5 0 Vh1 2
+
+.op
+.print v(5)
+.end
diff --git a/OSCAD/Examples/linear2/linear2.cir.ckt.sol b/OSCAD/Examples/linear2/linear2.cir.ckt.sol new file mode 100644 index 0000000..924ce9b --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.cir.ckt.sol @@ -0,0 +1,9 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +R 5 2 0.0000000000 0.0000000000 +R 4 0 0.0000000000 0.0000000000 +R 2 4 0.0000000000 0.0000000000 +R 3 0 0.0000000000 0.0000000000 +I 4 0 0.0000000000 0.0000000000 +V 2 3 0.0000000000 0.0000000000 +H 5 0 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/linear2/linear2.cir.out b/OSCAD/Examples/linear2/linear2.cir.out new file mode 100644 index 0000000..e0328e7 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:32:43 am ist
+
+* Printing option vprint1
+r4 5 2 0.1
+r1 4 0 0.2
+r2 2 4 0.1
+r3 3 0 0.2
+* h1
+i1 4 0 1
+Vh1 2 3 0
+h1 5 0 Vh1 2
+
+.op
+
+* Control Statements
+.control
+run
+print v(5)
+.endc
+.end
diff --git a/OSCAD/Examples/linear2/linear2.cmp b/OSCAD/Examples/linear2/linear2.cmp new file mode 100644 index 0000000..3d50822 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.cmp @@ -0,0 +1,45 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Tuesday 02 October 2012 12:41:01 AM IST + +BeginCmp +TimeStamp = /5069E78C; +Reference = H1; +ValeurCmp = 2; +IdModule = bornier4; +EndCmp + +BeginCmp +TimeStamp = /5069E6DB; +Reference = I1; +ValeurCmp = DC; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /5069E7AC; +Reference = R1; +ValeurCmp = 0.2; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /5069E7A9; +Reference = R2; +ValeurCmp = 0.1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /5069E7A6; +Reference = R3; +ValeurCmp = 0.2; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /5069E7B0; +Reference = R4; +ValeurCmp = 0.1; +IdModule = R3; +EndCmp + +EndListe diff --git a/OSCAD/Examples/linear2/linear2.net b/OSCAD/Examples/linear2/linear2.net new file mode 100644 index 0000000..11706cb --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.net @@ -0,0 +1,63 @@ +# EESchema Netlist Version 1.1 created Tuesday 02 October 2012 12:41:01 AM IST +( + ( /5069E78C bornier4 H1 2 + ( 1 N-000005 ) + ( 2 GND ) + ( 3 /a ) + ( 4 /b ) + ) + ( /5069E6DB R1 I1 DC + ( 1 N-000004 ) + ( 2 GND ) + ) + ( /5069E7AC R3 R1 0.2 + ( 1 N-000004 ) + ( 2 GND ) + ) + ( /5069E7A9 R3 R2 0.1 + ( 1 /a ) + ( 2 N-000004 ) + ) + ( /5069E7A6 R3 R3 0.2 + ( 1 /b ) + ( 2 GND ) + ) + ( /5069E7B0 R3 R4 0.1 + ( 1 N-000005 ) + ( 2 /a ) + ) +) +* +{ Allowed footprints by component: +$component H1 + 1_pin +$endlist +$component I1 + 1_pin +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R4 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} diff --git a/OSCAD/Examples/linear2/linear2.pro b/OSCAD/Examples/linear2/linear2.pro new file mode 100644 index 0000000..a5dcd33 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.pro @@ -0,0 +1,71 @@ +update=Monday 22 October 2012 04:17:19 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/linear2/linear2.proj b/OSCAD/Examples/linear2/linear2.proj new file mode 100644 index 0000000..8bb7fa3 --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.proj @@ -0,0 +1 @@ +schematicFile linear2.sch diff --git a/OSCAD/Examples/linear2/linear2.sch b/OSCAD/Examples/linear2/linear2.sch new file mode 100644 index 0000000..c85a06a --- /dev/null +++ b/OSCAD/Examples/linear2/linear2.sch @@ -0,0 +1,181 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:32:49 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:linear2-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6450 4000 +Wire Wire Line + 6450 4000 6450 3800 +Connection ~ 6750 3000 +Wire Wire Line + 6750 3000 6750 2850 +Connection ~ 6000 4000 +Wire Wire Line + 6000 3800 6000 4000 +Connection ~ 5300 3000 +Wire Wire Line + 5300 3300 5300 3000 +Wire Wire Line + 6850 3800 6850 4000 +Wire Wire Line + 6850 4000 4800 4000 +Wire Wire Line + 4800 4000 4800 3950 +Wire Wire Line + 5850 3000 6100 3000 +Wire Wire Line + 4800 3050 4800 3000 +Wire Wire Line + 4800 3000 5350 3000 +Wire Wire Line + 6600 3000 6850 3000 +Wire Wire Line + 6850 3000 6850 3200 +Wire Wire Line + 5300 3800 5300 4000 +Connection ~ 5300 4000 +Wire Wire Line + 6000 3000 6000 3150 +Connection ~ 6000 3000 +Wire Wire Line + 5600 4000 5600 4150 +Connection ~ 5600 4000 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5069EA51 +P 6450 3800 +F 0 "#FLG01" H 6450 4070 30 0001 C CNN +F 1 "PWR_FLAG" H 6450 4030 30 0000 C CNN + 1 6450 3800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5069EA30 +P 5600 4150 +F 0 "#PWR02" H 5600 4150 30 0001 C CNN +F 1 "GND" H 5600 4080 30 0001 C CNN + 1 5600 4150 + 1 0 0 -1 +$EndComp +$Comp +L VPRINT1 U1 +U 1 1 5069E9D3 +P 6750 2550 +F 0 "U1" H 6600 2650 50 0001 C CNN +F 1 "VPRINT1" H 6900 2650 50 0000 C CNN + 1 6750 2550 + 1 0 0 -1 +$EndComp +Text Label 6600 3550 0 60 ~ 0 +b +Text Label 6600 3450 0 60 ~ 0 +a +Text Label 6000 3300 0 60 ~ 0 +b +Text Label 6000 3150 0 60 ~ 0 +a +$Comp +L R R4 +U 1 1 5069E7B0 +P 6350 3000 +F 0 "R4" V 6430 3000 50 0000 C CNN +F 1 "0.1" V 6350 3000 50 0000 C CNN + 1 6350 3000 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 5069E7AC +P 5300 3550 +F 0 "R1" V 5380 3550 50 0000 C CNN +F 1 "0.2" V 5300 3550 50 0000 C CNN + 1 5300 3550 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5069E7A9 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "0.1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 5069E7A6 +P 6000 3550 +F 0 "R3" V 6080 3550 50 0000 C CNN +F 1 "0.2" V 6000 3550 50 0000 C CNN + 1 6000 3550 + 1 0 0 -1 +$EndComp +$Comp +L CCVS H1 +U 1 1 5069E78C +P 6800 3500 +F 0 "H1" H 6600 3600 50 0000 C CNN +F 1 "2" H 6600 3450 50 0000 C CNN + 1 6800 3500 + 0 1 1 0 +$EndComp +$Comp +L DC I1 +U 1 1 5069E6DB +P 4800 3500 +F 0 "I1" H 4600 3600 60 0000 C CNN +F 1 "1" H 4600 3450 60 0000 C CNN +F 2 "R1" H 4500 3500 60 0000 C CNN + 1 4800 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/mixMode/analysis b/OSCAD/Examples/mixMode/analysis new file mode 100644 index 0000000..bf5e632 --- /dev/null +++ b/OSCAD/Examples/mixMode/analysis @@ -0,0 +1 @@ +.tran 10e-09 1e-06 0e-00 diff --git a/OSCAD/Examples/mixMode/mixMode-cache.bak b/OSCAD/Examples/mixMode/mixMode-cache.bak new file mode 100644 index 0000000..9e5fbb3 --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode-cache.bak @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:40:24 AM IST +#encoding utf-8 +# +# 74HCT04 +# +DEF 74HCT04 U 0 30 Y Y 6 F N +F0 "U" 150 100 40 H V C CNN +F1 "74HCT04" 200 -100 40 H V C CNN +ALIAS 74HC14 74HC04 74LS14 +DRAW +P 4 0 0 0 -150 150 -150 -150 150 0 -150 150 N +X GND 7 -50 -100 0 U 30 20 0 0 W N +X VCC 14 -50 100 0 D 30 20 0 0 W N +X ~ 1 -450 0 300 R 60 60 1 1 I +X ~ 2 450 0 300 L 60 60 1 1 O I +X ~ 3 -450 0 300 R 60 60 2 1 I +X ~ 4 450 0 300 L 60 60 2 1 O I +X ~ 5 -450 0 300 R 60 60 3 1 I +X ~ 6 450 0 300 L 60 60 3 1 O I +X ~ 8 450 0 300 L 60 60 4 1 O I +X ~ 9 -450 0 300 R 60 60 4 1 I +X ~ 10 450 0 300 L 60 60 5 1 O I +X ~ 11 -450 0 300 R 60 60 5 1 I +X ~ 12 450 0 300 L 60 60 6 1 O I +X ~ 13 -450 0 300 R 60 60 6 1 I +X ~ 1 -450 0 300 R 60 60 1 2 I I +X ~ 2 450 0 300 L 60 60 1 2 O +X ~ 3 -450 0 300 R 60 60 2 2 I I +X ~ 4 450 0 300 L 60 60 2 2 O +X ~ 5 -450 0 300 R 60 60 3 2 I I +X ~ 6 450 0 300 L 60 60 3 2 O +X ~ 8 450 0 300 L 60 60 4 2 O +X ~ 9 -450 0 300 R 60 60 4 2 I I +X ~ 10 450 0 300 L 60 60 5 2 O +X ~ 11 -450 0 300 R 60 60 5 2 I I +X ~ 12 450 0 300 L 60 60 6 2 O +X ~ 13 -450 0 300 R 60 60 6 2 I I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/mixMode/mixMode-cache.lib b/OSCAD/Examples/mixMode/mixMode-cache.lib new file mode 100644 index 0000000..ab75e8e --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:41:04 AM IST +#encoding utf-8 +# +# 74HCT04 +# +DEF 74HCT04 U 0 30 Y Y 6 F N +F0 "U" 150 100 40 H V C CNN +F1 "74HCT04" 200 -100 40 H V C CNN +ALIAS 74HC14 74HC04 74LS14 +DRAW +P 4 0 0 0 -150 150 -150 -150 150 0 -150 150 N +X GND 7 -50 -100 0 U 30 20 0 0 W N +X VCC 14 -50 100 0 D 30 20 0 0 W N +X ~ 1 -450 0 300 R 60 60 1 1 I +X ~ 2 450 0 300 L 60 60 1 1 O I +X ~ 3 -450 0 300 R 60 60 2 1 I +X ~ 4 450 0 300 L 60 60 2 1 O I +X ~ 5 -450 0 300 R 60 60 3 1 I +X ~ 6 450 0 300 L 60 60 3 1 O I +X ~ 8 450 0 300 L 60 60 4 1 O I +X ~ 9 -450 0 300 R 60 60 4 1 I +X ~ 10 450 0 300 L 60 60 5 1 O I +X ~ 11 -450 0 300 R 60 60 5 1 I +X ~ 12 450 0 300 L 60 60 6 1 O I +X ~ 13 -450 0 300 R 60 60 6 1 I +X ~ 1 -450 0 300 R 60 60 1 2 I I +X ~ 2 450 0 300 L 60 60 1 2 O +X ~ 3 -450 0 300 R 60 60 2 2 I I +X ~ 4 450 0 300 L 60 60 2 2 O +X ~ 5 -450 0 300 R 60 60 3 2 I I +X ~ 6 450 0 300 L 60 60 3 2 O +X ~ 8 450 0 300 L 60 60 4 2 O +X ~ 9 -450 0 300 R 60 60 4 2 I I +X ~ 10 450 0 300 L 60 60 5 2 O +X ~ 11 -450 0 300 R 60 60 5 2 I I +X ~ 12 450 0 300 L 60 60 6 2 O +X ~ 13 -450 0 300 R 60 60 6 2 I I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/mixMode/mixMode.bak b/OSCAD/Examples/mixMode/mixMode.bak new file mode 100644 index 0000000..1f9d2dd --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.bak @@ -0,0 +1,165 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:40:24 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:mixMode-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB729 +P 7150 2900 +F 0 "U1" H 7000 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 7300 3000 50 0000 C CNN + 2 7150 2900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB722 +P 5600 2950 +F 0 "U1" H 5450 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 5750 3050 50 0000 C CNN + 1 5600 2950 + 1 0 0 -1 +$EndComp +Connection ~ 5750 4400 +Wire Wire Line + 5750 4400 5750 4300 +Connection ~ 7150 3350 +Wire Wire Line + 7150 3350 7150 3200 +Wire Wire Line + 5950 3350 4800 3350 +Wire Wire Line + 7350 4000 7350 4400 +Wire Wire Line + 7350 4400 4800 4400 +Connection ~ 5600 3350 +Wire Wire Line + 5600 3250 5600 3350 +Wire Wire Line + 5350 3350 5350 3650 +Wire Wire Line + 4800 4550 4800 4250 +Connection ~ 4800 4400 +Connection ~ 5350 3350 +Wire Wire Line + 6850 3350 7350 3350 +Wire Wire Line + 7350 3350 7350 3500 +Wire Wire Line + 6350 3000 6350 3250 +Wire Wire Line + 5350 4400 5350 4150 +Connection ~ 5350 4400 +$Comp +L PWR_FLAG #FLG01 +U 1 1 50653022 +P 6350 3000 +F 0 "#FLG01" H 6350 3270 30 0001 C CNN +F 1 "PWR_FLAG" H 6350 3230 30 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 7350 3750 +F 0 "R2" V 7430 3750 50 0000 C CNN +F 1 "1000" V 7350 3750 50 0000 C CNN + 1 7350 3750 + 1 0 0 -1 +$EndComp +$Comp +L 74HC04 U2 +U 1 1 505FDE5C +P 6400 3350 +F 0 "U2" H 6550 3450 40 0000 C CNN +F 1 "74HC04" H 6600 3250 40 0000 C CNN + 1 6400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 505CA177 +P 5750 4300 +F 0 "#FLG02" H 5750 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4530 30 0000 C CNN + 1 5750 4300 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 5350 3900 +F 0 "R1" V 5430 3900 50 0000 C CNN +F 1 "1000" V 5350 3900 50 0000 C CNN + 1 5350 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 505C9EE8 +P 4800 4550 +F 0 "#PWR03" H 4800 4550 30 0001 C CNN +F 1 "GND" H 4800 4480 30 0001 C CNN + 1 4800 4550 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 505C9ECF +P 4800 3800 +F 0 "v1" H 4600 3900 60 0000 C CNN +F 1 "PULSE" H 4600 3750 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/mixMode/mixMode.brd b/OSCAD/Examples/mixMode/mixMode.brd new file mode 100644 index 0000000..a68ce3f --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.brd @@ -0,0 +1,400 @@ +PCBNEW-BOARD Version 1 date Friday 28 September 2012 10:42:25 AM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 7 +NoConn 7 +Di 40017 31950 63751 53251 +Ndraw 0 +Ntrack 0 +Nzone 0 +BoardThickness 630 +Nmodule 7 +Nnets 7 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "28 sep 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000001" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000004" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000005" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 5 "N-000006" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 6 "VCC" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000001" +AddNet "N-000004" +AddNet "N-000005" +AddNet "N-000006" +AddNet "VCC" +$EndNCLASS +$MODULE R1 +Po 47000 39000 0 15 00200000 50653175 ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 50653175 +AR /505C9F25 +Op A A 0 +T0 -400 1000 550 500 0 80 N V 21 N "R1" +T1 -450 1000 550 500 0 80 N I 21 N "1000" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 5 "N-000006" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE R1 +Po 46000 43000 0 15 00200000 50653177 ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 50653177 +AR /50652FB6 +Op A A 0 +T0 -400 1000 550 500 0 80 N V 21 N "R2" +T1 -450 1000 550 500 0 80 N I 21 N "R" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE DIP-14__300_ELL +Po 52500 34000 0 15 00200000 50653178 ~~ +Li DIP-14__300_ELL +Cd 14 pins DIL package, elliptical pads +Kw DIL +Sc 50653178 +AR /505FDE5C +Op 0 0 0 +T0 -2000 -500 600 450 0 113 N V 21 N "U2" +T1 500 500 600 450 0 113 N V 21 N "74HC04" +DS -4000 -1000 4000 -1000 150 21 +DS 4000 1000 -4000 1000 150 21 +DS -4000 1000 -4000 -1000 150 21 +DS -4000 -500 -3500 -500 150 21 +DS -3500 -500 -3500 500 150 21 +DS -3500 500 -4000 500 150 21 +DS 4000 -1000 4000 1000 150 21 +$PAD +Sh "1" R 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000005" +Po -3000 1500 +$EndPAD +$PAD +Sh "2" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000004" +Po -2000 1500 +$EndPAD +$PAD +Sh "3" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -1000 1500 +$EndPAD +$PAD +Sh "4" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 0 1500 +$EndPAD +$PAD +Sh "5" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 1000 1500 +$EndPAD +$PAD +Sh "6" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 2000 1500 +$EndPAD +$PAD +Sh "7" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 3000 1500 +$EndPAD +$PAD +Sh "8" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 3000 -1500 +$EndPAD +$PAD +Sh "9" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 2000 -1500 +$EndPAD +$PAD +Sh "10" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 1000 -1500 +$EndPAD +$PAD +Sh "11" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 0 -1500 +$EndPAD +$PAD +Sh "12" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -1000 -1500 +$EndPAD +$PAD +Sh "13" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -2000 -1500 +$EndPAD +$PAD +Sh "14" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 6 "VCC" +Po -3000 -1500 +$EndPAD +$SHAPE3D +Na "dil/dil_14.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE DIP-14__300_ELL +$MODULE 2PIN_6mm +Po 55000 50500 0 15 00200000 50653179 ~~ +Li 2PIN_6mm +Cd module 2 pin (trou 6 mm) +Kw DEV +Sc 50653179 +AR /505C9ECF +Op 0 0 0 +T0 0 500 600 600 0 120 N V 21 N "v1" +T1 0 -500 600 600 0 120 N V 21 N "PULSE" +DS -8500 -2500 8500 -2500 150 21 +DS 8500 -2500 8500 2500 150 21 +DS 8500 2500 -8500 2500 150 21 +DS -8500 2500 -8500 -2500 150 21 +$PAD +Sh "1" C 4000 4000 0 0 0 +Dr 2400 0 0 +At STD N 00E0FFFF +Ne 5 "N-000006" +Po -5900 0 +$EndPAD +$PAD +Sh "2" C 4000 4000 0 0 0 +Dr 2400 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 5900 0 +$EndPAD +$SHAPE3D +Na "device/douille_4mm(red).wrl" +Sc 1.800000 1.800000 1.800000 +Of -0.590000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$SHAPE3D +Na "device/douille_4mm(red).wrl" +Sc 1.800000 1.800000 1.800000 +Of 0.590000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE 2PIN_6mm +$MODULE 1pin +Po 50000 44000 0 15 00200000 5065317A ~~ +Li 1pin +Cd module 1 pin (ou trou mecanique de percage) +Kw DEV +Sc 5065317A +AR /505FD8A0 +Op 0 0 0 +T0 0 -1200 400 400 0 100 N V 21 N "U1" +T1 0 1100 400 400 0 100 N I 21 N "ADC" +DC 0 0 0 -900 150 21 +$PAD +Sh "1" C 1600 1600 0 0 0 +Dr 1200 0 0 +At STD N 00E0FFFF +Ne 5 "N-000006" +Po 0 0 +$EndPAD +$EndMODULE 1pin +$MODULE 1pin +Po 59500 43500 0 15 00200000 5065317C ~~ +Li 1pin +Cd module 1 pin (ou trou mecanique de percage) +Kw DEV +Sc 5065317C +AR /505FDC21 +Op 0 0 0 +T0 0 -1200 400 400 0 100 N V 21 N "U3" +T1 0 1100 400 400 0 100 N I 21 N "DAC" +DC 0 0 0 -900 150 21 +$PAD +Sh "1" C 1600 1600 0 0 0 +Dr 1200 0 0 +At STD N 00E0FFFF +Ne 3 "N-000004" +Po 0 0 +$EndPAD +$EndMODULE 1pin +$MODULE 1pin +Po 41500 45500 0 15 00200000 5065317E ~~ +Li 1pin +Cd module 1 pin (ou trou mecanique de percage) +Kw DEV +Sc 5065317E +AR /5061678B +Op 0 0 0 +T0 0 -1200 400 400 0 100 N V 21 N "U4" +T1 0 1100 400 400 0 100 N I 21 N "VPLOT1" +DC 0 0 0 -900 150 21 +$PAD +Sh "1" C 1600 1600 0 0 0 +Dr 1200 0 0 +At STD N 00E0FFFF +Ne 5 "N-000006" +Po 0 0 +$EndPAD +$EndMODULE 1pin +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/mixMode/mixMode.cir b/OSCAD/Examples/mixMode/mixMode.cir new file mode 100644 index 0000000..3db9950 --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:41:09 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 3 4 VPLOT8_1 +R2 4 0 1000 +U2 3 4 0 2 74HC04 +R1 3 0 1000 +v1 3 0 PULSE + +.end diff --git a/OSCAD/Examples/mixMode/mixMode.cir.ckt b/OSCAD/Examples/mixMode/mixMode.cir.ckt new file mode 100644 index 0000000..590cf66 --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:41:09 am ist + +* Plotting option vplot8_1 +r2 4 0 1000 +* 74hc04 +r1 3 0 1000 +v1 3 0 pulse(0 5 0 1e-8 1e-8 0.25e-6 0.5e-6) +a1 [3] [3_in] u2adc +a2 3_in 4_out u2 +a3 [4_out] [4] u2dac +.model u2 d_inverter +.model u2adc adc_bridge(in_low=0.8 in_high=2.0) +.model u2dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 +.plot v(3) v(4) +.end diff --git a/OSCAD/Examples/mixMode/mixMode.cir.out b/OSCAD/Examples/mixMode/mixMode.cir.out new file mode 100644 index 0000000..27f8a8c --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:41:09 am ist + +* Plotting option vplot8_1 +r2 4 0 1000 +* 74hc04 +r1 3 0 1000 +v1 3 0 pulse(0 5 0 1e-8 1e-8 0.25e-6 0.5e-6) +a1 [3] [3_in] u2adc +a2 3_in 4_out u2 +a3 [4_out] [4] u2dac +.model u2 d_inverter +.model u2adc adc_bridge(in_low=0.8 in_high=2.0) +.model u2dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 + +* Control Statements +.control +run +plot v(3) v(4) +.endc +.end diff --git a/OSCAD/Examples/mixMode/mixMode.cmp b/OSCAD/Examples/mixMode/mixMode.cmp new file mode 100644 index 0000000..8a56a56 --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.cmp @@ -0,0 +1,52 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Friday 28 September 2012 10:41:02 AM IST + +BeginCmp +TimeStamp = /505C9F25; +Reference = R1; +ValeurCmp = 1000; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /50652FB6; +Reference = R2; +ValeurCmp = R; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /505FD8A0; +Reference = U1; +ValeurCmp = ADC; +IdModule = 1pin; +EndCmp + +BeginCmp +TimeStamp = /505FDE5C; +Reference = U2; +ValeurCmp = 74HC04; +IdModule = DIP-14__300_ELL; +EndCmp + +BeginCmp +TimeStamp = /505FDC21; +Reference = U3; +ValeurCmp = DAC; +IdModule = 1pin; +EndCmp + +BeginCmp +TimeStamp = /5061678B; +Reference = U4; +ValeurCmp = VPLOT1; +IdModule = 1pin; +EndCmp + +BeginCmp +TimeStamp = /505C9ECF; +Reference = v1; +ValeurCmp = PULSE; +IdModule = 2PIN_6mm; +EndCmp + +EndListe diff --git a/OSCAD/Examples/mixMode/mixMode.net b/OSCAD/Examples/mixMode/mixMode.net new file mode 100644 index 0000000..0175d5c --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.net @@ -0,0 +1,77 @@ +# EESchema Netlist Version 1.1 created Friday 28 September 2012 12:26:55 PM IST +( + ( /50653344 $noname U5 VPLOT1 {Lib=VPLOT1} + ( 1 N-000005 ) + ) + ( /50652FB6 $noname R2 1000 {Lib=R} + ( 1 N-000005 ) + ( 2 GND ) + ) + ( /5061678B $noname U4 VPLOT1 {Lib=VPLOT1} + ( 1 N-000001 ) + ) + ( /505FDE5C $noname U2 74HC04 {Lib=74HC04} + ( 1 N-000006 ) + ( 2 N-000004 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /505FDC21 $noname U3 DAC {Lib=DAC} + ( 1 N-000004 ) + ( 2 N-000005 ) + ) + ( /505FD8A0 $noname U1 ADC {Lib=ADC} + ( 1 N-000001 ) + ( 2 N-000006 ) + ) + ( /505C9F25 $noname R1 1000 {Lib=R} + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /505C9ECF $noname v1 PULSE {Lib=PULSE} + ( 1 N-000001 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component v1 + 1_pin +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + U1 1 + v1 1 + R1 1 + U4 1 +Net 2 "GND" "GND" + v1 2 + R2 2 + R1 2 + U2 7 +Net 4 "" "" + U2 2 + U3 1 +Net 5 "" "" + U3 2 + U5 1 + R2 1 +Net 6 "" "" + U1 2 + U2 1 +} +#End diff --git a/OSCAD/Examples/mixMode/mixMode.pro b/OSCAD/Examples/mixMode/mixMode.pro new file mode 100644 index 0000000..353cc12 --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.pro @@ -0,0 +1,71 @@ +update=Tuesday 30 October 2012 11:12:31 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/mixMode/mixMode.proj b/OSCAD/Examples/mixMode/mixMode.proj new file mode 100644 index 0000000..465ba2d --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.proj @@ -0,0 +1 @@ +schematicFile mixMode.sch diff --git a/OSCAD/Examples/mixMode/mixMode.sch b/OSCAD/Examples/mixMode/mixMode.sch new file mode 100644 index 0000000..493dc4e --- /dev/null +++ b/OSCAD/Examples/mixMode/mixMode.sch @@ -0,0 +1,165 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:41:04 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:mixMode-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB729 +P 7150 2900 +F 0 "U1" H 7000 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 7300 3000 50 0000 C CNN + 2 7150 2900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB722 +P 5600 2950 +F 0 "U1" H 5450 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 5750 3050 50 0000 C CNN + 1 5600 2950 + 1 0 0 -1 +$EndComp +Connection ~ 5750 4400 +Wire Wire Line + 5750 4400 5750 4300 +Connection ~ 7150 3350 +Wire Wire Line + 7150 3350 7150 3200 +Wire Wire Line + 5950 3350 4800 3350 +Wire Wire Line + 7350 4000 7350 4400 +Wire Wire Line + 7350 4400 4800 4400 +Connection ~ 5600 3350 +Wire Wire Line + 5600 3250 5600 3350 +Wire Wire Line + 5350 3350 5350 3650 +Wire Wire Line + 4800 4550 4800 4250 +Connection ~ 4800 4400 +Connection ~ 5350 3350 +Wire Wire Line + 6850 3350 7350 3350 +Wire Wire Line + 7350 3350 7350 3500 +Wire Wire Line + 6350 3000 6350 3250 +Wire Wire Line + 5350 4400 5350 4150 +Connection ~ 5350 4400 +$Comp +L PWR_FLAG #FLG01 +U 1 1 50653022 +P 6350 3000 +F 0 "#FLG01" H 6350 3270 30 0001 C CNN +F 1 "PWR_FLAG" H 6350 3230 30 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 7350 3750 +F 0 "R2" V 7430 3750 50 0000 C CNN +F 1 "1000" V 7350 3750 50 0000 C CNN + 1 7350 3750 + 1 0 0 -1 +$EndComp +$Comp +L 74HC04 U2 +U 1 1 505FDE5C +P 6400 3350 +F 0 "U2" H 6550 3450 40 0000 C CNN +F 1 "74HC04" H 6600 3250 40 0000 C CNN + 1 6400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 505CA177 +P 5750 4300 +F 0 "#FLG02" H 5750 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4530 30 0000 C CNN + 1 5750 4300 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 5350 3900 +F 0 "R1" V 5430 3900 50 0000 C CNN +F 1 "1000" V 5350 3900 50 0000 C CNN + 1 5350 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 505C9EE8 +P 4800 4550 +F 0 "#PWR03" H 4800 4550 30 0001 C CNN +F 1 "GND" H 4800 4480 30 0001 C CNN + 1 4800 4550 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 505C9ECF +P 4800 3800 +F 0 "v1" H 4600 3900 60 0000 C CNN +F 1 "PULSE" H 4600 3750 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/modifiedNodalExample/$savepcb.brd b/OSCAD/Examples/modifiedNodalExample/$savepcb.brd new file mode 100644 index 0000000..d688470 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/$savepcb.brd @@ -0,0 +1,366 @@ +PCBNEW-BOARD Version 1 date Monday 01 October 2012 11:13:48 AM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 8 +NoConn 2 +Di 48625 31085 56375 36121 +Ndraw 0 +Ntrack 20 +Nzone 0 +BoardThickness 630 +Nmodule 6 +Nnets 5 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "1 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000002" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000002" +AddNet "N-000003" +AddNet "N-000004" +$EndNCLASS +$MODULE R3 +Po 54500 32500 1800 15 50692D16 50692991 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50692991 +AR /50692613 +Op 0 A 0 +T0 0 0 550 500 2700 80 N V 21 N "R1" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 50500 35500 1800 15 00200000 50692993 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50692993 +AR /5067FEAC +Op 0 A 0 +T0 0 0 550 500 1800 80 N V 21 N "R2" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 54500 34000 0 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b/OSCAD/Examples/modifiedNodalExample/analysis new file mode 100644 index 0000000..162ad08 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/analysis @@ -0,0 +1 @@ +.op
\ No newline at end of file diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodal.proj b/OSCAD/Examples/modifiedNodalExample/modifiedNodal.proj new file mode 100644 index 0000000..7b01bfb --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodal.proj @@ -0,0 +1 @@ +schematicFile modifiedNodal.sch diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample-cache.bak b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample-cache.bak new file mode 100644 index 0000000..35c96a0 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample-cache.bak @@ -0,0 +1,72 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 22 October 2012 03:59:40 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 I +X - 2 0 -450 300 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -400 300 U 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample-cache.lib b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample-cache.lib new file mode 100644 index 0000000..7d128f1 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample-cache.lib @@ -0,0 +1,72 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:46:55 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.000 b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.000 new file mode 100644 index 0000000..8be4d3d --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.000 @@ -0,0 +1,326 @@ +PCBNEW-BOARD Version 1 date Monday 01 October 2012 10:59:42 AM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 8 +NoConn 8 +Di 48125 31765 56375 38121 +Ndraw 0 +Ntrack 0 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/5067FE8A +Op A A 0 +T0 -400 1000 550 500 0 80 N V 21 N "v1" +T1 -450 1000 550 500 0 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE R1 +Po 49500 35000 0 15 00200000 5069299A ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 5069299A +AR /5067FE8E +Op A A 0 +T0 -400 1000 550 500 0 80 N V 21 N "v2" +T1 -450 1000 550 500 0 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.bak b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.bak new file mode 100644 index 0000000..0917845 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.bak @@ -0,0 +1,169 @@ +EESchema Schematic File Version 2 date Monday 22 October 2012 03:59:40 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:modifiedNodalExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5300 2650 5300 3250 +Wire Wire Line + 5300 3250 4950 3250 +Wire Wire Line + 4950 3250 4950 3550 +Connection ~ 4750 4250 +Wire Wire Line + 4750 4250 4750 4400 +Wire Wire Line + 4650 3050 4100 3050 +Wire Wire Line + 4100 3050 4100 3350 +Wire Wire Line + 4100 4250 5800 4250 +Wire Wire Line + 5550 3350 5800 3350 +Wire Wire Line + 4100 3350 4350 3350 +Wire Wire Line + 4850 3350 5050 3350 +Connection ~ 4950 3350 +Wire Wire Line + 4950 4050 4950 4250 +Connection ~ 4950 4250 +Wire Wire Line + 5800 3350 5800 3050 +Wire Wire Line + 5800 3050 5150 3050 +Wire Wire Line + 5300 4250 5300 4100 +Connection ~ 5300 4250 +$Comp +L VPRINT1 U1 +U 1 1 50692E86 +P 5300 2250 +F 0 "U1" H 5150 2350 50 0001 C CNN +F 1 "VPRINT1" H 5450 2350 50 0000 C CNN + 1 5300 2250 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5069279A +P 5300 4100 +F 0 "#FLG01" H 5300 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 4330 30 0000 C CNN + 1 5300 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50692771 +P 4750 4400 +F 0 "#PWR02" H 4750 4400 30 0001 C CNN +F 1 "GND" H 4750 4330 30 0001 C CNN + 1 4750 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50692628 +P 5300 3350 +F 0 "R3" V 5380 3350 50 0000 C CNN +F 1 "1" V 5300 3350 50 0000 C CNN + 1 5300 3350 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 5069261E +P 4900 3050 +F 0 "R4" V 4980 3050 50 0000 C CNN +F 1 "1" V 4900 3050 50 0000 C CNN + 1 4900 3050 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 50692613 +P 4600 3350 +F 0 "R1" V 4680 3350 50 0000 C CNN +F 1 "1" V 4600 3350 50 0000 C CNN + 1 4600 3350 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5067FEAC +P 4950 3800 +F 0 "R2" V 5030 3800 50 0000 C CNN +F 1 "1" V 4950 3800 50 0000 C CNN + 1 4950 3800 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5067FE8E +P 5800 3800 +F 0 "v2" H 5600 3900 60 0000 C CNN +F 1 "10" H 5600 3750 60 0000 C CNN +F 2 "R3" H 5500 3800 60 0000 C CNN + 1 5800 3800 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5067FE8A +P 4100 3800 +F 0 "v1" H 3900 3900 60 0000 C CNN +F 1 "5" H 3900 3750 60 0000 C CNN +F 2 "R3" H 3800 3800 60 0000 C CNN + 1 4100 3800 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.brd b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.brd new file mode 100644 index 0000000..0eb5ac6 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.brd @@ -0,0 +1,386 @@ +PCBNEW-BOARD Version 1 date Monday 01 October 2012 11:15:23 AM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 8 +NoConn 0 +Di 48625 31085 57041 36121 +Ndraw 0 +Ntrack 30 +Nzone 0 +BoardThickness 630 +Nmodule 6 +Nnets 5 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "1 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000002" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000002" +AddNet "N-000003" +AddNet "N-000004" +$EndNCLASS +$MODULE R3 +Po 54500 32500 1800 15 50692D16 50692991 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50692991 +AR /50692613 +Op 0 A 0 +T0 0 0 550 500 2700 80 N V 21 N "R1" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 50500 35500 1800 15 00200000 50692993 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50692993 +AR /5067FEAC +Op 0 A 0 +T0 0 0 550 500 1800 80 N V 21 N "R2" +T1 0 0 550 500 1800 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 54500 34000 0 15 00200000 50692995 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50692995 +AR /50692628 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R3" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000002" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 54500 35500 0 15 00200000 50692997 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50692997 +AR /5069261E +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R4" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R1 +Po 49500 32500 1800 15 00200000 50692998 ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 50692998 +AR /5067FE8A +Op A A 0 +T0 -400 1000 550 500 1800 80 N V 21 N "v1" +T1 -450 1000 550 500 1800 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE R1 +Po 49500 34000 1800 15 00200000 5069299A ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 5069299A +AR /5067FE8E +Op A A 0 +T0 -400 1000 550 500 1800 80 N V 21 N "v2" +T1 -450 1000 550 500 1800 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$TRACK +Po 0 49000 34000 49500 33500 80 -1 +De 0 0 1 0 400000 +Po 0 49500 33000 49000 32500 80 -1 +De 0 0 1 0 800000 +Po 0 49500 33500 49500 33000 80 -1 +De 0 0 1 0 0 +Po 0 49000 35500 49500 35000 80 -1 +De 0 0 1 0 400000 +Po 0 49500 34500 49000 34000 80 -1 +De 0 0 1 0 800000 +Po 0 49500 35000 49500 34500 80 -1 +De 0 0 1 0 0 +Po 0 52000 35500 52500 36000 80 -1 +De 0 0 2 0 400000 +Po 0 57000 35000 56000 34000 80 -1 +De 0 0 2 0 800000 +Po 0 57000 35500 57000 35000 80 -1 +De 0 0 2 0 0 +Po 0 56500 36000 57000 35500 80 -1 +De 0 0 2 0 0 +Po 0 56000 36000 56500 36000 80 -1 +De 0 0 2 0 0 +Po 0 52500 36000 56000 36000 80 -1 +De 0 0 2 0 0 +Po 0 56000 32500 55500 33000 80 -1 +De 0 0 2 0 400000 +Po 0 55500 33500 56000 34000 80 -1 +De 0 0 2 0 800000 +Po 0 55500 33000 55500 33500 80 -1 +De 0 0 2 0 0 +Po 0 53000 32500 53500 33000 80 -1 +De 0 0 3 0 400000 +Po 0 54000 35500 56000 35500 80 -1 +De 0 0 3 0 800000 +Po 0 53500 35000 54000 35500 80 -1 +De 0 0 3 0 0 +Po 0 53500 33000 53500 35000 80 -1 +De 0 0 3 0 0 +Po 0 50000 32500 50500 32500 80 -1 +De 0 0 3 0 400000 +Po 0 52500 33000 53000 32500 80 -1 +De 0 0 3 0 800000 +Po 0 51000 33000 52500 33000 80 -1 +De 0 0 3 0 0 +Po 0 50500 32500 51000 33000 80 -1 +De 0 0 3 0 0 +Po 0 50000 34000 50500 34000 80 -1 +De 0 0 4 0 400000 +Po 0 52500 33500 53000 34000 80 -1 +De 0 0 4 0 800000 +Po 0 51000 33500 52500 33500 80 -1 +De 0 0 4 0 0 +Po 0 50500 34000 51000 33500 80 -1 +De 0 0 4 0 0 +Po 0 53000 35500 52500 35000 80 -1 +De 0 0 4 0 400000 +Po 0 52500 34500 53000 34000 80 -1 +De 0 0 4 0 800000 +Po 0 52500 35000 52500 34500 80 -1 +De 0 0 4 0 0 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir new file mode 100644 index 0000000..e2ac261 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:47:07 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 4 VPRINT1 +R3 2 4 1 +R4 2 3 1 +R1 4 3 1 +R2 4 0 1 +v2 2 0 10 +v1 3 0 5 + +.end diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.ckt b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.ckt new file mode 100644 index 0000000..3a980a1 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:47:07 am ist + +* Printing option vprint1 +r3 2 4 1 +r4 2 3 1 +r1 4 3 1 +r2 4 0 1 +v2 2 0 10 +v1 3 0 5 + +.op +.print v(4) +.end diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.ckt.sol b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.ckt.sol new file mode 100644 index 0000000..9332aad --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.ckt.sol @@ -0,0 +1,8 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +R 2 4 0.0000000000 0.0000000000 +R 2 3 0.0000000000 0.0000000000 +R 4 3 0.0000000000 0.0000000000 +R 4 0 0.0000000000 0.0000000000 +V 2 0 0.0000000000 0.0000000000 +V 3 0 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.out b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.out new file mode 100644 index 0000000..8ee50f6 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:47:07 am ist + +* Printing option vprint1 +r3 2 4 1 +r4 2 3 1 +r1 4 3 1 +r2 4 0 1 +v2 2 0 10 +v1 3 0 5 + +.op + +* Control Statements +.control +run +print v(4) +.endc +.end diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cmp b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cmp new file mode 100644 index 0000000..8d4d327 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.cmp @@ -0,0 +1,45 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 01 October 2012 11:03:36 AM IST + +BeginCmp +TimeStamp = /50692613; +Reference = R1; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /5067FEAC; +Reference = R2; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50692628; +Reference = R3; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /5069261E; +Reference = R4; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /5067FE8A; +Reference = v1; +ValeurCmp = DC; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /5067FE8E; +Reference = v2; +ValeurCmp = DC; +IdModule = R1; +EndCmp + +EndListe diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.net b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.net new file mode 100644 index 0000000..997296f --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.net @@ -0,0 +1,80 @@ +# EESchema Netlist Version 1.1 created Monday 01 October 2012 11:23:34 AM IST +( + ( /50692628 $noname R3 1 {Lib=R} + ( 1 N-000003 ) + ( 2 N-000004 ) + ) + ( /5069261E $noname R4 1 {Lib=R} + ( 1 N-000003 ) + ( 2 N-000001 ) + ) + ( /50692613 $noname R1 1 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000001 ) + ) + ( /5067FEAC $noname R2 1 {Lib=R} + ( 1 N-000004 ) + ( 2 GND ) + ) + ( /5067FE8E R3 v2 DC {Lib=DC} + ( 1 N-000003 ) + ( 2 GND ) + ) + ( /5067FE8A R3 v1 DC {Lib=DC} + ( 1 N-000001 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R4 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component v2 + 1_pin +$endlist +$component v1 + 1_pin +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R4 2 + R1 2 + v1 1 +Net 2 "GND" "GND" + v1 2 + v2 2 + R2 2 +Net 3 "" "" + v2 1 + R3 1 + R4 1 +Net 4 "" "" + R3 2 + R2 1 + R1 1 +} +#End diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.pro b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.pro new file mode 100644 index 0000000..5e4c1b7 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.pro @@ -0,0 +1,71 @@ +update=Monday 22 October 2012 03:55:41 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.proj b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.proj new file mode 100644 index 0000000..a5a0162 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.proj @@ -0,0 +1 @@ +schematicFile modifiedNodalExample.sch diff --git a/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.sch b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.sch new file mode 100644 index 0000000..634ee69 --- /dev/null +++ b/OSCAD/Examples/modifiedNodalExample/modifiedNodalExample.sch @@ -0,0 +1,169 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:46:55 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:modifiedNodalExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5300 3200 5300 3250 +Connection ~ 5300 4250 +Wire Wire Line + 5300 4250 5300 4100 +Wire Wire Line + 5150 3050 5800 3050 +Wire Wire Line + 5800 3050 5800 3350 +Connection ~ 4950 4250 +Wire Wire Line + 4950 4050 4950 4250 +Connection ~ 4950 3350 +Wire Wire Line + 4850 3350 5050 3350 +Wire Wire Line + 4350 3350 4100 3350 +Wire Wire Line + 5800 3350 5550 3350 +Wire Wire Line + 4100 4250 5800 4250 +Wire Wire Line + 4100 3350 4100 3050 +Wire Wire Line + 4100 3050 4650 3050 +Wire Wire Line + 4750 4250 4750 4400 +Connection ~ 4750 4250 +Wire Wire Line + 4950 3550 4950 3250 +Wire Wire Line + 4950 3250 5300 3250 +$Comp +L VPRINT1 U1 +U 1 1 50692E86 +P 5300 2900 +F 0 "U1" H 5150 3000 50 0001 C CNN +F 1 "VPRINT1" H 5450 3000 50 0000 C CNN + 1 5300 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5069279A +P 5300 4100 +F 0 "#FLG01" H 5300 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 4330 30 0000 C CNN + 1 5300 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50692771 +P 4750 4400 +F 0 "#PWR02" H 4750 4400 30 0001 C CNN +F 1 "GND" H 4750 4330 30 0001 C CNN + 1 4750 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50692628 +P 5300 3350 +F 0 "R3" V 5380 3350 50 0000 C CNN +F 1 "1" V 5300 3350 50 0000 C CNN + 1 5300 3350 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 5069261E +P 4900 3050 +F 0 "R4" V 4980 3050 50 0000 C CNN +F 1 "1" V 4900 3050 50 0000 C CNN + 1 4900 3050 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 50692613 +P 4600 3350 +F 0 "R1" V 4680 3350 50 0000 C CNN +F 1 "1" V 4600 3350 50 0000 C CNN + 1 4600 3350 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5067FEAC +P 4950 3800 +F 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\ No newline at end of file diff --git a/OSCAD/Examples/nodalExample/nodalExample-cache.bak b/OSCAD/Examples/nodalExample/nodalExample-cache.bak new file mode 100644 index 0000000..f0c5c5f --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample-cache.bak @@ -0,0 +1,72 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:49:30 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nodalExample/nodalExample-cache.lib b/OSCAD/Examples/nodalExample/nodalExample-cache.lib new file mode 100644 index 0000000..e1bdb6e --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample-cache.lib @@ -0,0 +1,72 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:49:49 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vprint1 +# +DEF vprint1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vprint1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End 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"GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 39500 38500 0 15 00200000 5064259E ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5064259E +AR /50640DAA +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R4" +T1 0 0 550 500 0 80 N I 21 N "2" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 43500 38500 0 15 00200000 50641561 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50641561 +AR /50641261 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R5" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$TRACK +Po 0 38000 33500 38500 33000 80 -1 +De 0 0 1 0 400000 +Po 0 39000 33000 39500 33500 80 -1 +De 0 0 1 0 800000 +Po 0 38500 33000 39000 33000 80 -1 +De 0 0 1 0 0 +Po 0 45000 36500 45500 37000 80 -1 +De 0 0 1 0 400000 +Po 0 45500 38000 45000 38500 80 -1 +De 0 0 1 0 800000 +Po 0 45500 37000 45500 38000 80 -1 +De 0 0 1 0 0 +Po 0 45000 33500 45500 34000 80 -1 +De 0 0 1 0 400000 +Po 0 45500 36000 45000 36500 80 -1 +De 0 0 1 0 800000 +Po 0 45500 34000 45500 36000 80 -1 +De 0 0 1 0 0 +Po 0 39500 33500 40000 33500 80 -1 +De 0 0 1 0 400000 +Po 0 44000 32500 45000 33500 80 -1 +De 0 0 1 0 800000 +Po 0 41000 32500 44000 32500 80 -1 +De 0 0 1 0 0 +Po 0 40000 33500 41000 32500 80 -1 +De 0 0 1 0 0 +Po 0 42000 33500 43000 33500 80 -1 +De 0 0 2 0 400000 +Po 0 44500 35000 45000 35000 80 -1 +De 0 0 2 0 800000 +Po 0 43000 33500 44500 35000 80 -1 +De 0 0 2 0 0 +Po 0 39500 36500 40500 36500 80 -1 +De 0 0 2 0 400000 +Po 0 41000 34500 42000 33500 80 -1 +De 0 0 2 0 800000 +Po 0 41000 36000 41000 34500 80 -1 +De 0 0 2 0 0 +Po 0 40500 36500 41000 36000 80 -1 +De 0 0 2 0 0 +Po 0 41000 38500 41000 37500 80 -1 +De 0 0 3 0 400000 +Po 0 41000 37500 42000 36500 80 -1 +De 0 0 3 0 800000 +Po 0 42000 35000 41500 35500 80 -1 +De 0 0 3 0 400000 +Po 0 41500 36000 42000 36500 80 -1 +De 0 0 3 0 800000 +Po 0 41500 35500 41500 36000 80 -1 +De 0 0 3 0 0 +Po 0 42000 38500 41500 39000 80 -1 +De 0 0 4 0 400000 +Po 0 38500 39000 38000 38500 80 -1 +De 0 0 4 0 800000 +Po 0 41500 39000 38500 39000 80 -1 +De 0 0 4 0 0 +Po 0 38000 36500 37500 37000 80 -1 +De 0 0 4 0 400000 +Po 0 37500 38000 38000 38500 80 -1 +De 0 0 4 0 800000 +Po 0 37500 37000 37500 38000 80 -1 +De 0 0 4 0 0 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/nodalExample/nodalExample.bak b/OSCAD/Examples/nodalExample/nodalExample.bak new file mode 100644 index 0000000..60ad6aa --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.bak @@ -0,0 +1,184 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:49:30 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:nodalExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6100 2850 6100 3250 +Connection ~ 5600 4000 +Wire Wire Line + 5600 3900 5600 4000 +Connection ~ 6100 4000 +Wire Wire Line + 6100 3750 6100 4000 +Wire Wire Line + 7850 3900 7850 4000 +Wire Wire Line + 7850 4000 4700 4000 +Wire Wire Line + 4700 4000 4700 3950 +Connection ~ 5250 3000 +Wire Wire Line + 5250 3300 5250 3000 +Wire Wire Line + 5850 3000 6350 3000 +Wire Wire Line + 4700 3050 4700 3000 +Wire Wire Line + 4700 3000 5350 3000 +Wire Wire Line + 6850 3000 7850 3000 +Wire Wire Line + 7100 3200 7100 3000 +Connection ~ 7100 3000 +Connection ~ 6100 3000 +Wire Wire Line + 7100 3700 7100 4000 +Connection ~ 7100 4000 +Wire Wire Line + 5250 3800 5250 4000 +Connection ~ 5250 4000 +Wire Wire Line + 5450 4100 5450 4000 +Connection ~ 5450 4000 +$Comp +L VPRINT1 U1 +U 1 1 506489B3 +P 6100 2550 +F 0 "U1" H 5950 2650 50 0000 C CNN +F 1 "VPRINT1" H 6250 2650 50 0000 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50641423 +P 5450 4100 +F 0 "#PWR01" H 5450 4100 30 0001 C CNN +F 1 "GND" H 5450 4030 30 0001 C CNN + 1 5450 4100 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 506413F9 +P 5600 3900 +F 0 "#FLG02" H 5600 4170 30 0001 C CNN +F 1 "PWR_FLAG" H 5600 4130 30 0000 C CNN + 1 5600 3900 + 1 0 0 -1 +$EndComp +$Comp +L DC i2 +U 1 1 50641279 +P 7850 3450 +F 0 "i2" H 7650 3550 60 0000 C CNN +F 1 "1" H 7650 3400 60 0000 C CNN +F 2 "R3" H 7550 3450 60 0000 C CNN + 1 7850 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50641261 +P 7100 3450 +F 0 "R5" V 7180 3450 50 0000 C CNN +F 1 "1" V 7100 3450 50 0000 C CNN + 1 7100 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50640DC3 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50640DAA +P 6600 3000 +F 0 "R4" V 6680 3000 50 0000 C CNN +F 1 "2" V 6600 3000 50 0000 C CNN + 1 6600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 50640DA8 +P 6100 3500 +F 0 "R3" V 6180 3500 50 0000 C CNN +F 1 "1" V 6100 3500 50 0000 C CNN + 1 6100 3500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50640DA0 +P 5250 3550 +F 0 "R1" V 5330 3550 50 0000 C CNN +F 1 "1" V 5250 3550 50 0000 C CNN + 1 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC i1 +U 1 1 5063F506 +P 4700 3500 +F 0 "i1" H 4500 3600 60 0000 C CNN +F 1 "1" H 4500 3450 60 0000 C CNN +F 2 "R3" H 4400 3500 60 0000 C CNN + 1 4700 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nodalExample/nodalExample.brd b/OSCAD/Examples/nodalExample/nodalExample.brd new file mode 100644 index 0000000..375772b --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.brd @@ -0,0 +1,423 @@ +PCBNEW-BOARD Version 1 date Sunday 30 September 2012 12:21:31 PM IST + +# Created by Pcbnew(2011-05-25)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 10 +NoConn 0 +Di 36959 32379 45541 37621 +Ndraw 0 +Ntrack 29 +Nzone 0 +BoardThickness 630 +Nmodule 7 +Nnets 5 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "30 sep 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000001" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000003" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "N-000004" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000001" +AddNet "N-000003" +AddNet "N-000004" +$EndNCLASS +$MODULE R3 +Po 43500 33000 0 15 00200000 50641559 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50641559 +AR /50640DA0 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R1" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 43500 35000 0 15 00200000 5064155B ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5064155B +AR /50640DC3 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R2" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 43500 37000 0 15 00200000 5064155D ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5064155D +AR /50640DA8 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R3" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 39000 35500 0 15 00200000 5064259E ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 5064259E +AR /50640DAA +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R4" +T1 0 0 550 500 0 80 N I 21 N "2" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "N-000003" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R3 +Po 39000 37000 0 15 00200000 50641561 ~~ +Li R3 +Cd Resitance 3 pas +Kw R +Sc 50641561 +AR /50641261 +Op 0 A 0 +T0 0 0 550 500 0 80 N V 21 N "R5" +T1 0 0 550 500 0 80 N I 21 N "1" +DS -1500 0 -1300 0 120 21 +DS 1500 0 1300 0 120 21 +DS 1300 0 1300 -400 120 21 +DS 1300 -400 -1300 -400 120 21 +DS -1300 -400 -1300 400 120 21 +DS -1300 400 1300 400 120 21 +DS 1300 400 1300 0 120 21 +DS -1300 -200 -1100 -400 120 21 +$PAD +Sh "1" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -1500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 1500 0 +$EndPAD +$SHAPE3D +Na "discret/resistor.wrl" +Sc 0.300000 0.300000 0.300000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R3 +$MODULE R1 +Po 40000 33500 900 15 00200000 50641555 ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 50641555 +AR /5063F506 +Op A A 0 +T0 -400 1000 550 500 900 80 N V 21 N "i1" +T1 -450 1000 550 500 900 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 900 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "N-000001" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 900 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$MODULE R1 +Po 38000 33500 900 15 00200000 50641557 ~~ +Li R1 +Cd Resistance verticale +Kw R +Sc 50641557 +AR /50641279 +Op A A 0 +T0 -400 1000 550 500 900 80 N V 21 N "i2" +T1 -450 1000 550 500 900 80 N I 21 N "DC" +DS -500 0 500 0 150 21 +DC -500 0 -250 500 150 21 +$PAD +Sh "1" C 550 550 0 0 900 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "N-000004" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 900 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 500 0 +$EndPAD +$SHAPE3D +Na "discret/verti_resistor.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE R1 +$TRACK +Po 0 40000 33000 40500 32500 80 -1 +De 0 0 1 0 400000 +Po 0 44500 32500 45000 33000 80 -1 +De 0 0 1 0 800000 +Po 0 40500 32500 44500 32500 80 -1 +De 0 0 1 0 0 +Po 0 38000 33000 38500 32500 80 -1 +De 0 0 1 0 400000 +Po 0 39500 32500 40000 33000 80 -1 +De 0 0 1 0 800000 +Po 0 38500 32500 39500 32500 80 -1 +De 0 0 1 0 0 +Po 0 40500 37000 41000 37000 80 -1 +De 0 0 1 0 400000 +Po 0 44500 37500 45000 37000 80 -1 +De 0 0 1 0 800000 +Po 0 41500 37500 44500 37500 80 -1 +De 0 0 1 0 0 +Po 0 41000 37000 41500 37500 80 -1 +De 0 0 1 0 0 +Po 0 45000 33000 45500 33500 80 -1 +De 0 0 1 0 400000 +Po 0 45500 33500 45500 36500 80 -1 +De 0 0 1 0 0 +Po 0 45500 36500 45000 37000 80 -1 +De 0 0 1 0 800000 +Po 0 42000 33000 43000 33000 80 -1 +De 0 0 2 0 400000 +Po 0 43000 33000 45000 35000 80 -1 +De 0 0 2 0 800000 +Po 0 40000 34000 41000 34000 80 -1 +De 0 0 2 0 400000 +Po 0 41000 34000 42000 33000 80 -1 +De 0 0 2 0 800000 +Po 0 40500 35500 41000 35000 80 -1 +De 0 0 3 0 400000 +Po 0 41000 35000 42000 35000 80 -1 +De 0 0 3 0 800000 +Po 0 42000 37000 41500 36500 80 -1 +De 0 0 3 0 400000 +Po 0 41500 35500 42000 35000 80 -1 +De 0 0 3 0 800000 +Po 0 41500 36500 41500 35500 80 -1 +De 0 0 3 0 0 +Po 0 37500 35500 37000 35000 80 -1 +De 0 0 4 0 400000 +Po 0 37500 34000 38000 34000 80 -1 +De 0 0 4 0 800000 +Po 0 37000 34500 37500 34000 80 -1 +De 0 0 4 0 0 +Po 0 37000 35000 37000 34500 80 -1 +De 0 0 4 0 0 +Po 0 37500 37000 37000 36500 80 -1 +De 0 0 4 0 400000 +Po 0 37000 36000 37500 35500 80 -1 +De 0 0 4 0 800000 +Po 0 37000 36500 37000 36000 80 -1 +De 0 0 4 0 0 +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/nodalExample/nodalExample.cir b/OSCAD/Examples/nodalExample/nodalExample.cir new file mode 100644 index 0000000..73cd5c1 --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:49:47 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 4 VPRINT1 +i2 1 0 1 +R5 1 0 1 +R2 4 3 1 +R4 1 4 2 +R3 4 0 1 +R1 3 0 1 +i1 3 0 1 + +.end diff --git a/OSCAD/Examples/nodalExample/nodalExample.cir.ckt b/OSCAD/Examples/nodalExample/nodalExample.cir.ckt new file mode 100644 index 0000000..84ba089 --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:49:47 am ist + +* Printing option vprint1 +i2 1 0 1 +r5 1 0 1 +r2 4 3 1 +r4 1 4 2 +r3 4 0 1 +r1 3 0 1 +i1 3 0 1 + +.op +.print v(4) +.end diff --git a/OSCAD/Examples/nodalExample/nodalExample.cir.ckt.sol b/OSCAD/Examples/nodalExample/nodalExample.cir.ckt.sol new file mode 100644 index 0000000..5c5bae8 --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.cir.ckt.sol @@ -0,0 +1,9 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +I 1 0 0.0000000000 0.0000000000 +R 1 0 0.0000000000 0.0000000000 +R 4 3 0.0000000000 0.0000000000 +R 1 4 0.0000000000 0.0000000000 +R 4 0 0.0000000000 0.0000000000 +R 3 0 0.0000000000 0.0000000000 +I 3 0 0.0000000000 0.0000000000 diff --git a/OSCAD/Examples/nodalExample/nodalExample.cir.out b/OSCAD/Examples/nodalExample/nodalExample.cir.out new file mode 100644 index 0000000..c1fe81b --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:49:47 am ist + +* Printing option vprint1 +i2 1 0 1 +r5 1 0 1 +r2 4 3 1 +r4 1 4 2 +r3 4 0 1 +r1 3 0 1 +i1 3 0 1 + +.op + +* Control Statements +.control +run +print v(4) +.endc +.end diff --git a/OSCAD/Examples/nodalExample/nodalExample.ckt b/OSCAD/Examples/nodalExample/nodalExample.ckt new file mode 100644 index 0000000..41347f6 --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) +* creation date: thursday 27 september 2012 02:26:44 pm ist + +i2 4 0 dc 1 +r5 4 0 1 +r2 3 1 1 +r4 4 3 2 +r3 3 0 1 +r1 1 0 1 +i1 1 0 dc 1 +.op +.end + diff --git a/OSCAD/Examples/nodalExample/nodalExample.ckt.sol b/OSCAD/Examples/nodalExample/nodalExample.ckt.sol new file mode 100644 index 0000000..f7eb9ba --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.ckt.sol @@ -0,0 +1,9 @@ +Name Source Sink Voltage Current +---------------------------------------------------- +I 4 0 -0.8181818182 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+IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50640DAA; +Reference = R4; +ValeurCmp = 2; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50641261; +Reference = R5; +ValeurCmp = 1; +IdModule = R3; +EndCmp + +EndListe diff --git a/OSCAD/Examples/nodalExample/nodalExample.net b/OSCAD/Examples/nodalExample/nodalExample.net new file mode 100644 index 0000000..14f7e3f --- /dev/null +++ b/OSCAD/Examples/nodalExample/nodalExample.net @@ -0,0 +1,71 @@ +# EESchema Netlist Version 1.1 created Sunday 30 September 2012 12:14:32 PM IST +( + ( /5063F506 R1 i1 DC + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /50641279 R1 i2 DC + ( 1 N-000004 ) + ( 2 GND ) + ) + ( /50640DA0 R3 R1 1 + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /50640DC3 R3 R2 1 + ( 1 N-000003 ) + ( 2 N-000001 ) + ) + ( /50640DA8 R3 R3 1 + ( 1 N-000003 ) + ( 2 GND ) + ) + ( /50640DAA R3 R4 2 + ( 1 N-000004 ) + ( 2 N-000003 ) + ) + ( /50641261 R3 R5 1 + ( 1 N-000004 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component i1 + 1_pin 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+LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:nodalExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6100 2850 6100 3250 +Connection ~ 5600 4000 +Wire Wire Line + 5600 3900 5600 4000 +Connection ~ 6100 4000 +Wire Wire Line + 6100 3750 6100 4000 +Wire Wire Line + 7850 3900 7850 4000 +Wire Wire Line + 7850 4000 4700 4000 +Wire Wire Line + 4700 4000 4700 3950 +Connection ~ 5250 3000 +Wire Wire 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+F 2 "R3" H 4400 3500 60 0000 C CNN + 1 4700 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nodalExample_plot/analysis b/OSCAD/Examples/nodalExample_plot/analysis new file mode 100644 index 0000000..7dd51c6 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/analysis @@ -0,0 +1 @@ +.dc i1 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot-cache.lib b/OSCAD/Examples/nodalExample_plot/nodalExample_plot-cache.lib new file mode 100644 index 0000000..532ca7e --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 24 May 2013 02:15:51 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.bak b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.bak new file mode 100644 index 0000000..c19435c --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.bak @@ -0,0 +1,187 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 02:14:17 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice 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5450 4000 +$Comp +L VPRINT1 U1 +U 1 1 506489B3 +P 6100 2550 +F 0 "U1" H 5950 2650 50 0000 C CNN +F 1 "VPRINT1" H 6250 2650 50 0000 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 50641423 +P 5450 4100 +F 0 "#PWR01" H 5450 4100 30 0001 C CNN +F 1 "GND" H 5450 4030 30 0001 C CNN + 1 5450 4100 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 506413F9 +P 5600 3900 +F 0 "#FLG02" H 5600 4170 30 0001 C CNN +F 1 "PWR_FLAG" H 5600 4130 30 0000 C CNN + 1 5600 3900 + 1 0 0 -1 +$EndComp +$Comp +L DC i2 +U 1 1 50641279 +P 7850 3450 +F 0 "i2" H 7650 3550 60 0000 C CNN +F 1 "1" H 7650 3400 60 0000 C CNN +F 2 "R3" H 7550 3450 60 0000 C CNN + 1 7850 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50641261 +P 7100 3450 +F 0 "R5" V 7180 3450 50 0000 C CNN +F 1 "1" V 7100 3450 50 0000 C CNN + 1 7100 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50640DC3 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50640DAA +P 6600 3000 +F 0 "R4" V 6680 3000 50 0000 C CNN +F 1 "2" V 6600 3000 50 0000 C CNN + 1 6600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 50640DA8 +P 6100 3500 +F 0 "R3" V 6180 3500 50 0000 C CNN +F 1 "1" V 6100 3500 50 0000 C CNN + 1 6100 3500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50640DA0 +P 5250 3550 +F 0 "R1" V 5330 3550 50 0000 C CNN +F 1 "1" V 5250 3550 50 0000 C CNN + 1 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC i1 +U 1 1 5063F506 +P 4700 3500 +F 0 "i1" H 4500 3600 60 0000 C CNN +F 1 "1" H 4500 3450 60 0000 C CNN +F 2 "R3" H 4400 3500 60 0000 C CNN + 1 4700 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir new file mode 100644 index 0000000..f2dda85 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 24 May 2013 02:18:18 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 4 VPLOT8_1 +i2 1 0 1 +R5 1 0 1 +R2 4 3 1 +R4 1 4 2 +R3 4 0 1 +R1 3 0 1 +i1 3 0 1 + +.end diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.ckt b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.ckt new file mode 100644 index 0000000..219dd07 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:18:18 pm ist + +* Plotting option vplot8_1 +i2 1 0 1 +r5 1 0 1 +r2 4 3 1 +r4 1 4 2 +r3 4 0 1 +r1 3 0 1 +i1 3 0 1 + +.dc i1 0e-00 10e-00 1e-00 +.plot v(4) +.end diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.out b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.out new file mode 100644 index 0000000..a7809b6 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:18:18 pm ist + +* Plotting option vplot8_1 +i2 1 0 1 +r5 1 0 1 +r2 4 3 1 +r4 1 4 2 +r3 4 0 1 +r1 3 0 1 +i1 3 0 1 + +.dc i1 0e-00 10e-00 1e-00 + +* Control Statements +.control +run +plot v(4) +.endc +.end diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.pro b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.pro new file mode 100644 index 0000000..fb3c608 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.pro @@ -0,0 +1,74 @@ +update=Friday 24 May 2013 02:15:07 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.proj b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.proj new file mode 100644 index 0000000..0f13a25 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.proj @@ -0,0 +1 @@ +schematicFile nodalExample_plot.sch diff --git a/OSCAD/Examples/nodalExample_plot/nodalExample_plot.sch b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.sch new file mode 100644 index 0000000..4ac9466 --- /dev/null +++ b/OSCAD/Examples/nodalExample_plot/nodalExample_plot.sch @@ -0,0 +1,186 @@ +EESchema Schematic File Version 2 date Friday 24 May 2013 02:15:51 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "24 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 1 1 519F28A8 +P 6100 2550 +F 0 "U1" H 5950 2650 50 0000 C CNN +F 1 "VPLOT8_1" H 6250 2650 50 0000 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2850 6100 3250 +Connection ~ 5600 4000 +Wire Wire Line + 5600 3900 5600 4000 +Connection ~ 6100 4000 +Wire Wire Line + 6100 3750 6100 4000 +Wire Wire Line + 7850 3900 7850 4000 +Wire Wire Line + 7850 4000 4700 4000 +Wire Wire Line + 4700 4000 4700 3950 +Connection ~ 5250 3000 +Wire Wire Line + 5250 3300 5250 3000 +Wire Wire Line + 5850 3000 6350 3000 +Wire Wire Line + 4700 3050 4700 3000 +Wire Wire Line + 4700 3000 5350 3000 +Wire Wire Line + 6850 3000 7850 3000 +Wire Wire Line + 7100 3200 7100 3000 +Connection ~ 7100 3000 +Connection ~ 6100 3000 +Wire Wire Line + 7100 3700 7100 4000 +Connection ~ 7100 4000 +Wire Wire Line + 5250 3800 5250 4000 +Connection ~ 5250 4000 +Wire Wire Line + 5450 4100 5450 4000 +Connection ~ 5450 4000 +$Comp +L GND #PWR1 +U 1 1 50641423 +P 5450 4100 +F 0 "#PWR1" H 5450 4100 30 0001 C CNN +F 1 "GND" H 5450 4030 30 0001 C CNN + 1 5450 4100 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 506413F9 +P 5600 3900 +F 0 "#FLG1" H 5600 4170 30 0001 C CNN +F 1 "PWR_FLAG" H 5600 4130 30 0000 C CNN + 1 5600 3900 + 1 0 0 -1 +$EndComp +$Comp +L DC i2 +U 1 1 50641279 +P 7850 3450 +F 0 "i2" H 7650 3550 60 0000 C CNN +F 1 "1" H 7650 3400 60 0000 C CNN +F 2 "R3" H 7550 3450 60 0000 C CNN + 1 7850 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50641261 +P 7100 3450 +F 0 "R5" V 7180 3450 50 0000 C CNN +F 1 "1" V 7100 3450 50 0000 C CNN + 1 7100 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50640DC3 +P 5600 3000 +F 0 "R2" V 5680 3000 50 0000 C CNN +F 1 "1" V 5600 3000 50 0000 C CNN + 1 5600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50640DAA +P 6600 3000 +F 0 "R4" V 6680 3000 50 0000 C CNN +F 1 "2" V 6600 3000 50 0000 C CNN + 1 6600 3000 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 50640DA8 +P 6100 3500 +F 0 "R3" V 6180 3500 50 0000 C CNN +F 1 "1" V 6100 3500 50 0000 C CNN + 1 6100 3500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50640DA0 +P 5250 3550 +F 0 "R1" V 5330 3550 50 0000 C CNN +F 1 "1" V 5250 3550 50 0000 C CNN + 1 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC i1 +U 1 1 5063F506 +P 4700 3500 +F 0 "i1" H 4500 3600 60 0000 C CNN +F 1 "1" H 4500 3450 60 0000 C CNN +F 2 "R3" H 4400 3500 60 0000 C CNN + 1 4700 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/analysis b/OSCAD/Examples/nonInvertingAmplifier/analysis new file mode 100644 index 0000000..888b3aa --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/analysis @@ -0,0 +1 @@ +.tran 100e-06 40e-03 0e-00 diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.bak b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.bak new file mode 100644 index 0000000..036ee3a --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:47:24 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.lib b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.lib new file mode 100644 index 0000000..8835104 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:47:58 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.bak b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.bak new file mode 100644 index 0000000..695fcbc --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.bak @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:47:24 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:nonInvertingAmplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4300 3300 +Wire Wire Line + 4300 3200 4300 3650 +Wire Wire Line + 5100 3300 5300 3300 +Wire Wire Line + 4600 3500 4600 3700 +Wire Wire Line + 5100 3500 5300 3500 +Connection ~ 6550 3400 +Wire Wire Line + 6300 3400 6850 3400 +Wire Wire Line + 6850 3100 6850 3650 +Connection ~ 6850 3400 +Connection ~ 4300 4650 +Wire Wire Line + 4300 4650 4600 4650 +Wire Wire Line + 4600 4650 4600 4400 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 6850 4150 6850 4400 +Wire Wire Line + 6050 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 3400 +Wire Wire Line + 5200 3500 5200 4050 +Wire Wire Line + 5200 4050 5550 4050 +Connection ~ 5200 3500 +Wire Wire Line + 4300 3300 4600 3300 +$Comp +L R R? +U 1 1 50D14DC5 +P 4850 3300 +F 0 "R?" V 4930 3300 50 0000 C CNN +F 1 "1000" V 4850 3300 50 0000 C CNN + 1 4850 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR01" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 4300 2900 +F 0 "U1" H 4150 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 4450 3000 50 0000 C CNN + 1 4300 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG02" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240CB +P 4600 3700 +F 0 "#PWR03" H 4600 3700 30 0001 C CNN +F 1 "GND" H 4600 3630 30 0001 C CNN + 1 4600 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR04" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 50824091 +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "SINE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4850 3500 +F 0 "R1" V 4930 3500 50 0000 C CNN +F 1 "1000" V 4850 3500 50 0000 C CNN + 1 4850 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir new file mode 100644 index 0000000..99dd1d0 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 19 December 2012 10:47:55 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R4 1 4 1000 +U1 4 3 VPLOT8_1 +X1 5 1 3 UA741 +v1 4 0 SINE +R3 3 0 10000 +R1 5 0 1000 +R2 3 5 2000 + +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.ckt b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.ckt new file mode 100644 index 0000000..1aac163 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 19 december 2012 10:47:55 am ist +.include ua741.sub + +r4 1 4 1000 +* Plotting option vplot8_1 +x1 5 1 3 ua741 +v1 4 0 sine(0 5 50 0 0) +r3 3 0 10000 +r1 5 0 1000 +r2 3 5 2000 + +.tran 100e-06 40e-03 0e-00 +.plot v(4) v(3) +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.out b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.out new file mode 100644 index 0000000..6417831 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 19 december 2012 10:47:55 am ist +.include ua741.sub + +r4 1 4 1000 +* Plotting option vplot8_1 +x1 5 1 3 ua741 +v1 4 0 sine(0 5 50 0 0) +r3 3 0 10000 +r1 5 0 1000 +r2 3 5 2000 + +.tran 100e-06 40e-03 0e-00 + +* Control Statements +.control +run +plot v(4) v(3) +.endc +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cmp b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cmp new file mode 100644 index 0000000..c3e04af --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.cmp @@ -0,0 +1,38 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Saturday 20 October 2012 11:59:17 AM IST + +BeginCmp +TimeStamp = /50824062; +Reference = R1; +ValeurCmp = 1000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824045; +Reference = R2; +ValeurCmp = 2000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824073; +Reference = R3; +ValeurCmp = 10000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824091; +Reference = v1; +ValeurCmp = SINE; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /50823E96; +Reference = X1; +ValeurCmp = LM741; +IdModule = DIP-8__300; +EndCmp + +EndListe diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.net b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.net new file mode 100644 index 0000000..938591e --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.net @@ -0,0 +1,70 @@ +# EESchema Netlist Version 1.1 created Saturday 20 October 2012 12:03:26 PM IST +( + ( /50824595 $noname X1 UA741 {Lib=UA741} + ( 2 N-000004 ) + ( 3 GND ) + ( 6 N-000001 ) + ) + ( /50824091 R1 v1 SINE {Lib=SINE} + ( 1 N-000002 ) + ( 2 GND ) + ) + ( /50824073 $noname R3 10000 {Lib=R} + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /50824062 $noname R1 1000 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000002 ) + ) + ( /50824045 $noname R2 2000 {Lib=R} + ( 1 N-000001 ) + ( 2 N-000004 ) + ) +) +* +{ Allowed footprints by component: +$component X1 + DIP-8__300 +$endlist +$component v1 + 1_pin +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R2 1 + X1 6 + R3 1 +Net 2 "" "" + R1 2 + v1 1 +Net 3 "GND" "GND" + X1 3 + v1 2 + R3 2 +Net 4 "" "" + X1 2 + R1 1 + R2 2 +} +#End diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.pro b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.pro new file mode 100644 index 0000000..9f5d056 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:16:29 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.proj b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.proj new file mode 100644 index 0000000..c78c533 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.proj @@ -0,0 +1 @@ +schematicFile InvertingAmplifier.sch diff --git a/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.sch b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.sch new file mode 100644 index 0000000..df340bb --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/nonInvertingAmplifier.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:47:58 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:nonInvertingAmplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4300 3300 +Wire Wire Line + 4300 3200 4300 3650 +Wire Wire Line + 5100 3300 5300 3300 +Wire Wire Line + 4600 3500 4600 3700 +Wire Wire Line + 5100 3500 5300 3500 +Connection ~ 6550 3400 +Wire Wire Line + 6300 3400 6850 3400 +Wire Wire Line + 6850 3100 6850 3650 +Connection ~ 6850 3400 +Connection ~ 4300 4650 +Wire Wire Line + 4300 4650 4600 4650 +Wire Wire Line + 4600 4650 4600 4400 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 6850 4150 6850 4400 +Wire Wire Line + 6050 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 3400 +Wire Wire Line + 5200 3500 5200 4050 +Wire Wire Line + 5200 4050 5550 4050 +Connection ~ 5200 3500 +Wire Wire Line + 4300 3300 4600 3300 +$Comp +L R R4 +U 1 1 50D14DC5 +P 4850 3300 +F 0 "R4" V 4930 3300 50 0000 C CNN +F 1 "1000" V 4850 3300 50 0000 C CNN + 1 4850 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR01" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 4300 2900 +F 0 "U1" H 4150 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 4450 3000 50 0000 C CNN + 1 4300 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG02" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240CB +P 4600 3700 +F 0 "#PWR03" H 4600 3700 30 0001 C CNN +F 1 "GND" H 4600 3630 30 0001 C CNN + 1 4600 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR04" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 50824091 +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "SINE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4850 3500 +F 0 "R1" V 4930 3500 50 0000 C CNN +F 1 "1000" V 4850 3500 50 0000 C CNN + 1 4850 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.bak b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.bak new file mode 100644 index 0000000..e2ece32 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.bak @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:17:01 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.lib b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.lib new file mode 100644 index 0000000..cbec3a5 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 19 December 2012 10:15:16 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.bak b/OSCAD/Examples/nonInvertingAmplifier/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.cir b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.ckt b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.out b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.pro b/OSCAD/Examples/nonInvertingAmplifier/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.sch b/OSCAD/Examples/nonInvertingAmplifier/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/nonInvertingAmplifier/ua741.sub b/OSCAD/Examples/nonInvertingAmplifier/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/nonInvertingAmplifier/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis new file mode 100644 index 0000000..ea22c29 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/analysis @@ -0,0 +1 @@ +.tran 1e-00 3e-00 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.bak new file mode 100644 index 0000000..c0bd60e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.bak @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 07 May 2013 12:28:25 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.lib new file mode 100644 index 0000000..dfad98c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 02:05:36 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.bak b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.bak new file mode 100644 index 0000000..025172a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.bak @@ -0,0 +1,193 @@ +EESchema Schematic File Version 2 date Tuesday 07 May 2013 12:28:25 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_12.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "7 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 8250 2800 8400 2800 +Connection ~ 7000 2750 +Wire Wire Line + 8600 2250 8600 2000 +Wire Wire Line + 8600 2000 7500 2000 +Wire Wire Line + 6900 3650 7900 3650 +Wire Wire Line + 7750 3650 7750 3300 +Wire Wire Line + 7500 2000 7500 2200 +Connection ~ 7200 2750 +Wire Wire Line + 7200 2750 6900 2750 +Wire Wire Line + 7750 2800 7750 2750 +Connection ~ 7500 2750 +Wire Wire Line + 7750 2750 7500 2750 +Wire Wire Line + 7500 2600 7500 2850 +Wire Wire Line + 7200 2400 7200 3050 +Connection ~ 7750 2750 +Wire Wire Line + 7500 3250 7500 3450 +Connection ~ 7750 3650 +Wire Wire Line + 7500 3450 8600 3450 +Wire Wire Line + 8600 3450 8600 3150 +Wire Wire Line + 7750 3300 8400 3300 +$Comp +L IPLOT U1 +U 1 1 5188A5F5 +P 8000 2800 +F 0 "U1" H 7850 2900 50 0000 C CNN +F 1 "IPLOT" H 8150 2900 50 0000 C CNN + 1 8000 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 5188A185 +P 7750 2450 +F 0 "U2" H 7600 2550 50 0000 C CNN +F 1 "VPLOT8_1" H 7900 2550 50 0000 C CNN + 2 7750 2450 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 51889CD8 +P 7000 2450 +F 0 "U2" H 6850 2550 50 0000 C CNN +F 1 "VPLOT8_1" H 7150 2550 50 0000 C CNN + 1 7000 2450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 518897EF +P 7200 2750 +F 0 "#FLG01" H 7200 3020 30 0001 C CNN +F 1 "PWR_FLAG" H 7200 2980 30 0000 C CNN + 1 7200 2750 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 51889574 +P 6900 3200 +F 0 "v1" H 6700 3300 60 0000 C CNN +F 1 "SINE" H 6700 3150 60 0000 C CNN +F 2 "R1" H 6600 3200 60 0000 C CNN + 1 6900 3200 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 51889502 +P 7750 3650 +F 0 "#FLG02" H 7750 3920 30 0001 C CNN +F 1 "PWR_FLAG" H 7750 3880 30 0000 C CNN + 1 7750 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 518894F5 +P 7900 3650 +F 0 "#PWR03" H 7900 3650 30 0001 C CNN +F 1 "GND" H 7900 3580 30 0001 C CNN + 1 7900 3650 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 518894AB +P 8600 2700 +F 0 "v2" H 8400 2800 60 0000 C CNN +F 1 "23" H 8400 2650 60 0000 C CNN +F 2 "R1" H 8300 2700 60 0000 C CNN + 1 8600 2700 + -1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5188943C +P 8400 3050 +F 0 "R1" V 8480 3050 50 0000 C CNN +F 1 "8" V 8400 3050 50 0000 C CNN + 1 8400 3050 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q2 +U 1 1 518893FC +P 7400 3050 +F 0 "Q2" H 7400 2900 60 0000 R CNN +F 1 "PNP" H 7400 3200 60 0000 R CNN + 1 7400 3050 + 1 0 0 1 +$EndComp +$Comp +L NPN Q1 +U 1 1 518893F7 +P 7400 2400 +F 0 "Q1" H 7400 2250 50 0000 R CNN +F 1 "NPN" H 7400 2550 50 0000 R CNN + 1 7400 2400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir new file mode 100644 index 0000000..93fe4d6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 02:05:33 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v3 0 5 23 +U1 6 4 IPLOT +U2 2 6 VPLOT8_1 +v1 2 0 SINE +v2 1 0 23 +R1 4 0 8 +Q2 6 2 5 PNP +Q1 6 2 1 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.ckt new file mode 100644 index 0000000..903850c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 02:05:33 pm ist + +v3 0 5 23 +V_u1 6 4 0 +* Plotting option vplot8_1 +v1 2 0 sine( 17.9 1000 ) +v2 1 0 23 +r1 4 0 8 +q2 5 2 6 pnp +q1 1 2 6 npn + +.tran 1e-00 3e-00 0e-00 +.plot i(V_u1) +.plot v(2) v(6) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.out new file mode 100644 index 0000000..061ce43 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 02:05:33 pm ist + +v3 0 5 23 +V_u1 6 4 0 +* Plotting option vplot8_1 +v1 2 0 sine( 17.9 1000 ) +v2 1 0 23 +r1 4 0 8 +q2 5 2 6 pnp +q1 1 2 6 npn + +.tran 1e-00 3e-00 0e-00 + +* Control Statements +.control +run +plot i(V_u1) +plot v(2) v(6) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.pro b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.pro new file mode 100644 index 0000000..c84bea9 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.pro @@ -0,0 +1,74 @@ +update=Tuesday 07 May 2013 11:10:57 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.proj b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.proj new file mode 100644 index 0000000..fdaaf23 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.proj @@ -0,0 +1 @@ +schematicFile example_12.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.sch b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.sch new file mode 100644 index 0000000..15b79e2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_12/example_12.8/example_12.8.sch @@ -0,0 +1,221 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 02:05:36 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_12.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L GND #PWR01 +U 1 1 5190A5AD +P 9250 2600 +F 0 "#PWR01" H 9250 2600 30 0001 C CNN +F 1 "GND" H 9250 2530 30 0001 C CNN + 1 9250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 8950 2600 +Wire Wire Line + 8950 2600 9250 2600 +Wire Wire Line + 8950 3600 8600 3600 +Wire Wire Line + 8600 3600 8600 3450 +Wire Wire Line + 8250 2800 8400 2800 +Connection ~ 7000 2750 +Wire Wire Line + 7500 2000 8600 2000 +Wire Wire Line + 6900 3650 7900 3650 +Wire Wire Line + 7750 3650 7750 3300 +Wire Wire Line + 7500 2000 7500 2200 +Connection ~ 7200 2750 +Wire Wire Line + 7200 2750 6900 2750 +Wire Wire Line + 7750 2800 7750 2750 +Connection ~ 7500 2750 +Wire Wire Line + 7750 2750 7500 2750 +Wire Wire Line + 7500 2600 7500 2850 +Wire Wire Line + 7200 2400 7200 3050 +Connection ~ 7750 2750 +Wire Wire Line + 7500 3250 7500 3450 +Connection ~ 7750 3650 +Wire Wire Line + 7500 3450 8600 3450 +Wire Wire Line + 7750 3300 8400 3300 +Wire Wire Line + 8600 2000 8600 1600 +Wire Wire Line + 8600 1600 8950 1600 +Wire Wire Line + 8950 2500 8950 2700 +$Comp +L DC v3 +U 1 1 5190A59B +P 8950 3150 +F 0 "v3" H 8750 3250 60 0000 C CNN +F 1 "23" H 8750 3100 60 0000 C CNN +F 2 "R1" H 8650 3150 60 0000 C CNN + 1 8950 3150 + -1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5188A5F5 +P 8000 2800 +F 0 "U1" H 7850 2900 50 0000 C CNN +F 1 "IPLOT" H 8150 2900 50 0000 C CNN + 1 8000 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 5188A185 +P 7750 2450 +F 0 "U2" H 7600 2550 50 0000 C CNN +F 1 "VPLOT8_1" H 7900 2550 50 0000 C CNN + 2 7750 2450 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 51889CD8 +P 7000 2450 +F 0 "U2" H 6850 2550 50 0000 C CNN +F 1 "VPLOT8_1" H 7150 2550 50 0000 C CNN + 1 7000 2450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 518897EF +P 7200 2750 +F 0 "#FLG02" H 7200 3020 30 0001 C CNN +F 1 "PWR_FLAG" H 7200 2980 30 0000 C CNN + 1 7200 2750 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 51889574 +P 6900 3200 +F 0 "v1" H 6700 3300 60 0000 C CNN +F 1 "SINE" H 6700 3150 60 0000 C CNN +F 2 "R1" H 6600 3200 60 0000 C CNN + 1 6900 3200 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 51889502 +P 7750 3650 +F 0 "#FLG03" H 7750 3920 30 0001 C CNN +F 1 "PWR_FLAG" H 7750 3880 30 0000 C CNN + 1 7750 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 518894F5 +P 7900 3650 +F 0 "#PWR04" H 7900 3650 30 0001 C CNN +F 1 "GND" H 7900 3580 30 0001 C CNN + 1 7900 3650 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 518894AB +P 8950 2050 +F 0 "v2" H 8750 2150 60 0000 C CNN +F 1 "23" H 8750 2000 60 0000 C CNN +F 2 "R1" H 8650 2050 60 0000 C CNN + 1 8950 2050 + -1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5188943C +P 8400 3050 +F 0 "R1" V 8480 3050 50 0000 C CNN +F 1 "8" V 8400 3050 50 0000 C CNN + 1 8400 3050 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q2 +U 1 1 518893FC +P 7400 3050 +F 0 "Q2" H 7400 2900 60 0000 R CNN +F 1 "PNP" H 7400 3200 60 0000 R CNN + 1 7400 3050 + 1 0 0 1 +$EndComp +$Comp +L NPN Q1 +U 1 1 518893F7 +P 7400 2400 +F 0 "Q1" H 7400 2250 50 0000 R CNN +F 1 "NPN" H 7400 2550 50 0000 R CNN + 1 7400 2400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib new file mode 100644 index 0000000..89d421d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib @@ -0,0 +1,2 @@ +.model 1n4007 D( IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1E-11 ++VJ=0.7 M=0.5 FC=0.5 TT=1E-07 KF=0 AF=1 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis new file mode 100644 index 0000000..09ae223 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis @@ -0,0 +1 @@ +.tran 10e-03 1e-01 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak new file mode 100644 index 0000000..a47b560 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 11:21:47 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib new file mode 100644 index 0000000..6d1cabe --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 11:52:16 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak new file mode 100644 index 0000000..3314c60 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak @@ -0,0 +1,133 @@ +EESchema Schematic File Version 2 date Tuesday 14 May 2013 11:21:47 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:example_2.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "14 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5750 5050 +Wire Wire Line + 5550 3150 5650 3150 +Wire Wire Line + 5050 4550 5050 5050 +Wire Wire Line + 6500 4900 6500 5050 +Wire Wire Line + 6050 3150 6500 3150 +Wire Wire Line + 5750 5050 5750 5800 +Connection ~ 5750 5550 +Connection ~ 6500 3150 +Wire Wire Line + 6500 3150 6500 3350 +Wire Wire Line + 6500 3850 6500 4000 +Wire Wire Line + 5050 3150 5050 3650 +Wire Wire Line + 6500 5050 5050 5050 +$Comp +L DC v2 +U 1 1 516BA020 +P 6500 4450 +F 0 "v2" H 6300 4550 60 0000 C CNN +F 1 "DC" H 6300 4400 60 0000 C CNN +F 2 "R1" H 6200 4450 60 0000 C CNN + 1 6500 4450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5167CC3A +P 5750 5550 +F 0 "#FLG01" H 5750 5645 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 5730 30 0000 C CNN + 1 5750 5550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5167CC15 +P 5750 5800 +F 0 "#PWR02" H 5750 5800 30 0001 C CNN +F 1 "GND" H 5750 5730 30 0001 C CNN + 1 5750 5800 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5166A34A +P 6500 3600 +F 0 "U1" H 6350 3700 50 0000 C CNN +F 1 "IPLOT" H 6650 3700 50 0000 C CNN + 1 6500 3600 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166A210 +P 5850 3150 +F 0 "D1" H 5850 3250 40 0000 C CNN +F 1 "DIODE" H 5850 3050 40 0000 C CNN + 1 5850 3150 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166A1EB +P 5300 3150 +F 0 "R1" V 5380 3150 50 0000 C CNN +F 1 "100" V 5300 3150 50 0000 C CNN + 1 5300 3150 + 0 -1 -1 0 +$EndComp +$Comp +L SINE v1 +U 1 1 5166A1AC +P 5050 4100 +F 0 "v1" H 4850 4200 60 0000 C CNN +F 1 "SINE" H 4850 4050 60 0000 C CNN +F 2 "R1" H 4750 4100 60 0000 C CNN + 1 5050 4100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd new file mode 100644 index 0000000..bf4bd89 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd @@ -0,0 +1,172 @@ +PCBNEW-BOARD Version 1 date Friday 12 April 2013 02:43:29 PM IST + +# Created by Pcbnew(2012-apr-16-27)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 0 +NoConn 0 +Di 40424 25540 76751 39450 +Ndraw 0 +Ntrack 0 +Nzone 0 +BoardThickness 630 +Nmodule 2 +Nnets 4 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "12 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Back signal +Layer[15] Front signal +TrackWidth 80 +TrackClearence 100 +ZoneClearence 200 +TrackMinWidth 80 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 350 +ViaDrill 250 +ViaMinSize 350 +ViaMinDrill 200 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 150 +TextModSize 600 600 +TextModWidth 120 +PadSize 600 600 +PadDrill 320 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "N-000018" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "N-000019" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "GND" +AddNet "N-000018" +AddNet "N-000019" +$EndNCLASS +$MODULE 1pin +Po 41500 38000 0 15 00200000 5167CFD9 ~~ +Li 1pin +Cd module 1 pin (ou trou mecanique de percage) +Kw DEV +Sc 5167CFD9 +AR 1pin +Op 0 0 0 +T0 0 -1200 400 400 0 100 N V 21 N "1PIN" +T1 0 1100 400 400 0 100 N I 21 N "P***" +DC 0 0 0 -900 150 21 +$PAD +Sh "1" C 1600 1600 0 0 0 +Dr 1200 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 0 0 +$EndPAD +$EndMODULE 1pin +$MODULE 3PIN_6mm +Po 68000 29000 0 15 00200000 5167CFEC ~~ +Li 3PIN_6mm +Cd module 2 pin (trou 6 mm) +Kw DEV +Sc 5167CFEC +AR +Op 0 0 0 +T0 4000 -3000 600 600 0 120 N V 21 N "K1" +T1 -3000 -3000 600 600 0 120 N V 21 N "CONN_3" +DS -8500 -2500 8500 -2500 150 21 +DS 8500 -2500 8500 2500 150 21 +DS 8500 2500 -8500 2500 150 21 +DS -8500 2500 -8500 -2500 150 21 +$PAD +Sh "1" C 4000 4000 0 0 0 +Dr 2400 0 0 +At STD N 00E0FFFF +Ne 2 "N-000018" +Po -5900 0 +$EndPAD +$PAD +Sh "3" C 4000 4000 0 0 0 +Dr 2400 0 0 +At STD N 00E0FFFF +Ne 3 "N-000019" +Po 5900 0 +$EndPAD +$PAD +Sh "2" C 4000 4000 0 0 0 +Dr 2400 0 0 +At STD N 00E0FFFF +Ne 1 "GND" +Po 0 0 +$EndPAD +$SHAPE3D +Na "device/douille_4mm(black).wrl" +Sc 1.800000 1.800000 1.800000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$SHAPE3D +Na "device/douille_4mm(red).wrl" +Sc 1.800000 1.800000 1.800000 +Of -0.590000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$SHAPE3D +Na "device/douille_4mm(green).wrl" +Sc 1.800000 1.800000 1.800000 +Of 0.590000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE 3PIN_6mm +$TRACK +$EndTRACK +$ZONE +$EndZONE +$EndBOARD diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir new file mode 100644 index 0000000..16861f7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 12:08:03 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v2 1 0 DC +U1 3 1 IPLOT +D1 5 3 DIODE +R1 2 5 100 +v1 2 0 SINE + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt new file mode 100644 index 0000000..6d02b34 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt @@ -0,0 +1,11 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 12:08:03 pm ist + +v2 1 0 dc 12 +V_u1 3 1 0 +d1 5 3 diode +r1 2 5 100 +v1 2 0 sine(0 24 50 0 0) + +.tran 10e-03 1e-01 0e-00 +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out new file mode 100644 index 0000000..52cc067 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 12:08:03 pm ist + +v2 1 0 dc 12 +V_u1 3 1 0 +d1 5 3 diode +r1 2 5 100 +v1 2 0 sine(0 24 50 0 0) + +.tran 10e-03 1e-01 0e-00 + +* Control Statements +.control +run +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp new file mode 100644 index 0000000..779ff51 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp @@ -0,0 +1,38 @@ +Cmp-Mod V01 Created by CvPcb (2012-apr-16-27)-stable date = Friday 12 April 2013 02:41:23 PM IST + +BeginCmp +TimeStamp = /5166A210; +Reference = D1; +ValeurCmp = DIODE; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /5166A1EB; +Reference = R1; +ValeurCmp = 100; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /5166A34A; +Reference = U1; +ValeurCmp = IPLOT; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /5166A1AC; +Reference = v1; +ValeurCmp = SINE; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /5166A26E; +Reference = v2; +ValeurCmp = 12V; +IdModule = R1; +EndCmp + +EndListe diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net new file mode 100644 index 0000000..eeea8db --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net @@ -0,0 +1,44 @@ +# EESchema Netlist Version 1.1 created Friday 12 April 2013 02:41:23 PM IST +( + ( /5166A210 $noname$ D1 DIODE + ( 1 N-000002 ) + ( 2 N-000004 ) + ) + ( /5166A1EB $noname$ R1 100 + ( 1 N-000001 ) + ( 2 N-000002 ) + ) + ( /5166A34A $noname$ U1 IPLOT + ( 1 N-000004 ) + ( 2 N-000003 ) + ) + ( /5166A1AC R1 v1 SINE + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /5166A26E R1 v2 12V + ( 1 N-000003 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component D1 + D? + S* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component v1 + 1_pin +$endlist +$component v2 + 1_pin +$endlist +$endfootprintlist +} diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro new file mode 100644 index 0000000..f5826c2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro @@ -0,0 +1,74 @@ +update=Thursday 11 April 2013 05:12:20 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj new file mode 100644 index 0000000..3cb5076 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj @@ -0,0 +1 @@ +schematicFile example_2.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch new file mode 100644 index 0000000..dfa5e1d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch @@ -0,0 +1,133 @@ +EESchema Schematic File Version 2 date Tuesday 14 May 2013 11:52:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:example_2.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "14 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5750 5050 +Wire Wire Line + 5550 3150 5650 3150 +Wire Wire Line + 5050 4550 5050 5050 +Wire Wire Line + 6500 4900 6500 5050 +Wire Wire Line + 6050 3150 6500 3150 +Wire Wire Line + 5750 5050 5750 5800 +Connection ~ 5750 5550 +Connection ~ 6500 3150 +Wire Wire Line + 6500 3150 6500 3350 +Wire Wire Line + 6500 3850 6500 4000 +Wire Wire Line + 5050 3150 5050 3650 +Wire Wire Line + 6500 5050 5050 5050 +$Comp +L DC v2 +U 1 1 516BA020 +P 6500 4450 +F 0 "v2" H 6300 4550 60 0000 C CNN +F 1 "DC" H 6300 4400 60 0000 C CNN +F 2 "R1" H 6200 4450 60 0000 C CNN + 1 6500 4450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5167CC3A +P 5750 5550 +F 0 "#FLG01" H 5750 5645 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 5730 30 0000 C CNN + 1 5750 5550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5167CC15 +P 5750 5800 +F 0 "#PWR02" H 5750 5800 30 0001 C CNN +F 1 "GND" H 5750 5730 30 0001 C CNN + 1 5750 5800 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5166A34A +P 6500 3600 +F 0 "U1" H 6350 3700 50 0000 C CNN +F 1 "IPLOT" H 6650 3700 50 0000 C CNN + 1 6500 3600 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166A210 +P 5850 3150 +F 0 "D1" H 5850 3250 40 0000 C CNN +F 1 "DIODE" H 5850 3050 40 0000 C CNN + 1 5850 3150 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166A1EB +P 5300 3150 +F 0 "R1" V 5380 3150 50 0000 C CNN +F 1 "100" V 5300 3150 50 0000 C CNN + 1 5300 3150 + 0 -1 -1 0 +$EndComp +$Comp +L SINE v1 +U 1 1 5166A1AC +P 5050 4100 +F 0 "v1" H 4850 4200 60 0000 C CNN +F 1 "SINE" H 4850 4050 60 0000 C CNN +F 2 "R1" H 4750 4100 60 0000 C CNN + 1 5050 4100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis new file mode 100644 index 0000000..403e10c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis @@ -0,0 +1 @@ +.dc v2 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak new file mode 100644 index 0000000..fc013c5 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 14 April 2013 04:43:15 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 30 H I C CNN +F1 "PWR_FLAG" 0 180 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* + SM1206 +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib new file mode 100644 index 0000000..aea3592 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 12:54:28 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak new file mode 100644 index 0000000..6ce76aa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak @@ -0,0 +1,162 @@ +EESchema Schematic File Version 2 date Sunday 14 April 2013 04:43:15 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.2-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "14 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PWR_FLAG #FLG01 +U 1 1 516A8F23 +P 4150 6650 +F 0 "#FLG01" H 4150 6745 30 0001 C CNN +F 1 "PWR_FLAG" H 4150 6830 30 0000 C CNN + 1 4150 6650 + 0 1 1 0 +$EndComp +Connection ~ 4150 6650 +Connection ~ 6350 4000 +Wire Wire Line + 6350 3350 6350 3150 +Connection ~ 4150 5200 +Wire Wire Line + 6350 5200 4150 5200 +Wire Wire Line + 4800 3150 4150 3150 +Wire Wire Line + 4150 5350 4150 4650 +Wire Wire Line + 6350 3150 5700 3150 +Wire Wire Line + 6350 4650 6350 4800 +Wire Wire Line + 4150 5750 4150 6000 +Wire Wire Line + 6350 3850 6350 4150 +Wire Wire Line + 4150 3150 4150 4150 +Wire Wire Line + 4150 6850 4150 6500 +$Comp +L GND #PWR02 +U 1 1 5167DAB9 +P 4150 6850 +F 0 "#PWR02" H 4150 6850 30 0001 C CNN +F 1 "GND" H 4150 6780 30 0001 C CNN + 1 4150 6850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5167DA8B +P 4150 6250 +F 0 "U1" H 4000 6350 50 0000 C CNN +F 1 "IPLOT" H 4300 6350 50 0000 C CNN + 1 4150 6250 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 5167D9D2 +P 6350 3600 +F 0 "U2" H 6200 3700 50 0000 C CNN +F 1 "IPLOT" H 6500 3700 50 0000 C CNN + 1 6350 3600 + 0 1 1 0 +$EndComp +$Comp +L DIODE D2 +U 1 1 5167D956 +P 6350 5000 +F 0 "D2" H 6350 5100 40 0000 C CNN +F 1 "DIODE" H 6350 4900 40 0000 C CNN + 1 6350 5000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5167D912 +P 5250 3150 +F 0 "v1" H 5050 3250 60 0000 C CNN +F 1 "10V" H 5050 3100 60 0000 C CNN +F 2 "R1" H 4950 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5167D8E5 +P 6350 4400 +F 0 "R2" V 6430 4400 50 0000 C CNN +F 1 "10k" V 6350 4400 50 0000 C CNN + 1 6350 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5167D8B8 +P 4150 4400 +F 0 "R1" V 4230 4400 50 0000 C CNN +F 1 "5k" V 4150 4400 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5167D869 +P 4150 5550 +F 0 "D1" H 4150 5650 40 0000 C CNN +F 1 "DIODE" H 4150 5450 40 0000 C CNN + 1 4150 5550 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir new file mode 100644 index 0000000..a8ccf76 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 12:54:07 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 6 VPLOT8_1 +v2 1 0 10V +v1 0 4 10V +U1 5 0 IPLOT +U2 1 7 IPLOT +D2 6 3 DIODE +R2 7 6 5k +R1 4 3 10k +D1 5 3 DIODE + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt new file mode 100644 index 0000000..ec3f080 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:54:07 pm ist + +* Plotting option vplot8_1 +v2 1 0 10v +v1 0 4 10v +V_u1 5 0 0 +V_u2 1 7 0 +d2 6 3 diode +r2 7 6 5k +r1 4 3 10k +d1 5 3 diode + +.dc v2 0e-00 10e-00 1e-00 +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out new file mode 100644 index 0000000..b89d0e8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:54:07 pm ist + +* Plotting option vplot8_1 +v2 1 0 10v +v1 0 4 10v +V_u1 5 0 0 +V_u2 1 7 0 +d2 6 3 diode +r2 7 6 5k +r1 4 3 10k +d1 5 3 diode + +.dc v2 0e-00 10e-00 1e-00 + +* Control Statements +.control +run +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro new file mode 100644 index 0000000..49fe832 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro @@ -0,0 +1,84 @@ +update=Monday 13 May 2013 12:52:59 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj new file mode 100644 index 0000000..049873b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj @@ -0,0 +1 @@ +schematicFile example_2.2.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch new file mode 100644 index 0000000..de929d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch @@ -0,0 +1,195 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 12:54:28 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.2-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6650 4750 +$Comp +L VPLOT8_1 U3 +U 1 1 519094DB +P 6650 4450 +F 0 "U3" H 6500 4550 50 0000 C CNN +F 1 "VPLOT8_1" H 6800 4550 50 0000 C CNN + 1 6650 4450 + 1 0 0 -1 +$EndComp +Connection ~ 6350 4750 +Wire Wire Line + 6350 4750 6650 4750 +Wire Wire Line + 5050 3150 5450 3150 +Wire Wire Line + 4150 6850 4150 6500 +Wire Wire Line + 4150 3150 4150 4150 +Wire Wire Line + 6350 3850 6350 4150 +Wire Wire Line + 4150 5750 4150 6000 +Wire Wire Line + 6350 4650 6350 4800 +Wire Wire Line + 4150 5350 4150 4650 +Wire Wire Line + 6350 5200 4150 5200 +Connection ~ 4150 5200 +Wire Wire Line + 6350 3350 6350 3150 +Connection ~ 6350 4000 +Connection ~ 4150 6650 +Wire Wire Line + 5250 3150 5250 3300 +Connection ~ 5250 3150 +$Comp +L GND #PWR01 +U 1 1 51909464 +P 5250 3300 +F 0 "#PWR01" H 5250 3300 30 0001 C CNN +F 1 "GND" H 5250 3230 30 0001 C CNN + 1 5250 3300 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 51909454 +P 5900 3150 +F 0 "v2" H 5700 3250 60 0000 C CNN +F 1 "10V" H 5700 3100 60 0000 C CNN +F 2 "R1" H 5600 3150 60 0000 C CNN + 1 5900 3150 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5167D912 +P 4600 3150 +F 0 "v1" H 4400 3250 60 0000 C CNN +F 1 "10V" H 4400 3100 60 0000 C CNN +F 2 "R1" H 4300 3150 60 0000 C CNN + 1 4600 3150 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516A8F23 +P 4150 6650 +F 0 "#FLG02" H 4150 6745 30 0001 C CNN +F 1 "PWR_FLAG" H 4150 6830 30 0000 C CNN + 1 4150 6650 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5167DAB9 +P 4150 6850 +F 0 "#PWR03" H 4150 6850 30 0001 C CNN +F 1 "GND" H 4150 6780 30 0001 C CNN + 1 4150 6850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5167DA8B +P 4150 6250 +F 0 "U1" H 4000 6350 50 0000 C CNN +F 1 "IPLOT" H 4300 6350 50 0000 C CNN + 1 4150 6250 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 5167D9D2 +P 6350 3600 +F 0 "U2" H 6200 3700 50 0000 C CNN +F 1 "IPLOT" H 6500 3700 50 0000 C CNN + 1 6350 3600 + 0 1 1 0 +$EndComp +$Comp +L DIODE D2 +U 1 1 5167D956 +P 6350 5000 +F 0 "D2" H 6350 5100 40 0000 C CNN +F 1 "DIODE" H 6350 4900 40 0000 C CNN + 1 6350 5000 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5167D8E5 +P 6350 4400 +F 0 "R2" V 6430 4400 50 0000 C CNN +F 1 "5k" V 6350 4400 50 0000 C CNN + 1 6350 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5167D8B8 +P 4150 4400 +F 0 "R1" V 4230 4400 50 0000 C CNN +F 1 "10k" V 4150 4400 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5167D869 +P 4150 5550 +F 0 "D1" H 4150 5650 40 0000 C CNN +F 1 "DIODE" H 4150 5450 40 0000 C CNN + 1 4150 5550 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis new file mode 100644 index 0000000..f481193 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 50e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib new file mode 100644 index 0000000..f4b7c8a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib @@ -0,0 +1,4 @@ +.model diode D( Vj=.65 Nbvl=14.976 Cjo=175p Rs=.20 Isr=1.859n ++ Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u ++ Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m ++ Is=880.5E-18 Xti=3 Ibvl=1.9556m )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak new file mode 100644 index 0000000..f7ad596 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak @@ -0,0 +1,105 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 12 April 2013 03:08:39 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* + SM1206 +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib new file mode 100644 index 0000000..1321f82 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 12:59:04 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak new file mode 100644 index 0000000..132334d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak @@ -0,0 +1,133 @@ +EESchema Schematic File Version 2 date Friday 12 April 2013 03:08:39 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "12 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5700 3600 5500 3600 +Wire Wire Line + 6100 3650 6100 4100 +Connection ~ 5500 4100 +Wire Wire Line + 6100 4100 4200 4100 +Wire Wire Line + 4650 2850 4200 2850 +Wire Wire Line + 4200 2850 4200 3200 +Wire Wire Line + 5700 3200 5700 2850 +Wire Wire Line + 5150 2850 6100 2850 +Connection ~ 5700 2850 +Wire Wire Line + 6100 2850 6100 3050 +Wire Wire Line + 5200 4100 5200 4650 +Connection ~ 5200 4100 +$Comp +L IPLOT U2 +U 1 1 5167D5E8 +P 5500 3850 +F 0 "U2" H 5350 3950 50 0000 C CNN +F 1 "IPLOT" H 5650 3950 50 0000 C CNN + 1 5500 3850 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5166ABF9 +P 5200 4650 +F 0 "#PWR01" H 5200 4650 30 0001 C CNN +F 1 "GND" H 5200 4580 30 0001 C CNN + 1 5200 4650 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8 U1 +U 1 1 5166A97D +P 6100 3350 +F 0 "U1" H 5950 3450 50 0000 C CNN +F 1 "VPLOT8" H 6250 3450 50 0000 C CNN + 1 6100 3350 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166A924 +P 5700 3400 +F 0 "D1" H 5700 3500 40 0000 C CNN +F 1 "DIODE" H 5700 3300 40 0000 C CNN + 1 5700 3400 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 5166A8EF +P 4900 2850 +F 0 "R1" V 4980 2850 50 0000 C CNN +F 1 "1000" V 4900 2850 50 0000 C CNN + 1 4900 2850 + 0 -1 -1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5166A8CD +P 4200 3650 +F 0 "v1" H 4000 3750 60 0000 C CNN +F 1 "5V" H 4000 3600 60 0000 C CNN +F 2 "R1" H 3900 3650 60 0000 C CNN + 1 4200 3650 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir new file mode 100644 index 0000000..3731a3e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 12:59:00 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 2 VPLOT8_1 +U2 3 0 IPLOT +D1 2 3 DIODE +R1 1 2 1000 +v1 1 0 5V + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt new file mode 100644 index 0000000..43a6aa9 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:59:00 pm ist +.include diode.lib + +* Plotting option vplot8_1 +V_u2 3 0 0 +d1 2 3 diode +r1 1 2 1000 +v1 1 0 5v + +.dc v1 0e-00 5e-00 50e-03 +.plot v(2) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out new file mode 100644 index 0000000..3ce4892 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:59:00 pm ist +.include diode.lib + +* Plotting option vplot8_1 +V_u2 3 0 0 +d1 2 3 diode +r1 1 2 1000 +v1 1 0 5v + +.dc v1 0e-00 5e-00 50e-03 + +* Control Statements +.control +run +plot v(2) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro new file mode 100644 index 0000000..9718ce6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro @@ -0,0 +1,84 @@ +update=Monday 13 May 2013 12:58:14 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj new file mode 100644 index 0000000..eb6337b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj @@ -0,0 +1 @@ +schematicFile example_2.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch new file mode 100644 index 0000000..7aac593 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 12:59:04 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PWR_FLAG #FLG01 +U 1 1 51909635 +P 5200 4200 +F 0 "#FLG01" H 5200 4470 30 0001 C CNN +F 1 "PWR_FLAG" H 5200 4430 30 0000 C CNN + 1 5200 4200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5190961B +P 5700 2550 +F 0 "U1" H 5550 2650 50 0000 C CNN +F 1 "VPLOT8_1" H 5850 2650 50 0000 C CNN + 1 5700 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 2850 5700 2850 +Wire Wire Line + 5700 3600 5700 3700 +Connection ~ 5200 4200 +Wire Wire Line + 5200 4200 5200 4750 +Connection ~ 5700 2850 +Wire Wire Line + 5700 2850 5700 3200 +Wire Wire Line + 4200 3200 4200 2850 +Wire Wire Line + 4200 2850 4650 2850 +Wire Wire Line + 4200 4100 4200 4200 +Wire Wire Line + 4200 4200 5700 4200 +$Comp +L IPLOT U2 +U 1 1 5167D5E8 +P 5700 3950 +F 0 "U2" H 5550 4050 50 0000 C CNN +F 1 "IPLOT" H 5850 4050 50 0000 C CNN + 1 5700 3950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166ABF9 +P 5200 4750 +F 0 "#PWR02" H 5200 4750 30 0001 C CNN +F 1 "GND" H 5200 4680 30 0001 C CNN + 1 5200 4750 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166A924 +P 5700 3400 +F 0 "D1" H 5700 3500 40 0000 C CNN +F 1 "DIODE" H 5700 3300 40 0000 C CNN + 1 5700 3400 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 5166A8EF +P 4900 2850 +F 0 "R1" V 4980 2850 50 0000 C CNN +F 1 "1000" V 4900 2850 50 0000 C CNN + 1 4900 2850 + 0 -1 -1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5166A8CD +P 4200 3650 +F 0 "v1" H 4000 3750 60 0000 C CNN +F 1 "5V" H 4000 3600 60 0000 C CNN +F 2 "R1" H 3900 3650 60 0000 C CNN + 1 4200 3650 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis new file mode 100644 index 0000000..0a70a74 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib new file mode 100644 index 0000000..d5c42a7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib @@ -0,0 +1,4 @@ +.model diode D( Is=880.5E-18 Nbvl=14.976 Cjo=175p Rs=20 Isr=1.859n ++ Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u ++ Bv=8.1 Fc=.5 Ikf=0 Xti=3 Nr=2 ++ Vj=.65 Ibv=20.245m Ibvl=1.9556m )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak new file mode 100644 index 0000000..4dd86fe --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 02:41:15 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib new file mode 100644 index 0000000..9adc092 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 21 May 2013 11:07:18 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak new file mode 100644 index 0000000..21d43d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak @@ -0,0 +1,164 @@ +EESchema Schematic File Version 2 date Tuesday 14 May 2013 02:41:15 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.5-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "14 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L DC v1 +U 1 1 5191FF90 +P 5000 3850 +F 0 "v1" H 4800 3950 60 0000 C CNN +F 1 "DC" H 4800 3800 60 0000 C CNN +F 2 "R1" H 4700 3850 60 0000 C CNN + 1 5000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5190978A +P 6250 5300 +F 0 "#FLG01" H 6250 5570 30 0001 C CNN +F 1 "PWR_FLAG" H 6250 5530 30 0000 C CNN + 1 6250 5300 + 1 0 0 -1 +$EndComp +Connection ~ 6600 2100 +$Comp +L VPLOT8_1 U1 +U 1 1 51909775 +P 6600 1800 +F 0 "U1" H 6450 1900 50 0000 C CNN +F 1 "VPLOT8_1" H 6750 1900 50 0000 C CNN + 1 6600 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6250 5300 5000 5300 +Wire Wire Line + 6250 3300 6250 3350 +Wire Wire Line + 6250 4850 6250 5500 +Wire Wire Line + 6250 2350 6250 2100 +Connection ~ 6250 5300 +Connection ~ 6250 2100 +Wire Wire Line + 5250 2100 5000 2100 +Wire Wire Line + 5750 2100 6600 2100 +Connection ~ 6250 5300 +Wire Wire Line + 6250 2750 6250 2800 +Wire Wire Line + 5000 2100 5000 3400 +Wire Wire Line + 6250 4250 6250 4350 +Wire Wire Line + 5000 5300 5000 4300 +$Comp +L IPLOT U2 +U 1 1 519096FE +P 6250 4600 +F 0 "U2" H 6100 4700 50 0000 C CNN +F 1 "IPLOT" H 6400 4700 50 0000 C CNN + 1 6250 4600 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 519096A6 +P 6250 3050 +F 0 "R2" V 6330 3050 50 0000 C CNN +F 1 "20m" V 6250 3050 50 0000 C CNN + 1 6250 3050 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5190969F +P 6250 3800 +F 0 "v2" H 6050 3900 60 0000 C CNN +F 1 "65m" H 6050 3750 60 0000 C CNN +F 2 "R1" H 5950 3800 60 0000 C CNN + 1 6250 3800 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516A928C +P 5500 2100 +F 0 "R1" V 5580 2100 50 0000 C CNN +F 1 "1000" V 5500 2100 50 0000 C CNN + 1 5500 2100 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166AFB9 +P 6250 5500 +F 0 "#PWR02" H 6250 5500 30 0001 C CNN +F 1 "GND" H 6250 5430 30 0001 C CNN + 1 6250 5500 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166AF28 +P 6250 2550 +F 0 "D1" H 6250 2650 40 0000 C CNN +F 1 "DIODE" H 6250 2450 40 0000 C CNN + 1 6250 2550 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir new file mode 100644 index 0000000..ab9de69 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 14 May 2013 02:41:09 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 1 0 DC +U1 5 VPLOT8_1 +U2 4 0 IPLOT +R2 3 2 20m +v2 2 4 65m +R1 1 5 1000 +D1 5 3 DIODE + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt new file mode 100644 index 0000000..eb19daf --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 14 may 2013 02:41:09 pm ist +.include diode.lib + +v1 1 0 dc 5 +* Plotting option vplot8_1 +V_u2 4 0 0 +r2 3 2 20m +v2 2 4 65m +r1 1 5 1000 +d1 5 3 diode + +.dc v1 0e-00 5e-00 1e-00 +.plot v(5) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out new file mode 100644 index 0000000..a3bbe2c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 14 may 2013 02:41:09 pm ist +.include diode.lib + +v1 1 0 dc 5 +* Plotting option vplot8_1 +V_u2 4 0 0 +r2 3 2 20m +v2 2 4 65m +r1 1 5 1000 +d1 5 3 diode + +.dc v1 0e-00 5e-00 1e-00 + +* Control Statements +.control +run +plot v(5) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro new file mode 100644 index 0000000..8e9a0fd --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro @@ -0,0 +1,84 @@ +update=Monday 13 May 2013 01:04:04 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj new file mode 100644 index 0000000..1148c23 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj @@ -0,0 +1 @@ +schematicFile example_2.5.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch new file mode 100644 index 0000000..ff9da18 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch @@ -0,0 +1,168 @@ +EESchema Schematic File Version 2 date Tuesday 21 May 2013 11:07:18 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.5-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 6650 2050 0 90 Italic 18 +Vd +Text Notes 6450 3850 0 90 Italic 18 +Id +$Comp +L DC v1 +U 1 1 5191FF90 +P 5000 3850 +F 0 "v1" H 4800 3950 60 0000 C CNN +F 1 "DC" H 4800 3800 60 0000 C CNN +F 2 "R1" H 4700 3850 60 0000 C CNN + 1 5000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5190978A +P 6250 5300 +F 0 "#FLG01" H 6250 5570 30 0001 C CNN +F 1 "PWR_FLAG" H 6250 5530 30 0000 C CNN + 1 6250 5300 + 1 0 0 -1 +$EndComp +Connection ~ 6600 2100 +$Comp +L VPLOT8_1 U1 +U 1 1 51909775 +P 6600 1800 +F 0 "U1" H 6450 1900 50 0000 C CNN +F 1 "VPLOT8_1" H 6750 1900 50 0000 C CNN + 1 6600 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6250 5300 5000 5300 +Wire Wire Line + 6250 3300 6250 3350 +Wire Wire Line + 6250 4850 6250 5500 +Wire Wire Line + 6250 2350 6250 2100 +Connection ~ 6250 5300 +Connection ~ 6250 2100 +Wire Wire Line + 5250 2100 5000 2100 +Wire Wire Line + 5750 2100 6600 2100 +Connection ~ 6250 5300 +Wire Wire Line + 6250 2750 6250 2800 +Wire Wire Line + 5000 2100 5000 3400 +Wire Wire Line + 6250 4250 6250 4350 +Wire Wire Line + 5000 5300 5000 4300 +$Comp +L IPLOT U2 +U 1 1 519096FE +P 6250 4600 +F 0 "U2" H 6100 4700 50 0000 C CNN +F 1 "IPLOT" H 6400 4700 50 0000 C CNN + 1 6250 4600 + 0 1 1 0 +$EndComp +$Comp +L R Rd +U 1 1 519096A6 +P 6250 3050 +F 0 "Rd" V 6330 3050 50 0000 C CNN +F 1 "20m" V 6250 3050 50 0000 C CNN + 1 6250 3050 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5190969F +P 6250 3800 +F 0 "v2" H 6050 3900 60 0000 C CNN +F 1 "65m" H 6050 3750 60 0000 C CNN +F 2 "R1" H 5950 3800 60 0000 C CNN + 1 6250 3800 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516A928C +P 5500 2100 +F 0 "R1" V 5580 2100 50 0000 C CNN +F 1 "1000" V 5500 2100 50 0000 C CNN + 1 5500 2100 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166AFB9 +P 6250 5500 +F 0 "#PWR02" H 6250 5500 30 0001 C CNN +F 1 "GND" H 6250 5430 30 0001 C CNN + 1 6250 5500 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166AF28 +P 6250 2550 +F 0 "D1" H 6250 2650 40 0000 C CNN +F 1 "DIODE" H 6250 2450 40 0000 C CNN + 1 6250 2550 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/analysis new file mode 100644 index 0000000..35318bb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.bak new file mode 100644 index 0000000..c86efd4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.bak @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 03:23:37 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +# ZENER +# +DEF ZENER D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "ZENER" 0 -100 40 H V C CNN +$FPLIST + D? + SO* + SM* +$ENDFPLIST +DRAW +P 5 0 1 0 50 0 -50 50 -50 -50 50 0 50 0 F +P 5 0 1 8 70 50 50 30 50 -30 30 -50 30 -50 N +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.lib new file mode 100644 index 0000000..68b8c20 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 03:25:17 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +# ZENER +# +DEF ZENER D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "ZENER" 0 -100 40 H V C CNN +$FPLIST + D? + SO* + SM* +$ENDFPLIST +DRAW +P 5 0 1 0 50 0 -50 50 -50 -50 50 0 50 0 F +P 5 0 1 8 70 50 50 30 50 -30 30 -50 30 -50 N +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.bak new file mode 100644 index 0000000..298b82a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.bak @@ -0,0 +1,132 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 03:23:37 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 7200 2400 +Connection ~ 7200 1800 +Wire Wire Line + 6450 2400 7550 2400 +Wire Wire Line + 6450 2400 6450 2250 +Connection ~ 6850 2400 +Wire Wire Line + 7550 2400 7550 2300 +Wire Wire Line + 6850 2000 6850 1700 +Wire Wire Line + 6850 1200 6450 1200 +Wire Wire Line + 7550 1800 6850 1800 +Connection ~ 6850 1800 +Wire Wire Line + 6450 1200 6450 1350 +Wire Wire Line + 7100 2400 7100 2600 +Connection ~ 7100 2400 +$Comp +L GND #PWR01 +U 1 1 516BCDAC +P 7100 2600 +F 0 "#PWR01" H 7100 2600 30 0001 C CNN +F 1 "GND" H 7100 2530 30 0001 C CNN + 1 7100 2600 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 516BCD76 +P 6450 1800 +F 0 "v1" H 6250 1900 60 0000 C CNN +F 1 "DC" H 6250 1750 60 0000 C CNN +F 2 "R1" H 6150 1800 60 0000 C CNN + 1 6450 1800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8 U1 +U 1 1 516BCD56 +P 7200 2100 +F 0 "U1" H 7050 2200 50 0000 C CNN +F 1 "VPLOT8" H 7350 2200 50 0000 C CNN + 1 7200 2100 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516BCD26 +P 7550 2050 +F 0 "R2" V 7630 2050 50 0000 C CNN +F 1 "R" V 7550 2050 50 0000 C CNN + 1 7550 2050 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516BCCFA +P 6850 1450 +F 0 "R1" V 6930 1450 50 0000 C CNN +F 1 "R" V 6850 1450 50 0000 C CNN + 1 6850 1450 + 1 0 0 -1 +$EndComp +$Comp +L ZENER D1 +U 1 1 516BCCC7 +P 6850 2200 +F 0 "D1" H 6850 2300 50 0000 C CNN +F 1 "ZENER" H 6850 2100 40 0000 C CNN + 1 6850 2200 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir new file mode 100644 index 0000000..69c2aea --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 03:25:12 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 3 0 DC +U1 0 1 VPLOT8 +R2 1 0 2000 +R1 3 1 500 +D1 0 1 ZENER + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.ckt new file mode 100644 index 0000000..cd705cf --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.ckt @@ -0,0 +1,10 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 03:25:12 pm ist + +v1 3 0 dc 10 +r2 1 0 2000 +r1 3 1 500 +d1 0 1 zener + +.dc v1 0e-00 10e-00 5e-03 +.plot -v(1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.out new file mode 100644 index 0000000..2cdd76d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.cir.out @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 03:25:12 pm ist + +v1 3 0 dc 10 +r2 1 0 2000 +r1 3 1 500 +d1 0 1 zener + +.dc v1 0e-00 10e-00 5e-03 + +* Control Statements +.control +run +plot -v(1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.proj new file mode 100644 index 0000000..e0d6a2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.proj @@ -0,0 +1 @@ +schematicFile example_2.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.sch new file mode 100644 index 0000000..ddb3704 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.8/example_2.8.sch @@ -0,0 +1,123 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 03:25:17 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:example_2.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 7200 2400 +Connection ~ 7200 1800 +Wire Wire Line + 6450 2400 7550 2400 +Wire Wire Line + 6450 2400 6450 2250 +Connection ~ 6850 2400 +Wire Wire Line + 7550 2400 7550 2300 +Wire Wire Line + 6850 2000 6850 1700 +Wire Wire Line + 6850 1200 6450 1200 +Wire Wire Line + 7550 1800 6850 1800 +Connection ~ 6850 1800 +Wire Wire Line + 6450 1200 6450 1350 +Wire Wire Line + 7100 2400 7100 2600 +Connection ~ 7100 2400 +$Comp +L GND #PWR01 +U 1 1 516BCDAC +P 7100 2600 +F 0 "#PWR01" H 7100 2600 30 0001 C CNN +F 1 "GND" H 7100 2530 30 0001 C CNN + 1 7100 2600 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 516BCD76 +P 6450 1800 +F 0 "v1" H 6250 1900 60 0000 C CNN +F 1 "DC" H 6250 1750 60 0000 C CNN +F 2 "R1" H 6150 1800 60 0000 C CNN + 1 6450 1800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8 U1 +U 1 1 516BCD56 +P 7200 2100 +F 0 "U1" H 7050 2200 50 0000 C CNN +F 1 "VPLOT8" H 7350 2200 50 0000 C CNN + 1 7200 2100 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516BCD26 +P 7550 2050 +F 0 "R2" V 7630 2050 50 0000 C CNN +F 1 "2000" V 7550 2050 50 0000 C CNN + 1 7550 2050 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516BCCFA +P 6850 1450 +F 0 "R1" V 6930 1450 50 0000 C CNN +F 1 "500" V 6850 1450 50 0000 C CNN + 1 6850 1450 + 1 0 0 -1 +$EndComp +$Comp +L ZENER D1 +U 1 1 516BCCC7 +P 6850 2200 +F 0 "D1" H 6850 2300 50 0000 C CNN +F 1 "ZENER" H 6850 2100 40 0000 C CNN + 1 6850 2200 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis new file mode 100644 index 0000000..73c8f09 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 4e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak new file mode 100644 index 0000000..1d8b498 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 04:09:27 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib new file mode 100644 index 0000000..f2704f3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:42:22 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak new file mode 100644 index 0000000..ca5b9de --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.bak @@ -0,0 +1,167 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 04:02:35 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example3.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 2550 5900 1050 +Wire Wire Line + 4400 4300 4400 3050 +Wire Wire Line + 5000 3800 5000 3250 +Wire Wire Line + 5000 2050 5000 1550 +Connection ~ 5000 5450 +Wire Wire Line + 4400 5450 5900 5450 +Wire Wire Line + 5900 1050 5000 1050 +Wire Wire Line + 4400 3050 4700 3050 +Wire Wire Line + 4400 5450 4400 5200 +Wire Wire Line + 5000 4950 5000 5750 +Connection ~ 5000 5600 +Connection ~ 5000 3450 +Wire Wire Line + 5000 2550 5000 2850 +Wire Wire Line + 5000 4300 5000 4450 +Wire Wire Line + 5900 5450 5900 3450 +$Comp +L IPLOT U2 +U 1 1 516BD643 +P 5000 4050 +F 0 "U2" H 4850 4150 50 0000 C CNN +F 1 "IPLOT" H 5150 4150 50 0000 C CNN + 1 5000 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516BD5F9 +P 5000 2300 +F 0 "U1" H 4850 2400 50 0000 C CNN +F 1 "IPLOT" H 5150 2400 50 0000 C CNN + 1 5000 2300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5166BF83 +P 5000 5600 +F 0 "#FLG01" H 5000 5695 30 0001 C CNN +F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN + 1 5000 5600 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166BF64 +P 5000 5750 +F 0 "#PWR02" H 5000 5750 30 0001 C CNN +F 1 "GND" H 5000 5680 30 0001 C CNN + 1 5000 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166BEE6 +P 4400 4750 +F 0 "v1" H 4200 4850 60 0000 C CNN +F 1 "4" H 4200 4700 60 0000 C CNN +F 2 "R1" H 4100 4750 60 0000 C CNN + 1 4400 4750 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5166BED7 +P 5900 3000 +F 0 "v2" H 5700 3100 60 0000 C CNN +F 1 "10V" H 5700 2950 60 0000 C CNN +F 2 "R1" H 5600 3000 60 0000 C CNN + 1 5900 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166BE96 +P 5000 4700 +F 0 "R2" V 5080 4700 50 0000 C CNN +F 1 "3300" V 5000 4700 50 0000 C CNN + 1 5000 4700 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166BE8E +P 5000 1300 +F 0 "R1" V 5080 1300 50 0000 C CNN +F 1 "4700" V 5000 1300 50 0000 C CNN + 1 5000 1300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166BE53 +P 4900 3050 +F 0 "Q1" H 4900 2900 50 0000 R CNN +F 1 "NPN" H 4900 3200 50 0000 R CNN + 1 4900 3050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir new file mode 100644 index 0000000..87e5f07 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 04:09:24 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 6 7 VPLOT8_1 +U2 7 3 IPLOT +U1 5 6 IPLOT +v1 2 0 4 +v2 4 0 10V +R2 3 0 3300 +R1 4 5 4700 +Q1 7 2 6 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt new file mode 100644 index 0000000..21ea9e6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.ckt @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 04:09:24 pm ist + +* Plotting option vplot8_1 +V_u2 7 3 0 +V_u1 5 6 0 +v1 2 0 4 +v2 4 0 10v +r2 3 0 3300 +r1 4 5 4700 +q1 6 2 7 npn + +.dc v1 0e-00 4e-00 5e-03 +.plot v(6) v(7) +.plot i(V_u2) +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out new file mode 100644 index 0000000..b00fc82 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.cir.out @@ -0,0 +1,21 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 04:09:24 pm ist + +* Plotting option vplot8_1 +V_u2 7 3 0 +V_u1 5 6 0 +v1 2 0 4 +v2 4 0 10v +r2 3 0 3300 +r1 4 5 4700 +q1 6 2 7 npn + +.dc v1 0e-00 4e-00 5e-03 + +* Control Statements +.control +run +plot v(6) v(7) +plot i(V_u2) +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro new file mode 100644 index 0000000..a38bf27 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.pro @@ -0,0 +1,84 @@ +update=Monday 15 April 2013 04:08:24 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj new file mode 100644 index 0000000..9978f31 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.proj @@ -0,0 +1 @@ +schematicFile example3.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch new file mode 100644 index 0000000..4138df7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example3.4/example3.4.sch @@ -0,0 +1,186 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 04:09:27 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example3.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5000 2650 +$Comp +L VPLOT8_1 U3 +U 1 1 516BD8B9 +P 5300 2650 +F 0 "U3" H 5150 2750 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN + 1 5300 2650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516BD8AC +P 5300 3450 +F 0 "U3" H 5150 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN + 2 5300 3450 + 0 1 1 0 +$EndComp +Wire Wire Line + 5900 2550 5900 1050 +Wire Wire Line + 4400 4300 4400 3050 +Wire Wire Line + 5000 3800 5000 3250 +Wire Wire Line + 5000 2050 5000 1550 +Connection ~ 5000 5450 +Wire Wire Line + 4400 5450 5900 5450 +Wire Wire Line + 5900 1050 5000 1050 +Wire Wire Line + 4400 3050 4700 3050 +Wire Wire Line + 4400 5450 4400 5200 +Wire Wire Line + 5000 4950 5000 5750 +Connection ~ 5000 5600 +Connection ~ 5000 3450 +Wire Wire Line + 5000 2550 5000 2850 +Wire Wire Line + 5000 4300 5000 4450 +Wire Wire Line + 5900 5450 5900 3450 +$Comp +L IPLOT U2 +U 1 1 516BD643 +P 5000 4050 +F 0 "U2" H 4850 4150 50 0000 C CNN +F 1 "IPLOT" H 5150 4150 50 0000 C CNN + 1 5000 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516BD5F9 +P 5000 2300 +F 0 "U1" H 4850 2400 50 0000 C CNN +F 1 "IPLOT" H 5150 2400 50 0000 C CNN + 1 5000 2300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5166BF83 +P 5000 5600 +F 0 "#FLG01" H 5000 5695 30 0001 C CNN +F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN + 1 5000 5600 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166BF64 +P 5000 5750 +F 0 "#PWR02" H 5000 5750 30 0001 C CNN +F 1 "GND" H 5000 5680 30 0001 C CNN + 1 5000 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166BEE6 +P 4400 4750 +F 0 "v1" H 4200 4850 60 0000 C CNN +F 1 "4" H 4200 4700 60 0000 C CNN +F 2 "R1" H 4100 4750 60 0000 C CNN + 1 4400 4750 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5166BED7 +P 5900 3000 +F 0 "v2" H 5700 3100 60 0000 C CNN +F 1 "10V" H 5700 2950 60 0000 C CNN +F 2 "R1" H 5600 3000 60 0000 C CNN + 1 5900 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166BE96 +P 5000 4700 +F 0 "R2" V 5080 4700 50 0000 C CNN +F 1 "3300" V 5000 4700 50 0000 C CNN + 1 5000 4700 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166BE8E +P 5000 1300 +F 0 "R1" V 5080 1300 50 0000 C CNN +F 1 "4700" V 5000 1300 50 0000 C CNN + 1 5000 1300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166BE53 +P 4900 3050 +F 0 "Q1" H 4900 2900 50 0000 R CNN +F 1 "NPN" H 4900 3200 50 0000 R CNN + 1 4900 3050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis new file mode 100644 index 0000000..395e205 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/analysis @@ -0,0 +1 @@ +.dc v2 0e-00 15e-00 15e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak new file mode 100644 index 0000000..3c23bc8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:57:20 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib new file mode 100644 index 0000000..b1e32d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 06:59:23 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak new file mode 100644 index 0000000..9b63b41 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.bak @@ -0,0 +1,154 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:57:20 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5750 5350 5750 5950 +Connection ~ 4300 4400 +Connection ~ 5750 4100 +Wire Wire Line + 4300 4500 4300 4400 +Wire Wire Line + 4300 4400 5450 4400 +Connection ~ 4750 4400 +Wire Wire Line + 4750 4600 4750 4050 +Wire Wire Line + 4750 3150 4750 2750 +Wire Wire Line + 4750 2750 5750 2750 +Wire Wire Line + 5750 4600 5750 4850 +Wire Wire Line + 4750 5500 4750 5950 +Wire Wire Line + 4750 5950 5750 5950 +Wire Wire Line + 5750 4200 5750 3250 +$Comp +L DC v1 +U 1 1 517A27AF +P 4750 3600 +F 0 "v1" H 4550 3700 60 0000 C CNN +F 1 "DC" H 4550 3550 60 0000 C CNN +F 2 "R1" H 4450 3600 60 0000 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 517A278C +P 4750 5050 +F 0 "v2" H 4550 5150 60 0000 C CNN +F 1 "DC" H 4550 5000 60 0000 C CNN +F 2 "R1" H 4450 5050 60 0000 C CNN + 1 4750 5050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5178C864 +P 6050 4100 +F 0 "U1" H 5900 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 6200 4200 50 0000 C CNN + 1 6050 4100 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 5178C812 +P 5650 4400 +F 0 "Q1" H 5650 4250 50 0000 R CNN +F 1 "NPN" H 5650 4550 50 0000 R CNN + 1 5650 4400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516BDAF0 +P 4300 4400 +F 0 "#FLG01" H 4300 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4300 4630 30 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516BDAE0 +P 4300 4500 +F 0 "#PWR02" H 4300 4500 30 0001 C CNN +F 1 "GND" H 4300 4430 30 0001 C CNN + 1 4300 4500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516BD9B5 +P 5750 3000 +F 0 "R1" V 5830 3000 50 0000 C CNN +F 1 "5k" V 5750 3000 50 0000 C CNN + 1 5750 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516BD9A9 +P 5750 5100 +F 0 "R2" V 5850 5100 50 0000 C CNN +F 1 "7.07k" V 5750 5100 50 0000 C CNN + 1 5750 5100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir new file mode 100644 index 0000000..bdacb65 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 06:59:18 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 4 3 IPLOT +v1 1 0 DC +v2 0 5 DC +U1 3 VPLOT8_1 +Q1 2 0 3 NPN +R1 1 4 5k +R2 2 5 7.07k + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt new file mode 100644 index 0000000..055c4d2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 06:59:18 pm ist +.include npn.lib + +V_u2 4 3 0 +v1 1 0 dc 15 +v2 0 5 dc 15 +* Plotting option vplot8_1 +q1 3 0 2 npn +r1 1 4 5k +r2 2 5 7.07k + +.dc v2 0e-00 15e-00 15e-00 +.plot i(V_u2) +.plot v(3) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out new file mode 100644 index 0000000..17c61c2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 06:59:18 pm ist +.include npn.lib + +V_u2 4 3 0 +v1 1 0 dc 15 +v2 0 5 dc 15 +* Plotting option vplot8_1 +q1 3 0 2 npn +r1 1 4 5k +r2 2 5 7.07k + +.dc v2 0e-00 15e-00 15e-00 + +* Control Statements +.control +run +plot i(V_u2) +plot v(3) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro new file mode 100644 index 0000000..5bf994d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.pro @@ -0,0 +1,74 @@ +update=Monday 15 April 2013 04:46:53 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj new file mode 100644 index 0000000..3a2ba21 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.proj @@ -0,0 +1 @@ +schematicFile example_3.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch new file mode 100644 index 0000000..7873ea6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/example_3.1.sch @@ -0,0 +1,165 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 06:59:23 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5750 4200 5750 3850 +Wire Wire Line + 5750 5350 5750 5950 +Connection ~ 4300 4400 +Connection ~ 5750 4100 +Wire Wire Line + 4300 4500 4300 4400 +Wire Wire Line + 4300 4400 5450 4400 +Connection ~ 4750 4400 +Wire Wire Line + 4750 4600 4750 4050 +Wire Wire Line + 4750 3150 4750 2750 +Wire Wire Line + 4750 2750 5750 2750 +Wire Wire Line + 5750 4600 5750 4850 +Wire Wire Line + 4750 5500 4750 5950 +Wire Wire Line + 4750 5950 5750 5950 +Wire Wire Line + 5750 3250 5750 3350 +$Comp +L IPLOT U2 +U 1 1 51938D87 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "IPLOT" H 5900 3700 50 0000 C CNN + 1 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 517A27AF +P 4750 3600 +F 0 "v1" H 4550 3700 60 0000 C CNN +F 1 "DC" H 4550 3550 60 0000 C CNN +F 2 "R1" H 4450 3600 60 0000 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 517A278C +P 4750 5050 +F 0 "v2" H 4550 5150 60 0000 C CNN +F 1 "DC" H 4550 5000 60 0000 C CNN +F 2 "R1" H 4450 5050 60 0000 C CNN + 1 4750 5050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5178C864 +P 6050 4100 +F 0 "U1" H 5900 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 6200 4200 50 0000 C CNN + 1 6050 4100 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 5178C812 +P 5650 4400 +F 0 "Q1" H 5650 4250 50 0000 R CNN +F 1 "NPN" H 5650 4550 50 0000 R CNN + 1 5650 4400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516BDAF0 +P 4300 4400 +F 0 "#FLG1" H 4300 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4300 4630 30 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516BDAE0 +P 4300 4500 +F 0 "#PWR1" H 4300 4500 30 0001 C CNN +F 1 "GND" H 4300 4430 30 0001 C CNN + 1 4300 4500 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516BD9B5 +P 5750 3000 +F 0 "R1" V 5830 3000 50 0000 C CNN +F 1 "5k" V 5750 3000 50 0000 C CNN + 1 5750 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516BD9A9 +P 5750 5100 +F 0 "R2" V 5850 5100 50 0000 C CNN +F 1 "7.07k" V 5750 5100 50 0000 C CNN + 1 5750 5100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib new file mode 100644 index 0000000..1ff6b05 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.1/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 ++ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 ++ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 ++ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 ++ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 ++ Is=6.734f Eg=1.11 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/analysis new file mode 100644 index 0000000..bd0d4e6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 15e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10-cache.lib new file mode 100644 index 0000000..a66f15e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 10:01:35 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir new file mode 100644 index 0000000..6cc7243 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 10:01:31 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 3 7 VPLOT8_1 +R2 1 0 50000 +R1 5 1 100000 +R4 4 0 3000 +U4 7 4 IPLOT +v1 5 0 15V +U3 6 3 IPLOT +R3 5 6 5000 +Q1 7 1 3 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.ckt new file mode 100644 index 0000000..6b82c7f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:01:31 pm ist + +* Plotting option vplot8_1 +r2 1 0 50000 +r1 5 1 100000 +r4 4 0 3000 +V_u4 7 4 0 +v1 5 0 15v +V_u3 6 3 0 +r3 5 6 5000 +q1 3 1 7 npn + +.dc v1 0e-00 15e-00 5e-03 +.plot v(1) v(3) v(7) +.plot i(V_u4) +.plot i(V_u3) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.out new file mode 100644 index 0000000..0e51a81 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:01:31 pm ist + +* Plotting option vplot8_1 +r2 1 0 50000 +r1 5 1 100000 +r4 4 0 3000 +V_u4 7 4 0 +v1 5 0 15v +V_u3 6 3 0 +r3 5 6 5000 +q1 3 1 7 npn + +.dc v1 0e-00 15e-00 5e-03 + +* Control Statements +.control +run +plot v(1) v(3) v(7) +plot i(V_u4) +plot i(V_u3) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.pro new file mode 100644 index 0000000..78f9f3c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.pro @@ -0,0 +1,74 @@ +update=Monday 15 April 2013 09:51:55 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.proj new file mode 100644 index 0000000..6fef01d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.proj @@ -0,0 +1 @@ +schematicFile example_3.10.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.sch new file mode 100644 index 0000000..54adb65 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.10/example_3.10.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 10:01:35 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5050 3350 4200 3350 +Wire Wire Line + 6850 2850 6850 1300 +Wire Wire Line + 6850 1300 4200 1300 +Wire Wire Line + 4200 1300 4200 2200 +Connection ~ 4200 3350 +Wire Wire Line + 4200 2700 4200 3800 +Wire Wire Line + 6850 3750 6850 5150 +Wire Wire Line + 5350 3550 5350 3750 +Wire Wire Line + 5350 2050 5350 2250 +Wire Wire Line + 5350 1550 5350 1300 +Wire Wire Line + 5350 2750 5350 3150 +Wire Wire Line + 5350 4250 5350 4400 +Wire Wire Line + 4200 4300 4200 5150 +Wire Wire Line + 4200 5150 6850 5150 +Connection ~ 5350 5150 +Connection ~ 5350 1300 +Wire Wire Line + 5350 5650 5350 4900 +Connection ~ 5350 5500 +Connection ~ 5350 3650 +Connection ~ 5350 2900 +Connection ~ 5000 3350 +$Comp +L VPLOT8_1 U2 +U 3 1 516C2B0C +P 5650 3650 +F 0 "U2" H 5500 3750 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN + 3 5650 3650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516C2B05 +P 5650 2900 +F 0 "U2" H 5500 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN + 2 5650 2900 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516C2AFE +P 5000 3050 +F 0 "U2" H 4850 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN + 1 5000 3050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C2AB7 +P 5350 5500 +F 0 "#FLG01" H 5350 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN + 1 5350 5500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C2AAB +P 5350 5650 +F 0 "#PWR02" H 5350 5650 30 0001 C CNN +F 1 "GND" H 5350 5580 30 0001 C CNN + 1 5350 5650 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516C2A3E +P 4200 4050 +F 0 "R2" V 4280 4050 50 0000 C CNN +F 1 "50000" V 4200 4050 50 0000 C CNN + 1 4200 4050 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516C2A13 +P 4200 2450 +F 0 "R1" V 4280 2450 50 0000 C CNN +F 1 "100000" V 4200 2450 50 0000 C CNN + 1 4200 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 516C29D9 +P 5350 4650 +F 0 "R4" V 5430 4650 50 0000 C CNN +F 1 "3000" V 5350 4650 50 0000 C CNN + 1 5350 4650 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C29CD +P 5350 4000 +F 0 "U4" H 5200 4100 50 0000 C CNN +F 1 "IPLOT" H 5500 4100 50 0000 C CNN + 1 5350 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C296E +P 6850 3300 +F 0 "v1" H 6650 3400 60 0000 C CNN +F 1 "15V" H 6650 3250 60 0000 C CNN +F 2 "R1" H 6550 3300 60 0000 C CNN + 1 6850 3300 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C2958 +P 5350 2500 +F 0 "U3" H 5200 2600 50 0000 C CNN +F 1 "IPLOT" H 5500 2600 50 0000 C CNN + 1 5350 2500 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C293A +P 5350 1800 +F 0 "R3" V 5430 1800 50 0000 C CNN +F 1 "5000" V 5350 1800 50 0000 C CNN + 1 5350 1800 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516C2934 +P 5250 3350 +F 0 "Q1" H 5250 3200 50 0000 R CNN +F 1 "NPN" H 5250 3500 50 0000 R CNN + 1 5250 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/analysis new file mode 100644 index 0000000..bd0d4e6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 15e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11-cache.lib new file mode 100644 index 0000000..c412639 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11-cache.lib @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 10:18:23 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir new file mode 100644 index 0000000..72eb140 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir @@ -0,0 +1,23 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 10:18:19 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U4 11 VPLOT8_1 +R1 7 11 100000 +U3 1 4 6 5 VPLOT8_1 +R5 7 3 2000 +U5 3 6 IPLOT +R6 2 0 2700 +U6 5 2 IPLOT +R4 10 0 3000 +U2 4 10 IPLOT +R3 7 9 5000 +U1 9 1 IPLOT +v1 7 0 DC +R2 11 0 50000 +Q2 6 1 5 PNP +Q1 4 11 1 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.ckt new file mode 100644 index 0000000..5e6583e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.ckt @@ -0,0 +1,26 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:18:19 pm ist + +* Plotting option vplot8_1 +r1 7 11 100000 +* Plotting option vplot8_1 +r5 7 3 2000 +V_u5 3 6 0 +r6 2 0 2700 +V_u6 5 2 0 +r4 10 0 3000 +V_u2 4 10 0 +r3 7 9 5000 +V_u1 9 1 0 +v1 7 0 dc 15 +r2 11 0 50000 +q2 5 1 6 pnp +q1 1 11 4 npn + +.dc v1 0e-00 15e-00 5e-03 +.plot v(11) +.plot v(1) v(4) v(6) v(5) +.plot i(V_u5) +.plot i(V_u6) +.plot i(V_u2) +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.out new file mode 100644 index 0000000..1a2f17d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.cir.out @@ -0,0 +1,31 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 10:18:19 pm ist + +* Plotting option vplot8_1 +r1 7 11 100000 +* Plotting option vplot8_1 +r5 7 3 2000 +V_u5 3 6 0 +r6 2 0 2700 +V_u6 5 2 0 +r4 10 0 3000 +V_u2 4 10 0 +r3 7 9 5000 +V_u1 9 1 0 +v1 7 0 dc 15 +r2 11 0 50000 +q2 5 1 6 pnp +q1 1 11 4 npn + +.dc v1 0e-00 15e-00 5e-03 + +* Control Statements +.control +run +plot v(11) +plot v(1) v(4) v(6) v(5) +plot i(V_u5) +plot i(V_u6) +plot i(V_u2) +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.pro new file mode 100644 index 0000000..9c11e90 --- /dev/null +++ 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b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.sch new file mode 100644 index 0000000..766b40d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.11/example_3.11.sch @@ -0,0 +1,295 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 10:18:23 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title 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+++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:09:27 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.lib new file mode 100644 index 0000000..b975094 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:31:57 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.bak new file mode 100644 index 0000000..99334cc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.bak @@ -0,0 +1,207 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:09:27 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.12-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4900 3850 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE3EB +P 4900 3850 +F 0 "#FLG01" H 4900 3945 30 0001 C CNN +F 1 "PWR_FLAG" H 4900 4030 30 0000 C CNN + 1 4900 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 4950 3850 3850 +Wire Wire Line + 6650 4100 6650 5950 +Wire Wire Line + 5350 3400 5350 3450 +Wire Wire Line + 3850 5850 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 5050 3850 +Wire Wire Line + 4700 3850 5050 3850 +Wire Wire Line + 5700 4100 5350 4100 +Connection ~ 5350 4100 +Connection ~ 6500 4100 +Wire Wire Line + 6500 2550 5350 2550 +Wire Wire Line + 5350 2550 5350 3000 +Wire Wire Line + 5350 4900 5350 4600 +Wire Wire Line + 5350 5300 5350 5850 +Wire Wire Line + 5350 5850 6500 5850 +Wire Wire Line + 6750 4100 6200 4100 +Connection ~ 6650 4100 +Wire Wire Line + 3850 3850 4200 3850 +Wire Wire Line + 5050 5100 5050 3200 +Wire Wire Line + 5350 4100 5350 3950 +Wire Wire Line + 6500 4950 6500 3450 +$Comp +L IPLOT U1 +U 1 1 516C3068 +P 5350 3700 +F 0 "U1" H 5200 3800 50 0000 C CNN +F 1 "IPLOT" H 5500 3800 50 0000 C CNN + 1 5350 3700 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C304B +P 5350 4350 +F 0 "U2" H 5200 4450 50 0000 C CNN +F 1 "IPLOT" H 5500 4450 50 0000 C CNN + 1 5350 4350 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5166EE0B +P 3850 5400 +F 0 "v3" H 3650 5500 60 0000 C CNN +F 1 "5V" H 3650 5350 60 0000 C CNN +F 2 "R1" H 3550 5400 60 0000 C CNN + 1 3850 5400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166ED91 +P 4450 3850 +F 0 "R2" V 4530 3850 50 0000 C CNN +F 1 "10000" V 4450 3850 50 0000 C CNN + 1 4450 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5166ED50 +P 6650 4100 +F 0 "#FLG02" H 6650 4195 30 0001 C CNN +F 1 "PWR_FLAG" H 6650 4280 30 0000 C CNN + 1 6650 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5166ED33 +P 6750 4100 +F 0 "#PWR03" H 6750 4100 30 0001 C CNN +F 1 "GND" H 6750 4030 30 0001 C CNN + 1 6750 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166ED03 +P 5950 4100 +F 0 "R1" V 6030 4100 50 0000 C CNN +F 1 "1000" V 5950 4100 50 0000 C CNN + 1 5950 4100 + 0 -1 -1 0 +$EndComp +$Comp +L DC v2 +U 1 1 5166ECC4 +P 6500 5400 +F 0 "v2" H 6300 5500 60 0000 C CNN +F 1 "5V" H 6300 5350 60 0000 C CNN +F 2 "R1" H 6200 5400 60 0000 C CNN + 1 6500 5400 + -1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166EC91 +P 6500 3000 +F 0 "v1" H 6300 3100 60 0000 C CNN +F 1 "5V" H 6300 2950 60 0000 C CNN +F 2 "R1" H 6200 3000 60 0000 C CNN + 1 6500 3000 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q2 +U 1 1 5166EC64 +P 5250 5100 +F 0 "Q2" H 5250 4950 60 0000 R CNN +F 1 "PNP" H 5250 5250 60 0000 R CNN + 1 5250 5100 + 1 0 0 1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166EC56 +P 5250 3200 +F 0 "Q1" H 5250 3050 50 0000 R CNN +F 1 "NPN" H 5250 3350 50 0000 R CNN + 1 5250 3200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir new file mode 100644 index 0000000..1961478 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:31:53 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 5 1 IPLOT +U1 3 8 IPLOT +U2 1 7 IPLOT +v3 4 0 5V +R2 4 2 10000 +R1 5 0 1000 +v2 0 6 5V +v1 3 0 5V +Q2 7 2 6 PNP +Q1 1 2 8 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.ckt new file mode 100644 index 0000000..2283488 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.ckt @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:31:53 pm ist + +V_u3 5 1 0 +V_u1 3 8 0 +V_u2 1 7 0 +v3 4 0 5v +r2 4 2 10000 +r1 5 0 1000 +v2 0 6 5v +v1 3 0 5v +q2 6 2 7 pnp +q1 8 2 1 npn + +.dc v3 0e-00 5e-00 1e-00 +.plot i(V_u3) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.out new file mode 100644 index 0000000..61a3934 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.cir.out @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:31:53 pm ist + +V_u3 5 1 0 +V_u1 3 8 0 +V_u2 1 7 0 +v3 4 0 5v +r2 4 2 10000 +r1 5 0 1000 +v2 0 6 5v +v1 3 0 5v +q2 6 2 7 pnp +q1 8 2 1 npn + +.dc v3 0e-00 5e-00 1e-00 + +* Control Statements +.control +run +plot i(V_u3) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.pro new file mode 100644 index 0000000..d4fedff --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.pro @@ -0,0 +1,84 @@ +update=Monday 15 April 2013 10:21:09 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.proj new file mode 100644 index 0000000..cf8b515 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.proj @@ -0,0 +1 @@ +schematicFile example_3.12.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.sch new file mode 100644 index 0000000..a133513 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.12/example_3.12.sch @@ -0,0 +1,222 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 01:31:57 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.12-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5350 4000 +Connection ~ 6300 4100 +Wire Wire Line + 6300 4350 6300 4100 +Wire Wire Line + 5350 3400 5350 4100 +Wire Wire Line + 4950 2500 4950 2550 +Wire Wire Line + 4950 2550 6500 2550 +Wire Wire Line + 6500 4950 6500 3450 +Wire Wire Line + 5050 5100 5050 3200 +Wire Wire Line + 4200 3850 3850 3850 +Connection ~ 6650 4100 +Wire Wire Line + 6750 4100 6200 4100 +Wire Wire Line + 6500 5850 5350 5850 +Wire Wire Line + 5350 5850 5350 5300 +Wire Wire Line + 5350 4900 5350 4600 +Connection ~ 6500 4100 +Connection ~ 5350 4100 +Wire Wire Line + 4700 3850 5050 3850 +Connection ~ 5050 3850 +Wire Wire Line + 3850 5950 6650 5950 +Wire Wire Line + 3850 5950 3850 5850 +Wire Wire Line + 6650 5950 6650 4100 +Wire Wire Line + 3850 3850 3850 4950 +Connection ~ 4900 3850 +Wire Wire Line + 4950 3000 5350 3000 +Wire Wire Line + 5850 4000 5850 4350 +Wire Wire Line + 5850 4350 5800 4350 +$Comp +L IPLOT U3 +U 1 1 51909DB6 +P 5600 4000 +F 0 "U3" H 5450 4100 50 0000 C CNN +F 1 "IPLOT" H 5750 4100 50 0000 C CNN + 1 5600 4000 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE3EB +P 4900 3850 +F 0 "#FLG01" H 4900 3945 30 0001 C CNN +F 1 "PWR_FLAG" H 4900 4030 30 0000 C CNN + 1 4900 3850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516C3068 +P 4950 2750 +F 0 "U1" H 4800 2850 50 0000 C CNN +F 1 "IPLOT" H 5100 2850 50 0000 C CNN + 1 4950 2750 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C304B +P 5350 4350 +F 0 "U2" H 5200 4450 50 0000 C CNN +F 1 "IPLOT" H 5500 4450 50 0000 C CNN + 1 5350 4350 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5166EE0B +P 3850 5400 +F 0 "v3" H 3650 5500 60 0000 C CNN +F 1 "5V" H 3650 5350 60 0000 C CNN +F 2 "R1" H 3550 5400 60 0000 C CNN + 1 3850 5400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166ED91 +P 4450 3850 +F 0 "R2" V 4530 3850 50 0000 C CNN +F 1 "10000" V 4450 3850 50 0000 C CNN + 1 4450 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5166ED50 +P 6650 4100 +F 0 "#FLG02" H 6650 4195 30 0001 C CNN +F 1 "PWR_FLAG" H 6650 4280 30 0000 C CNN + 1 6650 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5166ED33 +P 6750 4100 +F 0 "#PWR03" H 6750 4100 30 0001 C CNN +F 1 "GND" H 6750 4030 30 0001 C CNN + 1 6750 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166ED03 +P 6050 4350 +F 0 "R1" V 6130 4350 50 0000 C CNN +F 1 "1000" V 6050 4350 50 0000 C CNN + 1 6050 4350 + 0 -1 -1 0 +$EndComp +$Comp +L DC v2 +U 1 1 5166ECC4 +P 6500 5400 +F 0 "v2" H 6300 5500 60 0000 C CNN +F 1 "5V" H 6300 5350 60 0000 C CNN +F 2 "R1" H 6200 5400 60 0000 C CNN + 1 6500 5400 + -1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166EC91 +P 6500 3000 +F 0 "v1" H 6300 3100 60 0000 C CNN +F 1 "5V" H 6300 2950 60 0000 C CNN +F 2 "R1" H 6200 3000 60 0000 C CNN + 1 6500 3000 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q2 +U 1 1 5166EC64 +P 5250 5100 +F 0 "Q2" H 5250 4950 60 0000 R CNN +F 1 "PNP" H 5250 5250 60 0000 R CNN + 1 5250 5100 + 1 0 0 1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166EC56 +P 5250 3200 +F 0 "Q1" H 5250 3050 50 0000 R CNN +F 1 "NPN" H 5250 3350 50 0000 R CNN + 1 5250 3200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis new file mode 100644 index 0000000..11459c7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 12e-00 12e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib new file mode 100644 index 0000000..efa56af --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:31:21 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak new file mode 100644 index 0000000..db1ff38 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak @@ -0,0 +1,210 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:16:49 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.10-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5050 3350 4200 3350 +Wire Wire Line + 6850 2850 6850 1300 +Wire Wire Line + 6850 1300 4200 1300 +Wire Wire Line + 4200 1300 4200 2200 +Connection ~ 4200 3350 +Wire Wire Line + 4200 2700 4200 3800 +Wire Wire Line + 6850 3750 6850 5150 +Wire Wire Line + 5350 3550 5350 3750 +Wire Wire Line + 5350 2050 5350 2250 +Wire Wire Line + 5350 1550 5350 1300 +Wire Wire Line + 5350 2750 5350 3150 +Wire Wire Line + 5350 4250 5350 4400 +Wire Wire Line + 4200 4300 4200 5150 +Wire Wire Line + 4200 5150 6850 5150 +Connection ~ 5350 5150 +Connection ~ 5350 1300 +Wire Wire Line + 5350 5650 5350 4900 +Connection ~ 5350 5500 +Connection ~ 5350 3650 +Connection ~ 5350 2900 +Connection ~ 5000 3350 +$Comp +L VPLOT8_1 U2 +U 3 1 516C2B0C +P 5650 3650 +F 0 "U2" H 5500 3750 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN + 3 5650 3650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516C2B05 +P 5650 2900 +F 0 "U2" H 5500 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN + 2 5650 2900 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516C2AFE +P 5000 3050 +F 0 "U2" H 4850 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN + 1 5000 3050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C2AB7 +P 5350 5500 +F 0 "#FLG01" H 5350 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN + 1 5350 5500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C2AAB +P 5350 5650 +F 0 "#PWR02" H 5350 5650 30 0001 C CNN +F 1 "GND" H 5350 5580 30 0001 C CNN + 1 5350 5650 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516C2A3E +P 4200 4050 +F 0 "R2" V 4280 4050 50 0000 C CNN +F 1 "50000" V 4200 4050 50 0000 C CNN + 1 4200 4050 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516C2A13 +P 4200 2450 +F 0 "R1" V 4280 2450 50 0000 C CNN +F 1 "100000" V 4200 2450 50 0000 C CNN + 1 4200 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 516C29D9 +P 5350 4650 +F 0 "R4" V 5430 4650 50 0000 C CNN +F 1 "3000" V 5350 4650 50 0000 C CNN + 1 5350 4650 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C29CD +P 5350 4000 +F 0 "U4" H 5200 4100 50 0000 C CNN +F 1 "IPLOT" H 5500 4100 50 0000 C CNN + 1 5350 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C296E +P 6850 3300 +F 0 "v1" H 6650 3400 60 0000 C CNN +F 1 "15V" H 6650 3250 60 0000 C CNN +F 2 "R1" H 6550 3300 60 0000 C CNN + 1 6850 3300 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C2958 +P 5350 2500 +F 0 "U3" H 5200 2600 50 0000 C CNN +F 1 "IPLOT" H 5500 2600 50 0000 C CNN + 1 5350 2500 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C293A +P 5350 1800 +F 0 "R3" V 5430 1800 50 0000 C CNN +F 1 "5000" V 5350 1800 50 0000 C CNN + 1 5350 1800 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516C2934 +P 5250 3350 +F 0 "Q1" H 5250 3200 50 0000 R CNN +F 1 "NPN" H 5250 3500 50 0000 R CNN + 1 5250 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir new file mode 100644 index 0000000..2015439 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 11:31:17 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R1 5 7 80000 +U2 7 2 1 VPLOT8_1 +R2 7 0 40000 +R4 4 0 3300 +U4 1 4 IPLOT +v1 5 0 12V +U3 6 2 IPLOT +R3 5 6 4000 +Q1 1 7 2 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt new file mode 100644 index 0000000..cc4fac4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 11:31:17 am ist + +r1 5 7 80000 +* Plotting option vplot8_1 +r2 7 0 40000 +r4 4 0 3300 +V_u4 1 4 0 +v1 5 0 12v +V_u3 6 2 0 +r3 5 6 4000 +q1 2 7 1 npn + +.dc v1 0e-00 12e-00 12e-03 +.plot v(7) v(2) v(1) +.plot i(V_u4) +.plot i(V_u3) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out new file mode 100644 index 0000000..d5ce68a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 11:31:17 am ist + +r1 5 7 80000 +* Plotting option vplot8_1 +r2 7 0 40000 +r4 4 0 3300 +V_u4 1 4 0 +v1 5 0 12v +V_u3 6 2 0 +r3 5 6 4000 +q1 2 7 1 npn + +.dc v1 0e-00 12e-00 12e-03 + +* Control Statements +.control +run +plot v(7) v(2) v(1) +plot i(V_u4) +plot i(V_u3) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro new file mode 100644 index 0000000..9ed7c71 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 11:12:52 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj new file mode 100644 index 0000000..a04af44 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj @@ -0,0 +1 @@ +schematicFile example_3.13.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch new file mode 100644 index 0000000..d0ef771 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:31:21 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 516CE8DE +P 4200 2450 +F 0 "R1" V 4280 2450 50 0000 C CNN +F 1 "80000" V 4200 2450 50 0000 C CNN + 1 4200 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 3350 4200 3350 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VPLOT8_1 U2 +U 1 1 516C2AFE +P 5000 3050 +F 0 "U2" H 4850 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN + 1 5000 3050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C2AB7 +P 5350 5500 +F 0 "#FLG01" H 5350 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN + 1 5350 5500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C2AAB +P 5350 5650 +F 0 "#PWR02" H 5350 5650 30 0001 C CNN +F 1 "GND" H 5350 5580 30 0001 C CNN + 1 5350 5650 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516C2A3E +P 4200 4050 +F 0 "R2" V 4280 4050 50 0000 C CNN +F 1 "40000" V 4200 4050 50 0000 C CNN + 1 4200 4050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 516C29D9 +P 5350 4650 +F 0 "R4" V 5430 4650 50 0000 C CNN +F 1 "3300" V 5350 4650 50 0000 C CNN + 1 5350 4650 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C29CD +P 5350 4000 +F 0 "U4" H 5200 4100 50 0000 C CNN +F 1 "IPLOT" H 5500 4100 50 0000 C CNN + 1 5350 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C296E +P 6850 3300 +F 0 "v1" H 6650 3400 60 0000 C CNN +F 1 "12V" H 6650 3250 60 0000 C CNN +F 2 "R1" H 6550 3300 60 0000 C CNN + 1 6850 3300 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C2958 +P 5350 2500 +F 0 "U3" H 5200 2600 50 0000 C CNN +F 1 "IPLOT" H 5500 2600 50 0000 C CNN + 1 5350 2500 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C293A +P 5350 1800 +F 0 "R3" V 5430 1800 50 0000 C CNN +F 1 "4000" V 5350 1800 50 0000 C CNN + 1 5350 1800 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516C2934 +P 5250 3350 +F 0 "Q1" H 5250 3200 50 0000 R CNN +F 1 "NPN" H 5250 3500 50 0000 R CNN + 1 5250 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/analysis new file mode 100644 index 0000000..6295799 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/analysis @@ -0,0 +1 @@ +.tran 5e-00 100e-00 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14-cache.lib new file mode 100644 index 0000000..4090ea9 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:35:55 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.bak new file mode 100644 index 0000000..850e6be --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.bak @@ -0,0 +1,227 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:42:22 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example3.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5000 5750 5000 4300 +Connection ~ 4550 3050 +Connection ~ 4650 3050 +Wire Wire Line + 4300 3050 4700 3050 +Wire Wire Line + 3800 3050 3700 3050 +Connection ~ 5000 2650 +Wire Wire Line + 5900 2550 5900 1050 +Wire Wire Line + 5000 3800 5000 3250 +Wire Wire Line + 5000 2050 5000 1550 +Connection ~ 5000 5450 +Wire Wire Line + 5900 1050 5000 1050 +Wire Wire Line + 2900 3050 3200 3050 +Wire Wire Line + 2900 5200 2900 5450 +Connection ~ 5000 5600 +Connection ~ 5000 3450 +Wire Wire Line + 5000 2550 5000 2850 +Wire Wire Line + 5900 3450 5900 5450 +Wire Wire Line + 2900 3950 2900 4300 +Wire Wire Line + 5900 5450 2900 5450 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CEB5B +P 4550 3050 +F 0 "#FLG01" H 4550 3145 30 0001 C CNN +F 1 "PWR_FLAG" H 4550 3230 30 0000 C CNN + 1 4550 3050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U5 +U 1 1 516CEB46 +P 4650 3350 +F 0 "U5" H 4500 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 4800 3450 50 0000 C CNN + 1 4650 3350 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CEB0E +P 4050 3050 +F 0 "U4" H 3900 3150 50 0000 C CNN +F 1 "IPLOT" H 4200 3150 50 0000 C CNN + 1 4050 3050 + -1 0 0 1 +$EndComp +$Comp +L R R2 +U 1 1 516CEAFA +P 3450 3050 +F 0 "R2" V 3530 3050 50 0000 C CNN +F 1 "100000" V 3450 3050 50 0000 C CNN + 1 3450 3050 + 0 1 1 0 +$EndComp +$Comp +L PULSE v3 +U 1 1 516CEAC5 +P 2900 3500 +F 0 "v3" H 2700 3600 60 0000 C CNN +F 1 "PULSE" H 2700 3450 60 0000 C CNN +F 2 "R1" H 2600 3500 60 0000 C CNN + 1 2900 3500 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516BD8B9 +P 5300 2650 +F 0 "U3" H 5150 2750 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN + 1 5300 2650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516BD8AC +P 5300 3450 +F 0 "U3" H 5150 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN + 2 5300 3450 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516BD643 +P 5000 4050 +F 0 "U2" H 4850 4150 50 0000 C CNN +F 1 "IPLOT" H 5150 4150 50 0000 C CNN + 1 5000 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516BD5F9 +P 5000 2300 +F 0 "U1" H 4850 2400 50 0000 C CNN +F 1 "IPLOT" H 5150 2400 50 0000 C CNN + 1 5000 2300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5166BF83 +P 5000 5600 +F 0 "#FLG02" H 5000 5695 30 0001 C CNN +F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN + 1 5000 5600 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5166BF64 +P 5000 5750 +F 0 "#PWR03" H 5000 5750 30 0001 C CNN +F 1 "GND" H 5000 5680 30 0001 C CNN + 1 5000 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166BEE6 +P 2900 4750 +F 0 "v1" H 2700 4850 60 0000 C CNN +F 1 "3V" H 2700 4700 60 0000 C CNN +F 2 "R1" H 2600 4750 60 0000 C CNN + 1 2900 4750 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5166BED7 +P 5900 3000 +F 0 "v2" H 5700 3100 60 0000 C CNN +F 1 "10V" H 5700 2950 60 0000 C CNN +F 2 "R1" H 5600 3000 60 0000 C CNN + 1 5900 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166BE8E +P 5000 1300 +F 0 "R1" V 5080 1300 50 0000 C CNN +F 1 "3000" V 5000 1300 50 0000 C CNN + 1 5000 1300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166BE53 +P 4900 3050 +F 0 "Q1" H 4900 2900 50 0000 R CNN +F 1 "NPN" H 4900 3200 50 0000 R CNN + 1 4900 3050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir new file mode 100644 index 0000000..e9d15ad --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir @@ -0,0 +1,20 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:35:51 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U6 8 VPLOT8_1 +U5 9 VPLOT8_1 +U4 9 1 IPLOT +R2 1 8 100000 +v3 8 4 PULSE +U3 2 3 VPLOT8_1 +U2 3 0 IPLOT +U1 7 2 IPLOT +v1 4 0 3V +v2 6 0 10V +R1 6 7 3000 +Q1 3 9 2 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.ckt new file mode 100644 index 0000000..b1e99c7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.ckt @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:35:51 pm ist + +* Plotting option vplot8_1 +* Plotting option vplot8_1 +V_u4 9 1 0 +r2 1 8 100000 +v3 8 4 pulse(0 1 0 0 0 2 ) +* Plotting option vplot8_1 +V_u2 3 0 0 +V_u1 7 2 0 +v1 4 0 3v +v2 6 0 10v +r1 6 7 3000 +q1 2 9 3 npn + +.tran 5e-00 100e-00 0e-00 +.plot v(8) +.plot v(9) +.plot i(V_u4) +.plot v(2) v(3) +.plot i(V_u2) +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.out new file mode 100644 index 0000000..be85aa9 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.cir.out @@ -0,0 +1,28 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:35:51 pm ist + +* Plotting option vplot8_1 +* Plotting option vplot8_1 +V_u4 9 1 0 +r2 1 8 100000 +v3 8 4 pulse(0 1 0 0 0 2 ) +* Plotting option vplot8_1 +V_u2 3 0 0 +V_u1 7 2 0 +v1 4 0 3v +v2 6 0 10v +r1 6 7 3000 +q1 2 9 3 npn + +.tran 5e-00 100e-00 0e-00 + +* Control Statements +.control +run +plot v(8) +plot v(9) +plot i(V_u4) +plot v(2) v(3) +plot i(V_u2) +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.pro new file mode 100644 index 0000000..b5f9bd7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 11:34:19 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.proj new file mode 100644 index 0000000..2c95037 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.proj @@ -0,0 +1 @@ +schematicFile example_3.14.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.sch new file mode 100644 index 0000000..4f4f51a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.14/example_3.14.sch @@ -0,0 +1,236 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 01:35:55 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 3050 3050 +$Comp +L VPLOT8_1 U6 +U 1 1 51909ECA +P 3050 3350 +F 0 "U6" H 2900 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 3200 3450 50 0000 C CNN + 1 3050 3350 + -1 0 0 1 +$EndComp +Wire Wire Line + 5000 5750 5000 4300 +Connection ~ 4550 3050 +Connection ~ 4650 3050 +Wire Wire Line + 4300 3050 4700 3050 +Wire Wire Line + 3800 3050 3700 3050 +Connection ~ 5000 2650 +Wire Wire Line + 5900 2550 5900 1050 +Wire Wire Line + 5000 3800 5000 3250 +Wire Wire Line + 5000 2050 5000 1550 +Connection ~ 5000 5450 +Wire Wire Line + 5900 1050 5000 1050 +Wire Wire Line + 2900 3050 3200 3050 +Wire Wire Line + 2900 5200 2900 5450 +Connection ~ 5000 5600 +Connection ~ 5000 3450 +Wire Wire Line + 5000 2550 5000 2850 +Wire Wire Line + 5900 3450 5900 5450 +Wire Wire Line + 2900 3950 2900 4300 +Wire Wire Line + 5900 5450 2900 5450 +$Comp +L PWR_FLAG #FLG1 +U 1 1 516CEB5B +P 4550 3050 +F 0 "#FLG1" H 4550 3145 30 0001 C CNN +F 1 "PWR_FLAG" H 4550 3230 30 0000 C CNN + 1 4550 3050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U5 +U 1 1 516CEB46 +P 4650 3350 +F 0 "U5" H 4500 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 4800 3450 50 0000 C CNN + 1 4650 3350 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CEB0E +P 4050 3050 +F 0 "U4" H 3900 3150 50 0000 C CNN +F 1 "IPLOT" H 4200 3150 50 0000 C CNN + 1 4050 3050 + -1 0 0 1 +$EndComp +$Comp +L R R2 +U 1 1 516CEAFA +P 3450 3050 +F 0 "R2" V 3530 3050 50 0000 C CNN +F 1 "100000" V 3450 3050 50 0000 C CNN + 1 3450 3050 + 0 1 1 0 +$EndComp +$Comp +L PULSE v3 +U 1 1 516CEAC5 +P 2900 3500 +F 0 "v3" H 2700 3600 60 0000 C CNN +F 1 "PULSE" H 2700 3450 60 0000 C CNN +F 2 "R1" H 2600 3500 60 0000 C CNN + 1 2900 3500 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516BD8B9 +P 5300 2650 +F 0 "U3" H 5150 2750 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 2750 50 0000 C CNN + 1 5300 2650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516BD8AC +P 5300 3450 +F 0 "U3" H 5150 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 3550 50 0000 C CNN + 2 5300 3450 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516BD643 +P 5000 4050 +F 0 "U2" H 4850 4150 50 0000 C CNN +F 1 "IPLOT" H 5150 4150 50 0000 C CNN + 1 5000 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516BD5F9 +P 5000 2300 +F 0 "U1" H 4850 2400 50 0000 C CNN +F 1 "IPLOT" H 5150 2400 50 0000 C CNN + 1 5000 2300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG2 +U 1 1 5166BF83 +P 5000 5600 +F 0 "#FLG2" H 5000 5695 30 0001 C CNN +F 1 "PWR_FLAG" H 5000 5780 30 0000 C CNN + 1 5000 5600 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 5166BF64 +P 5000 5750 +F 0 "#PWR1" H 5000 5750 30 0001 C CNN +F 1 "GND" H 5000 5680 30 0001 C CNN + 1 5000 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166BEE6 +P 2900 4750 +F 0 "v1" H 2700 4850 60 0000 C CNN +F 1 "3V" H 2700 4700 60 0000 C CNN +F 2 "R1" H 2600 4750 60 0000 C CNN + 1 2900 4750 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5166BED7 +P 5900 3000 +F 0 "v2" H 5700 3100 60 0000 C CNN +F 1 "10V" H 5700 2950 60 0000 C CNN +F 2 "R1" H 5600 3000 60 0000 C CNN + 1 5900 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166BE8E +P 5000 1300 +F 0 "R1" V 5080 1300 50 0000 C CNN +F 1 "3000" V 5000 1300 50 0000 C CNN + 1 5000 1300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166BE53 +P 4900 3050 +F 0 "Q1" H 4900 2900 50 0000 R CNN +F 1 "NPN" H 4900 3200 50 0000 R CNN + 1 4900 3050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/analysis new file mode 100644 index 0000000..05351e0 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/analysis @@ -0,0 +1 @@ +.tran 1e-00 10e-00 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16-cache.lib new file mode 100644 index 0000000..e8eb963 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 12:27:16 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.bak new file mode 100644 index 0000000..8773c0d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.bak @@ -0,0 +1,221 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 12:24:14 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5450 4850 5450 5350 +Connection ~ 4300 5050 +Wire Wire Line + 4300 5050 4300 3300 +Wire Wire Line + 6650 5050 3500 5050 +Connection ~ 5450 5050 +Wire Wire Line + 6650 5050 6650 4450 +Wire Wire Line + 3500 5050 3500 4450 +Wire Wire Line + 5450 3700 5450 3500 +Wire Wire Line + 5450 2950 5450 3100 +Wire Wire Line + 5450 2300 5450 2450 +Connection ~ 5450 3050 +Connection ~ 5450 3600 +Wire Wire Line + 5450 1800 6650 1800 +Wire Wire Line + 6650 1800 6650 3550 +Wire Wire Line + 4800 3300 5150 3300 +Connection ~ 5100 3300 +Connection ~ 6650 5050 +Connection ~ 4950 3300 +Connection ~ 5450 5200 +Wire Wire Line + 3500 3550 3500 3050 +Wire Wire Line + 3500 3050 5450 3050 +Wire Wire Line + 5450 4200 5450 4350 +$Comp +L R R1 +U 1 1 516CF523 +P 5450 4600 +F 0 "R1" V 5530 4600 50 0000 C CNN +F 1 "5000" V 5450 4600 50 0000 C CNN + 1 5450 4600 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE235 +P 4950 3300 +F 0 "#FLG01" H 4950 3570 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516CE22C +P 5450 5200 +F 0 "#FLG02" H 5450 5470 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN + 1 5450 5200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516CE20C +P 5450 5350 +F 0 "#PWR03" H 5450 5350 30 0001 C CNN +F 1 "GND" H 5450 5280 30 0001 C CNN + 1 5450 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516CE1D8 +P 5100 3000 +F 0 "U2" H 4950 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516CE177 +P 4550 3300 +F 0 "U1" H 4400 3400 50 0000 C CNN +F 1 "IPLOT" H 4700 3400 50 0000 C CNN + 1 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L DC v1 +U 1 1 516CE159 +P 3500 4000 +F 0 "v1" H 3300 4100 60 0000 C CNN +F 1 "5V" H 3300 3950 60 0000 C CNN +F 2 "R1" H 3200 4000 60 0000 C CNN + 1 3500 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516CE102 +P 5750 3050 +F 0 "U2" H 5600 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN + 2 5750 3050 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516CE0C0 +P 5450 2050 +F 0 "R2" V 5530 2050 50 0000 C CNN +F 1 "10000" V 5450 2050 50 0000 C CNN + 1 5450 2050 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516CE0B6 +P 5450 2700 +F 0 "U3" H 5300 2800 50 0000 C CNN +F 1 "IPLOT" H 5600 2800 50 0000 C CNN + 1 5450 2700 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 516CE08D +P 6650 4000 +F 0 "v2" H 6450 4100 60 0000 C CNN +F 1 "10V" H 6450 3950 60 0000 C CNN +F 2 "R1" H 6350 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516CE083 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN + 3 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CE07C +P 5450 3950 +F 0 "U4" H 5300 4050 50 0000 C CNN +F 1 "IPLOT" H 5600 4050 50 0000 C CNN + 1 5450 3950 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 516CE055 +P 5350 3300 +F 0 "Q1" H 5350 3150 50 0000 R CNN +F 1 "NPN" H 5350 3450 50 0000 R CNN + 1 5350 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir new file mode 100644 index 0000000..e62088b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 12:27:13 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 7 0 PULSE +R1 1 0 5000 +U2 2 7 6 VPLOT8_1 +U1 2 0 IPLOT +R2 4 5 10000 +U3 5 7 IPLOT +v2 4 0 10V +U4 6 1 IPLOT +Q1 6 2 7 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.ckt new file mode 100644 index 0000000..3741239 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.ckt @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 12:27:13 pm ist + +v1 7 0 pulse(0 5 0 0 0 1 2) +r1 1 0 5000 +* Plotting option vplot8_1 +V_u1 2 0 0 +r2 4 5 10000 +V_u3 5 7 0 +v2 4 0 10v +V_u4 6 1 0 +q1 7 2 6 npn + +.tran 1e-00 10e-00 0e-00 +.plot v(2) v(7) v(6) +.plot i(V_u1) +.plot i(V_u3) +.plot i(V_u4) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.out new file mode 100644 index 0000000..86e4303 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.cir.out @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 12:27:13 pm ist + +v1 7 0 pulse(0 5 0 0 0 1 2) +r1 1 0 5000 +* Plotting option vplot8_1 +V_u1 2 0 0 +r2 4 5 10000 +V_u3 5 7 0 +v2 4 0 10v +V_u4 6 1 0 +q1 7 2 6 npn + +.tran 1e-00 10e-00 0e-00 + +* Control Statements +.control +run +plot v(2) v(7) v(6) +plot i(V_u1) +plot i(V_u3) +plot i(V_u4) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.pro new file mode 100644 index 0000000..ebd9c0e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 12:26:32 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.proj new file mode 100644 index 0000000..5af6371 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.proj @@ -0,0 +1 @@ +schematicFile example_3.16.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.sch new file mode 100644 index 0000000..95e37c9 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.16/example_3.16.sch @@ -0,0 +1,220 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 12:27:16 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PULSE v1 +U 1 1 516CF62D +P 3500 4000 +F 0 "v1" H 3300 4100 60 0000 C CNN +F 1 "PULSE" H 3300 3950 60 0000 C CNN +F 2 "R1" H 3200 4000 60 0000 C CNN + 1 3500 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 4850 5450 5350 +Connection ~ 4300 5050 +Wire Wire Line + 4300 5050 4300 3300 +Wire Wire Line + 6650 5050 3500 5050 +Connection ~ 5450 5050 +Wire Wire Line + 6650 5050 6650 4450 +Wire Wire Line + 3500 5050 3500 4450 +Wire Wire Line + 5450 3700 5450 3500 +Wire Wire Line + 5450 2950 5450 3100 +Wire Wire Line + 5450 2300 5450 2450 +Connection ~ 5450 3050 +Connection ~ 5450 3600 +Wire Wire Line + 5450 1800 6650 1800 +Wire Wire Line + 6650 1800 6650 3550 +Wire Wire Line + 4800 3300 5150 3300 +Connection ~ 5100 3300 +Connection ~ 6650 5050 +Connection ~ 4950 3300 +Connection ~ 5450 5200 +Wire Wire Line + 3500 3550 3500 3050 +Wire Wire Line + 3500 3050 5450 3050 +Wire Wire Line + 5450 4200 5450 4350 +$Comp +L R R1 +U 1 1 516CF523 +P 5450 4600 +F 0 "R1" V 5530 4600 50 0000 C CNN +F 1 "5000" V 5450 4600 50 0000 C CNN + 1 5450 4600 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE235 +P 4950 3300 +F 0 "#FLG01" H 4950 3570 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516CE22C +P 5450 5200 +F 0 "#FLG02" H 5450 5470 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN + 1 5450 5200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516CE20C +P 5450 5350 +F 0 "#PWR03" H 5450 5350 30 0001 C CNN +F 1 "GND" H 5450 5280 30 0001 C CNN + 1 5450 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516CE1D8 +P 5100 3000 +F 0 "U2" H 4950 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516CE177 +P 4550 3300 +F 0 "U1" H 4400 3400 50 0000 C CNN +F 1 "IPLOT" H 4700 3400 50 0000 C CNN + 1 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516CE102 +P 5750 3050 +F 0 "U2" H 5600 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN + 2 5750 3050 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516CE0C0 +P 5450 2050 +F 0 "R2" V 5530 2050 50 0000 C CNN +F 1 "10000" V 5450 2050 50 0000 C CNN + 1 5450 2050 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516CE0B6 +P 5450 2700 +F 0 "U3" H 5300 2800 50 0000 C CNN +F 1 "IPLOT" H 5600 2800 50 0000 C CNN + 1 5450 2700 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 516CE08D +P 6650 4000 +F 0 "v2" H 6450 4100 60 0000 C CNN +F 1 "10V" H 6450 3950 60 0000 C CNN +F 2 "R1" H 6350 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516CE083 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN + 3 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CE07C +P 5450 3950 +F 0 "U4" H 5300 4050 50 0000 C CNN +F 1 "IPLOT" H 5600 4050 50 0000 C CNN + 1 5450 3950 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 516CE055 +P 5350 3300 +F 0 "Q1" H 5350 3150 50 0000 R CNN +F 1 "NPN" H 5350 3450 50 0000 R CNN + 1 5350 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/analysis new file mode 100644 index 0000000..31f2ad8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 2e-00 2e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.bak new file mode 100644 index 0000000..646744a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.bak @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 26 April 2013 04:00:58 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# Idc +# +DEF Idc i 0 40 Y Y 1 F N +F0 "i" -200 100 60 H V C CNN +F1 "Idc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.lib new file mode 100644 index 0000000..b92ac3a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 26 April 2013 04:23:31 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# Idc +# +DEF Idc i 0 40 Y Y 1 F N +F0 "i" -200 100 60 H V C CNN +F1 "Idc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.bak new file mode 100644 index 0000000..65ec82c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.bak @@ -0,0 +1,188 @@ +EESchema Schematic File Version 2 date Friday 26 April 2013 04:00:58 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.20-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "26 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6350 3300 6350 2800 +Wire Wire Line + 6350 2800 5950 2800 +Wire Wire Line + 4750 4200 4950 4200 +Wire Wire Line + 5450 4200 5650 4200 +Wire Wire Line + 5950 3300 5950 3650 +Wire Wire Line + 5950 4200 5950 4050 +Connection ~ 5950 5350 +Connection ~ 5950 5450 +Connection ~ 5950 3450 +Connection ~ 5950 4100 +Wire Wire Line + 6350 4200 6350 5350 +Wire Wire Line + 5650 4200 5650 3850 +Connection ~ 5650 3850 +Connection ~ 5650 3950 +Wire Wire Line + 5950 5600 5950 4700 +Wire Wire Line + 6350 5350 5450 5350 +Wire Wire Line + 5450 5350 5450 5100 +Wire Wire Line + 5450 5100 4750 5100 +$Comp +L IDC i1 +U 1 1 517A17EC +P 4750 4650 +F 0 "i1" H 4550 4750 60 0000 C CNN +F 1 "IDC" H 4550 4600 60 0000 C CNN +F 2 "R1" H 4450 4650 60 0000 C CNN + 1 4750 4650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 517A1753 +P 5950 5350 +F 0 "#FLG01" H 5950 5620 30 0001 C CNN +F 1 "PWR_FLAG" H 5950 5580 30 0000 C CNN + 1 5950 5350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 517A174B +P 5650 3950 +F 0 "#FLG02" H 5650 4220 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4180 30 0000 C CNN + 1 5650 3950 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 517A172B +P 5950 4450 +F 0 "U4" H 5800 4550 50 0000 C CNN +F 1 "IPLOT" H 6100 4550 50 0000 C CNN + 1 5950 4450 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 517A1709 +P 5200 4200 +F 0 "U2" H 5050 4300 50 0000 C CNN +F 1 "IPLOT" H 5350 4300 50 0000 C CNN + 1 5200 4200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 517A16C8 +P 5950 3050 +F 0 "U3" H 5800 3150 50 0000 C CNN +F 1 "IPLOT" H 6100 3150 50 0000 C CNN + 1 5950 3050 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 5166CA3C +P 5650 4100 +F 0 "U1" H 5500 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN + 2 5650 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5166C9F3 +P 5650 3450 +F 0 "U1" H 5500 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN + 1 5650 3450 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5166C87D +P 5950 5600 +F 0 "#PWR03" H 5950 5600 30 0001 C CNN +F 1 "GND" H 5950 5530 30 0001 C CNN + 1 5950 5600 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166C79C +P 6350 3750 +F 0 "v1" H 6150 3850 60 0000 C CNN +F 1 "2" H 6150 3700 60 0000 C CNN +F 2 "R1" H 6050 3750 60 0000 C CNN + 1 6350 3750 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166C72A +P 5850 3850 +F 0 "Q1" H 5850 3700 50 0000 R CNN +F 1 "NPN" H 5850 4000 50 0000 R CNN + 1 5850 3850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir new file mode 100644 index 0000000..419bc05 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 26 April 2013 03:55:55 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +i1 5 0 IDC +U4 0 1 IPLOT +U2 3 5 IPLOT +U3 4 6 IPLOT +U1 6 1 VPLOT8_1 +v1 4 0 2 +Q1 1 3 6 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.ckt new file mode 100644 index 0000000..a91b990 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 26 april 2013 03:55:55 pm ist +.include npn.lib + +i1 5 0 idc +V_u4 0 1 0 +V_u2 3 5 0 +V_u3 4 6 0 +* Plotting option vplot8_1 +v1 4 0 2 +q1 6 3 1 npn + +.dc v1 0e-00 2e-00 2e-03 +.plot i(V_u4) +.plot i(V_u2) +.plot i(V_u3) +.plot v(6) v(1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.out new file mode 100644 index 0000000..b2caa59 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 26 april 2013 03:55:55 pm ist +.include npn.lib + +i1 5 0 idc +V_u4 0 1 0 +V_u2 3 5 0 +V_u3 4 6 0 +* Plotting option vplot8_1 +v1 4 0 2 +q1 6 3 1 npn + +.dc v1 0e-00 2e-00 2e-03 + +* Control Statements +.control +run +plot i(V_u4) +plot i(V_u2) +plot i(V_u3) +plot v(6) v(1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.pro new file mode 100644 index 0000000..d4ac2ef --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 12:53:24 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.proj new file mode 100644 index 0000000..231747a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.proj @@ -0,0 +1 @@ +schematicFile example_3.20.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.sch new file mode 100644 index 0000000..a694eb1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/example_3.20.sch @@ -0,0 +1,183 @@ +EESchema Schematic File Version 2 date Friday 26 April 2013 04:23:31 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.20-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "26 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6350 4200 6350 5100 +Wire Wire Line + 6350 3300 6350 2800 +Wire Wire Line + 6350 2800 5950 2800 +Wire Wire Line + 4750 4200 4950 4200 +Wire Wire Line + 5450 4200 5650 4200 +Wire Wire Line + 5950 3300 5950 3650 +Wire Wire Line + 5950 4200 5950 4050 +Connection ~ 5950 5100 +Connection ~ 5950 3450 +Connection ~ 5950 4100 +Wire Wire Line + 5650 4200 5650 3850 +Connection ~ 5650 3850 +Connection ~ 5650 3950 +Wire Wire Line + 6350 5100 4750 5100 +Wire Wire Line + 5950 5200 5950 4700 +$Comp +L IDC i1 +U 1 1 517A17EC +P 4750 4650 +F 0 "i1" H 4550 4750 60 0000 C CNN +F 1 "IDC" H 4550 4600 60 0000 C CNN +F 2 "R1" H 4450 4650 60 0000 C CNN + 1 4750 4650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 517A1753 +P 5950 5100 +F 0 "#FLG01" H 5950 5370 30 0001 C CNN +F 1 "PWR_FLAG" H 5950 5330 30 0000 C CNN + 1 5950 5100 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 517A174B +P 5650 3950 +F 0 "#FLG02" H 5650 4220 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4180 30 0000 C CNN + 1 5650 3950 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 517A172B +P 5950 4450 +F 0 "U4" H 5800 4550 50 0000 C CNN +F 1 "IPLOT" H 6100 4550 50 0000 C CNN + 1 5950 4450 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 517A1709 +P 5200 4200 +F 0 "U2" H 5050 4300 50 0000 C CNN +F 1 "IPLOT" H 5350 4300 50 0000 C CNN + 1 5200 4200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 517A16C8 +P 5950 3050 +F 0 "U3" H 5800 3150 50 0000 C CNN +F 1 "IPLOT" H 6100 3150 50 0000 C CNN + 1 5950 3050 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 5166CA3C +P 5650 4100 +F 0 "U1" H 5500 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN + 2 5650 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5166C9F3 +P 5650 3450 +F 0 "U1" H 5500 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN + 1 5650 3450 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5166C87D +P 5950 5200 +F 0 "#PWR03" H 5950 5200 30 0001 C CNN +F 1 "GND" H 5950 5130 30 0001 C CNN + 1 5950 5200 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166C79C +P 6350 3750 +F 0 "v1" H 6150 3850 60 0000 C CNN +F 1 "2" H 6150 3700 60 0000 C CNN +F 2 "R1" H 6050 3750 60 0000 C CNN + 1 6350 3750 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166C72A +P 5850 3850 +F 0 "Q1" H 5850 3700 50 0000 R CNN +F 1 "NPN" H 5850 4000 50 0000 R CNN + 1 5850 3850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/npn.lib new file mode 100644 index 0000000..1ff6b05 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.20/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 ++ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 ++ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 ++ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 ++ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 ++ Is=6.734f Eg=1.11 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/analysis new file mode 100644 index 0000000..10c280a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/bjt.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/bjt.lib new file mode 100644 index 0000000..a8411e8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/bjt.lib @@ -0,0 +1,6 @@ +.model bjt NPN( Vtf=1.7 Cjc=7.306p Nc=2 Tr=46.91n Ne=1.307 ++ Cje=22.01p Isc=0 Xtb=1.5 Rb=10 Rc=1 ++ Tf=411.1p Xti=3 Ikr=0 Bf=50 Fc=.5 ++ Ise=14.34f Br=6.092 Ikf=.2847 Mje=.377 Mjc=.3416 ++ Vaf=74.03 Vjc=.2 Vje=.75 Xtf=3 Itf=.6 ++ Is=14.34f Eg=1.11 )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.bak new file mode 100644 index 0000000..dad7e0c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.bak @@ -0,0 +1,218 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:57:15 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4000 3300 +Wire Wire Line + 5450 4200 5450 5350 +Wire Wire Line + 6650 5050 3500 5050 +Connection ~ 5450 5050 +Wire Wire Line + 6650 5050 6650 4450 +Wire Wire Line + 3500 5050 3500 4450 +Wire Wire Line + 4300 3300 3500 3300 +Wire Wire Line + 5450 3700 5450 3500 +Wire Wire Line + 5450 2950 5450 3100 +Wire Wire Line + 5450 2300 5450 2450 +Connection ~ 5450 3050 +Connection ~ 5450 3600 +Wire Wire Line + 3500 3300 3500 3550 +Wire Wire Line + 5450 1800 6650 1800 +Wire Wire Line + 6650 1800 6650 3550 +Wire Wire Line + 4800 3300 5150 3300 +Connection ~ 5100 3300 +Connection ~ 6650 5050 +Connection ~ 4950 3300 +Connection ~ 5450 5200 +Connection ~ 5450 4400 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE235 +P 4950 3300 +F 0 "#FLG01" H 4950 3570 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516CE22C +P 5450 5200 +F 0 "#FLG02" H 5450 5470 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN + 1 5450 5200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516CE20C +P 5450 5350 +F 0 "#PWR03" H 5450 5350 30 0001 C CNN +F 1 "GND" H 5450 5280 30 0001 C CNN + 1 5450 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516CE1D8 +P 5100 3000 +F 0 "U2" H 4950 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516CE177 +P 4550 3300 +F 0 "U1" H 4400 3400 50 0000 C CNN +F 1 "IPLOT" H 4700 3400 50 0000 C CNN + 1 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L DC v1 +U 1 1 516CE159 +P 3500 4000 +F 0 "v1" H 3300 4100 60 0000 C CNN +F 1 "5V" H 3300 3950 60 0000 C CNN +F 2 "R1" H 3200 4000 60 0000 C CNN + 1 3500 4000 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516CE13E +P 3750 3300 +F 0 "R1" V 3830 3300 50 0000 C CNN +F 1 "2200" V 3750 3300 50 0000 C CNN + 1 3750 3300 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516CE102 +P 5750 3050 +F 0 "U2" H 5600 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN + 2 5750 3050 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516CE0C0 +P 5450 2050 +F 0 "R2" V 5530 2050 50 0000 C CNN +F 1 "1000" V 5450 2050 50 0000 C CNN + 1 5450 2050 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516CE0B6 +P 5450 2700 +F 0 "U3" H 5300 2800 50 0000 C CNN +F 1 "IPLOT" H 5600 2800 50 0000 C CNN + 1 5450 2700 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 516CE08D +P 6650 4000 +F 0 "v2" H 6450 4100 60 0000 C CNN +F 1 "10V" H 6450 3950 60 0000 C CNN +F 2 "R1" H 6350 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516CE083 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN + 3 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CE07C +P 5450 3950 +F 0 "U4" H 5300 4050 50 0000 C CNN +F 1 "IPLOT" H 5600 4050 50 0000 C CNN + 1 5450 3950 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 516CE055 +P 5350 3300 +F 0 "Q1" H 5350 3150 50 0000 R CNN +F 1 "NPN" H 5350 3450 50 0000 R CNN + 1 5350 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.cir new file mode 100644 index 0000000..2e072a8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 12:03:45 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +Q1 7 1 5 PNP +v1 7 0 PULSE +R1 6 0 5000 +U2 1 7 5 VPLOT8_1 +U1 1 0 IPLOT +R2 3 4 10000 +U3 4 7 IPLOT +v2 3 0 10V +U4 5 6 IPLOT + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.sch new file mode 100644 index 0000000..e0eb696 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.16.sch @@ -0,0 +1,235 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 12:03:50 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CF0A9 +P 4000 3050 +F 0 "#FLG01" H 4000 3320 30 0001 C CNN +F 1 "PWR_FLAG" H 4000 3280 30 0000 C CNN + 1 4000 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 4200 3500 5050 +Connection ~ 4300 5050 +Wire Wire Line + 4300 5050 4300 3300 +Connection ~ 3500 3300 +Wire Wire Line + 3500 3550 3500 3050 +Wire Wire Line + 5450 4200 5450 4350 +Connection ~ 4000 3050 +Wire Wire Line + 3500 5050 6650 5050 +Connection ~ 5450 5050 +Wire Wire Line + 6650 5050 6650 4450 +Wire Wire Line + 5450 3700 5450 3500 +Wire Wire Line + 5450 2950 5450 3100 +Wire Wire Line + 5450 2300 5450 2450 +Connection ~ 5450 3050 +Connection ~ 5450 3600 +Wire Wire Line + 5450 1800 6650 1800 +Wire Wire Line + 6650 1800 6650 3550 +Connection ~ 5100 3300 +Connection ~ 6650 5050 +Connection ~ 4950 3300 +Connection ~ 5450 5200 +Wire Wire Line + 5450 5350 5450 4850 +Wire Wire Line + 5150 3300 4800 3300 +Wire Wire Line + 3500 3050 5450 3050 +Wire Wire Line + 5450 3050 5450 3000 +Connection ~ 5450 3000 +$Comp +L PNP Q1 +U 1 1 516CEFD3 +P 5350 3300 +F 0 "Q1" H 5350 3150 60 0000 R CNN +F 1 "PNP" H 5350 3450 60 0000 R CNN + 1 5350 3300 + 1 0 0 1 +$EndComp +$Comp +L PULSE v1 +U 1 1 516CEF97 +P 3500 3750 +F 0 "v1" H 3300 3850 60 0000 C CNN +F 1 "PULSE" H 3300 3700 60 0000 C CNN +F 2 "R1" H 3200 3750 60 0000 C CNN + 1 3500 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516CEF60 +P 5450 4600 +F 0 "R1" V 5530 4600 50 0000 C CNN +F 1 "5000" V 5450 4600 50 0000 C CNN + 1 5450 4600 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516CE235 +P 4950 3300 +F 0 "#FLG02" H 4950 3570 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 516CE22C +P 5450 5200 +F 0 "#FLG03" H 5450 5470 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN + 1 5450 5200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 516CE20C +P 5450 5350 +F 0 "#PWR04" H 5450 5350 30 0001 C CNN +F 1 "GND" H 5450 5280 30 0001 C CNN + 1 5450 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516CE1D8 +P 5100 3000 +F 0 "U2" H 4950 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516CE177 +P 4550 3300 +F 0 "U1" H 4400 3400 50 0000 C CNN +F 1 "IPLOT" H 4700 3400 50 0000 C CNN + 1 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516CE102 +P 5750 3050 +F 0 "U2" H 5600 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN + 2 5750 3050 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516CE0C0 +P 5450 2050 +F 0 "R2" V 5530 2050 50 0000 C CNN +F 1 "10000" V 5450 2050 50 0000 C CNN + 1 5450 2050 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516CE0B6 +P 5450 2700 +F 0 "U3" H 5300 2800 50 0000 C CNN +F 1 "IPLOT" H 5600 2800 50 0000 C CNN + 1 5450 2700 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 516CE08D +P 6650 4000 +F 0 "v2" H 6450 4100 60 0000 C CNN +F 1 "10V" H 6450 3950 60 0000 C CNN +F 2 "R1" H 6350 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516CE083 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN + 3 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CE07C +P 5450 3950 +F 0 "U4" H 5300 4050 50 0000 C CNN +F 1 "IPLOT" H 5600 4050 50 0000 C CNN + 1 5450 3950 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.bak new file mode 100644 index 0000000..f265808 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 12:24:14 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.lib new file mode 100644 index 0000000..8652c69 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 25 April 2013 02:05:06 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.bak new file mode 100644 index 0000000..246ba5c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.bak @@ -0,0 +1,217 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:04:07 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4000 3300 +Wire Wire Line + 5450 4200 5450 5350 +Wire Wire Line + 6650 5050 3500 5050 +Connection ~ 5450 5050 +Wire Wire Line + 6650 5050 6650 4450 +Wire Wire Line + 3500 5050 3500 4450 +Wire Wire Line + 4300 3300 3500 3300 +Wire Wire Line + 5450 3700 5450 3500 +Wire Wire Line + 5450 2950 5450 3100 +Wire Wire Line + 5450 2300 5450 2450 +Connection ~ 5450 3050 +Connection ~ 5450 3600 +Wire Wire Line + 3500 3300 3500 3550 +Wire Wire Line + 5450 1800 6650 1800 +Wire Wire Line + 6650 1800 6650 3550 +Wire Wire Line + 4800 3300 5150 3300 +Connection ~ 5100 3300 +Connection ~ 6650 5050 +Connection ~ 4950 3300 +Connection ~ 5450 5200 +Connection ~ 5450 4400 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE235 +P 4950 3300 +F 0 "#FLG01" H 4950 3570 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516CE22C +P 5450 5200 +F 0 "#FLG02" H 5450 5470 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN + 1 5450 5200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516CE20C +P 5450 5350 +F 0 "#PWR03" H 5450 5350 30 0001 C CNN +F 1 "GND" H 5450 5280 30 0001 C CNN + 1 5450 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516CE1D8 +P 5100 3000 +F 0 "U2" H 4950 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516CE177 +P 4550 3300 +F 0 "U1" H 4400 3400 50 0000 C CNN +F 1 "IPLOT" H 4700 3400 50 0000 C CNN + 1 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L DC v1 +U 1 1 516CE159 +P 3500 4000 +F 0 "v1" H 3300 4100 60 0000 C CNN +F 1 "5V" H 3300 3950 60 0000 C CNN +F 2 "R1" H 3200 4000 60 0000 C CNN + 1 3500 4000 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516CE13E +P 3750 3300 +F 0 "R1" V 3830 3300 50 0000 C CNN +F 1 "2200" V 3750 3300 50 0000 C CNN + 1 3750 3300 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516CE102 +P 5750 3050 +F 0 "U2" H 5600 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN + 2 5750 3050 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516CE0C0 +P 5450 2050 +F 0 "R2" V 5530 2050 50 0000 C CNN +F 1 "1000" V 5450 2050 50 0000 C CNN + 1 5450 2050 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516CE0B6 +P 5450 2700 +F 0 "U3" H 5300 2800 50 0000 C CNN +F 1 "IPLOT" H 5600 2800 50 0000 C CNN + 1 5450 2700 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 516CE08D +P 6650 4000 +F 0 "v2" H 6450 4100 60 0000 C CNN +F 1 "10V" H 6450 3950 60 0000 C CNN +F 2 "R1" H 6350 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516CE083 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN + 3 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CE07C +P 5450 3950 +F 0 "U4" H 5300 4050 50 0000 C CNN +F 1 "IPLOT" H 5600 4050 50 0000 C CNN + 1 5450 3950 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 516CE055 +P 5350 3300 +F 0 "Q1" H 5350 3150 50 0000 R CNN +F 1 "NPN" H 5350 3450 50 0000 R CNN + 1 5350 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir new file mode 100644 index 0000000..97a0042 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 25 April 2013 02:05:01 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 7 2 5 VPLOT8_1 +U1 7 1 IPLOT +v1 1 0 5V +R1 1 1 2200 +R2 3 4 1k +U3 4 2 IPLOT +v2 3 0 10V +U4 5 0 IPLOT +Q1 5 7 2 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.ckt new file mode 100644 index 0000000..51d6e2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.ckt @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 02:05:01 pm ist +.include npn.lib + +* Plotting option vplot8_1 +V_u1 7 1 0 +v1 1 0 5v +r1 1 1 2200 +r2 3 4 1k +V_u3 4 2 0 +v2 3 0 10v +V_u4 5 0 0 +q1 2 7 5 npn + +.dc v1 0e-00 5e-00 5e-00 +.plot v(7) v(2) v(5) +.plot i(V_u1) +.plot i(V_u3) +.plot i(V_u4) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.out new file mode 100644 index 0000000..30154d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.cir.out @@ -0,0 +1,24 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 02:05:01 pm ist +.include npn.lib + +* Plotting option vplot8_1 +V_u1 7 1 0 +v1 1 0 5v +r1 1 1 2200 +r2 3 4 1k +V_u3 4 2 0 +v2 3 0 10v +V_u4 5 0 0 +q1 2 7 5 npn + +.dc v1 0e-00 5e-00 5e-00 + +* Control Statements +.control +run +plot v(7) v(2) v(5) +plot i(V_u1) +plot i(V_u3) +plot i(V_u4) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.pro new file mode 100644 index 0000000..f37394e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 10:53:01 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.proj new file mode 100644 index 0000000..00153d6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.proj @@ -0,0 +1 @@ +schematicFile example_3.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.sch new file mode 100644 index 0000000..0bfa3f7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/example_3.3.sch @@ -0,0 +1,218 @@ +EESchema Schematic File Version 2 date Thursday 25 April 2013 02:05:06 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "25 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4000 3300 +Wire Wire Line + 5450 4200 5450 5350 +Wire Wire Line + 6650 5050 3500 5050 +Connection ~ 5450 5050 +Wire Wire Line + 6650 5050 6650 4450 +Wire Wire Line + 3500 5050 3500 4450 +Wire Wire Line + 4300 3300 3500 3300 +Wire Wire Line + 5450 3700 5450 3500 +Wire Wire Line + 5450 2950 5450 3100 +Wire Wire Line + 5450 2300 5450 2450 +Connection ~ 5450 3050 +Connection ~ 5450 3600 +Wire Wire Line + 3500 3300 3500 3550 +Wire Wire Line + 5450 1800 6650 1800 +Wire Wire Line + 6650 1800 6650 3550 +Wire Wire Line + 4800 3300 5150 3300 +Connection ~ 5100 3300 +Connection ~ 6650 5050 +Connection ~ 4950 3300 +Connection ~ 5450 5200 +Connection ~ 5450 4400 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CE235 +P 4950 3300 +F 0 "#FLG01" H 4950 3570 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 3530 30 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516CE22C +P 5450 5200 +F 0 "#FLG02" H 5450 5470 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5430 30 0000 C CNN + 1 5450 5200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516CE20C +P 5450 5350 +F 0 "#PWR03" H 5450 5350 30 0001 C CNN +F 1 "GND" H 5450 5280 30 0001 C CNN + 1 5450 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516CE1D8 +P 5100 3000 +F 0 "U2" H 4950 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516CE177 +P 4550 3300 +F 0 "U1" H 4400 3400 50 0000 C CNN +F 1 "IPLOT" H 4700 3400 50 0000 C CNN + 1 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L DC v1 +U 1 1 516CE159 +P 3500 4000 +F 0 "v1" H 3300 4100 60 0000 C CNN +F 1 "5V" H 3300 3950 60 0000 C CNN +F 2 "R1" H 3200 4000 60 0000 C CNN + 1 3500 4000 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516CE13E +P 3750 3300 +F 0 "R1" V 3830 3300 50 0000 C CNN +F 1 "2200" V 3750 3300 50 0000 C CNN + 1 3750 3300 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516CE102 +P 5750 3050 +F 0 "U2" H 5600 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3150 50 0000 C CNN + 2 5750 3050 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516CE0C0 +P 5450 2050 +F 0 "R2" V 5530 2050 50 0000 C CNN +F 1 "1k" V 5450 2050 50 0000 C CNN + 1 5450 2050 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516CE0B6 +P 5450 2700 +F 0 "U3" H 5300 2800 50 0000 C CNN +F 1 "IPLOT" H 5600 2800 50 0000 C CNN + 1 5450 2700 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 516CE08D +P 6650 4000 +F 0 "v2" H 6450 4100 60 0000 C CNN +F 1 "10V" H 6450 3950 60 0000 C CNN +F 2 "R1" H 6350 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516CE083 +P 5750 3600 +F 0 "U2" H 5600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 5900 3700 50 0000 C CNN + 3 5750 3600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516CE07C +P 5450 3950 +F 0 "U4" H 5300 4050 50 0000 C CNN +F 1 "IPLOT" H 5600 4050 50 0000 C CNN + 1 5450 3950 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 516CE055 +P 5350 3300 +F 0 "Q1" H 5350 3150 50 0000 R CNN +F 1 "NPN" H 5350 3450 50 0000 R CNN + 1 5350 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/npn.lib new file mode 100644 index 0000000..5aecc2e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.3/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf= Cjc= Nc= Tr= Ne= ++ Cje= Vjc= Xtb= Rb= Rc= ++ Tf= Xti= Ikr= Bf=50 Fc= ++ Ikf= Br= Mje= Mjc= Vaf= ++ Isc= Ise= Xtf= Vje= Is= ++ Itf= Eg= )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/analysis new file mode 100644 index 0000000..35318bb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.bak new file mode 100644 index 0000000..ea673cb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 10:43:17 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.lib new file mode 100644 index 0000000..ee59c22 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 12:52:43 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.bak new file mode 100644 index 0000000..6e5ac9b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.bak @@ -0,0 +1,172 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 07:53:26 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.6-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5650 3850 5650 5350 +Wire Wire Line + 5950 4700 5950 4850 +Wire Wire Line + 5950 2800 5950 2650 +Wire Wire Line + 5950 3300 5950 3650 +Wire Wire Line + 5950 2150 6350 2150 +Wire Wire Line + 5950 4200 5950 4050 +Wire Wire Line + 5650 5350 6350 5350 +Connection ~ 5950 5350 +Wire Wire Line + 5950 5350 5950 5600 +Connection ~ 5950 5450 +Connection ~ 5950 3450 +Connection ~ 5950 4100 +Wire Wire Line + 6350 2150 6350 3300 +Wire Wire Line + 6350 5350 6350 4200 +$Comp +L IPLOT U3 +U 1 1 516C0D28 +P 5950 4450 +F 0 "U3" H 5800 4550 50 0000 C CNN +F 1 "IPLOT" H 6100 4550 50 0000 C CNN + 1 5950 4450 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C0CED +P 5950 3050 +F 0 "U2" H 5800 3150 50 0000 C CNN +F 1 "IPLOT" H 6100 3150 50 0000 C CNN + 1 5950 3050 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 5166CA3C +P 5650 4100 +F 0 "U1" H 5500 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN + 2 5650 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5166C9F3 +P 5650 3450 +F 0 "U1" H 5500 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN + 1 5650 3450 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5166C8C4 +P 5950 5450 +F 0 "#FLG01" H 5950 5545 30 0001 C CNN +F 1 "PWR_FLAG" H 5950 5630 30 0000 C CNN + 1 5950 5450 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166C87D +P 5950 5600 +F 0 "#PWR02" H 5950 5600 30 0001 C CNN +F 1 "GND" H 5950 5530 30 0001 C CNN + 1 5950 5600 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166C822 +P 5950 2400 +F 0 "R1" V 6030 2400 50 0000 C CNN +F 1 "4700" V 5950 2400 50 0000 C CNN + 1 5950 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166C7EC +P 5950 5100 +F 0 "R2" V 6030 5100 50 0000 C CNN +F 1 "3300" V 5950 5100 50 0000 C CNN + 1 5950 5100 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166C79C +P 6350 3750 +F 0 "v1" H 6150 3850 60 0000 C CNN +F 1 "10V" H 6150 3700 60 0000 C CNN +F 2 "R1" H 6050 3750 60 0000 C CNN + 1 6350 3750 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166C72A +P 5850 3850 +F 0 "Q1" H 5850 3700 50 0000 R CNN +F 1 "NPN" H 5850 4000 50 0000 R CNN + 1 5850 3850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir new file mode 100644 index 0000000..c9bc6a1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 10:43:13 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U4 0 7 IPLOT +U3 4 1 IPLOT +U2 2 3 IPLOT +U1 2 1 VPLOT8_1 +R1 5 3 4700 +R2 4 0 3300 +v1 5 0 10V +Q1 1 7 2 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.ckt new file mode 100644 index 0000000..f76426b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.ckt @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 10:43:13 am ist +.include npn.lib + +V_u4 0 7 0 +V_u3 4 1 0 +V_u2 2 3 0 +* Plotting option vplot8_1 +r1 5 3 4700 +r2 4 0 3300 +v1 5 0 10v +q1 2 7 1 npn + +.dc v1 0e-00 10e-00 5e-03 +.plot i(V_u4) +.plot i(V_u3) +.plot i(V_u2) +.plot v(2) v(1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.out new file mode 100644 index 0000000..c87b0a7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.cir.out @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 10:43:13 am ist +.include npn.lib + +V_u4 0 7 0 +V_u3 4 1 0 +V_u2 2 3 0 +* Plotting option vplot8_1 +r1 5 3 4700 +r2 4 0 3300 +v1 5 0 10v +q1 2 7 1 npn + +.dc v1 0e-00 10e-00 5e-03 + +* Control Statements +.control +run +plot i(V_u4) +plot i(V_u3) +plot i(V_u2) +plot v(2) v(1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.pro new file mode 100644 index 0000000..36d0202 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.pro @@ -0,0 +1,84 @@ +update=Tuesday 16 April 2013 12:39:39 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.proj new file mode 100644 index 0000000..3ace945 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.proj @@ -0,0 +1 @@ +schematicFile example_3.6.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.sch new file mode 100644 index 0000000..d3d6988 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/example_3.6.sch @@ -0,0 +1,195 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 10:43:17 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.6-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5650 3950 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516CDDBE +P 5650 3950 +F 0 "#FLG01" H 5650 4220 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4180 30 0000 C CNN + 1 5650 3950 + 0 -1 -1 0 +$EndComp +Connection ~ 5650 3850 +Connection ~ 5700 5350 +Wire Wire Line + 5650 4700 5650 5350 +Wire Wire Line + 5650 3850 5650 4200 +Wire Wire Line + 6350 4200 6350 5350 +Wire Wire Line + 6350 3300 6350 2150 +Connection ~ 5950 4100 +Connection ~ 5950 3450 +Connection ~ 5950 5450 +Wire Wire Line + 5950 5350 5950 5600 +Connection ~ 5950 5350 +Wire Wire Line + 6350 5350 5650 5350 +Wire Wire Line + 5950 4200 5950 4050 +Wire Wire Line + 6350 2150 5950 2150 +Wire Wire Line + 5950 3300 5950 3650 +Wire Wire Line + 5950 2800 5950 2650 +Wire Wire Line + 5950 4700 5950 4850 +$Comp +L IPLOT U4 +U 1 1 516CDCFB +P 5650 4450 +F 0 "U4" H 5500 4550 50 0000 C CNN +F 1 "IPLOT" H 5800 4550 50 0000 C CNN + 1 5650 4450 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C0D28 +P 5950 4450 +F 0 "U3" H 5800 4550 50 0000 C CNN +F 1 "IPLOT" H 6100 4550 50 0000 C CNN + 1 5950 4450 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C0CED +P 5950 3050 +F 0 "U2" H 5800 3150 50 0000 C CNN +F 1 "IPLOT" H 6100 3150 50 0000 C CNN + 1 5950 3050 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 5166CA3C +P 5650 4100 +F 0 "U1" H 5500 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 4200 50 0000 C CNN + 2 5650 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5166C9F3 +P 5650 3450 +F 0 "U1" H 5500 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3550 50 0000 C CNN + 1 5650 3450 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5166C8C4 +P 5700 5350 +F 0 "#FLG02" H 5700 5445 30 0001 C CNN +F 1 "PWR_FLAG" H 5700 5530 30 0000 C CNN + 1 5700 5350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5166C87D +P 5950 5600 +F 0 "#PWR03" H 5950 5600 30 0001 C CNN +F 1 "GND" H 5950 5530 30 0001 C CNN + 1 5950 5600 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166C822 +P 5950 2400 +F 0 "R1" V 6030 2400 50 0000 C CNN +F 1 "4700" V 5950 2400 50 0000 C CNN + 1 5950 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5166C7EC +P 5950 5100 +F 0 "R2" V 6030 5100 50 0000 C CNN +F 1 "3300" V 5950 5100 50 0000 C CNN + 1 5950 5100 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5166C79C +P 6350 3750 +F 0 "v1" H 6150 3850 60 0000 C CNN +F 1 "10V" H 6150 3700 60 0000 C CNN +F 2 "R1" H 6050 3750 60 0000 C CNN + 1 6350 3750 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5166C72A +P 5850 3850 +F 0 "Q1" H 5850 3700 50 0000 R CNN +F 1 "NPN" H 5850 4000 50 0000 R CNN + 1 5850 3850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/npn.lib new file mode 100644 index 0000000..f84808e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.6/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=1.7 Cjc=7.306p Nc=2 Tr=46.91n Ne=1.307 ++ Cje=22.01p Isc=0 Xtb=1.5 Rb=10 Rc=1 ++ Tf=411.1p Xti=3 Ikr=0 Bf=400 Fc=.5 ++ Ise=14.34f Br=6.092 Ikf=.2847 Mje=.377 Mjc=.3416 ++ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=3 Itf=.6 ++ Is=14.34f Eg=1.11 )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/analysis new file mode 100644 index 0000000..35318bb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.bak new file mode 100644 index 0000000..1c7c96a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 08:09:14 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.lib new file mode 100644 index 0000000..0acf0b6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 08:10:59 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.bak new file mode 100644 index 0000000..ca1bf82 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.bak @@ -0,0 +1,172 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 08:09:14 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5050 4700 +Connection ~ 5050 3500 +Connection ~ 4500 5050 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C10CC +P 4500 5050 +F 0 "#FLG01" H 4500 5320 30 0001 C CNN +F 1 "PWR_FLAG" H 4500 5280 30 0000 C CNN + 1 4500 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C10B9 +P 4450 5350 +F 0 "#PWR02" H 4450 5350 30 0001 C CNN +F 1 "GND" H 4450 5280 30 0001 C CNN + 1 4450 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 5350 4500 5350 +Wire Wire Line + 4500 5350 4500 3750 +Wire Wire Line + 4500 3750 4750 3750 +Wire Wire Line + 5050 4550 5050 4850 +Wire Wire Line + 5050 5350 5650 5350 +Wire Wire Line + 5050 3450 5050 3550 +Wire Wire Line + 5050 2850 5050 2950 +Wire Wire Line + 5050 3950 5050 4050 +Wire Wire Line + 5050 2350 5650 2350 +Wire Wire Line + 5650 2350 5650 3200 +Wire Wire Line + 5650 5350 5650 4100 +$Comp +L VPLOT8_1 U3 +U 2 1 516C107A +P 5350 4700 +F 0 "U3" H 5200 4800 50 0000 C CNN +F 1 "VPLOT8_1" H 5500 4800 50 0000 C CNN + 2 5350 4700 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C103D +P 5650 3650 +F 0 "v1" H 5450 3750 60 0000 C CNN +F 1 "DC" H 5450 3600 60 0000 C CNN +F 2 "R1" H 5350 3650 60 0000 C CNN + 1 5650 3650 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516C1001 +P 5350 3500 +F 0 "U3" H 5200 3600 50 0000 C CNN +F 1 "VPLOT8_1" H 5500 3600 50 0000 C CNN + 1 5350 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516C0FB5 +P 5050 5100 +F 0 "R2" V 5130 5100 50 0000 C CNN +F 1 "R" V 5050 5100 50 0000 C CNN + 1 5050 5100 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C0FAB +P 5050 4300 +F 0 "U2" H 4900 4400 50 0000 C CNN +F 1 "IPLOT" H 5200 4400 50 0000 C CNN + 1 5050 4300 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516C0F0F +P 5050 3200 +F 0 "U1" H 4900 3300 50 0000 C CNN +F 1 "IPLOT" H 5200 3300 50 0000 C CNN + 1 5050 3200 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 516C0F01 +P 5050 2600 +F 0 "R1" V 5130 2600 50 0000 C CNN +F 1 "R" V 5050 2600 50 0000 C CNN + 1 5050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q1 +U 1 1 516C0EEC +P 4950 3750 +F 0 "Q1" H 4950 3600 60 0000 R CNN +F 1 "PNP" H 4950 3900 60 0000 R CNN + 1 4950 3750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir new file mode 100644 index 0000000..7d111e3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 08:10:56 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 4 6 VPLOT8_1 +v1 3 5 10 +R2 6 3 2000 +U2 6 2 IPLOT +U1 4 1 IPLOT +R1 5 1 1000 +Q1 2 0 4 PNP + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.ckt new file mode 100644 index 0000000..d569e7a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:10:56 pm ist + +* Plotting option vplot8_1 +v1 3 5 10 +r2 6 3 2000 +V_u2 6 2 0 +V_u1 4 1 0 +r1 5 1 1000 +q1 4 0 2 pnp + +.dc v1 0e-00 10e-00 5e-03 +.plot v(4) v(6) +.plot i(V_u2) +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.out new file mode 100644 index 0000000..946ba9b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:10:56 pm ist + +* Plotting option vplot8_1 +v1 3 5 10 +r2 6 3 2000 +V_u2 6 2 0 +V_u1 4 1 0 +r1 5 1 1000 +q1 4 0 2 pnp + +.dc v1 0e-00 10e-00 5e-03 + +* Control Statements +.control +run +plot v(4) v(6) +plot i(V_u2) +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.pro new file mode 100644 index 0000000..7b4f272 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.pro @@ -0,0 +1,74 @@ +update=Monday 15 April 2013 07:58:37 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.proj new file mode 100644 index 0000000..b07d448 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.proj @@ -0,0 +1 @@ +schematicFile example_3.7.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.sch new file mode 100644 index 0000000..c9780ef --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.7/example_3.7.sch @@ -0,0 +1,173 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 08:10:59 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.7-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5050 4700 +Connection ~ 5050 3500 +Connection ~ 4500 5050 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C10CC +P 4500 5050 +F 0 "#FLG01" H 4500 5320 30 0001 C CNN +F 1 "PWR_FLAG" H 4500 5280 30 0000 C CNN + 1 4500 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C10B9 +P 4450 5350 +F 0 "#PWR02" H 4450 5350 30 0001 C CNN +F 1 "GND" H 4450 5280 30 0001 C CNN + 1 4450 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 5350 4500 5350 +Wire Wire Line + 4500 5350 4500 3750 +Wire Wire Line + 4500 3750 4750 3750 +Wire Wire Line + 5050 4550 5050 4850 +Wire Wire Line + 5050 5350 5650 5350 +Wire Wire Line + 5050 3450 5050 3550 +Wire Wire Line + 5050 2850 5050 2950 +Wire Wire Line + 5050 3950 5050 4050 +Wire Wire Line + 5050 2350 5650 2350 +Wire Wire Line + 5650 2350 5650 3200 +Wire Wire Line + 5650 5350 5650 4100 +$Comp +L VPLOT8_1 U3 +U 2 1 516C107A +P 5350 4700 +F 0 "U3" H 5200 4800 50 0000 C CNN +F 1 "VPLOT8_1" H 5500 4800 50 0000 C CNN + 2 5350 4700 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C103D +P 5650 3650 +F 0 "v1" H 5450 3750 60 0000 C CNN +F 1 "10" H 5450 3600 60 0000 C CNN +F 2 "R1" H 5350 3650 60 0000 C CNN + 1 5650 3650 + 1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516C1001 +P 5350 3500 +F 0 "U3" H 5200 3600 50 0000 C CNN +F 1 "VPLOT8_1" H 5500 3600 50 0000 C CNN + 1 5350 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516C0FB5 +P 5050 5100 +F 0 "R2" V 5130 5100 50 0000 C CNN +F 1 "2000" V 5050 5100 50 0000 C CNN + 1 5050 5100 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C0FAB +P 5050 4300 +F 0 "U2" H 4900 4400 50 0000 C CNN +F 1 "IPLOT" H 5200 4400 50 0000 C CNN + 1 5050 4300 + 0 -1 -1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516C0F0F +P 5050 3200 +F 0 "U1" H 4900 3300 50 0000 C CNN +F 1 "IPLOT" H 5200 3300 50 0000 C CNN + 1 5050 3200 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 516C0F01 +P 5050 2600 +F 0 "R1" V 5130 2600 50 0000 C CNN +F 1 "1000" V 5050 2600 50 0000 C CNN + 1 5050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q1 +U 1 1 516C0EEC +P 4950 3750 +F 0 "Q1" H 4950 3600 60 0000 R CNN +F 1 "PNP" H 4950 3900 60 0000 R CNN + 1 4950 3750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/analysis new file mode 100644 index 0000000..7946c35 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8-cache.lib new file mode 100644 index 0000000..c582dbc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 08:58:27 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir new file mode 100644 index 0000000..073dc21 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 08:58:23 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 3 0 5V +v2 2 0 10V +R1 6 3 100 +U3 1 4 VPLOT8_1 +U2 0 4 IPLOT +U1 1 5 IPLOT +R2 2 5 2000 +Q1 4 6 1 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.ckt new file mode 100644 index 0000000..bf04d00 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.ckt @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:58:23 pm ist + +v1 3 0 5v +v2 2 0 10v +r1 6 3 100 +* Plotting option vplot8_1 +V_u2 0 4 0 +V_u1 1 5 0 +r2 2 5 2000 +q1 1 6 4 npn + +.dc v1 0e-00 5e-00 5e-03 +.plot v(1) v(4) +.plot i(V_u2) +.plot i(V_u1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.out new file mode 100644 index 0000000..4fa87ff --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.cir.out @@ -0,0 +1,21 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 08:58:23 pm ist + +v1 3 0 5v +v2 2 0 10v +r1 6 3 100 +* Plotting option vplot8_1 +V_u2 0 4 0 +V_u1 1 5 0 +r2 2 5 2000 +q1 1 6 4 npn + +.dc v1 0e-00 5e-00 5e-03 + +* Control Statements +.control +run +plot v(1) v(4) +plot i(V_u2) +plot i(V_u1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.pro new file mode 100644 index 0000000..829ea15 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.pro @@ -0,0 +1,74 @@ +update=Monday 15 April 2013 08:14:03 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.proj new file mode 100644 index 0000000..2797ff1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.proj @@ -0,0 +1 @@ +schematicFile example_3.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.sch new file mode 100644 index 0000000..f8c5751 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.8/example_3.8.sch @@ -0,0 +1,181 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 08:58:27 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5500 4450 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C1C70 +P 5500 4450 +F 0 "#FLG01" H 5500 4720 30 0001 C CNN +F 1 "PWR_FLAG" H 5500 4680 30 0000 C CNN + 1 5500 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C1C57 +P 5500 4500 +F 0 "#PWR02" H 5500 4500 30 0001 C CNN +F 1 "GND" H 5500 4430 30 0001 C CNN + 1 5500 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 4500 5500 4000 +Connection ~ 5500 4350 +Wire Wire Line + 4600 4350 6400 4350 +Wire Wire Line + 6400 2150 6400 1800 +Wire Wire Line + 6400 1800 5500 1800 +Connection ~ 5500 3450 +Connection ~ 5500 2950 +Wire Wire Line + 5500 2300 5500 2400 +Wire Wire Line + 5500 3000 5500 2900 +Wire Wire Line + 5500 3400 5500 3500 +Wire Wire Line + 5200 3200 5100 3200 +Wire Wire Line + 4600 4350 4600 4100 +Wire Wire Line + 6400 4350 6400 3050 +$Comp +L DC v1 +U 1 1 516C1BAA +P 4600 3650 +F 0 "v1" H 4400 3750 60 0000 C CNN +F 1 "5V" H 4400 3600 60 0000 C CNN +F 2 "R1" H 4300 3650 60 0000 C CNN + 1 4600 3650 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 516C1B93 +P 6400 2600 +F 0 "v2" H 6200 2700 60 0000 C CNN +F 1 "10V" H 6200 2550 60 0000 C CNN +F 2 "R1" H 6100 2600 60 0000 C CNN + 1 6400 2600 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516C130D +P 4850 3200 +F 0 "R1" V 4930 3200 50 0000 C CNN +F 1 "100" V 4850 3200 50 0000 C CNN + 1 4850 3200 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516C12F0 +P 5800 3450 +F 0 "U3" H 5650 3550 50 0000 C CNN +F 1 "VPLOT8_1" H 5950 3550 50 0000 C CNN + 2 5800 3450 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516C12D2 +P 5500 3750 +F 0 "U2" H 5350 3850 50 0000 C CNN +F 1 "IPLOT" H 5650 3850 50 0000 C CNN + 1 5500 3750 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516C128C +P 5800 2950 +F 0 "U3" H 5650 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 5950 3050 50 0000 C CNN + 1 5800 2950 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516C1282 +P 5500 2650 +F 0 "U1" H 5350 2750 50 0000 C CNN +F 1 "IPLOT" H 5650 2750 50 0000 C CNN + 1 5500 2650 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516C125F +P 5500 2050 +F 0 "R2" V 5580 2050 50 0000 C CNN +F 1 "2000" V 5500 2050 50 0000 C CNN + 1 5500 2050 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516C1252 +P 5400 3200 +F 0 "Q1" H 5400 3050 50 0000 R CNN +F 1 "NPN" H 5400 3350 50 0000 R CNN + 1 5400 3200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis new file mode 100644 index 0000000..7946c35 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak new file mode 100644 index 0000000..ab4ac6a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 15 April 2013 09:47:58 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib new file mode 100644 index 0000000..19bc1ef --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:19:52 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PNP +# +DEF PNP Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 60 H V R CNN +F1 "PNP" 0 150 60 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 F +P 3 0 1 0 25 -25 0 0 0 0 N +P 3 0 1 0 100 -100 65 -65 65 -65 N +P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak new file mode 100644 index 0000000..9b2890f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.bak @@ -0,0 +1,200 @@ +EESchema Schematic File Version 2 date Monday 15 April 2013 09:47:58 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4800 3600 4150 3600 +Wire Wire Line + 6500 2900 6500 2050 +Wire Wire Line + 6500 2050 5100 2050 +Wire Wire Line + 5100 5100 5100 5250 +Wire Wire Line + 5100 3800 5100 3950 +Wire Wire Line + 5100 3250 5100 3400 +Wire Wire Line + 5100 2650 5100 2750 +Wire Wire Line + 5100 4450 5100 4600 +Wire Wire Line + 5100 2050 5100 2150 +Connection ~ 5100 3350 +Connection ~ 5100 3900 +Wire Wire Line + 3650 3600 3650 5100 +Connection ~ 5100 2050 +Connection ~ 5100 2050 +Connection ~ 5100 2050 +Wire Wire Line + 6500 3800 6500 5250 +Wire Wire Line + 6500 5250 5100 5250 +Connection ~ 4750 3600 +Connection ~ 3650 3600 +Connection ~ 4150 3600 +Connection ~ 3950 3600 +Connection ~ 4800 3600 +Connection ~ 3650 4850 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C1E89 +P 3650 4850 +F 0 "#FLG01" H 3650 5120 30 0001 C CNN +F 1 "PWR_FLAG" H 3650 5080 30 0000 C CNN + 1 3650 4850 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516C1EFD +P 4750 3300 +F 0 "U2" H 4600 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 4900 3400 50 0000 C CNN + 1 4750 3300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C1E7B +P 3650 5100 +F 0 "#PWR02" H 3650 5100 30 0001 C CNN +F 1 "GND" H 3650 5030 30 0001 C CNN + 1 3650 5100 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516C1E56 +P 3900 3600 +F 0 "R1" V 3980 3600 50 0000 C CNN +F 1 "10000" V 3900 3600 50 0000 C CNN + 1 3900 3600 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516C1E37 +P 5400 3900 +F 0 "U2" H 5250 4000 50 0000 C CNN +F 1 "VPLOT8_1" H 5550 4000 50 0000 C CNN + 3 5400 3900 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C1E04 +P 5100 4850 +F 0 "R3" V 5180 4850 50 0000 C CNN +F 1 "10000" V 5100 4850 50 0000 C CNN + 1 5100 4850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C1DF8 +P 5100 4200 +F 0 "U4" H 4950 4300 50 0000 C CNN +F 1 "IPLOT" H 5250 4300 50 0000 C CNN + 1 5100 4200 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516C1DCB +P 5400 3350 +F 0 "U2" H 5250 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 5550 3450 50 0000 C CNN + 2 5400 3350 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C1DBD +P 6500 3350 +F 0 "v1" H 6300 3450 60 0000 C CNN +F 1 "5" H 6300 3300 60 0000 C CNN +F 2 "R1" H 6200 3350 60 0000 C CNN + 1 6500 3350 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C1DAD +P 5100 3000 +F 0 "U3" H 4950 3100 50 0000 C CNN +F 1 "IPLOT" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516C1D7F +P 5100 2400 +F 0 "R2" V 5180 2400 50 0000 C CNN +F 1 "1000" V 5100 2400 50 0000 C CNN + 1 5100 2400 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q1 +U 1 1 516C1D57 +P 5000 3600 +F 0 "Q1" H 5000 3450 60 0000 R CNN +F 1 "PNP" H 5000 3750 60 0000 R CNN + 1 5000 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir new file mode 100644 index 0000000..484dfb8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:19:49 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v2 0 4 5 +U2 2 6 3 VPLOT8_1 +R1 2 0 10000 +R3 5 4 10000 +U4 3 5 IPLOT +v1 7 0 5 +U3 8 6 IPLOT +R2 7 8 1000 +Q1 3 2 6 PNP + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt new file mode 100644 index 0000000..3c4d3e8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:19:49 pm ist + +v2 0 4 5 +* Plotting option vplot8_1 +r1 2 0 10000 +r3 5 4 10000 +V_u4 3 5 0 +v1 7 0 5 +V_u3 8 6 0 +r2 7 8 1000 +q1 6 2 3 pnp + +.dc v1 0e-00 5e-00 5e-03 +.plot v(2) v(6) v(3) +.plot i(V_u4) +.plot i(V_u3) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out new file mode 100644 index 0000000..00c3815 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:19:49 pm ist + +v2 0 4 5 +* Plotting option vplot8_1 +r1 2 0 10000 +r3 5 4 10000 +V_u4 3 5 0 +v1 7 0 5 +V_u3 8 6 0 +r2 7 8 1000 +q1 6 2 3 pnp + +.dc v1 0e-00 5e-00 5e-03 + +* Control Statements +.control +run +plot v(2) v(6) v(3) +plot i(V_u4) +plot i(V_u3) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro new file mode 100644 index 0000000..50bea06 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.pro @@ -0,0 +1,74 @@ +update=Monday 15 April 2013 09:01:17 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj new file mode 100644 index 0000000..cf438f1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.proj @@ -0,0 +1 @@ +schematicFile example_3.9.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch new file mode 100644 index 0000000..da988b4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.9/example_3.9.sch @@ -0,0 +1,221 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 01:19:52 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.9-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L GND #PWR01 +U 1 1 51909AF0 +P 6700 3550 +F 0 "#PWR01" H 6700 3550 30 0001 C CNN +F 1 "GND" H 6700 3480 30 0001 C CNN + 1 6700 3550 + 1 0 0 -1 +$EndComp +Connection ~ 6500 3550 +Wire Wire Line + 6500 3550 6700 3550 +Wire Wire Line + 4800 3600 4150 3600 +Wire Wire Line + 6500 2050 5100 2050 +Wire Wire Line + 5100 5100 5100 5250 +Wire Wire Line + 5100 3800 5100 3950 +Wire Wire Line + 5100 3250 5100 3400 +Wire Wire Line + 5100 2650 5100 2750 +Wire Wire Line + 5100 4450 5100 4600 +Wire Wire Line + 5100 2050 5100 2150 +Connection ~ 5100 3350 +Connection ~ 5100 3900 +Wire Wire Line + 3650 3600 3650 5100 +Connection ~ 5100 2050 +Connection ~ 5100 2050 +Connection ~ 5100 2050 +Wire Wire Line + 5100 5250 6500 5250 +Connection ~ 4750 3600 +Connection ~ 3650 3600 +Connection ~ 4150 3600 +Connection ~ 3950 3600 +Connection ~ 4800 3600 +Connection ~ 3650 4850 +Wire Wire Line + 6500 2950 6500 4350 +$Comp +L DC v2 +U 1 1 51909ACB +P 6500 4800 +F 0 "v2" H 6300 4900 60 0000 C CNN +F 1 "5" H 6300 4750 60 0000 C CNN +F 2 "R1" H 6200 4800 60 0000 C CNN + 1 6500 4800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516C1E89 +P 3650 4850 +F 0 "#FLG02" H 3650 5120 30 0001 C CNN +F 1 "PWR_FLAG" H 3650 5080 30 0000 C CNN + 1 3650 4850 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516C1EFD +P 4750 3300 +F 0 "U2" H 4600 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 4900 3400 50 0000 C CNN + 1 4750 3300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516C1E7B +P 3650 5100 +F 0 "#PWR03" H 3650 5100 30 0001 C CNN +F 1 "GND" H 3650 5030 30 0001 C CNN + 1 3650 5100 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516C1E56 +P 3900 3600 +F 0 "R1" V 3980 3600 50 0000 C CNN +F 1 "10000" V 3900 3600 50 0000 C CNN + 1 3900 3600 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 3 1 516C1E37 +P 5400 3900 +F 0 "U2" H 5250 4000 50 0000 C CNN +F 1 "VPLOT8_1" H 5550 4000 50 0000 C CNN + 3 5400 3900 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C1E04 +P 5100 4850 +F 0 "R3" V 5180 4850 50 0000 C CNN +F 1 "10000" V 5100 4850 50 0000 C CNN + 1 5100 4850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C1DF8 +P 5100 4200 +F 0 "U4" H 4950 4300 50 0000 C CNN +F 1 "IPLOT" H 5250 4300 50 0000 C CNN + 1 5100 4200 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516C1DCB +P 5400 3350 +F 0 "U2" H 5250 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 5550 3450 50 0000 C CNN + 2 5400 3350 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C1DBD +P 6500 2500 +F 0 "v1" H 6300 2600 60 0000 C CNN +F 1 "5" H 6300 2450 60 0000 C CNN +F 2 "R1" H 6200 2500 60 0000 C CNN + 1 6500 2500 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C1DAD +P 5100 3000 +F 0 "U3" H 4950 3100 50 0000 C CNN +F 1 "IPLOT" H 5250 3100 50 0000 C CNN + 1 5100 3000 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 516C1D7F +P 5100 2400 +F 0 "R2" V 5180 2400 50 0000 C CNN +F 1 "1000" V 5100 2400 50 0000 C CNN + 1 5100 2400 + 1 0 0 -1 +$EndComp +$Comp +L PNP Q1 +U 1 1 516C1D57 +P 5000 3600 +F 0 "Q1" H 5000 3450 60 0000 R CNN +F 1 "PNP" H 5000 3750 60 0000 R CNN + 1 5000 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/npn.lib b/OSCAD/Examples/sedra_smith/chapter_3/npn.lib new file mode 100644 index 0000000..caa3cb7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 ++ Cje=4.493p Isc=0 Xtb=1.5 Rb=10 Rc=1 ++ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 ++ Ise=6.734f Br=.7371 Ikf=66.78m Mje=.2593 Mjc=.3085 ++ Vaf=74.03 Vjc=.75 Vje=.75 Xtf=2 Itf=.4 ++ Is=6.734 Eg=1.11 )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib new file mode 100644 index 0000000..89d421d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib @@ -0,0 +1,2 @@ +.model 1n4007 D( IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1E-11 ++VJ=0.7 M=0.5 FC=0.5 TT=1E-07 KF=0 AF=1 ) diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis new file mode 100644 index 0000000..f74e3c8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt new file mode 100644 index 0000000..0552575 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt @@ -0,0 +1,22 @@ +* CD4007 NMOS and PMOS transistor SPICE models + +* Typical - Typical Condition + +.model mos_n NMOS ++ Level=1 Gamma= 0 Xj=0 ++ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=1.4 Lambda=0.01 ++ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p ++ Cgdo=0.1p Is=16.64p N=1 + +*The default W and L is 30 and 10 um respectively and AD and AS +*should not be included. + + +.model mos_p PMOS ++ Level=1 Gamma= 0 Xj=0 ++ Tox=1200n Phi=.6 Rs=0 Kp=1u Vto=-1.2 Lambda=0.04 ++ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p ++ Cgdo=0.2p Is=16.64p N=1 + +*The default W and L is 60 and 10 um respectively and AD and AS +*should not be included. diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak new file mode 100644 index 0000000..5cb1eee --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 16 May 2013 11:39:19 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N M 0 0 N Y 1 F N +F0 "M" 10 170 60 H V R CNN +F1 "MOS_N" 10 -150 60 H V R CNN +ALIAS MOSFET_N +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 8 100 -100 100 0 50 0 N +P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib new file mode 100644 index 0000000..df97081 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 16 May 2013 11:43:16 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N M 0 0 N Y 1 F N +F0 "M" 10 170 60 H V R CNN +F1 "MOS_N" 10 -150 60 H V R CNN +ALIAS MOSFET_N +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 8 100 -100 100 0 50 0 N +P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak new file mode 100644 index 0000000..c4bf9b0 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak @@ -0,0 +1,214 @@ +EESchema Schematic File Version 2 date Thursday 16 May 2013 11:39:19 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_4.5-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6600 3650 +$Comp +L VPLOT8_1 U4 +U 2 1 519477A9 +P 6900 3650 +F 0 "U4" H 6750 3750 50 0000 C CNN +F 1 "VPLOT8_1" H 7050 3750 50 0000 C CNN + 2 6900 3650 + 0 1 1 0 +$EndComp +Wire Wire Line + 6600 4350 6600 4700 +Wire Wire Line + 5800 5500 5800 5550 +Wire Wire Line + 6600 2700 6600 3000 +Connection ~ 5800 5500 +Wire Wire Line + 5000 2850 5000 850 +Connection ~ 5700 850 +Wire Wire Line + 5000 850 6600 850 +Connection ~ 5700 3200 +Wire Wire Line + 5700 5500 5700 5200 +Wire Wire Line + 5700 1200 5700 850 +Wire Wire Line + 6600 850 6600 1200 +Wire Wire Line + 6600 5200 6600 5500 +Wire Wire Line + 6300 3200 5700 3200 +Connection ~ 5700 3200 +Connection ~ 6600 2850 +Connection ~ 6600 850 +Connection ~ 6600 5500 +Wire Wire Line + 5700 4700 5700 1700 +Wire Wire Line + 6600 5500 5000 5500 +Connection ~ 5700 5500 +Wire Wire Line + 5000 5500 5000 3750 +Wire Wire Line + 6600 1700 6600 2200 +Wire Wire Line + 6600 3400 6600 3800 +$Comp +L IPLOT U2 +U 1 1 51947793 +P 6600 4050 +F 0 "U2" H 6450 4150 50 0000 C CNN +F 1 "IPLOT" H 6750 4150 50 0000 C CNN + 1 6600 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 518B75C0 +P 6600 2450 +F 0 "U1" H 6450 2550 50 0000 C CNN +F 1 "IPLOT" H 6750 2550 50 0000 C CNN + 1 6600 2450 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U4 +U 1 1 518B74B3 +P 6000 3200 +F 0 "U4" H 5850 3300 50 0000 C CNN +F 1 "VPLOT8_1" H 6150 3300 50 0000 C CNN + 1 6000 3200 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 517A3B91 +P 5800 5550 +F 0 "#PWR01" H 5800 5550 30 0001 C CNN +F 1 "GND" H 5800 5480 30 0001 C CNN + 1 5800 5550 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 517A3B8C +P 5800 5500 +F 0 "#FLG02" H 5800 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5800 5730 30 0000 C CNN + 1 5800 5500 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 517A3ABD +P 5000 3300 +F 0 "v1" H 4800 3400 60 0000 C CNN +F 1 "10" H 4800 3250 60 0000 C CNN +F 2 "R1" H 4700 3300 60 0000 C CNN + 1 5000 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516BA47D +P 6900 2850 +F 0 "U3" H 6750 2950 50 0000 C CNN +F 1 "VPLOT8_1" H 7050 2950 50 0000 C CNN + 1 6900 2850 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5166F1C0 +P 5700 4950 +F 0 "R2" V 5780 4950 50 0000 C CNN +F 1 "10M" V 5700 4950 50 0000 C CNN + 1 5700 4950 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166F1AE +P 5700 1450 +F 0 "R1" V 5780 1450 50 0000 C CNN +F 1 "10M" V 5700 1450 50 0000 C CNN + 1 5700 1450 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5166F187 +P 6600 4950 +F 0 "R4" V 6680 4950 50 0000 C CNN +F 1 "6k" V 6600 4950 50 0000 C CNN + 1 6600 4950 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5166F163 +P 6600 1450 +F 0 "R3" V 6680 1450 50 0000 C CNN +F 1 "6k" V 6600 1450 50 0000 C CNN + 1 6600 1450 + 1 0 0 -1 +$EndComp +$Comp +L MOS_N M1 +U 1 1 5166F12C +P 6500 3200 +F 0 "M1" H 6510 3370 60 0000 R CNN +F 1 "MOS_N" H 6510 3050 60 0000 R CNN + 1 6500 3200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir new file mode 100644 index 0000000..4a904e0 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 16 May 2013 11:43:12 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U4 6 7 VPLOT8_1 +U2 7 4 IPLOT +U1 5 1 IPLOT +v1 3 0 10 +U3 1 VPLOT8_1 +R2 6 0 10M +R1 3 6 10M +R4 4 0 6k +R3 3 5 6k +M1 1 6 7 MOS_N + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt new file mode 100644 index 0000000..68ce4e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:43:12 am ist + +* Plotting option vplot8_1 +V_u2 7 4 0 +V_u1 5 1 0 +v1 3 0 10 +* Plotting option vplot8_1 +r2 6 0 10m +r1 3 6 10m +r4 4 0 6k +r3 3 5 6k +m1 1 6 7 mos_n + +.dc v1 0e-00 10e-00 1e-00 +.plot v(6) v(7) +.plot i(V_u2) +.plot i(V_u1) +.plot v(1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out new file mode 100644 index 0000000..b363435 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out @@ -0,0 +1,24 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:43:12 am ist + +* Plotting option vplot8_1 +V_u2 7 4 0 +V_u1 5 1 0 +v1 3 0 10 +* Plotting option vplot8_1 +r2 6 0 10m +r1 3 6 10m +r4 4 0 6k +r3 3 5 6k +m1 1 6 7 mos_n + +.dc v1 0e-00 10e-00 1e-00 + +* Control Statements +.control +run +plot v(6) v(7) +plot i(V_u2) +plot i(V_u1) +plot v(1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro new file mode 100644 index 0000000..2585a32 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro @@ -0,0 +1,84 @@ +update=Tuesday 07 May 2013 02:38:55 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj new file mode 100644 index 0000000..2320ec1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj @@ -0,0 +1 @@ +schematicFile example_4.5.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch new file mode 100644 index 0000000..a1406f4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch @@ -0,0 +1,214 @@ +EESchema Schematic File Version 2 date Thursday 16 May 2013 11:43:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_4.5-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6600 4300 6600 4700 +Wire Wire Line + 6600 3400 6600 3800 +Wire Wire Line + 6600 1700 6600 2200 +Wire Wire Line + 5000 3750 5000 5500 +Connection ~ 5700 5500 +Wire Wire Line + 5000 5500 6600 5500 +Wire Wire Line + 5700 4700 5700 1700 +Connection ~ 6600 5500 +Connection ~ 6600 850 +Connection ~ 6600 2850 +Connection ~ 5700 3200 +Wire Wire Line + 6300 3200 5700 3200 +Wire Wire Line + 6600 5500 6600 5200 +Wire Wire Line + 6600 1200 6600 850 +Wire Wire Line + 5700 1200 5700 850 +Wire Wire Line + 5700 5500 5700 5200 +Connection ~ 5700 3200 +Wire Wire Line + 6600 850 5000 850 +Connection ~ 5700 850 +Wire Wire Line + 5000 850 5000 2850 +Connection ~ 5800 5500 +Wire Wire Line + 6600 2700 6600 3000 +Wire Wire Line + 5800 5500 5800 5550 +Connection ~ 6600 3650 +$Comp +L VPLOT8_1 U4 +U 2 1 519477A9 +P 6900 3650 +F 0 "U4" H 6750 3750 50 0000 C CNN +F 1 "VPLOT8_1" H 7050 3750 50 0000 C CNN + 2 6900 3650 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 51947793 +P 6600 4050 +F 0 "U2" H 6450 4150 50 0000 C CNN +F 1 "IPLOT" H 6750 4150 50 0000 C CNN + 1 6600 4050 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U1 +U 1 1 518B75C0 +P 6600 2450 +F 0 "U1" H 6450 2550 50 0000 C CNN +F 1 "IPLOT" H 6750 2550 50 0000 C CNN + 1 6600 2450 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U4 +U 1 1 518B74B3 +P 6000 3200 +F 0 "U4" H 5850 3300 50 0000 C CNN +F 1 "VPLOT8_1" H 6150 3300 50 0000 C CNN + 1 6000 3200 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 517A3B91 +P 5800 5550 +F 0 "#PWR01" H 5800 5550 30 0001 C CNN +F 1 "GND" H 5800 5480 30 0001 C CNN + 1 5800 5550 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 517A3B8C +P 5800 5500 +F 0 "#FLG02" H 5800 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5800 5730 30 0000 C CNN + 1 5800 5500 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 517A3ABD +P 5000 3300 +F 0 "v1" H 4800 3400 60 0000 C CNN +F 1 "10" H 4800 3250 60 0000 C CNN +F 2 "R1" H 4700 3300 60 0000 C CNN + 1 5000 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516BA47D +P 6900 2850 +F 0 "U3" H 6750 2950 50 0000 C CNN +F 1 "VPLOT8_1" H 7050 2950 50 0000 C CNN + 1 6900 2850 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5166F1C0 +P 5700 4950 +F 0 "R2" V 5780 4950 50 0000 C CNN +F 1 "10M" V 5700 4950 50 0000 C CNN + 1 5700 4950 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5166F1AE +P 5700 1450 +F 0 "R1" V 5780 1450 50 0000 C CNN +F 1 "10M" V 5700 1450 50 0000 C CNN + 1 5700 1450 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5166F187 +P 6600 4950 +F 0 "R4" V 6680 4950 50 0000 C CNN +F 1 "6k" V 6600 4950 50 0000 C CNN + 1 6600 4950 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5166F163 +P 6600 1450 +F 0 "R3" V 6680 1450 50 0000 C CNN +F 1 "6k" V 6600 1450 50 0000 C CNN + 1 6600 1450 + 1 0 0 -1 +$EndComp +$Comp +L MOS_N M1 +U 1 1 5166F12C +P 6500 3200 +F 0 "M1" H 6510 3370 60 0000 R CNN +F 1 "MOS_N" H 6510 3050 60 0000 R CNN + 1 6500 3200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis new file mode 100644 index 0000000..1665db7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 100e-03 100e-06 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak new file mode 100644 index 0000000..7a3e4b4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 09 May 2013 05:04:50 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# LM741 +# +DEF LM741 U 0 20 Y Y 1 F N +F0 "U" 150 150 60 H V C CNN +F1 "LM741" 150 250 60 H V C CNN +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X ~ 1 0 -400 300 U 40 40 1 1 I +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X V- 4 -100 -400 250 U 40 40 1 1 I +X ~ 5 100 -400 350 U 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +X V+ 7 -100 400 250 D 40 40 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib new file mode 100644 index 0000000..5b4c901 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 10:18:21 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak new file mode 100644 index 0000000..abf9a53 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak @@ -0,0 +1,181 @@ +EESchema Schematic File Version 2 date Thursday 09 May 2013 05:04:50 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LM741 U? +U 1 1 518B89AE +P 8800 3550 +F 0 "U?" H 8950 3700 60 0000 C CNN +F 1 "LM741" H 8950 3800 60 0000 C CNN + 1 8800 3550 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X? +U 1 1 518B899E +P 9050 2450 +F 0 "X?" H 9200 2600 60 0000 C CNN +F 1 "UA741" H 9200 2700 60 0000 C CNN + 1 9050 2450 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 516F84E1 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7150 3300 6350 3300 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6900 2400 7050 2400 +Wire Wire Line + 7050 2400 7050 3300 +Wire Wire Line + 6400 2400 5800 2400 +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7050 3600 +F 0 "U3" H 6900 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN + 1 7050 3600 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6650 2400 +F 0 "R2" V 6730 2400 50 0000 C CNN +F 1 "10000" V 6650 2400 50 0000 C CNN + 1 6650 2400 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir new file mode 100644 index 0000000..d11b7e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir @@ -0,0 +1,24 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:42:46 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 4 0 PULSE +v2 11 0 10V +U3 8 3 VPLOT8_1 +R5 13 3 10000 +R4 0 13 10000 +R3 1 11 10000 +U5 8 2 IPLOT +Q2 1 1 2 NPN +X2 1 13 3 UA741 +U4 10 8 IPLOT +Q1 10 0 9 NPN +U1 6 7 IPLOT +U2 7 9 IPLOT +R2 8 5 10000 +R1 6 4 1000 +X1 7 0 5 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt new file mode 100644 index 0000000..db0e45e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist +.include ua741.sub + +* Plotting option vplot8_1 +V_u1 6 5 0 +V_u2 5 4 0 +r2 1 4 100000 +v1 3 0 100m +r1 6 3 1000 +x1 5 0 1 ua741 + +.dc v1 0e-00 100e-03 100e-06 +.plot v(1) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out new file mode 100644 index 0000000..d01be76 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out @@ -0,0 +1,21 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist +.include ua741.sub + +* Plotting option vplot8_1 +V_u1 6 5 0 +V_u2 5 4 0 +r2 1 4 100000 +v1 3 0 100m +r1 6 3 1000 +x1 5 0 1 ua741 + +.dc v1 0e-00 100e-03 100e-06 + +* Control Statements +.control +run +plot v(1) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net new file mode 100644 index 0000000..6696e60 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net @@ -0,0 +1,76 @@ +# EESchema Netlist Version 1.1 created Thursday 18 April 2013 11:00:24 AM IST +( + ( /516F84E1 R1 v1 SINE {Lib=SINE} + ( 1 N-000005 ) + ( 2 GND ) + ) + ( /516D117B $noname U3 VPLOT8_1 {Lib=VPLOT8_1} + ( 1 N-000004 ) + ) + ( /516D1019 $noname U1 IPLOT {Lib=IPLOT} + ( 1 N-000002 ) + ( 2 N-000003 ) + ) + ( /516D0FEC $noname U2 IPLOT {Lib=IPLOT} + ( 1 N-000003 ) + ( 2 N-000001 ) + ) + ( /516D0FE2 $noname R2 10000 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000001 ) + ) + ( /516D0F10 $noname R1 1000 {Lib=R} + ( 1 N-000002 ) + ( 2 N-000005 ) + ) + ( /516D0E60 $noname X1 UA741 {Lib=UA741} + ( 2 N-000003 ) + ( 3 GND ) + ( 6 N-000004 ) + ) +) +* +{ Allowed footprints by component: +$component v1 + 1_pin +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component X1 + DIP-8__300 +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R2 2 + U2 2 +Net 2 "" "" + R1 1 + U1 1 +Net 3 "" "" + X1 2 + U2 1 + U1 2 +Net 4 "" "" + U3 1 + R2 1 + X1 6 +Net 5 "" "" + v1 1 + R1 2 +Net 6 "GND" "GND" + X1 3 + v1 2 +} +#End diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro new file mode 100644 index 0000000..2d33bde --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 02:06:21 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj new file mode 100644 index 0000000..fb6ad90 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj @@ -0,0 +1 @@ +schematicFile example_5.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch new file mode 100644 index 0000000..9267154 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch @@ -0,0 +1,163 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 10:18:21 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SINE v1 +U 1 1 516F84E1 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7150 3300 6350 3300 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6900 2400 7050 2400 +Wire Wire Line + 7050 2400 7050 3300 +Wire Wire Line + 6400 2400 5800 2400 +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7050 3600 +F 0 "U3" H 6900 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN + 1 7050 3600 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6650 2400 +F 0 "R2" V 6730 2400 50 0000 C CNN +F 1 "10000" V 6650 2400 50 0000 C CNN + 1 6650 2400 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib new file mode 100644 index 0000000..e9ec641 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 02:55:26 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro new file mode 100644 index 0000000..46bdf8d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro @@ -0,0 +1,82 @@ +update=Tuesday 16 April 2013 02:56:39 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis new file mode 100644 index 0000000..63f4a40 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/analysis @@ -0,0 +1,8 @@ + +.ac lin 20 1Hz 10Meg + + +.end +.control +run +.endc diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak new file mode 100644 index 0000000..3c7e9ce --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.bak @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 12 May 2013 08:39:09 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib new file mode 100644 index 0000000..1541b6a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 01:50:16 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak new file mode 100644 index 0000000..7d24c57 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.bak @@ -0,0 +1,143 @@ +EESchema Schematic File Version 2 date Sunday 12 May 2013 08:39:09 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.10-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "12 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5200 3800 +$Comp +L VPLOT8_1 U1 +U 1 1 51877E04 +P 5200 4100 +F 0 "U1" H 5050 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 5350 4200 50 0000 C CNN + 1 5200 4100 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 51877DFD +P 6500 3400 +F 0 "U1" H 6350 3500 50 0000 C CNN +F 1 "VPLOT8_1" H 6650 3500 50 0000 C CNN + 2 6500 3400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51877DEF +P 4850 4700 +F 0 "#FLG01" H 4850 4970 30 0001 C CNN +F 1 "PWR_FLAG" H 4850 4930 30 0000 C CNN + 1 4850 4700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 51877DE4 +P 4850 4850 +F 0 "#PWR02" H 4850 4850 30 0001 C CNN +F 1 "GND" H 4850 4780 30 0001 C CNN + 1 4850 4850 + 1 0 0 -1 +$EndComp +Connection ~ 4850 4700 +Wire Wire Line + 4850 4700 4850 4850 +Connection ~ 6350 3700 +Wire Wire Line + 6500 3700 6250 3700 +Wire Wire Line + 5050 3800 5250 3800 +Wire Wire Line + 5250 3600 5050 3600 +Wire Wire Line + 5150 3600 5150 3200 +Connection ~ 5150 3600 +Wire Wire Line + 5150 3200 6350 3200 +Wire Wire Line + 6350 3200 6350 3700 +Wire Wire Line + 4550 3600 4550 4700 +Wire Wire Line + 4550 4700 5050 4700 +$Comp +L AC V1 +U 1 1 51877DB5 +P 5050 4250 +F 0 "V1" H 4850 4350 60 0000 C CNN +F 1 "AC" H 4850 4200 60 0000 C CNN +F 2 "R1" H 4750 4250 60 0000 C CNN + 1 5050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51877DA4 +P 4800 3600 +F 0 "R1" V 4880 3600 50 0000 C CNN +F 1 "R" V 4800 3600 50 0000 C CNN + 1 4800 3600 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 51877D93 +P 5750 3700 +F 0 "X1" H 5900 3850 60 0000 C CNN +F 1 "UA741" H 5900 3950 60 0000 C CNN + 1 5750 3700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir new file mode 100644 index 0000000..103691f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 01:50:12 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R2 1 4 100k +U1 3 1 VPLOT8_1 +V1 3 0 AC +R1 4 0 1k +X1 3 4 1 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt new file mode 100644 index 0000000..b3db0c4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.ckt @@ -0,0 +1,12 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:50:12 pm ist +.include ua741.sub + +r2 1 4 100k +* Plotting option vplot8_1 +v1 3 0 ac 1 +r1 4 0 1k +x1 3 4 1 ua741 + +.ac lin 10 1Hz 1Meg +.plot v(3) v(1) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out new file mode 100644 index 0000000..3554667 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.cir.out @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 01:50:12 pm ist +.include ua741.sub + +r2 1 4 100k +* Plotting option vplot8_1 +v1 3 0 ac 1 +r1 4 0 1k +x1 3 4 1 ua741 + +.ac lin 10 1Hz 1Meg + +* Control Statements +.control +run +plot v(3) v(1) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro new file mode 100644 index 0000000..77913bc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.pro @@ -0,0 +1,74 @@ +update=Monday 06 May 2013 03:19:21 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.proj new file mode 100644 index 0000000..81a471e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.proj @@ -0,0 +1 @@ +schematicFile example_5.10.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.sch new file mode 100644 index 0000000..8601e68 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/example_5.10.sch @@ -0,0 +1,154 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 01:50:16 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.10-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 6000 3200 6350 3200 +Connection ~ 5200 3800 +Connection ~ 4850 4700 +Wire Wire Line + 4850 4700 4850 4850 +Connection ~ 6350 3700 +Wire Wire Line + 6500 3700 6250 3700 +Wire Wire Line + 5050 3800 5250 3800 +Wire Wire Line + 5250 3600 5050 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4850 4850 + 1 0 0 -1 +$EndComp +$Comp +L AC V1 +U 1 1 51877DB5 +P 5050 4250 +F 0 "V1" H 4850 4350 60 0000 C CNN +F 1 "AC" H 4850 4200 60 0000 C CNN +F 2 "R1" H 4750 4250 60 0000 C CNN + 1 5050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51877DA4 +P 4800 3600 +F 0 "R1" V 4880 3600 50 0000 C CNN +F 1 "1k" V 4800 3600 50 0000 C CNN + 1 4800 3600 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 51877D93 +P 5750 3700 +F 0 "X1" H 5900 3850 60 0000 C CNN +F 1 "UA741" H 5900 3950 60 0000 C CNN + 1 5750 3700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak new file mode 100644 index 0000000..696ddb5 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.bak @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 07 May 2013 04:32:37 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib new file mode 100644 index 0000000..4ffd70b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 08 May 2013 02:27:06 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" -200 100 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro new file mode 100644 index 0000000..e55b2df --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.pro @@ -0,0 +1,82 @@ +update=Sunday 12 May 2013 08:34:27 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.10/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis new file mode 100644 index 0000000..7946c35 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib new file mode 100644 index 0000000..40f51d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 03:05:48 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak new file mode 100644 index 0000000..9eb4b13 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.bak @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 02:59:48 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6400 3350 6400 2950 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5300 2950 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Connection ~ 6400 3300 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Wire Wire Line + 6350 3300 6400 3300 +Connection ~ 6350 3300 +Connection ~ 6400 3350 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 6700 3350 +F 0 "U3" H 6550 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 6850 3450 50 0000 C CNN + 1 6700 3350 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "100000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "100m" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir new file mode 100644 index 0000000..b0ee189 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir @@ -0,0 +1,19 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 03:05:45 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 3 8 IPLOT +U4 2 VPLOT8_1 +R3 0 2 100000 +R4 3 2 100000 +U3 8 VPLOT8_1 +U1 6 4 IPLOT +U2 4 5 IPLOT +R2 2 5 100000 +v1 7 0 100m +R1 6 7 1000 +X1 4 0 8 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt new file mode 100644 index 0000000..ea512f4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.ckt @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 03:05:45 pm ist +.include ua741.sub + +V_u5 3 8 0 +* Plotting option vplot8_1 +r3 0 2 100000 +r4 3 2 100000 +* Plotting option vplot8_1 +V_u1 6 4 0 +V_u2 4 5 0 +r2 2 5 100000 +v1 7 0 100m +r1 6 7 1000 +x1 4 0 8 ua741 + +.dc v1 0e-00 5e-00 5e-03 +.plot i(V_u5) +.plot v(2) +.plot v(8) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out new file mode 100644 index 0000000..fdcc306 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.cir.out @@ -0,0 +1,27 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 03:05:45 pm ist +.include ua741.sub + +V_u5 3 8 0 +* Plotting option vplot8_1 +r3 0 2 100000 +r4 3 2 100000 +* Plotting option vplot8_1 +V_u1 6 4 0 +V_u2 4 5 0 +r2 2 5 100000 +v1 7 0 100m +r1 6 7 1000 +x1 4 0 8 ua741 + +.dc v1 0e-00 5e-00 5e-03 + +* Control Statements +.control +run +plot i(V_u5) +plot v(2) +plot v(8) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro new file mode 100644 index 0000000..4197879 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 02:59:20 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj new file mode 100644 index 0000000..e56c1d2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.proj @@ -0,0 +1 @@ +schematicFile example_5.2.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch new file mode 100644 index 0000000..5dbaecc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/example_5.2.sch @@ -0,0 +1,224 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 03:05:48 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7000 3000 7000 3350 +Connection ~ 7000 2400 +Connection ~ 6450 2500 +Connection ~ 6450 2400 +Wire Wire Line + 6350 3300 7000 3300 +Wire Wire Line + 6450 2900 6450 3000 +Connection ~ 7000 3350 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2400 5800 2400 +Connection ~ 7000 3300 +Wire Wire Line + 5350 3200 5250 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6400 2400 6500 2400 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 7000 2400 7000 2500 +$Comp +L IPLOT U5 +U 1 1 516D1AB3 +P 7000 2750 +F 0 "U5" H 6850 2850 50 0000 C CNN +F 1 "IPLOT" H 7150 2850 50 0000 C CNN + 1 7000 2750 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U4 +U 1 1 516D1A8F +P 6450 2100 +F 0 "U4" H 6300 2200 50 0000 C CNN +F 1 "VPLOT8_1" H 6600 2200 50 0000 C CNN + 1 6450 2100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 516D1A5C +P 6450 3000 +F 0 "#PWR01" H 6450 3000 30 0001 C CNN +F 1 "GND" H 6450 2930 30 0001 C CNN + 1 6450 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 516D1A47 +P 6450 2650 +F 0 "R3" V 6530 2650 50 0000 C CNN +F 1 "100000" V 6450 2650 50 0000 C CNN + 1 6450 2650 + -1 0 0 1 +$EndComp +$Comp +L R R4 +U 1 1 516D1A3E +P 6750 2400 +F 0 "R4" V 6830 2400 50 0000 C CNN +F 1 "100000" V 6750 2400 50 0000 C CNN + 1 6750 2400 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG02" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7300 3350 +F 0 "U3" H 7150 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 7450 3450 50 0000 C CNN + 1 7300 3350 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG03" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2400 +F 0 "R2" V 6230 2400 50 0000 C CNN +F 1 "100000" V 6150 2400 50 0000 C CNN + 1 6150 2400 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "100m" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR04" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro new file mode 100644 index 0000000..34303c7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.pro @@ -0,0 +1,82 @@ +update=Tuesday 16 April 2013 03:06:44 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.2/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis new file mode 100644 index 0000000..7946c35 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak new file mode 100644 index 0000000..e6f6afe --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.bak @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 09:35:11 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib new file mode 100644 index 0000000..4daeb80 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 21 May 2013 11:13:50 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak new file mode 100644 index 0000000..d0ef6de --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.bak @@ -0,0 +1,182 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 09:35:11 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7050 3300 7050 2950 +Wire Wire Line + 6450 3300 6350 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 3400 5350 4200 +Connection ~ 5300 3200 +Wire Wire Line + 5300 2950 5300 3200 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 3300 6950 3300 +Wire Wire Line + 7050 2950 6400 2950 +$Comp +L R R3 +U 1 1 516D1D5E +P 6700 3300 +F 0 "R3" V 6780 3300 50 0000 C CNN +F 1 "100k" V 6700 3300 50 0000 C CNN + 1 6700 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "1000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "10" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir new file mode 100644 index 0000000..25f7e67 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 09:29:30 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 1 7 100k +U3 1 VPLOT8_1 +U1 5 2 IPLOT +U2 2 3 IPLOT +R2 1 3 1000 +v1 6 0 10 +R1 5 6 10 +X1 2 0 7 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt new file mode 100644 index 0000000..5cc8d66 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 09:29:30 pm ist +.include ua741.sub + +r3 1 7 100k +* Plotting option vplot8_1 +V_u1 5 2 0 +V_u2 2 3 0 +r2 1 3 1000 +v1 6 0 10 +r1 5 6 10 +x1 2 0 7 ua741 + +.dc v1 0e-00 5e-00 5e-03 +.plot v(1) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out new file mode 100644 index 0000000..1d3b745 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 09:29:30 pm ist +.include ua741.sub + +r3 1 7 100k +* Plotting option vplot8_1 +V_u1 5 2 0 +V_u2 2 3 0 +r2 1 3 1000 +v1 6 0 10 +r1 5 6 10 +x1 2 0 7 ua741 + +.dc v1 0e-00 5e-00 5e-03 + +* Control Statements +.control +run +plot v(1) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro new file mode 100644 index 0000000..68ef472 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 03:20:48 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj new file mode 100644 index 0000000..36f23a8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.proj @@ -0,0 +1 @@ +schematicFile example_5.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch new file mode 100644 index 0000000..a549a57 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/example_5.3.sch @@ -0,0 +1,183 @@ +EESchema Schematic File Version 2 date Tuesday 21 May 2013 11:13:50 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 7050 3300 7050 2950 +Wire Wire Line + 6450 3300 6350 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 3400 5350 4200 +Connection ~ 5300 3200 +Wire Wire Line + 5300 2950 5300 3200 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 3300 6950 3300 +Wire Wire Line + 7050 2950 6400 2950 +$Comp +L R RL +U 1 1 516D1D5E +P 6700 3300 +F 0 "RL" V 6780 3300 50 0000 C CNN +F 1 "100k" V 6700 3300 50 0000 C CNN + 1 6700 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R Rf +U 1 1 516D0FE2 +P 6150 2950 +F 0 "Rf" V 6230 2950 50 0000 C CNN +F 1 "1000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516D0FD3 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "10" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro new file mode 100644 index 0000000..1f35813 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 15 May 2013 09:42:35 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.3/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis new file mode 100644 index 0000000..35318bb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 5e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak new file mode 100644 index 0000000..c4ca8fc --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.bak @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:43:16 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib new file mode 100644 index 0000000..18a7cf4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:47:25 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak new file mode 100644 index 0000000..f68a6c8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.bak @@ -0,0 +1,345 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:43:16 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 1400 6300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D2826 +P 1400 6300 +F 0 "#FLG01" H 1400 6570 30 0001 C CNN +F 1 "PWR_FLAG" H 1400 6530 30 0000 C CNN + 1 1400 6300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516D27F8 +P 1400 6450 +F 0 "#PWR02" H 1400 6450 30 0001 C CNN +F 1 "GND" H 1400 6380 30 0001 C CNN + 1 1400 6450 + 1 0 0 -1 +$EndComp +Connection ~ 1400 6100 +Wire Wire Line + 1400 6100 1400 6450 +Connection ~ 2400 3250 +Connection ~ 4500 3450 +Connection ~ 4500 4400 +Connection ~ 6750 3900 +Wire Wire Line + 5100 4700 5100 4850 +Wire Wire Line + 1600 5200 1600 5000 +Wire Wire Line + 1600 5000 2400 5000 +Connection ~ 3650 4900 +Wire Wire Line + 3900 4400 3900 4900 +Wire Wire Line + 3900 4900 3400 4900 +Connection ~ 2400 4500 +Wire Wire Line + 2400 4500 2600 4500 +Wire Wire Line + 3650 3000 3650 3550 +Wire Wire Line + 3650 3550 3100 3550 +Wire Wire Line + 2400 4250 2400 4800 +Wire Wire Line + 6750 3900 6750 3950 +Wire Wire Line + 6750 3950 6150 3950 +Wire Wire Line + 5300 3350 5100 3350 +Connection ~ 5100 3850 +Wire Wire Line + 5100 3350 5100 3850 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3850 +Wire Wire Line + 5150 3850 5050 3850 +Wire Wire Line + 5150 4050 5050 4050 +Wire Wire Line + 4550 4050 4550 4400 +Wire Wire Line + 4550 4400 4400 4400 +Wire Wire Line + 5800 3350 5950 3350 +Wire Wire Line + 6450 3350 6450 3950 +Connection ~ 6450 3950 +Wire Wire Line + 2400 3750 2400 3100 +Wire Wire Line + 2400 3550 2600 3550 +Connection ~ 2400 3550 +Wire Wire Line + 3400 3000 3900 3000 +Wire Wire Line + 3900 3000 3900 3450 +Connection ~ 3650 3000 +Wire Wire Line + 3100 4500 3650 4500 +Wire Wire Line + 3650 4500 3650 4900 +Wire Wire Line + 2400 2900 1150 2900 +Wire Wire Line + 1150 2900 1150 3600 +Wire Wire Line + 5100 4050 5100 4200 +Connection ~ 5100 4050 +Wire Wire Line + 1150 4500 1150 6100 +Wire Wire Line + 1150 6100 1600 6100 +$Comp +L DC v2 +U 1 1 516D27D5 +P 1600 5650 +F 0 "v2" H 1400 5750 60 0000 C CNN +F 1 "DC" H 1400 5600 60 0000 C CNN +F 2 "R1" H 1300 5650 60 0000 C CNN + 1 1600 5650 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 516D27D0 +P 1150 4050 +F 0 "v1" H 950 4150 60 0000 C CNN +F 1 "DC" H 950 4000 60 0000 C CNN +F 2 "R1" H 850 4050 60 0000 C CNN + 1 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 516D27AE +P 2400 4200 +F 0 "U1" H 2250 4300 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 4300 50 0000 C CNN + 2 2400 4200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 516D27A5 +P 2400 3250 +F 0 "U1" H 2250 3350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3350 50 0000 C CNN + 1 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 5 1 516D278E +P 6750 3600 +F 0 "U1" H 6600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 6900 3700 50 0000 C CNN + 5 6750 3600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 4 1 516D2789 +P 4500 4100 +F 0 "U1" H 4350 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 4200 50 0000 C CNN + 4 4500 4100 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 3 1 516D2785 +P 4500 3150 +F 0 "U1" H 4350 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 3250 50 0000 C CNN + 3 4500 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D274C +P 5100 4850 +F 0 "#PWR03" H 5100 4850 30 0001 C CNN +F 1 "GND" H 5100 4780 30 0001 C CNN + 1 5100 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 516D2736 +P 5100 4450 +F 0 "R6" V 5180 4450 50 0000 C CNN +F 1 "R" V 5100 4450 50 0000 C CNN + 1 5100 4450 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 516D26F4 +P 2850 4500 +F 0 "R3" V 2930 4500 50 0000 C CNN +F 1 "R" V 2850 4500 50 0000 C CNN + 1 2850 4500 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516D26CE +P 2850 3550 +F 0 "R2" V 2930 3550 50 0000 C CNN +F 1 "R" V 2850 3550 50 0000 C CNN + 1 2850 3550 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 516D26AE +P 2400 4000 +F 0 "R1" V 2480 4000 50 0000 C CNN +F 1 "R" V 2400 4000 50 0000 C CNN + 1 2400 4000 + -1 0 0 1 +$EndComp +$Comp +L R R7 +U 1 1 516D268C +P 6200 3350 +F 0 "R7" V 6280 3350 50 0000 C CNN +F 1 "R" V 6200 3350 50 0000 C CNN + 1 6200 3350 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516D267F +P 5550 3350 +F 0 "U4" H 5400 3450 50 0000 C CNN +F 1 "IPLOT" H 5700 3450 50 0000 C CNN + 1 5550 3350 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X2 +U 1 1 516D2661 +P 2900 4900 +F 0 "X2" H 3050 5050 60 0000 C CNN +F 1 "UA741" H 3050 5150 60 0000 C CNN + 1 2900 4900 + 1 0 0 1 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D2656 +P 2900 3000 +F 0 "X1" H 3050 3150 60 0000 C CNN +F 1 "UA741" H 3050 3250 60 0000 C CNN + 1 2900 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516D264E +P 4150 4400 +F 0 "U3" H 4000 4500 50 0000 C CNN +F 1 "IPLOT" H 4300 4500 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D2648 +P 4150 3450 +F 0 "U2" H 4000 3550 50 0000 C CNN +F 1 "IPLOT" H 4300 3550 50 0000 C CNN + 1 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 516D2600 +P 4800 4050 +F 0 "R5" V 4880 4050 50 0000 C CNN +F 1 "R" V 4800 4050 50 0000 C CNN + 1 4800 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 516D25EC +P 4800 3850 +F 0 "R4" V 4880 3850 50 0000 C CNN +F 1 "R" V 4800 3850 50 0000 C CNN + 1 4800 3850 + 0 1 1 0 +$EndComp +$Comp +L UA741 X3 +U 1 1 516D25CD +P 5650 3950 +F 0 "X3" H 5800 4100 60 0000 C CNN +F 1 "UA741" H 5800 4200 60 0000 C CNN + 1 5650 3950 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir new file mode 100644 index 0000000..4788ef3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir @@ -0,0 +1,24 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:47:21 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v2 5 0 10V +v1 9 0 20V +U1 3 4 6 2 11 VPLOT8_1 +R6 0 7 R +R3 4 12 R +R2 3 8 R +R1 4 3 R +R7 11 10 R +U4 13 10 IPLOT +X2 4 5 12 UA741 +X1 3 9 8 UA741 +U3 12 2 IPLOT +U2 8 6 IPLOT +R5 7 2 R +R4 13 6 R +X3 13 7 11 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt new file mode 100644 index 0000000..2fc3967 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.ckt @@ -0,0 +1,26 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:47:21 pm ist +.include ua741.sub + +v2 5 0 10v +v1 9 0 20v +* Plotting option vplot8_1 +r6 0 7 r +r3 4 12 r +r2 3 8 r +r1 4 3 r +r7 11 10 r +V_u4 13 10 0 +x2 4 5 12 ua741 +x1 3 9 8 ua741 +V_u3 12 2 0 +V_u2 8 6 0 +r5 7 2 r +r4 13 6 r +x3 13 7 11 ua741 + +.dc v1 0e-00 10e-00 5e-03 +.plot v(3) v(4) v(6) v(2) v(11) +.plot i(V_u4) +.plot i(V_u3) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out new file mode 100644 index 0000000..98912a5 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.cir.out @@ -0,0 +1,31 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:47:21 pm ist +.include ua741.sub + +v2 5 0 10v +v1 9 0 20v +* Plotting option vplot8_1 +r6 0 7 r +r3 4 12 r +r2 3 8 r +r1 4 3 r +r7 11 10 r +V_u4 13 10 0 +x2 4 5 12 ua741 +x1 3 9 8 ua741 +V_u3 12 2 0 +V_u2 8 6 0 +r5 7 2 r +r4 13 6 r +x3 13 7 11 ua741 + +.dc v1 0e-00 10e-00 5e-03 + +* Control Statements +.control +run +plot v(3) v(4) v(6) v(2) v(11) +plot i(V_u4) +plot i(V_u3) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro new file mode 100644 index 0000000..ac34f0e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 03:49:31 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj new file mode 100644 index 0000000..799253b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.proj @@ -0,0 +1 @@ +schematicFile example_5.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch new file mode 100644 index 0000000..8b83c0d --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/example_5.4.sch @@ -0,0 +1,345 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:47:25 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 1400 6300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D2826 +P 1400 6300 +F 0 "#FLG01" H 1400 6570 30 0001 C CNN +F 1 "PWR_FLAG" H 1400 6530 30 0000 C CNN + 1 1400 6300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516D27F8 +P 1400 6450 +F 0 "#PWR02" H 1400 6450 30 0001 C CNN +F 1 "GND" H 1400 6380 30 0001 C CNN + 1 1400 6450 + 1 0 0 -1 +$EndComp +Connection ~ 1400 6100 +Wire Wire Line + 1400 6100 1400 6450 +Connection ~ 2400 3250 +Connection ~ 4500 3450 +Connection ~ 4500 4400 +Connection ~ 6750 3900 +Wire Wire Line + 5100 4700 5100 4850 +Wire Wire Line + 1600 5200 1600 5000 +Wire Wire Line + 1600 5000 2400 5000 +Connection ~ 3650 4900 +Wire Wire Line + 3900 4400 3900 4900 +Wire Wire Line + 3900 4900 3400 4900 +Connection ~ 2400 4500 +Wire Wire Line + 2400 4500 2600 4500 +Wire Wire Line + 3650 3000 3650 3550 +Wire Wire Line + 3650 3550 3100 3550 +Wire Wire Line + 2400 4250 2400 4800 +Wire Wire Line + 6750 3900 6750 3950 +Wire Wire Line + 6750 3950 6150 3950 +Wire Wire Line + 5300 3350 5100 3350 +Connection ~ 5100 3850 +Wire Wire Line + 5100 3350 5100 3850 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3850 +Wire Wire Line + 5150 3850 5050 3850 +Wire Wire Line + 5150 4050 5050 4050 +Wire Wire Line + 4550 4050 4550 4400 +Wire Wire Line + 4550 4400 4400 4400 +Wire Wire Line + 5800 3350 5950 3350 +Wire Wire Line + 6450 3350 6450 3950 +Connection ~ 6450 3950 +Wire Wire Line + 2400 3750 2400 3100 +Wire Wire Line + 2400 3550 2600 3550 +Connection ~ 2400 3550 +Wire Wire Line + 3400 3000 3900 3000 +Wire Wire Line + 3900 3000 3900 3450 +Connection ~ 3650 3000 +Wire Wire Line + 3100 4500 3650 4500 +Wire Wire Line + 3650 4500 3650 4900 +Wire Wire Line + 2400 2900 1150 2900 +Wire Wire Line + 1150 2900 1150 3600 +Wire Wire Line + 5100 4050 5100 4200 +Connection ~ 5100 4050 +Wire Wire Line + 1150 4500 1150 6100 +Wire Wire Line + 1150 6100 1600 6100 +$Comp +L DC v2 +U 1 1 516D27D5 +P 1600 5650 +F 0 "v2" H 1400 5750 60 0000 C CNN +F 1 "10V" H 1400 5600 60 0000 C CNN +F 2 "R1" H 1300 5650 60 0000 C CNN + 1 1600 5650 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 516D27D0 +P 1150 4050 +F 0 "v1" H 950 4150 60 0000 C CNN +F 1 "20V" H 950 4000 60 0000 C CNN +F 2 "R1" H 850 4050 60 0000 C CNN + 1 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 516D27AE +P 2400 4200 +F 0 "U1" H 2250 4300 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 4300 50 0000 C CNN + 2 2400 4200 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 516D27A5 +P 2400 3250 +F 0 "U1" H 2250 3350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3350 50 0000 C CNN + 1 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 5 1 516D278E +P 6750 3600 +F 0 "U1" H 6600 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 6900 3700 50 0000 C CNN + 5 6750 3600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 4 1 516D2789 +P 4500 4100 +F 0 "U1" H 4350 4200 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 4200 50 0000 C CNN + 4 4500 4100 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 3 1 516D2785 +P 4500 3150 +F 0 "U1" H 4350 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 4650 3250 50 0000 C CNN + 3 4500 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D274C +P 5100 4850 +F 0 "#PWR03" H 5100 4850 30 0001 C CNN +F 1 "GND" H 5100 4780 30 0001 C CNN + 1 5100 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 516D2736 +P 5100 4450 +F 0 "R6" V 5180 4450 50 0000 C CNN +F 1 "R" V 5100 4450 50 0000 C CNN + 1 5100 4450 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 516D26F4 +P 2850 4500 +F 0 "R3" V 2930 4500 50 0000 C CNN +F 1 "R" V 2850 4500 50 0000 C CNN + 1 2850 4500 + 0 -1 -1 0 +$EndComp +$Comp +L R R2 +U 1 1 516D26CE +P 2850 3550 +F 0 "R2" V 2930 3550 50 0000 C CNN +F 1 "R" V 2850 3550 50 0000 C CNN + 1 2850 3550 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 516D26AE +P 2400 4000 +F 0 "R1" V 2480 4000 50 0000 C CNN +F 1 "R" V 2400 4000 50 0000 C CNN + 1 2400 4000 + -1 0 0 1 +$EndComp +$Comp +L R R7 +U 1 1 516D268C +P 6200 3350 +F 0 "R7" V 6280 3350 50 0000 C CNN +F 1 "R" V 6200 3350 50 0000 C CNN + 1 6200 3350 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516D267F +P 5550 3350 +F 0 "U4" H 5400 3450 50 0000 C CNN +F 1 "IPLOT" H 5700 3450 50 0000 C CNN + 1 5550 3350 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X2 +U 1 1 516D2661 +P 2900 4900 +F 0 "X2" H 3050 5050 60 0000 C CNN +F 1 "UA741" H 3050 5150 60 0000 C CNN + 1 2900 4900 + 1 0 0 1 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D2656 +P 2900 3000 +F 0 "X1" H 3050 3150 60 0000 C CNN +F 1 "UA741" H 3050 3250 60 0000 C CNN + 1 2900 3000 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516D264E +P 4150 4400 +F 0 "U3" H 4000 4500 50 0000 C CNN +F 1 "IPLOT" H 4300 4500 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D2648 +P 4150 3450 +F 0 "U2" H 4000 3550 50 0000 C CNN +F 1 "IPLOT" H 4300 3550 50 0000 C CNN + 1 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 516D2600 +P 4800 4050 +F 0 "R5" V 4880 4050 50 0000 C CNN +F 1 "R" V 4800 4050 50 0000 C CNN + 1 4800 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 516D25EC +P 4800 3850 +F 0 "R4" V 4880 3850 50 0000 C CNN +F 1 "R" V 4800 3850 50 0000 C CNN + 1 4800 3850 + 0 1 1 0 +$EndComp +$Comp +L UA741 X3 +U 1 1 516D25CD +P 5650 3950 +F 0 "X3" H 5800 4100 60 0000 C CNN +F 1 "UA741" H 5800 4200 60 0000 C CNN + 1 5650 3950 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro new file mode 100644 index 0000000..0d94955 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 17 April 2013 12:46:01 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.4/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis new file mode 100644 index 0000000..c9183fa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak new file mode 100644 index 0000000..79f0251 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.bak @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 11:57:44 AM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib new file mode 100644 index 0000000..951b224 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 17 April 2013 12:50:53 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak new file mode 100644 index 0000000..9eaa078 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.bak @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 11:57:44 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SINE v1 +U 1 1 516E3BC9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3300 +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "9000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir new file mode 100644 index 0000000..cbcca2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 17 April 2013 12:50:50 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 6 0 1000 +v1 5 0 SINE +U3 6 VPLOT8_1 +U1 4 2 IPLOT +U2 2 3 IPLOT +R2 6 3 9000 +R1 4 5 1000 +X1 2 0 6 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt new file mode 100644 index 0000000..6843d47 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist +.include ua741.sub + +r3 6 0 1000 +v1 5 0 sine(0 5 50 0 0) +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 9000 +r1 4 5 1000 +x1 2 0 6 ua741 + +.tran 10e-03 20e-03 0e-00 +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out new file mode 100644 index 0000000..9e60789 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 17 april 2013 12:50:50 pm ist +.include ua741.sub + +r3 6 0 1000 +v1 5 0 sine(0 5 50 0 0) +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 9000 +r1 4 5 1000 +x1 2 0 6 ua741 + +.tran 10e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro new file mode 100644 index 0000000..ead436b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 11:37:31 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj new file mode 100644 index 0000000..8554126 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.proj @@ -0,0 +1 @@ +schematicFile example_5.6.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch new file mode 100644 index 0000000..73864f6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/example_5.6.sch @@ -0,0 +1,183 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 12:50:53 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.6-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Wire Wire Line + 7050 3300 6350 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3500 +$Comp +L R R3 +U 1 1 516E4D07 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "1000" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 516E3BC9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "9000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro new file mode 100644 index 0000000..1235eb1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.pro @@ -0,0 +1,82 @@ +update=Wednesday 17 April 2013 12:51:39 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.6/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis new file mode 100644 index 0000000..234e759 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/analysis @@ -0,0 +1,8 @@ + +.ac lin 10 1Hz 1Meg + + +.end +.control +run +.endc diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak new file mode 100644 index 0000000..bef6862 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.bak @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 10:40:53 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib new file mode 100644 index 0000000..a99ee60 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7-cache.lib @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.3 Date: Wednesday 15 May 2013 10:41:23 PM IST +#encoding utf-8 +# +# AC +# +DEF AC AC 0 40 Y Y 1 F N +F0 "AC" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak new file mode 100644 index 0000000..5b65555 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.bak @@ -0,0 +1,210 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 10:40:53 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.7-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L AC AC1 +U 1 1 5193C186 +P 4050 3650 +F 0 "AC1" H 3850 3750 60 0000 C CNN +F 1 "AC" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 3500 7050 2950 +Connection ~ 6500 2950 +Wire Wire Line + 6500 2950 6500 2550 +Wire Wire Line + 6500 2550 6300 2550 +Connection ~ 5300 2950 +Wire Wire Line + 5300 2550 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 5800 2550 5900 2550 +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Connection ~ 7050 3400 +$Comp +L R R3 +U 1 1 516E71B7 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "R" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG2 +U 1 1 516E6E61 +P 5350 4100 +F 0 "#FLG2" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516E6E43 +P 7350 3400 +F 0 "U3" H 7200 3500 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3500 50 0000 C CNN + 1 7350 3400 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L C C1 +U 1 1 516E6B62 +P 6100 2550 +F 0 "C1" H 6150 2650 50 0000 L CNN +F 1 "1.59n" H 6150 2450 50 0000 L CNN + 1 6100 2550 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E6B56 +P 5550 2550 +F 0 "U4" H 5400 2650 50 0000 C CNN +F 1 "IPLOT" H 5700 2650 50 0000 C CNN + 1 5550 2550 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "10000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir new file mode 100644 index 0000000..944330f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wednesday 15 May 2013 10:41:20 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 6 0 AC +R3 7 0 R +U3 7 VPLOT8_1 +C1 7 3 1.59n +U4 1 3 IPLOT +U1 5 1 IPLOT +U2 1 4 IPLOT +R2 7 4 10000 +R1 5 6 1000 +X1 1 0 7 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt new file mode 100644 index 0000000..28de072 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.ckt @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 10:41:20 pm ist +.include ua741.sub + +v1 6 0 ac 1 +r3 7 0 r +* Plotting option vplot8_1 +c1 7 3 1.59n +V_u4 1 3 0 +V_u1 5 1 0 +V_u2 1 4 0 +r2 7 4 10000 +r1 5 6 1000 +x1 1 0 7 ua741 + +.ac lin 10 1Hz 1Meg +.plot v(7) +.plot i(V_u4) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out new file mode 100644 index 0000000..9002bf8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.cir.out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 15 may 2013 10:41:20 pm ist +.include ua741.sub + +v1 6 0 ac 1 +r3 7 0 r +* Plotting option vplot8_1 +c1 7 3 1.59n +V_u4 1 3 0 +V_u1 5 1 0 +V_u2 1 4 0 +r2 7 4 10000 +r1 5 6 1000 +x1 1 0 7 ua741 + +.ac lin 10 1Hz 1Meg + +* Control Statements +.control +run +plot v(7) +plot i(V_u4) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro new file mode 100644 index 0000000..a2b4ce1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 12:56:50 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj new file mode 100644 index 0000000..304c734 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.proj @@ -0,0 +1 @@ +schematicFile example_5.7.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch new file mode 100644 index 0000000..d7677e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/example_5.7.sch @@ -0,0 +1,210 @@ +EESchema Schematic File Version 2 date Wednesday 15 May 2013 10:41:23 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.7-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L AC v1 +U 1 1 5193C186 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "AC" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 3500 7050 2950 +Connection ~ 6500 2950 +Wire Wire Line + 6500 2950 6500 2550 +Wire Wire Line + 6500 2550 6300 2550 +Connection ~ 5300 2950 +Wire Wire Line + 5300 2550 5300 3200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 5800 2550 5900 2550 +Wire Wire Line + 4050 4100 7050 4100 +Wire Wire Line + 7050 4100 7050 4000 +Connection ~ 7050 3400 +$Comp +L R R3 +U 1 1 516E71B7 +P 7050 3750 +F 0 "R3" V 7130 3750 50 0000 C CNN +F 1 "R" V 7050 3750 50 0000 C CNN + 1 7050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516E6E61 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + -1 0 0 1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516E6E43 +P 7350 3400 +F 0 "U3" H 7200 3500 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3500 50 0000 C CNN + 1 7350 3400 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L C C1 +U 1 1 516E6B62 +P 6100 2550 +F 0 "C1" H 6150 2650 50 0000 L CNN +F 1 "1.59n" H 6150 2450 50 0000 L CNN + 1 6100 2550 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E6B56 +P 5550 2550 +F 0 "U4" H 5400 2650 50 0000 C CNN +F 1 "IPLOT" H 5700 2650 50 0000 C CNN + 1 5550 2550 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "10000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.7/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis new file mode 100644 index 0000000..64c6d69 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/analysis @@ -0,0 +1 @@ +.tran 1e-03 2e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch new file mode 100644 index 0000000..d6f19aa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.1.sch @@ -0,0 +1,172 @@ +EESchema Schematic File Version 2 date Wednesday 17 April 2013 05:15:51 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 6400 2950 7050 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 5300 2950 5300 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 4200 5350 3400 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 7050 2950 7050 3300 +$Comp +L SINE v1 +U 1 1 516E3AE9 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "SINE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG01" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG02" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "10000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR03" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak new file mode 100644 index 0000000..969d8ac --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.bak @@ -0,0 +1,157 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 18 April 2013 09:19:41 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib new file mode 100644 index 0000000..32852ba --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8-cache.lib @@ -0,0 +1,157 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 18 April 2013 10:25:50 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak new file mode 100644 index 0000000..a102621 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.bak @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Thursday 18 April 2013 09:19:41 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "18 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3300 3700 3300 4300 +Wire Wire Line + 3300 3100 3300 2850 +Wire Wire Line + 3300 2850 4200 2850 +Wire Wire Line + 4200 2850 4200 3200 +Wire Wire Line + 5800 2600 5900 2600 +Wire Wire Line + 4050 4100 5350 4100 +Wire Wire Line + 6350 3300 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Connection ~ 7050 3300 +Connection ~ 6350 3300 +Connection ~ 5350 4100 +Wire Wire Line + 4150 3200 4050 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 5250 3200 5350 3200 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3400 5350 4200 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5300 3200 5300 2600 +Connection ~ 5300 2950 +Wire Wire Line + 6300 2600 7050 2600 +Wire Wire Line + 7050 2600 7050 3300 +Connection ~ 7050 2950 +Connection ~ 4100 3200 +Wire Wire Line + 4250 4100 4250 4300 +Connection ~ 4250 4100 +Wire Wire Line + 4250 4300 3300 4300 +$Comp +L VPLOT8 U5 +U 1 1 516F6D28 +P 3300 3400 +F 0 "U5" H 3150 3500 50 0000 C CNN +F 1 "VPLOT8" H 3450 3500 50 0000 C CNN + 1 3300 3400 + 0 1 1 0 +$EndComp +$Comp +L PULSE v1 +U 1 1 516E8CD4 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "PULSE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 516E8BE7 +P 6100 2600 +F 0 "C1" H 6150 2700 50 0000 L CNN +F 1 "10n" H 6150 2500 50 0000 L CNN + 1 6100 2600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E8BCF +P 5550 2600 +F 0 "U4" H 5400 2700 50 0000 C CNN +F 1 "IPLOT" H 5700 2700 50 0000 C CNN + 1 5550 2600 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG2 +U 1 1 516D11A2 +P 5350 4100 +F 0 "#FLG2" H 5350 4370 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 4330 30 0000 C CNN + 1 5350 4100 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG1" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "1000000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR1" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir new file mode 100644 index 0000000..b53502b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:25:46 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 0 VPLOT8 +v1 5 0 PULSE +C1 6 1 10n +U4 2 1 IPLOT +U3 6 VPLOT8_1 +U1 4 2 IPLOT +U2 2 3 IPLOT +R2 6 3 1000000 +R1 4 5 10000 +X1 2 0 6 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt new file mode 100644 index 0000000..63570ef --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.ckt @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:25:46 am ist +.include ua741.sub + +v1 5 0 pulse(1 0 0 0 0 0.001 0.002) +c1 6 1 10n +V_u4 2 1 0 +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 1000000 +r1 4 5 10000 +x1 2 0 6 ua741 + +.tran 1e-03 2e-03 0e-00 +.plot v(5) +.plot i(V_u4) +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out new file mode 100644 index 0000000..ed95f2f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.cir.out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:25:46 am ist +.include ua741.sub + +v1 5 0 pulse(1 0 0 0 0 0.001 0.002) +c1 6 1 10n +V_u4 2 1 0 +* Plotting option vplot8_1 +V_u1 4 2 0 +V_u2 2 3 0 +r2 6 3 1000000 +r1 4 5 10000 +x1 2 0 6 ua741 + +.tran 1e-03 2e-03 0e-00 + +* Control Statements +.control +run +plot v(5) +plot i(V_u4) +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro new file mode 100644 index 0000000..62130f3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.pro @@ -0,0 +1,74 @@ +update=Wednesday 17 April 2013 05:14:42 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj new file mode 100644 index 0000000..a7ce942 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.proj @@ -0,0 +1 @@ +schematicFile example_5.8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch new file mode 100644 index 0000000..976a836 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/example_5.8.sch @@ -0,0 +1,214 @@ +EESchema Schematic File Version 2 date Thursday 18 April 2013 10:25:50 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "18 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4100 3200 4100 2950 +Wire Wire Line + 4100 2950 4200 2950 +Wire Wire Line + 4200 2950 4200 2850 +Wire Wire Line + 4250 4300 3300 4300 +Connection ~ 4250 4100 +Wire Wire Line + 4250 4300 4250 4100 +Connection ~ 4100 3200 +Connection ~ 7050 2950 +Wire Wire Line + 7050 2600 7050 3300 +Wire Wire Line + 7050 2600 6300 2600 +Connection ~ 5300 2950 +Wire Wire Line + 5300 3200 5300 2600 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 3400 5350 4200 +Connection ~ 5300 3200 +Wire Wire Line + 5250 3200 5350 3200 +Wire Wire Line + 5900 2950 5800 2950 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 7050 2950 6400 2950 +Wire Wire Line + 7050 3300 6350 3300 +Wire Wire Line + 4050 4100 5350 4100 +Wire Wire Line + 5800 2600 5900 2600 +Wire Wire Line + 3300 4300 3300 3700 +Wire Wire Line + 3300 3100 3300 2850 +Wire Wire Line + 3300 2850 4200 2850 +$Comp +L VPLOT8 U5 +U 1 1 516F6D28 +P 3300 3400 +F 0 "U5" H 3150 3500 50 0000 C CNN +F 1 "VPLOT8" H 3450 3500 50 0000 C CNN + 1 3300 3400 + 0 1 1 0 +$EndComp +$Comp +L PULSE v1 +U 1 1 516E8CD4 +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "PULSE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 516E8BE7 +P 6100 2600 +F 0 "C1" H 6150 2700 50 0000 L CNN +F 1 "10n" H 6150 2500 50 0000 L CNN + 1 6100 2600 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516E8BCF +P 5550 2600 +F 0 "U4" H 5400 2700 50 0000 C CNN +F 1 "IPLOT" H 5700 2700 50 0000 C CNN + 1 5550 2600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7350 3300 +F 0 "U3" H 7200 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 7500 3400 50 0000 C CNN + 1 7350 3300 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG01" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2950 +F 0 "U2" H 5400 3050 50 0000 C CNN +F 1 "IPLOT" H 5700 3050 50 0000 C CNN + 1 5550 2950 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6150 2950 +F 0 "R2" V 6230 2950 50 0000 C CNN +F 1 "1000000" V 6150 2950 50 0000 C CNN + 1 6150 2950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR02" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "10000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro new file mode 100644 index 0000000..9aa118e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.8/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis new file mode 100644 index 0000000..48302a3 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/analysis @@ -0,0 +1 @@ +.tran 2e-03 4e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir new file mode 100644 index 0000000..d30b232 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir @@ -0,0 +1,24 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:53:39 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 4 0 PULSE +v2 11 0 10V +U3 8 3 VPLOT8_1 +R5 13 3 10000 +R4 0 13 10000 +R3 1 11 10000 +U5 8 2 IPLOT +Q2 1 1 2 NPN +X2 1 13 3 UA741 +U4 10 8 IPLOT +Q1 10 0 9 NPN +U1 6 7 IPLOT +U2 7 9 IPLOT +R2 8 5 10000 +R1 6 4 1000 +X1 7 0 5 UA741 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt new file mode 100644 index 0000000..0decb7c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.ckt @@ -0,0 +1,27 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:53:39 am ist +.include ua741.sub + +v1 4 0 pulse(0 1 0.002 0.004) +v2 11 0 10v +* Plotting option vplot8_1 +r5 13 3 10000 +r4 0 13 10000 +r3 1 11 10000 +V_u5 8 2 0 +q2 2 1 1 npn +x2 1 13 3 ua741 +V_u4 10 8 0 +q1 10 0 9 npn +V_u1 6 7 0 +V_u2 7 9 0 +r2 8 5 10000 +r1 6 4 1000 +x1 7 0 5 ua741 + +.tran 2e-03 4e-03 0e-00 +.plot v(8) v(3) +.plot i(V_u5) +.plot i(V_u4) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out new file mode 100644 index 0000000..f4b917f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.cir.out @@ -0,0 +1,32 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 18 april 2013 10:53:39 am ist +.include ua741.sub + +v1 4 0 pulse(0 1 0.002 0.004) +v2 11 0 10v +* Plotting option vplot8_1 +r5 13 3 10000 +r4 0 13 10000 +r3 1 11 10000 +V_u5 8 2 0 +q2 2 1 1 npn +x2 1 13 3 ua741 +V_u4 10 8 0 +q1 10 0 9 npn +V_u1 6 7 0 +V_u2 7 9 0 +r2 8 5 10000 +r1 6 4 1000 +x1 7 0 5 ua741 + +.tran 2e-03 4e-03 0e-00 + +* Control Statements +.control +run +plot v(8) v(3) +plot i(V_u5) +plot i(V_u4) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro new file mode 100644 index 0000000..6a09490 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.pro @@ -0,0 +1,74 @@ +update=Thursday 18 April 2013 10:31:10 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj new file mode 100644 index 0000000..da8b8d1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.proj @@ -0,0 +1 @@ +schematicFile example_5.9.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch new file mode 100644 index 0000000..481506c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/example_5.9.sch @@ -0,0 +1,324 @@ +EESchema Schematic File Version 2 date Thursday 18 April 2013 10:52:19 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_5.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "18 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L GND #PWR01 +U 1 1 516F8096 +P 6150 2850 +F 0 "#PWR01" H 6150 2850 30 0001 C CNN +F 1 "GND" H 6150 2780 30 0001 C CNN + 1 6150 2850 + 1 0 0 -1 +$EndComp +Connection ~ 6150 2750 +$Comp +L PWR_FLAG #FLG02 +U 1 1 516F807F +P 6150 2750 +F 0 "#FLG02" H 6150 3020 30 0001 C CNN +F 1 "PWR_FLAG" H 6150 2980 30 0000 C CNN + 1 6150 2750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6150 2700 6150 2850 +Wire Wire Line + 10200 3750 10200 5050 +Wire Wire Line + 10200 2850 10200 2400 +Wire Wire Line + 10200 2400 8100 2400 +Wire Wire Line + 9250 3700 9400 3700 +Wire Wire Line + 8250 3800 8250 4100 +Connection ~ 8100 3300 +Wire Wire Line + 8100 3050 8100 3600 +Wire Wire Line + 7900 3600 8250 3600 +Wire Wire Line + 7150 3300 6950 3300 +Wire Wire Line + 6350 2400 6400 2400 +Wire Wire Line + 5300 2400 5300 3200 +Wire Wire Line + 6350 3300 6450 3300 +Wire Wire Line + 4750 3200 4650 3200 +Wire Wire Line + 5350 4200 5350 3400 +Connection ~ 5300 3200 +Wire Wire Line + 5350 3200 5250 3200 +Wire Wire Line + 4150 3200 4050 3200 +Connection ~ 5350 4100 +Connection ~ 6350 3300 +Connection ~ 7050 3300 +Wire Wire Line + 5350 4100 4050 4100 +Wire Wire Line + 5800 2400 5950 2400 +Wire Wire Line + 6900 2400 7050 2400 +Wire Wire Line + 7050 2400 7050 3300 +Wire Wire Line + 7650 3300 7700 3300 +Connection ~ 8100 3600 +Wire Wire Line + 8100 2400 8100 2550 +Wire Wire Line + 8250 4000 8450 4000 +Connection ~ 8250 4000 +Wire Wire Line + 9300 3700 9300 4000 +Wire Wire Line + 9300 4000 8950 4000 +Connection ~ 9300 3700 +Connection ~ 9400 3700 +Connection ~ 8100 2400 +Wire Wire Line + 10200 5050 8250 5050 +Wire Wire Line + 8250 5250 8250 4600 +Connection ~ 8250 5050 +Connection ~ 8250 5150 +$Comp +L GND #PWR03 +U 1 1 516F8034 +P 8250 5250 +F 0 "#PWR03" H 8250 5250 30 0001 C CNN +F 1 "GND" H 8250 5180 30 0001 C CNN + 1 8250 5250 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 516F801F +P 4050 3650 +F 0 "v1" H 3850 3750 60 0000 C CNN +F 1 "PULSE" H 3850 3600 60 0000 C CNN +F 2 "R1" H 3750 3650 60 0000 C CNN + 1 4050 3650 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 516F7FED +P 10200 3300 +F 0 "v2" H 10000 3400 60 0000 C CNN +F 1 "10V" H 10000 3250 60 0000 C CNN +F 2 "R1" H 9900 3300 60 0000 C CNN + 1 10200 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U3 +U 2 1 516F7F85 +P 9400 4000 +F 0 "U3" H 9250 4100 50 0000 C CNN +F 1 "VPLOT8_1" H 9550 4100 50 0000 C CNN + 2 9400 4000 + -1 0 0 1 +$EndComp +$Comp +L R R5 +U 1 1 516F7F66 +P 8700 4000 +F 0 "R5" V 8780 4000 50 0000 C CNN +F 1 "10000" V 8700 4000 50 0000 C CNN + 1 8700 4000 + 0 -1 -1 0 +$EndComp +$Comp +L R R4 +U 1 1 516F7F56 +P 8250 4350 +F 0 "R4" V 8330 4350 50 0000 C CNN +F 1 "10000" V 8250 4350 50 0000 C CNN + 1 8250 4350 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 516F7F35 +P 8100 2800 +F 0 "R3" V 8180 2800 50 0000 C CNN +F 1 "10000" V 8100 2800 50 0000 C CNN + 1 8100 2800 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U5 +U 1 1 516F7EEB +P 7400 3300 +F 0 "U5" H 7250 3400 50 0000 C CNN +F 1 "IPLOT" H 7550 3400 50 0000 C CNN + 1 7400 3300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q2 +U 1 1 516F7EDC +P 7900 3400 +F 0 "Q2" H 7900 3250 50 0000 R CNN +F 1 "NPN" H 7900 3550 50 0000 R CNN + 1 7900 3400 + 0 -1 -1 0 +$EndComp +$Comp +L UA741 X2 +U 1 1 516F7ED1 +P 8750 3700 +F 0 "X2" H 8900 3850 60 0000 C CNN +F 1 "UA741" H 8900 3950 60 0000 C CNN + 1 8750 3700 + 1 0 0 1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516F7EB1 +P 6650 2400 +F 0 "U4" H 6500 2500 50 0000 C CNN +F 1 "IPLOT" H 6800 2500 50 0000 C CNN + 1 6650 2400 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516F7E9D +P 6150 2500 +F 0 "Q1" H 6150 2350 50 0000 R CNN +F 1 "NPN" H 6150 2650 50 0000 R CNN + 1 6150 2500 + 0 -1 -1 0 +$EndComp +$Comp +L VPLOT8_1 U3 +U 1 1 516D117B +P 7050 3600 +F 0 "U3" H 6900 3700 50 0000 C CNN +F 1 "VPLOT8_1" H 7200 3700 50 0000 C CNN + 1 7050 3600 + -1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 516D1102 +P 5300 3200 +F 0 "#FLG04" H 5300 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 5300 3430 30 0000 C CNN + 1 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 516D1019 +P 5000 3200 +F 0 "U1" H 4850 3300 50 0000 C CNN +F 1 "IPLOT" H 5150 3300 50 0000 C CNN + 1 5000 3200 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U2 +U 1 1 516D0FEC +P 5550 2400 +F 0 "U2" H 5400 2500 50 0000 C CNN +F 1 "IPLOT" H 5700 2500 50 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516D0FE2 +P 6700 3300 +F 0 "R2" V 6780 3300 50 0000 C CNN +F 1 "10000" V 6700 3300 50 0000 C CNN + 1 6700 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR05 +U 1 1 516D0F6B +P 5350 4200 +F 0 "#PWR05" H 5350 4200 30 0001 C CNN +F 1 "GND" H 5350 4130 30 0001 C CNN + 1 5350 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516D0F10 +P 4400 3200 +F 0 "R1" V 4480 3200 50 0000 C CNN +F 1 "1000" V 4400 3200 50 0000 C CNN + 1 4400 3200 + 0 1 1 0 +$EndComp +$Comp +L UA741 X1 +U 1 1 516D0E60 +P 5850 3300 +F 0 "X1" H 6000 3450 60 0000 C CNN +F 1 "UA741" H 6000 3550 60 0000 C CNN + 1 5850 3300 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro new file mode 100644 index 0000000..df98e42 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.pro @@ -0,0 +1,82 @@ +update=Thursday 18 April 2013 01:48:22 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice +LibName39=/home/holy/OSCAD/library/analogSpice +LibName40=/home/holy/OSCAD/library/analogXSpice +LibName41=/home/holy/OSCAD/library/convergenceAidSpice +LibName42=/home/holy/OSCAD/library/converterSpice +LibName43=/home/holy/OSCAD/library/digitalSpice +LibName44=/home/holy/OSCAD/library/digitalXSpice +LibName45=/home/holy/OSCAD/library/linearSpice +LibName46=/home/holy/OSCAD/library/measurementSpice +LibName47=/home/holy/OSCAD/library/portSpice +LibName48=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch new file mode 100644 index 0000000..7dfc5e1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.9/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis new file mode 100644 index 0000000..0e8f996 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis @@ -0,0 +1 @@ +.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak new file mode 100644 index 0000000..6284625 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 22 April 2013 12:05:40 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib new file mode 100644 index 0000000..388a263 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 22 April 2013 12:09:56 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak new file mode 100644 index 0000000..cc13116 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak @@ -0,0 +1,231 @@ +EESchema Schematic File Version 2 date Monday 22 April 2013 12:05:40 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_7.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 1050 3250 +$Comp +L VPLOT8_1 U2 +U 1 1 5174D971 +P 1050 2950 +F 0 "U2" H 900 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 1200 3050 50 0000 C CNN + 1 1050 2950 + 1 0 0 -1 +$EndComp +Connection ~ 2950 3200 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5174D14C +P 2050 5350 +F 0 "#FLG01" H 2050 5620 30 0001 C CNN +F 1 "PWR_FLAG" H 2050 5580 30 0000 C CNN + 1 2050 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 5174D02B +P 2950 2900 +F 0 "U1" H 2800 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 3100 3000 50 0000 C CNN + 2 2950 2900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5174D021 +P 2050 2900 +F 0 "U1" H 1900 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 2200 3000 50 0000 C CNN + 1 2050 2900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 3 1 5174D010 +P 4050 2900 +F 0 "U1" H 3900 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 4200 3000 50 0000 C CNN + 3 4050 2900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5174CFD9 +P 2050 5500 +F 0 "#PWR02" H 2050 5500 30 0001 C CNN +F 1 "GND" H 2050 5430 30 0001 C CNN + 1 2050 5500 + 1 0 0 -1 +$EndComp +Connection ~ 2750 5350 +Wire Wire Line + 2750 3950 2750 5350 +Connection ~ 2050 5350 +Wire Wire Line + 1050 4200 1050 5350 +Connection ~ 2050 4600 +Wire Wire Line + 2050 4800 2050 4000 +Wire Wire Line + 3650 4600 3800 4600 +Connection ~ 3800 3200 +Wire Wire Line + 3800 4600 3800 3200 +Connection ~ 4050 3200 +Wire Wire Line + 4050 3200 4050 3350 +Wire Wire Line + 2050 4200 2500 4200 +Connection ~ 2050 4200 +Wire Wire Line + 2500 4200 2500 3700 +Wire Wire Line + 1050 3200 1050 3300 +Wire Wire Line + 2050 3200 2050 3500 +Wire Wire Line + 1550 3200 2500 3200 +Wire Wire Line + 2500 3200 2500 3600 +Connection ~ 2050 3200 +Wire Wire Line + 2750 3350 2750 3200 +Wire Wire Line + 2750 3200 3100 3200 +Wire Wire Line + 3600 3200 4250 3200 +Wire Wire Line + 2050 4600 3150 4600 +Wire Wire Line + 2050 5300 2050 5500 +Wire Wire Line + 4050 3850 4050 5350 +Wire Wire Line + 4050 5350 1050 5350 +$Comp +L R R3 +U 1 1 5174CF9E +P 2050 5050 +F 0 "R3" V 2130 5050 50 0000 C CNN +F 1 "1000" V 2050 5050 50 0000 C CNN + 1 2050 5050 + -1 0 0 1 +$EndComp +$Comp +L R R5 +U 1 1 5174CF7E +P 3400 4600 +F 0 "R5" V 3480 4600 50 0000 C CNN +F 1 "100000" V 3400 4600 50 0000 C CNN + 1 3400 4600 + 0 1 1 0 +$EndComp +$Comp +L R R6 +U 1 1 5174CF4D +P 4050 3600 +F 0 "R6" V 4130 3600 50 0000 C CNN +F 1 "2000" V 4050 3600 50 0000 C CNN + 1 4050 3600 + -1 0 0 1 +$EndComp +$Comp +L R R4 +U 1 1 5174CF16 +P 3350 3200 +F 0 "R4" V 3430 3200 50 0000 C CNN +F 1 "1000" V 3350 3200 50 0000 C CNN + 1 3350 3200 + 0 1 1 0 +$EndComp +$Comp +L VCVS E1 +U 1 1 5174CEE8 +P 2700 3650 +F 0 "E1" H 2500 3750 50 0000 C CNN +F 1 "10000" H 2500 3600 50 0000 C CNN + 1 2700 3650 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5174CEC2 +P 2050 3750 +F 0 "R2" V 2130 3750 50 0000 C CNN +F 1 "100000" V 2050 3750 50 0000 C CNN + 1 2050 3750 + -1 0 0 1 +$EndComp +$Comp +L SINE v1 +U 1 1 5174CE88 +P 1050 3750 +F 0 "v1" H 850 3850 60 0000 C CNN +F 1 "SINE" H 850 3700 60 0000 C CNN +F 2 "R1" H 750 3750 60 0000 C CNN + 1 1050 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5174CE5E +P 1300 3200 +F 0 "R1" V 1380 3200 50 0000 C CNN +F 1 "10000" V 1300 3200 50 0000 C CNN + 1 1300 3200 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir new file mode 100644 index 0000000..c73ab3c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir @@ -0,0 +1,18 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 22 April 2013 12:19:08 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +XU2 1 VPLOT8_1 +XU1 4 3 5 VPLOT8_1 +R3 0 6 1000 +R5 5 6 100000 +R6 0 5 2000 +R4 5 3 1000 +E1 3 0 4 6 2 +R2 6 4 100000 +v1 1 0 SINE +R1 4 1 10000 + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt new file mode 100644 index 0000000..9a79ca6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 12:09:21 pm ist + +* Plotting option vplot8_1 +* Plotting option vplot8_1 +r3 0 6 1000 +r5 5 6 100000 +r6 0 5 2000 +r4 5 3 1000 +e1 3 0 4 6 2 +r2 6 4 100000 +v1 1 0 sine(0 5 50 0 0) +r1 4 1 10000 + +.tran 2e-03 20e-03 0e-00 +.plot v(1) +.plot v(4) v(3) v(5) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out new file mode 100644 index 0000000..222f9bd --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 12:09:21 pm ist + +* Plotting option vplot8_1 +* Plotting option vplot8_1 +r3 0 6 1000 +r5 5 6 100000 +r6 0 5 2000 +r4 5 3 1000 +e1 3 0 4 6 2 +r2 6 4 100000 +v1 1 0 sine(0 5 50 0 0) +r1 4 1 10000 + +.tran 2e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(1) +plot v(4) v(3) v(5) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro new file mode 100644 index 0000000..414c8ad --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro @@ -0,0 +1,74 @@ +update=Monday 22 April 2013 11:14:03 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj new file mode 100644 index 0000000..dafbe48 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj @@ -0,0 +1 @@ +schematicFile example_7.1.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch new file mode 100644 index 0000000..7980439 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch @@ -0,0 +1,231 @@ +EESchema Schematic File Version 2 date Monday 22 April 2013 12:09:56 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_7.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 1050 3250 +$Comp +L VPLOT8_1 U2 +U 1 1 5174D971 +P 1050 2950 +F 0 "U2" H 900 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 1200 3050 50 0000 C CNN + 1 1050 2950 + 1 0 0 -1 +$EndComp +Connection ~ 2950 3200 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5174D14C +P 2050 5350 +F 0 "#FLG01" H 2050 5620 30 0001 C CNN +F 1 "PWR_FLAG" H 2050 5580 30 0000 C CNN + 1 2050 5350 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 5174D02B +P 2950 2900 +F 0 "U1" H 2800 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 3100 3000 50 0000 C CNN + 2 2950 2900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 5174D021 +P 2050 2900 +F 0 "U1" H 1900 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 2200 3000 50 0000 C CNN + 1 2050 2900 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 3 1 5174D010 +P 4050 2900 +F 0 "U1" H 3900 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 4200 3000 50 0000 C CNN + 3 4050 2900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5174CFD9 +P 2050 5500 +F 0 "#PWR02" H 2050 5500 30 0001 C CNN +F 1 "GND" H 2050 5430 30 0001 C CNN + 1 2050 5500 + 1 0 0 -1 +$EndComp +Connection ~ 2750 5350 +Wire Wire Line + 2750 3950 2750 5350 +Connection ~ 2050 5350 +Wire Wire Line + 1050 4200 1050 5350 +Connection ~ 2050 4600 +Wire Wire Line + 2050 4800 2050 4000 +Wire Wire Line + 3650 4600 3800 4600 +Connection ~ 3800 3200 +Wire Wire Line + 3800 4600 3800 3200 +Connection ~ 4050 3200 +Wire Wire Line + 4050 3200 4050 3350 +Wire Wire Line + 2050 4200 2500 4200 +Connection ~ 2050 4200 +Wire Wire Line + 2500 4200 2500 3700 +Wire Wire Line + 1050 3200 1050 3300 +Wire Wire Line + 2050 3200 2050 3500 +Wire Wire Line + 1550 3200 2500 3200 +Wire Wire Line + 2500 3200 2500 3600 +Connection ~ 2050 3200 +Wire Wire Line + 2750 3350 2750 3200 +Wire Wire Line + 2750 3200 3100 3200 +Wire Wire Line + 3600 3200 4250 3200 +Wire Wire Line + 2050 4600 3150 4600 +Wire Wire Line + 2050 5300 2050 5500 +Wire Wire Line + 4050 3850 4050 5350 +Wire Wire Line + 4050 5350 1050 5350 +$Comp +L R R3 +U 1 1 5174CF9E +P 2050 5050 +F 0 "R3" V 2130 5050 50 0000 C CNN +F 1 "1000" V 2050 5050 50 0000 C CNN + 1 2050 5050 + -1 0 0 1 +$EndComp +$Comp +L R R5 +U 1 1 5174CF7E +P 3400 4600 +F 0 "R5" V 3480 4600 50 0000 C CNN +F 1 "100000" V 3400 4600 50 0000 C CNN + 1 3400 4600 + 0 1 1 0 +$EndComp +$Comp +L R R6 +U 1 1 5174CF4D +P 4050 3600 +F 0 "R6" V 4130 3600 50 0000 C CNN +F 1 "2000" V 4050 3600 50 0000 C CNN + 1 4050 3600 + -1 0 0 1 +$EndComp +$Comp +L R R4 +U 1 1 5174CF16 +P 3350 3200 +F 0 "R4" V 3430 3200 50 0000 C CNN +F 1 "1000" V 3350 3200 50 0000 C CNN + 1 3350 3200 + 0 1 1 0 +$EndComp +$Comp +L VCVS E1 +U 1 1 5174CEE8 +P 2700 3650 +F 0 "E1" H 2500 3750 50 0000 C CNN +F 1 "2" H 2500 3600 50 0000 C CNN + 1 2700 3650 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5174CEC2 +P 2050 3750 +F 0 "R2" V 2130 3750 50 0000 C CNN +F 1 "100000" V 2050 3750 50 0000 C CNN + 1 2050 3750 + -1 0 0 1 +$EndComp +$Comp +L SINE v1 +U 1 1 5174CE88 +P 1050 3750 +F 0 "v1" H 850 3850 60 0000 C CNN +F 1 "SINE" H 850 3700 60 0000 C CNN +F 2 "R1" H 750 3750 60 0000 C CNN + 1 1050 3750 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5174CE5E +P 1300 3200 +F 0 "R1" V 1380 3200 50 0000 C CNN +F 1 "10000" V 1300 3200 50 0000 C CNN + 1 1300 3200 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis new file mode 100644 index 0000000..0e8f996 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis @@ -0,0 +1 @@ +.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib new file mode 100644 index 0000000..394db4b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 22 April 2013 02:21:52 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir new file mode 100644 index 0000000..fc9aa74 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 22 April 2013 02:21:49 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 5 4 VPLOT8_1 +v2 2 0 12 +R2 4 3 47000 +R1 3 5 10000 +v1 5 0 SINE +R3 2 4 4700 +Q1 0 3 4 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt new file mode 100644 index 0000000..421fe94 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 02:21:49 pm ist + +* Plotting option vplot8_1 +v2 2 0 12 +r2 4 3 47000 +r1 3 5 10000 +v1 5 0 sine( 5 50 ) +r3 2 4 4700 +q1 4 3 0 npn + +.tran 2e-03 20e-03 0e-00 +.plot v(5) v(4) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out new file mode 100644 index 0000000..db0fe26 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 02:21:49 pm ist + +* Plotting option vplot8_1 +v2 2 0 12 +r2 4 3 47000 +r1 3 5 10000 +v1 5 0 sine( 5 50 ) +r3 2 4 4700 +q1 4 3 0 npn + +.tran 2e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(5) v(4) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro new file mode 100644 index 0000000..1618111 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro @@ -0,0 +1,74 @@ +update=Monday 22 April 2013 02:17:45 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj new file mode 100644 index 0000000..ff14336 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj @@ -0,0 +1 @@ +schematicFile example_7.3.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch new file mode 100644 index 0000000..fddbc06 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 date Monday 22 April 2013 02:21:52 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 43 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 1 1 5174FA0E +P 3850 3350 +F 0 "U1" H 3700 3450 50 0000 C CNN +F 1 "VPLOT8_1" H 4000 3450 50 0000 C CNN + 1 3850 3350 + 1 0 0 -1 +$EndComp +Connection ~ 3850 3650 +Wire Wire Line + 3850 3650 3800 3650 +Connection ~ 4350 3650 +Connection ~ 5300 3350 +Wire Wire Line + 4950 4650 4950 3850 +Wire Wire Line + 5800 3200 5800 2800 +Wire Wire Line + 5800 2800 4950 2800 +Wire Wire Line + 4350 3350 4350 3650 +Wire Wire Line + 4350 3350 4450 3350 +Wire Wire Line + 4950 3450 4950 3300 +Wire Wire Line + 4350 3650 4650 3650 +Wire Wire Line + 4950 3350 5300 3350 +Connection ~ 4950 3350 +Wire Wire Line + 5800 4100 5800 4550 +Wire Wire Line + 5800 4550 3800 4550 +Connection ~ 4950 4550 +$Comp +L VPLOT8_1 U1 +U 2 1 5174F9F2 +P 5300 3050 +F 0 "U1" H 5150 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5450 3150 50 0000 C CNN + 2 5300 3050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5174F9DF +P 4950 4550 +F 0 "#FLG01" H 4950 4820 30 0001 C CNN +F 1 "PWR_FLAG" H 4950 4780 30 0000 C CNN + 1 4950 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5174F9D4 +P 4950 4650 +F 0 "#PWR02" H 4950 4650 30 0001 C CNN +F 1 "GND" H 4950 4580 30 0001 C CNN + 1 4950 4650 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5174F994 +P 5800 3650 +F 0 "v2" H 5600 3750 60 0000 C CNN +F 1 "12" H 5600 3600 60 0000 C CNN +F 2 "R1" H 5500 3650 60 0000 C CNN + 1 5800 3650 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5174F959 +P 4700 3350 +F 0 "R2" V 4780 3350 50 0000 C CNN +F 1 "47000" V 4700 3350 50 0000 C CNN + 1 4700 3350 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 5174F943 +P 4100 3650 +F 0 "R1" V 4180 3650 50 0000 C CNN +F 1 "10000" V 4100 3650 50 0000 C CNN + 1 4100 3650 + 0 1 1 0 +$EndComp +$Comp +L SINE v1 +U 1 1 5174F939 +P 3800 4100 +F 0 "v1" H 3600 4200 60 0000 C CNN +F 1 "SINE" H 3600 4050 60 0000 C CNN +F 2 "R1" H 3500 4100 60 0000 C CNN + 1 3800 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5174F90B +P 4950 3050 +F 0 "R3" V 5030 3050 50 0000 C CNN +F 1 "4700" V 4950 3050 50 0000 C CNN + 1 4950 3050 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 5174F8FA +P 4850 3650 +F 0 "Q1" H 4850 3500 50 0000 R CNN +F 1 "NPN" H 4850 3800 50 0000 R CNN + 1 4850 3650 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis new file mode 100644 index 0000000..0e8f996 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis @@ -0,0 +1 @@ +.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak new file mode 100644 index 0000000..61d077a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak @@ -0,0 +1,133 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 23 April 2013 11:46:23 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib new file mode 100644 index 0000000..b4c0e94 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib @@ -0,0 +1,133 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 23 April 2013 12:03:44 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak new file mode 100644 index 0000000..0eedc93 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak @@ -0,0 +1,348 @@ +EESchema Schematic File Version 2 date Tuesday 23 April 2013 11:46:23 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_7.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "23 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6350 3000 +$Comp +L VPLOT8_1 U1 +U 1 1 517625EA +P 6350 2700 +F 0 "U1" H 6200 2800 50 0000 C CNN +F 1 "VPLOT8_1" H 6500 2800 50 0000 C CNN + 1 6350 2700 + 1 0 0 -1 +$EndComp +Connection ~ 7000 2450 +$Comp +L VPLOT8_1 U1 +U 2 1 517625DB +P 7000 2150 +F 0 "U1" H 6850 2250 50 0000 C CNN +F 1 "VPLOT8_1" H 7150 2250 50 0000 C CNN + 2 7000 2150 + 1 0 0 -1 +$EndComp +Connection ~ 5800 2700 +$Comp +L PWR_FLAG #FLG01 +U 1 1 517625B5 +P 5800 2700 +F 0 "#FLG01" H 5800 2970 30 0001 C CNN +F 1 "PWR_FLAG" H 5800 2930 30 0000 C CNN + 1 5800 2700 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 517625AE +P 4050 3100 +F 0 "#FLG02" H 4050 3370 30 0001 C CNN +F 1 "PWR_FLAG" H 4050 3330 30 0000 C CNN + 1 4050 3100 + 1 0 0 -1 +$EndComp +Connection ~ 3250 4150 +$Comp +L PWR_FLAG #FLG03 +U 1 1 5176256A +P 3250 4150 +F 0 "#FLG03" H 3250 4420 30 0001 C CNN +F 1 "PWR_FLAG" H 3250 4380 30 0000 C CNN + 1 3250 4150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 5176255C +P 3250 4300 +F 0 "#PWR04" H 3250 4300 30 0001 C CNN +F 1 "GND" H 3250 4230 30 0001 C CNN + 1 3250 4300 + 1 0 0 -1 +$EndComp +Connection ~ 3250 3950 +Wire Wire Line + 3250 3950 3250 4300 +Wire Wire Line + 2500 3100 2750 3100 +Connection ~ 6200 1700 +Wire Wire Line + 7500 2400 7500 1700 +Wire Wire Line + 7500 1700 4050 1700 +Wire Wire Line + 5200 4350 5000 4350 +Wire Wire Line + 6600 3000 6600 4350 +Connection ~ 6200 3000 +Wire Wire Line + 6600 3000 6200 3000 +Connection ~ 4050 3950 +Wire Wire Line + 3850 3100 4400 3100 +Connection ~ 4050 3100 +Wire Wire Line + 4050 3450 4050 2650 +Connection ~ 4700 1700 +Wire Wire Line + 4050 1700 4050 2150 +Connection ~ 6200 3950 +Wire Wire Line + 6200 3550 6200 3950 +Wire Wire Line + 6900 2450 7050 2450 +Wire Wire Line + 5200 3450 5200 3400 +Connection ~ 4700 3400 +Wire Wire Line + 5200 3400 4700 3400 +Wire Wire Line + 4700 3300 4700 3450 +Wire Wire Line + 6200 2500 6200 2350 +Wire Wire Line + 4700 2600 4700 2900 +Wire Wire Line + 5900 2700 4700 2700 +Connection ~ 4700 2700 +Wire Wire Line + 6200 2450 6500 2450 +Connection ~ 6200 2450 +Wire Wire Line + 6200 2900 6200 3050 +Wire Wire Line + 5200 3950 5200 3850 +Wire Wire Line + 7050 3950 7050 2950 +Connection ~ 5200 3950 +Wire Wire Line + 4700 1700 4700 2100 +Wire Wire Line + 6200 1700 6200 1850 +Connection ~ 4700 3950 +Wire Wire Line + 3450 3100 3250 3100 +Wire Wire Line + 6600 4350 5600 4350 +Wire Wire Line + 4500 4350 3950 4350 +Wire Wire Line + 3950 4350 3950 3100 +Connection ~ 3950 3100 +Wire Wire Line + 7500 3300 7500 3950 +Wire Wire Line + 7500 3950 2750 3950 +Connection ~ 7050 3950 +Wire Wire Line + 2750 3950 2750 4000 +Wire Wire Line + 2750 4000 2500 4000 +$Comp +L SINE v1 +U 1 1 5176244C +P 2500 3550 +F 0 "v1" H 2300 3650 60 0000 C CNN +F 1 "SINE" H 2300 3500 60 0000 C CNN +F 2 "R1" H 2200 3550 60 0000 C CNN + 1 2500 3550 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 51761AB3 +P 4750 4350 +F 0 "R6" V 4830 4350 50 0000 C CNN +F 1 "10k" V 4750 4350 50 0000 C CNN + 1 4750 4350 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 51761A46 +P 3000 3100 +F 0 "R1" V 3080 3100 50 0000 C CNN +F 1 "10k" V 3000 3100 50 0000 C CNN + 1 3000 3100 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 51761A2D +P 3650 3100 +F 0 "C1" H 3700 3200 50 0000 L CNN +F 1 "1k" H 3700 3000 50 0000 L CNN + 1 3650 3100 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 51761A14 +P 4050 3700 +F 0 "R3" V 4130 3700 50 0000 C CNN +F 1 "15k" V 4050 3700 50 0000 C CNN + 1 4050 3700 + 1 0 0 -1 +$EndComp +$Comp +L R R9 +U 1 1 517619D2 +P 7050 2700 +F 0 "R9" V 7130 2700 50 0000 C CNN +F 1 "1k" V 7050 2700 50 0000 C CNN + 1 7050 2700 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 517619B5 +P 5200 3650 +F 0 "C2" H 5250 3750 50 0000 L CNN +F 1 "1k" H 5250 3550 50 0000 L CNN + 1 5200 3650 + 1 0 0 -1 +$EndComp +$Comp +L R R7 +U 1 1 517619A1 +P 6200 2100 +F 0 "R7" V 6280 2100 50 0000 C CNN +F 1 "8k" V 6200 2100 50 0000 C CNN + 1 6200 2100 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 5176198B +P 6200 3300 +F 0 "R8" V 6280 3300 50 0000 C CNN +F 1 "3.4k" V 6200 3300 50 0000 C CNN + 1 6200 3300 + 1 0 0 -1 +$EndComp +$Comp +L C C4 +U 1 1 5176197A +P 6700 2450 +F 0 "C4" H 6750 2550 50 0000 L CNN +F 1 "1k" H 6750 2350 50 0000 L CNN + 1 6700 2450 + 0 1 1 0 +$EndComp +$Comp +L R R5 +U 1 1 51761974 +P 4700 3700 +F 0 "R5" V 4780 3700 50 0000 C CNN +F 1 "870" V 4700 3700 50 0000 C CNN + 1 4700 3700 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 51761961 +P 4700 2350 +F 0 "R4" V 4780 2350 50 0000 C CNN +F 1 "10k" V 4700 2350 50 0000 C CNN + 1 4700 2350 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5176195A +P 7500 2850 +F 0 "v2" H 7300 2950 60 0000 C CNN +F 1 "12" H 7300 2800 60 0000 C CNN +F 2 "R1" H 7200 2850 60 0000 C CNN + 1 7500 2850 + 1 0 0 -1 +$EndComp +$Comp +L C C3 +U 1 1 51761951 +P 5400 4350 +F 0 "C3" H 5450 4450 50 0000 L CNN +F 1 "1k" H 5450 4250 50 0000 L CNN + 1 5400 4350 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5176194E +P 4050 2400 +F 0 "R2" V 4130 2400 50 0000 C CNN +F 1 "100k" V 4050 2400 50 0000 C CNN + 1 4050 2400 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q2 +U 1 1 5176191C +P 6100 2700 +F 0 "Q2" H 6100 2550 50 0000 R CNN +F 1 "NPN" H 6100 2850 50 0000 R CNN + 1 6100 2700 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 517618FE +P 4600 3100 +F 0 "Q1" H 4600 2950 50 0000 R CNN +F 1 "NPN" H 4600 3250 50 0000 R CNN + 1 4600 3100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir new file mode 100644 index 0000000..66167e8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir @@ -0,0 +1,26 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 23 April 2013 12:03:40 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 8 7 VPLOT8_1 +v1 2 0 SINE +R6 3 6 10k +R1 1 2 10k +C1 6 1 1m +R3 6 0 15k +R9 7 0 1k +C2 11 0 1m +R7 4 9 8k +R8 8 0 3.4k +C4 7 9 1m +R5 11 0 870 +R4 4 10 10k +v2 4 0 12 +C3 8 3 1m +R2 4 6 100k +Q2 8 10 9 NPN +Q1 11 6 10 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt new file mode 100644 index 0000000..d627f6f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt @@ -0,0 +1,24 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 23 april 2013 12:03:40 pm ist + +* Plotting option vplot8_1 +v1 2 0 sine(0 1 50 ) +r6 3 6 10k +r1 1 2 10k +c1 6 1 1m +r3 6 0 15k +r9 7 0 1k +c2 11 0 1m +r7 4 9 8k +r8 8 0 3.4k +c4 7 9 1m +r5 11 0 870 +r4 4 10 10k +v2 4 0 12 +c3 8 3 1m +r2 4 6 100k +q2 9 10 8 npn +q1 10 6 11 npn + +.tran 2e-03 20e-03 0e-00 +.plot v(8) v(7) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out new file mode 100644 index 0000000..669fcbb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out @@ -0,0 +1,29 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 23 april 2013 12:03:40 pm ist + +* Plotting option vplot8_1 +v1 2 0 sine(0 1 50 ) +r6 3 6 10k +r1 1 2 10k +c1 6 1 1m +r3 6 0 15k +r9 7 0 1k +c2 11 0 1m +r7 4 9 8k +r8 8 0 3.4k +c4 7 9 1m +r5 11 0 870 +r4 4 10 10k +v2 4 0 12 +c3 8 3 1m +r2 4 6 100k +q2 9 10 8 npn +q1 10 6 11 npn + +.tran 2e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(8) v(7) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro new file mode 100644 index 0000000..29f504b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro @@ -0,0 +1,74 @@ +update=Tuesday 23 April 2013 10:45:01 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj new file mode 100644 index 0000000..a6cb330 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj @@ -0,0 +1 @@ +schematicFile example_7.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch new file mode 100644 index 0000000..1f165d6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch @@ -0,0 +1,348 @@ +EESchema Schematic File Version 2 date Tuesday 23 April 2013 12:03:44 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_7.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "23 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6350 3000 +$Comp +L VPLOT8_1 U1 +U 1 1 517625EA +P 6350 2700 +F 0 "U1" H 6200 2800 50 0000 C CNN +F 1 "VPLOT8_1" H 6500 2800 50 0000 C CNN + 1 6350 2700 + 1 0 0 -1 +$EndComp +Connection ~ 7000 2450 +$Comp +L VPLOT8_1 U1 +U 2 1 517625DB +P 7000 2150 +F 0 "U1" H 6850 2250 50 0000 C CNN +F 1 "VPLOT8_1" H 7150 2250 50 0000 C CNN + 2 7000 2150 + 1 0 0 -1 +$EndComp +Connection ~ 5800 2700 +$Comp +L PWR_FLAG #FLG01 +U 1 1 517625B5 +P 5800 2700 +F 0 "#FLG01" H 5800 2970 30 0001 C CNN +F 1 "PWR_FLAG" H 5800 2930 30 0000 C CNN + 1 5800 2700 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 517625AE +P 4050 3100 +F 0 "#FLG02" H 4050 3370 30 0001 C CNN +F 1 "PWR_FLAG" H 4050 3330 30 0000 C CNN + 1 4050 3100 + 1 0 0 -1 +$EndComp +Connection ~ 3250 4150 +$Comp +L PWR_FLAG #FLG03 +U 1 1 5176256A +P 3250 4150 +F 0 "#FLG03" H 3250 4420 30 0001 C CNN +F 1 "PWR_FLAG" H 3250 4380 30 0000 C CNN + 1 3250 4150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 5176255C +P 3250 4300 +F 0 "#PWR04" H 3250 4300 30 0001 C CNN +F 1 "GND" H 3250 4230 30 0001 C CNN + 1 3250 4300 + 1 0 0 -1 +$EndComp +Connection ~ 3250 3950 +Wire Wire Line + 3250 3950 3250 4300 +Wire Wire Line + 2500 3100 2750 3100 +Connection ~ 6200 1700 +Wire Wire Line + 7500 2400 7500 1700 +Wire Wire Line + 7500 1700 4050 1700 +Wire Wire Line + 5200 4350 5000 4350 +Wire Wire Line + 6600 3000 6600 4350 +Connection ~ 6200 3000 +Wire Wire Line + 6600 3000 6200 3000 +Connection ~ 4050 3950 +Wire Wire Line + 3850 3100 4400 3100 +Connection ~ 4050 3100 +Wire Wire Line + 4050 3450 4050 2650 +Connection ~ 4700 1700 +Wire Wire Line + 4050 1700 4050 2150 +Connection ~ 6200 3950 +Wire Wire Line + 6200 3550 6200 3950 +Wire Wire Line + 6900 2450 7050 2450 +Wire Wire Line + 5200 3450 5200 3400 +Connection ~ 4700 3400 +Wire Wire Line + 5200 3400 4700 3400 +Wire Wire Line + 4700 3300 4700 3450 +Wire Wire Line + 6200 2500 6200 2350 +Wire Wire Line + 4700 2600 4700 2900 +Wire Wire Line + 5900 2700 4700 2700 +Connection ~ 4700 2700 +Wire Wire Line + 6200 2450 6500 2450 +Connection ~ 6200 2450 +Wire Wire Line + 6200 2900 6200 3050 +Wire Wire Line + 5200 3950 5200 3850 +Wire Wire Line + 7050 3950 7050 2950 +Connection ~ 5200 3950 +Wire Wire Line + 4700 1700 4700 2100 +Wire Wire Line + 6200 1700 6200 1850 +Connection ~ 4700 3950 +Wire Wire Line + 3450 3100 3250 3100 +Wire Wire Line + 6600 4350 5600 4350 +Wire Wire Line + 4500 4350 3950 4350 +Wire Wire Line + 3950 4350 3950 3100 +Connection ~ 3950 3100 +Wire Wire Line + 7500 3300 7500 3950 +Wire Wire Line + 7500 3950 2750 3950 +Connection ~ 7050 3950 +Wire Wire Line + 2750 3950 2750 4000 +Wire Wire Line + 2750 4000 2500 4000 +$Comp +L SINE v1 +U 1 1 5176244C +P 2500 3550 +F 0 "v1" H 2300 3650 60 0000 C CNN +F 1 "SINE" H 2300 3500 60 0000 C CNN +F 2 "R1" H 2200 3550 60 0000 C CNN + 1 2500 3550 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 51761AB3 +P 4750 4350 +F 0 "R6" V 4830 4350 50 0000 C CNN +F 1 "10k" V 4750 4350 50 0000 C CNN + 1 4750 4350 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 51761A46 +P 3000 3100 +F 0 "R1" V 3080 3100 50 0000 C CNN +F 1 "10k" V 3000 3100 50 0000 C CNN + 1 3000 3100 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 51761A2D +P 3650 3100 +F 0 "C1" H 3700 3200 50 0000 L CNN +F 1 "1m" H 3700 3000 50 0000 L CNN + 1 3650 3100 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 51761A14 +P 4050 3700 +F 0 "R3" V 4130 3700 50 0000 C CNN +F 1 "15k" V 4050 3700 50 0000 C CNN + 1 4050 3700 + 1 0 0 -1 +$EndComp +$Comp +L R R9 +U 1 1 517619D2 +P 7050 2700 +F 0 "R9" V 7130 2700 50 0000 C CNN +F 1 "1k" V 7050 2700 50 0000 C CNN + 1 7050 2700 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 517619B5 +P 5200 3650 +F 0 "C2" H 5250 3750 50 0000 L CNN +F 1 "1m" H 5250 3550 50 0000 L CNN + 1 5200 3650 + 1 0 0 -1 +$EndComp +$Comp +L R R7 +U 1 1 517619A1 +P 6200 2100 +F 0 "R7" V 6280 2100 50 0000 C CNN +F 1 "8k" V 6200 2100 50 0000 C CNN + 1 6200 2100 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 5176198B +P 6200 3300 +F 0 "R8" V 6280 3300 50 0000 C CNN +F 1 "3.4k" V 6200 3300 50 0000 C CNN + 1 6200 3300 + 1 0 0 -1 +$EndComp +$Comp +L C C4 +U 1 1 5176197A +P 6700 2450 +F 0 "C4" H 6750 2550 50 0000 L CNN +F 1 "1m" H 6750 2350 50 0000 L CNN + 1 6700 2450 + 0 1 1 0 +$EndComp +$Comp +L R R5 +U 1 1 51761974 +P 4700 3700 +F 0 "R5" V 4780 3700 50 0000 C CNN +F 1 "870" V 4700 3700 50 0000 C CNN + 1 4700 3700 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 51761961 +P 4700 2350 +F 0 "R4" V 4780 2350 50 0000 C CNN +F 1 "10k" V 4700 2350 50 0000 C CNN + 1 4700 2350 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5176195A +P 7500 2850 +F 0 "v2" H 7300 2950 60 0000 C CNN +F 1 "12" H 7300 2800 60 0000 C CNN +F 2 "R1" H 7200 2850 60 0000 C CNN + 1 7500 2850 + 1 0 0 -1 +$EndComp +$Comp +L C C3 +U 1 1 51761951 +P 5400 4350 +F 0 "C3" H 5450 4450 50 0000 L CNN +F 1 "1m" H 5450 4250 50 0000 L CNN + 1 5400 4350 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5176194E +P 4050 2400 +F 0 "R2" V 4130 2400 50 0000 C CNN +F 1 "100k" V 4050 2400 50 0000 C CNN + 1 4050 2400 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q2 +U 1 1 5176191C +P 6100 2700 +F 0 "Q2" H 6100 2550 50 0000 R CNN +F 1 "NPN" H 6100 2850 50 0000 R CNN + 1 6100 2700 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 517618FE +P 4600 3100 +F 0 "Q1" H 4600 2950 50 0000 R CNN +F 1 "NPN" H 4600 3250 50 0000 R CNN + 1 4600 3100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis new file mode 100644 index 0000000..0e8f996 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis @@ -0,0 +1 @@ +.tran 2e-03 20e-03 0e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak new file mode 100644 index 0000000..6eed972 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 25 April 2013 11:20:04 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# Idc +# +DEF Idc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "Idc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib new file mode 100644 index 0000000..008a8d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 26 April 2013 04:42:05 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# Idc +# +DEF Idc i 0 40 Y Y 1 F N +F0 "i" -200 100 60 H V C CNN +F1 "Idc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# vplot8 +# +DEF vplot8 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -300 0 200 R 40 40 1 1 O +X - 9 300 0 200 L 40 40 1 1 O +X + 2 -300 0 200 R 40 40 2 1 O +X - 10 300 0 200 L 40 40 2 1 O +X + 3 -300 0 200 R 40 40 3 1 O +X - 11 300 0 200 L 40 40 3 1 O +X + 4 -300 0 200 R 40 40 4 1 O +X - 12 300 0 200 L 40 40 4 1 O +X + 5 -300 0 200 R 40 40 5 1 O +X - 13 300 0 200 L 40 40 5 1 O +X + 6 -300 0 200 R 40 40 6 1 O +X - 14 300 0 200 L 40 40 6 1 O +X + 7 -300 0 200 R 40 40 7 1 O +X - 15 300 0 200 L 40 40 7 1 O +X + 8 -300 0 200 R 40 40 8 1 O +X - 16 300 0 200 L 40 40 8 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak new file mode 100644 index 0000000..a480fc4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 date Thursday 25 April 2013 11:20:04 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_8-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "25 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 4700 4600 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5178C3EF +P 4700 4600 +F 0 "#FLG01" H 4700 4870 30 0001 C CNN +F 1 "PWR_FLAG" H 4700 4830 30 0000 C CNN + 1 4700 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5178C3E3 +P 4700 4700 +F 0 "#PWR02" H 4700 4700 30 0001 C CNN +F 1 "GND" H 4700 4630 30 0001 C CNN + 1 4700 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 4500 4700 4700 +Connection ~ 5800 2350 +Wire Wire Line + 5600 2350 5800 2350 +Wire Wire Line + 3600 4250 3600 5000 +Wire Wire Line + 6100 2700 6100 5000 +Wire Wire Line + 6600 3750 6600 4750 +Wire Wire Line + 6600 4750 5300 4750 +Wire Wire Line + 4450 2700 4100 2700 +Wire Wire Line + 4750 1650 5800 1650 +Wire Wire Line + 5800 2900 5800 3200 +Wire Wire Line + 4750 2900 4750 3200 +Wire Wire Line + 4750 2150 4750 2500 +Wire Wire Line + 5800 2150 5800 2500 +Wire Wire Line + 5800 3700 4750 3700 +Wire Wire Line + 6100 5000 4100 5000 +Wire Wire Line + 5300 3700 5300 3850 +Connection ~ 5300 3700 +Wire Wire Line + 5750 1650 5750 1400 +Connection ~ 5750 1650 +Wire Wire Line + 5750 1400 6600 1400 +Wire Wire Line + 6600 1400 6600 2850 +Wire Wire Line + 3600 2700 3600 3350 +Wire Wire Line + 5000 2350 4750 2350 +Connection ~ 4750 2350 +Wire Wire Line + 5300 3800 4700 3800 +Connection ~ 5300 3800 +Wire Wire Line + 4700 3800 4700 4000 +$Comp +L R R7 +U 1 1 5178C3D2 +P 4700 4250 +F 0 "R7" V 4780 4250 50 0000 C CNN +F 1 "150" V 4700 4250 50 0000 C CNN + 1 4700 4250 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 5178C33C +P 3600 3800 +F 0 "v1" H 3400 3900 60 0000 C CNN +F 1 "SINE" H 3400 3750 60 0000 C CNN +F 2 "R1" H 3300 3800 60 0000 C CNN + 1 3600 3800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8 U1 +U 1 1 51779652 +P 5300 2350 +F 0 "U1" H 5150 2450 50 0000 C CNN +F 1 "VPLOT8" H 5450 2450 50 0000 C CNN + 1 5300 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 517794FF +P 3850 2700 +F 0 "R1" V 3930 2700 50 0000 C CNN +F 1 "5k" V 3850 2700 50 0000 C CNN + 1 3850 2700 + 0 1 1 0 +$EndComp +$Comp +L R R6 +U 1 1 517794EA +P 5800 3450 +F 0 "R6" V 5880 3450 50 0000 C CNN +F 1 "150" V 5800 3450 50 0000 C CNN + 1 5800 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 517794E3 +P 4750 3450 +F 0 "R4" V 4830 3450 50 0000 C CNN +F 1 "150" V 4750 3450 50 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 517794C9 +P 5800 1900 +F 0 "R5" V 5880 1900 50 0000 C CNN +F 1 "10k" V 5800 1900 50 0000 C CNN + 1 5800 1900 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 517794BE +P 4750 1900 +F 0 "R3" V 4830 1900 50 0000 C CNN +F 1 "10k" V 4750 1900 50 0000 C CNN + 1 4750 1900 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q2 +U 1 1 5177949E +P 5900 2700 +F 0 "Q2" H 5900 2550 50 0000 R CNN +F 1 "NPN" H 5900 2850 50 0000 R CNN + 1 5900 2700 + -1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 51779433 +P 3850 5000 +F 0 "R2" V 3930 5000 50 0000 C CNN +F 1 "R" V 3850 5000 50 0000 C CNN + 1 3850 5000 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 51779424 +P 6600 3300 +F 0 "v3" H 6400 3400 60 0000 C CNN +F 1 "15" H 6400 3250 60 0000 C CNN +F 2 "R1" H 6300 3300 60 0000 C CNN + 1 6600 3300 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 51779415 +P 4650 2700 +F 0 "Q1" H 4650 2550 50 0000 R CNN +F 1 "NPN" H 4650 2850 50 0000 R CNN + 1 4650 2700 + 1 0 0 -1 +$EndComp +$Comp +L IDC v2 +U 1 1 5177940C +P 5300 4300 +F 0 "v2" H 5100 4400 60 0000 C CNN +F 1 "1m" H 5100 4250 60 0000 C CNN +F 2 "R1" H 5000 4300 60 0000 C CNN + 1 5300 4300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir new file mode 100644 index 0000000..b1cc053 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir @@ -0,0 +1,21 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 25 April 2013 11:19:59 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R7 9 0 150 +v1 2 5 SINE +U1 1 11 VPLOT8 +R1 8 2 5k +R6 3 9 150 +R4 7 9 150 +R5 12 11 10k +R3 12 1 10k +Q2 3 4 11 NPN +R2 4 5 R +v3 12 6 15 +Q1 7 8 1 NPN +v2 9 6 1m + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt new file mode 100644 index 0000000..d42cb97 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 11:19:59 am ist + +r7 9 0 150 +v1 2 5 sine( 5 50 ) +r1 8 2 5k +r6 3 9 150 +r4 7 9 150 +r5 12 11 10k +r3 12 1 10k +q2 11 4 3 npn +r2 4 5 r +v3 12 6 15 +q1 1 8 7 npn +v2 9 6 1m + +.tran 2e-03 20e-03 0e-00 +.plot v(1)-v(11) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out new file mode 100644 index 0000000..95b8ceb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 11:19:59 am ist + +r7 9 0 150 +v1 2 5 sine( 5 50 ) +r1 8 2 5k +r6 3 9 150 +r4 7 9 150 +r5 12 11 10k +r3 12 1 10k +q2 11 4 3 npn +r2 4 5 r +v3 12 6 15 +q1 1 8 7 npn +v2 9 6 1m + +.tran 2e-03 20e-03 0e-00 + +* Control Statements +.control +run +plot v(1)-v(11) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro new file mode 100644 index 0000000..71bd9f1 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro @@ -0,0 +1,74 @@ +update=Thursday 18 April 2013 03:16:09 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj new file mode 100644 index 0000000..fe0de23 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj @@ -0,0 +1 @@ +schematicFile example_8.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch new file mode 100644 index 0000000..06b9dfa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 date Friday 26 April 2013 04:42:05 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_8.1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "26 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5450 5400 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5178C3EF +P 5450 5400 +F 0 "#FLG01" H 5450 5670 30 0001 C CNN +F 1 "PWR_FLAG" H 5450 5630 30 0000 C CNN + 1 5450 5400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5178C3E3 +P 5450 5500 +F 0 "#PWR02" H 5450 5500 30 0001 C CNN +F 1 "GND" H 5450 5430 30 0001 C CNN + 1 5450 5500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 5300 5450 5500 +Connection ~ 6550 3150 +Wire Wire Line + 6350 3150 6550 3150 +Wire Wire Line + 4350 5050 4350 5800 +Wire Wire Line + 6850 3500 6850 5800 +Wire Wire Line + 7350 4550 7350 5550 +Wire Wire Line + 7350 5550 6050 5550 +Wire Wire Line + 5200 3500 4850 3500 +Wire Wire Line + 5500 2450 6550 2450 +Wire Wire Line + 6550 3700 6550 4000 +Wire Wire Line + 5500 3700 5500 4000 +Wire Wire Line + 5500 2950 5500 3300 +Wire Wire Line + 6550 2950 6550 3300 +Wire Wire Line + 6550 4500 5500 4500 +Wire Wire Line + 6850 5800 4850 5800 +Wire Wire Line + 6050 4500 6050 4650 +Connection ~ 6050 4500 +Wire Wire Line + 6500 2450 6500 2200 +Connection ~ 6500 2450 +Wire Wire Line + 6500 2200 7350 2200 +Wire Wire Line + 7350 2200 7350 3650 +Wire Wire Line + 4350 3500 4350 4150 +Wire Wire Line + 5750 3150 5500 3150 +Connection ~ 5500 3150 +Wire Wire Line + 6050 4600 5450 4600 +Connection ~ 6050 4600 +Wire Wire Line + 5450 4600 5450 4800 +$Comp +L R R7 +U 1 1 5178C3D2 +P 5450 5050 +F 0 "R7" V 5530 5050 50 0000 C CNN +F 1 "150" V 5450 5050 50 0000 C CNN + 1 5450 5050 + 1 0 0 -1 +$EndComp +$Comp +L SINE v1 +U 1 1 5178C33C +P 4350 4600 +F 0 "v1" H 4150 4700 60 0000 C CNN +F 1 "SINE" H 4150 4550 60 0000 C CNN +F 2 "R1" H 4050 4600 60 0000 C CNN + 1 4350 4600 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8 U1 +U 1 1 51779652 +P 6050 3150 +F 0 "U1" H 5900 3250 50 0000 C CNN +F 1 "VPLOT8" H 6200 3250 50 0000 C CNN + 1 6050 3150 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 517794FF +P 4600 3500 +F 0 "R1" V 4680 3500 50 0000 C CNN +F 1 "5k" V 4600 3500 50 0000 C CNN + 1 4600 3500 + 0 1 1 0 +$EndComp +$Comp +L R R6 +U 1 1 517794EA +P 6550 4250 +F 0 "R6" V 6630 4250 50 0000 C CNN +F 1 "150" V 6550 4250 50 0000 C CNN + 1 6550 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 517794E3 +P 5500 4250 +F 0 "R4" V 5580 4250 50 0000 C CNN +F 1 "150" V 5500 4250 50 0000 C CNN + 1 5500 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 517794C9 +P 6550 2700 +F 0 "R5" V 6630 2700 50 0000 C CNN +F 1 "10k" V 6550 2700 50 0000 C CNN + 1 6550 2700 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 517794BE +P 5500 2700 +F 0 "R3" V 5580 2700 50 0000 C CNN +F 1 "10k" V 5500 2700 50 0000 C CNN + 1 5500 2700 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q2 +U 1 1 5177949E +P 6650 3500 +F 0 "Q2" H 6650 3350 50 0000 R CNN +F 1 "NPN" H 6650 3650 50 0000 R CNN + 1 6650 3500 + -1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 51779433 +P 4600 5800 +F 0 "R2" V 4680 5800 50 0000 C CNN +F 1 "R" V 4600 5800 50 0000 C CNN + 1 4600 5800 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 51779424 +P 7350 4100 +F 0 "v3" H 7150 4200 60 0000 C CNN +F 1 "15" H 7150 4050 60 0000 C CNN +F 2 "R1" H 7050 4100 60 0000 C CNN + 1 7350 4100 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 51779415 +P 5400 3500 +F 0 "Q1" H 5400 3350 50 0000 R CNN +F 1 "NPN" H 5400 3650 50 0000 R CNN + 1 5400 3500 + 1 0 0 -1 +$EndComp +$Comp +L IDC v2 +U 1 1 5177940C +P 6050 5100 +F 0 "v2" H 5850 5200 60 0000 C CNN +F 1 "1m" H 5850 5050 60 0000 C CNN +F 2 "R1" H 5750 5100 60 0000 C CNN + 1 6050 5100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis new file mode 100644 index 0000000..722124c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 15e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib Binary files differnew file mode 100644 index 0000000..e93b428 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir new file mode 100644 index 0000000..7f3611e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir @@ -0,0 +1,41 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 29 April 2013 11:24:11 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 0 25 0 21 25 24 22 21 VPLOT8_1 +U13 23 VPLOT8_1 +v2 0 8 15 +U14 12 6 IPLOT +U11 5 18 IPLOT +R7 7 8 3k +U15 9 7 IPLOT +Q9 9 23 6 NPN +U12 23 1 IPLOT +R6 1 8 15.7k +U9 2 8 IPLOT +U6 11 8 IPLOT +U2 10 8 IPLOT +Q6 2 25 4 NPN +U8 3 4 IPLOT +R5 12 5 2.3k +U10 19 22 IPLOT +U7 13 21 IPLOT +U4 14 24 IPLOT +U5 15 16 IPLOT +U1 17 25 IPLOT +Q8 23 22 18 NPN +R4 12 19 3k +Q7 3 21 22 NPN +Q5 3 24 12 NPN +R1 0 17 28.6k +Q1 10 25 25 NPN +Q3 11 25 16 NPN +R3 12 13 20k +Q4 15 0 21 NPN +v1 12 0 15 +R2 12 14 20k +Q2 15 0 24 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt new file mode 100644 index 0000000..14076b8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt @@ -0,0 +1,53 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 29 april 2013 11:24:11 am ist
+
+* Plotting option vplot8_1
+* Plotting option vplot8_1
+v2 0 8 15
+V_u14 12 6 0
+V_u11 5 18 0
+r7 7 8 3k
+V_u15 9 7 0
+q9 6 23 9 npn
+V_u12 23 1 0
+r6 1 8 15.7k
+V_u9 2 8 0
+V_u6 11 8 0
+V_u2 10 8 0
+q6 4 25 2 npn
+V_u8 3 4 0
+r5 12 5 2.3k
+V_u10 19 22 0
+V_u7 13 21 0
+V_u4 14 24 0
+V_u5 15 16 0
+V_u1 17 25 0
+q8 18 22 23 npn
+r4 12 19 3k
+q7 22 21 3 npn
+q5 12 24 3 npn
+r1 0 17 28.6k
+q1 25 25 10 npn
+q3 16 25 11 npn
+r3 12 13 20k
+q4 21 0 15 npn
+v1 12 0 15
+r2 12 14 20k
+q2 24 0 15 npn
+
+.dc v1 0e-00 15e-00 1e-00
+.plot v(0) v(25) v(0) v(21) v(25) v(24) v(22) v(21)
+.plot v(23)
+.plot i(V_u14)
+.plot i(V_u11)
+.plot i(V_u15)
+.plot i(V_u12)
+.plot i(V_u9)
+.plot i(V_u6)
+.plot i(V_u2)
+.plot i(V_u8)
+.plot i(V_u10)
+.plot i(V_u7)
+.plot i(V_u4)
+.plot i(V_u5)
+.plot i(V_u1)
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out new file mode 100644 index 0000000..a08c832 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out @@ -0,0 +1,58 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 29 april 2013 11:24:11 am ist
+
+* Plotting option vplot8_1
+* Plotting option vplot8_1
+v2 0 8 15
+V_u14 12 6 0
+V_u11 5 18 0
+r7 7 8 3k
+V_u15 9 7 0
+q9 6 23 9 npn
+V_u12 23 1 0
+r6 1 8 15.7k
+V_u9 2 8 0
+V_u6 11 8 0
+V_u2 10 8 0
+q6 4 25 2 npn
+V_u8 3 4 0
+r5 12 5 2.3k
+V_u10 19 22 0
+V_u7 13 21 0
+V_u4 14 24 0
+V_u5 15 16 0
+V_u1 17 25 0
+q8 18 22 23 npn
+r4 12 19 3k
+q7 22 21 3 npn
+q5 12 24 3 npn
+r1 0 17 28.6k
+q1 25 25 10 npn
+q3 16 25 11 npn
+r3 12 13 20k
+q4 21 0 15 npn
+v1 12 0 15
+r2 12 14 20k
+q2 24 0 15 npn
+
+.dc v1 0e-00 15e-00 1e-00
+
+* Control Statements
+.control
+run
+plot v(0) v(25) v(0) v(21) v(25) v(24) v(22) v(21)
+plot v(23)
+plot i(V_u14)
+plot i(V_u11)
+plot i(V_u15)
+plot i(V_u12)
+plot i(V_u9)
+plot i(V_u6)
+plot i(V_u2)
+plot i(V_u8)
+plot i(V_u10)
+plot i(V_u7)
+plot i(V_u4)
+plot i(V_u5)
+plot i(V_u1)
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro new file mode 100644 index 0000000..767e17f --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro @@ -0,0 +1,74 @@ +update=Monday 29 April 2013 10:50:36 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip 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b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj @@ -0,0 +1 @@ +schematicFile example_8.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch new file mode 100644 index 0000000..cc68262 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch @@ -0,0 +1,573 @@ +EESchema Schematic File Version 2 date Monday 29 April 2013 11:24:17 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice 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b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt new file mode 100644 index 0000000..cb5beb4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt @@ -0,0 +1,22 @@ +* CD4007 NMOS and PMOS transistor SPICE models + +* Typical - Typical Condition + +.model MbreakND NMOS ++ Level=1 Gamma= 0 Xj=0 ++ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=1.4 Lambda=0.01 ++ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p ++ Cgdo=0.1p Is=16.64p N=1 + +*The default W and L is 30 and 10 um respectively and AD and AS +*should not be included. + + +.model MbreakPD PMOS ++ Level=1 Gamma= 0 Xj=0 ++ Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=-1.2 Lambda=0.04 ++ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p ++ Cgdo=0.2p Is=16.64p N=1 + +*The default W and L is 60 and 10 um respectively and AD and AS +*should not be included. diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak new file mode 100644 index 0000000..cc8bedb --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak @@ -0,0 +1,118 @@ +EESchema-LIBRARY Version 2.3 Date: Friday 10 May 2013 04:54:25 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N M 0 0 N Y 1 F N +F0 "M" 10 170 60 H V R CNN +F1 "MOS_N" 10 -150 60 H V R CNN +ALIAS MOSFET_N +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 8 100 -100 100 0 50 0 N +P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# MOS_P +# +DEF MOS_P M 0 40 Y N 1 F N +F0 "M" 0 190 60 H V R CNN +F1 "MOS_P" 0 -180 60 H V R CNN +ALIAS MOSFET_P +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 8 30 0 0 0 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 0 80 0 100 0 100 -100 N +P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# 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Version 2.3 Date: Thursday 16 May 2013 11:24:57 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N M 0 0 N Y 1 F N +F0 "M" 10 170 60 H V R CNN +F1 "MOS_N" 10 -150 60 H V R CNN +ALIAS MOSFET_N +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 8 100 -100 100 0 50 0 N +P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# MOS_P +# +DEF MOS_P M 0 40 Y N 1 F N +F0 "M" 0 190 60 H V R CNN +F1 "MOS_P" 0 -180 60 H V R CNN +ALIAS MOSFET_P +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 8 30 0 0 0 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 0 80 0 100 0 100 -100 N +P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak new file mode 100644 index 0000000..e14fb9e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak @@ -0,0 +1,194 @@ +EESchema Schematic File Version 2 date Friday 10 May 2013 04:54:25 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_9.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "10 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5750 3600 +Wire Wire Line + 5750 3600 5300 3600 +Wire Wire Line + 5300 3600 5300 3850 +Connection ~ 5600 3450 +Wire Wire Line + 5600 3650 5600 3450 +Wire Wire Line + 6050 3450 6400 3450 +Connection ~ 6050 4300 +Wire Wire Line + 6050 4050 6050 4350 +Wire Wire Line + 6050 4350 5100 4350 +Wire Wire Line + 6650 3900 6650 4300 +Wire Wire Line + 6050 2850 6050 2700 +Wire Wire Line + 6050 3250 6050 3650 +Wire Wire Line + 5750 3050 5750 3850 +Connection ~ 6050 3450 +Wire Wire Line + 6400 3450 6400 3750 +Connection ~ 6400 4300 +Wire Wire Line + 6050 2700 6650 2700 +Wire Wire Line + 6650 2700 6650 3000 +Wire Wire Line + 5750 3450 5100 3450 +Connection ~ 5750 3450 +Wire Wire Line + 5100 3450 5100 3550 +Wire Wire Line + 6400 4400 6400 4150 +Connection ~ 5500 3450 +Wire Wire Line + 6650 4300 6050 4300 +Connection ~ 6200 3450 +Wire Wire Line + 5600 4050 5600 4350 +Connection ~ 5600 4350 +$Comp +L MOS_N M3 +U 1 1 518CD8BE +P 5500 3850 +F 0 "M3" H 5510 4020 60 0000 R CNN +F 1 "MOS_N" H 5510 3700 60 0000 R CNN + 1 5500 3850 + 1 0 0 -1 +$EndComp +$Comp +L MOS_P M1 +U 1 1 5188E486 +P 5950 3050 +F 0 "M1" H 5950 3240 60 0000 R CNN +F 1 "MOS_P" H 5950 2870 60 0000 R CNN + 1 5950 3050 + 1 0 0 1 +$EndComp +$Comp +L MOS_N M2 +U 1 1 5188E477 +P 5950 3850 +F 0 "M2" H 5960 4020 60 0000 R CNN +F 1 "MOS_N" H 5960 3700 60 0000 R CNN + 1 5950 3850 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 5188E0A2 +P 6200 3150 +F 0 "U2" H 6050 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 6350 3250 50 0000 C CNN + 2 6200 3150 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5188E094 +P 6400 4300 +F 0 "#FLG01" H 6400 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 6400 4530 30 0000 C CNN + 1 6400 4300 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 517F5425 +P 6650 3450 +F 0 "v2" H 6450 3550 60 0000 C CNN +F 1 "10" H 6450 3400 60 0000 C CNN +F 2 "R1" H 6350 3450 60 0000 C CNN + 1 6650 3450 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 517F5879 +P 5500 3150 +F 0 "U2" H 5350 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 5650 3250 50 0000 C CNN + 1 5500 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 517F5470 +P 6400 4400 +F 0 "#PWR02" H 6400 4400 30 0001 C CNN +F 1 "GND" H 6400 4330 30 0001 C CNN + 1 6400 4400 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 517F544C +P 5100 3900 +F 0 "v1" H 4900 4000 60 0000 C CNN +F 1 "DC" H 4900 3850 60 0000 C CNN +F 2 "R1" H 4800 3900 60 0000 C CNN + 1 5100 3900 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 517F53E7 +P 6400 3950 +F 0 "C1" H 6450 4050 50 0000 L CNN +F 1 ".5p" H 6450 3850 50 0000 L CNN + 1 6400 3950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir new file mode 100644 index 0000000..f3aa33e --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir @@ -0,0 +1,14 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 16 May 2013 11:24:53 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +M1 4 3 1 MOS_P +M2 4 3 0 MOS_N +U2 3 4 VPLOT8_1 +v2 1 0 10 +v1 3 0 DC +C1 4 0 .5p + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt new file mode 100644 index 0000000..0699b0a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:24:53 am ist +.include mos_p.lib +.include mos_n.lib + +m1 4 3 1 1 mos_p +m2 4 3 0 0 mos_n +* Plotting option vplot8_1 +v2 1 0 10 +v1 3 0 dc 10 +c1 4 0 .5p + +.dc v1 0e-00 10e-00 1e-00 +.plot v(3) v(4) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out new file mode 100644 index 0000000..4fc3ec2 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:24:53 am ist +.include mos_p.lib +.include mos_n.lib + +m1 4 3 1 1 mos_p +m2 4 3 0 0 mos_n +* Plotting option vplot8_1 +v2 1 0 10 +v1 3 0 dc 10 +c1 4 0 .5p + +.dc v1 0e-00 10e-00 1e-00 + +* Control Statements +.control +run +plot v(3) v(4) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro new file mode 100644 index 0000000..d4ca737 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro @@ -0,0 +1,74 @@ +update=Tuesday 30 April 2013 10:42:25 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj new file mode 100644 index 0000000..8fac45c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj @@ -0,0 +1 @@ +schematicFile example_9.4.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch new file mode 100644 index 0000000..de8111b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 date Thursday 16 May 2013 11:24:57 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_9.4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5750 3600 +Wire Wire Line + 6050 3450 6400 3450 +Connection ~ 6050 4300 +Wire Wire Line + 6050 4050 6050 4350 +Wire Wire Line + 6050 4350 5100 4350 +Wire Wire Line + 6650 3900 6650 4300 +Wire Wire Line + 6050 2850 6050 2700 +Wire Wire Line + 6050 3250 6050 3650 +Wire Wire Line + 5750 3050 5750 3850 +Connection ~ 6050 3450 +Wire Wire Line + 6400 3450 6400 3750 +Connection ~ 6400 4300 +Wire Wire Line + 6050 2700 6650 2700 +Wire Wire Line + 6650 2700 6650 3000 +Wire Wire Line + 5750 3450 5100 3450 +Connection ~ 5750 3450 +Wire Wire Line + 5100 3450 5100 3550 +Wire Wire Line + 6400 4400 6400 4150 +Connection ~ 5500 3450 +Wire Wire Line + 6650 4300 6050 4300 +Connection ~ 6200 3450 +$Comp +L MOS_P M1 +U 1 1 5188E486 +P 5950 3050 +F 0 "M1" H 5950 3240 60 0000 R CNN +F 1 "MOS_P" H 5950 2870 60 0000 R CNN + 1 5950 3050 + 1 0 0 1 +$EndComp +$Comp +L MOS_N M2 +U 1 1 5188E477 +P 5950 3850 +F 0 "M2" H 5960 4020 60 0000 R CNN +F 1 "MOS_N" H 5960 3700 60 0000 R CNN + 1 5950 3850 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 5188E0A2 +P 6200 3150 +F 0 "U2" H 6050 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 6350 3250 50 0000 C CNN + 2 6200 3150 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5188E094 +P 6400 4300 +F 0 "#FLG01" H 6400 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 6400 4530 30 0000 C CNN + 1 6400 4300 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 517F5425 +P 6650 3450 +F 0 "v2" H 6450 3550 60 0000 C CNN +F 1 "10" H 6450 3400 60 0000 C CNN +F 2 "R1" H 6350 3450 60 0000 C CNN + 1 6650 3450 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 517F5879 +P 5500 3150 +F 0 "U2" H 5350 3250 50 0000 C CNN +F 1 "VPLOT8_1" H 5650 3250 50 0000 C CNN + 1 5500 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 517F5470 +P 6400 4400 +F 0 "#PWR02" H 6400 4400 30 0001 C CNN +F 1 "GND" H 6400 4330 30 0001 C CNN + 1 6400 4400 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 517F544C +P 5100 3900 +F 0 "v1" H 4900 4000 60 0000 C CNN +F 1 "DC" H 4900 3850 60 0000 C CNN +F 2 "R1" H 4800 3900 60 0000 C CNN + 1 5100 3900 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 517F53E7 +P 6400 3950 +F 0 "C1" H 6450 4050 50 0000 L CNN +F 1 ".5p" H 6450 3850 50 0000 L CNN + 1 6400 3950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib new file mode 100644 index 0000000..23ac1f6 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( Cgso=877.2p Tox=100n Rs=70.6m Tt=140n Vto=-3.67 ++ Pb=.8 Rg=.811 Theta=0 Phi=.6 Fc=.5 ++ Delta=0 Vmax=0 Kappa=0 Rds=444.4K Level=3 ++ L=2u Mj=.5 Uo=300 Eta=0 W=1.9 ++ Cgdo=369.3p Gamma=0 Xj=0 Rd=60.66m Cbd=2.141n ++ Is=52.23E-18 N=2 Kp=10.15u ) diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib new file mode 100644 index 0000000..2c58d87 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( Cgso=877.2p Tox=100n Rs=70.6m Tt=140n Vto=-3.67 ++ Pb=.8 Rg=.811 Theta=0 Phi=.6 Fc=.5 ++ Delta=0 Vmax=0 Kappa=0 Rds=444.4K Level=3 ++ L=2u Mj=.5 Uo=300 Eta=0 W=1.9 ++ Cgdo=369.3p Gamma=0 Xj=0 Rd=60.66m Cbd=2.141n ++ Is=52.23E-18 N=2 Kp=10.15u )
\ No newline at end of file diff --git a/OSCAD/Examples/simpleTTL/analysis b/OSCAD/Examples/simpleTTL/analysis new file mode 100644 index 0000000..bf5e632 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/analysis @@ -0,0 +1 @@ +.tran 10e-09 1e-06 0e-00 diff --git a/OSCAD/Examples/simpleTTL/simpleTTL-cache.bak b/OSCAD/Examples/simpleTTL/simpleTTL-cache.bak new file mode 100644 index 0000000..4bb51e9 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL-cache.bak @@ -0,0 +1,148 @@ +EESchema-LIBRARY Version 2.3 Date: Thursday 20 December 2012 12:04:47 AM IST +#encoding utf-8 +# +# 74LS00 +# +DEF 74LS00 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS00" 0 -100 60 H V C CNN +ALIAS 74LS37 7400 74HCT00 74HC00 +$FPLIST + 14DIP300* + SO14* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A 100 0 200 -899 899 0 1 0 N 100 -200 100 200 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O I +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O I +X ~ 8 600 0 300 L 60 60 3 1 O I +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O I +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -465 0 259 504 -504 0 2 0 N -300 200 -300 -200 +A -11 143 343 -881 -246 0 2 0 N 0 -200 300 0 +A -10 -141 340 244 883 0 2 0 N 300 0 0 200 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O +X ~ 8 600 0 300 L 60 60 3 2 O +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/simpleTTL/simpleTTL-cache.lib b/OSCAD/Examples/simpleTTL/simpleTTL-cache.lib new file mode 100644 index 0000000..bd572f0 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL-cache.lib @@ -0,0 +1,148 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 02 April 2013 03:01:00 PM IST +#encoding utf-8 +# +# 74LS00 +# +DEF 74LS00 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS00" 0 -100 60 H V C CNN +ALIAS 74LS37 7400 74HCT00 74HC00 +$FPLIST + 14DIP300* + SO14* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A 100 0 200 -899 899 0 1 0 N 100 -200 100 200 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O I +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O I +X ~ 8 600 0 300 L 60 60 3 1 O I +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O I +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -465 0 259 504 -504 0 2 0 N -300 200 -300 -200 +A -11 143 343 -881 -246 0 2 0 N 0 -200 300 0 +A -10 -141 340 244 883 0 2 0 N 300 0 0 200 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O +X ~ 8 600 0 300 L 60 60 3 2 O +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.bak b/OSCAD/Examples/simpleTTL/simpleTTL.bak new file mode 100644 index 0000000..2bf0b11 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.bak @@ -0,0 +1,166 @@ +EESchema Schematic File Version 2 date Thursday 20 December 2012 12:04:47 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:analogXSpice +LIBS:simpleTTL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5550 3450 +Wire Wire Line + 5550 3300 5550 3600 +Wire Wire Line + 2950 4600 5550 4600 +Connection ~ 4500 4600 +Wire Wire Line + 4500 4300 4500 4600 +Wire Wire Line + 3700 4600 3700 4450 +Connection ~ 2950 4600 +Wire Wire Line + 2950 3350 4150 3350 +Wire Wire Line + 2950 4250 2950 4800 +Wire Wire Line + 3700 3550 4150 3550 +Connection ~ 3700 4600 +Wire Wire Line + 4550 2900 4550 3250 +Wire Wire Line + 3450 3350 3450 3250 +Connection ~ 3450 3350 +Wire Wire Line + 5550 3450 5350 3450 +Wire Wire Line + 5550 4600 5550 4100 +$Comp +L VPLOT8_1 U2 +U 2 1 50CEBA04 +P 5550 3000 +F 0 "U2" H 5400 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5700 3100 50 0000 C CNN + 2 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 50CEBA01 +P 3450 2950 +F 0 "U2" H 3300 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 3600 3050 50 0000 C CNN + 1 3450 2950 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50862FAD +P 4550 2900 +F 0 "#FLG01" H 4550 3170 30 0001 C CNN +F 1 "PWR_FLAG" H 4550 3130 30 0000 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 50862FA6 +P 4500 4300 +F 0 "#FLG02" H 4500 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 4500 4530 30 0000 C CNN + 1 4500 4300 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50862F73 +P 5550 3850 +F 0 "R1" V 5630 3850 50 0000 C CNN +F 1 "1000" V 5550 3850 50 0000 C CNN + 1 5550 3850 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 50862F55 +P 2950 3800 +F 0 "v1" H 2750 3900 60 0000 C CNN +F 1 "PULSE" H 2750 3750 60 0000 C CNN +F 2 "R1" H 2650 3800 60 0000 C CNN + 1 2950 3800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 50862CF3 +P 2950 4800 +F 0 "#PWR03" H 2950 4800 30 0001 C CNN +F 1 "GND" H 2950 4730 30 0001 C CNN + 1 2950 4800 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 50862BA3 +P 3700 4000 +F 0 "v2" H 3500 4100 60 0000 C CNN +F 1 "5" H 3500 3950 60 0000 C CNN +F 2 "R1" H 3400 4000 60 0000 C CNN + 1 3700 4000 + 1 0 0 -1 +$EndComp +$Comp +L 7400 U1 +U 3 1 50862B5B +P 4750 3450 +F 0 "U1" H 4750 3500 60 0000 C CNN +F 1 "7400" H 4750 3350 60 0000 C CNN + 3 4750 3450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.cir b/OSCAD/Examples/simpleTTL/simpleTTL.cir new file mode 100644 index 0000000..b4463d3 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 02 April 2013 03:00:52 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +XU2 1 5 VPLOT8_1 +R1 5 0 1000 +v1 1 0 PULSE +v2 4 0 5 +XU1 0 5 1 4 3 7400 + +.end diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.cir.ckt b/OSCAD/Examples/simpleTTL/simpleTTL.cir.ckt new file mode 100644 index 0000000..7bbb5a4 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.cir.ckt @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 20 december 2012 12:05:00 am ist + +* Plotting option vplot8_1 +r1 5 0 1000 +v1 1 0 pulse(0 5 0 0 0 0.25e-6 0.5e-6) +v2 4 0 5 +* 7400 +a1 [1] [1_in] u1adc +a2 [4] [4_in] u1adc +a3 [1_in 4_in] 5_out u1 +a4 [5_out] [5] u1dac +.model u1 d_nand +.model u1adc adc_bridge(in_low=0.8 in_high=2.0) +.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 +.plot v(1) v(5) +.end diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.cir.out b/OSCAD/Examples/simpleTTL/simpleTTL.cir.out new file mode 100644 index 0000000..666b204 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.cir.out @@ -0,0 +1,23 @@ +* eeschema netlist version 1.1 (spice format) creation date: thursday 20 december 2012 12:05:00 am ist + +* Plotting option vplot8_1 +r1 5 0 1000 +v1 1 0 pulse(0 5 0 0 0 0.25e-6 0.5e-6) +v2 4 0 5 +* 7400 +a1 [1] [1_in] u1adc +a2 [4] [4_in] u1adc +a3 [1_in 4_in] 5_out u1 +a4 [5_out] [5] u1dac +.model u1 d_nand +.model u1adc adc_bridge(in_low=0.8 in_high=2.0) +.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 + +* Control Statements +.control +run +plot v(1) v(5) +.endc +.end diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.pro b/OSCAD/Examples/simpleTTL/simpleTTL.pro new file mode 100644 index 0000000..b16deac --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.pro @@ -0,0 +1,73 @@ +update=Tuesday 18 December 2012 10:13:38 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=digitalXSpice +LibName39=analogXSpice diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.proj b/OSCAD/Examples/simpleTTL/simpleTTL.proj new file mode 100644 index 0000000..72370e2 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.proj @@ -0,0 +1 @@ +schematicFile simpleTTL.sch diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.sch b/OSCAD/Examples/simpleTTL/simpleTTL.sch new file mode 100644 index 0000000..cb6e4f2 --- /dev/null +++ b/OSCAD/Examples/simpleTTL/simpleTTL.sch @@ -0,0 +1,157 @@ +EESchema Schematic File Version 2 date Tuesday 02 April 2013 03:01:00 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:simpleTTL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "2 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5550 3450 +Wire Wire Line + 5550 3300 5550 3600 +Wire Wire Line + 2950 4600 5550 4600 +Connection ~ 4500 4600 +Wire Wire Line + 4500 4300 4500 4600 +Wire Wire Line + 3700 4600 3700 4450 +Connection ~ 2950 4600 +Wire Wire Line + 2950 3350 4150 3350 +Wire Wire Line + 2950 4250 2950 4800 +Wire Wire Line + 3700 3550 4150 3550 +Connection ~ 3700 4600 +Wire Wire Line + 4550 2900 4550 3250 +Wire Wire Line + 3450 3350 3450 3250 +Connection ~ 3450 3350 +Wire Wire Line + 5550 3450 5350 3450 +Wire Wire Line + 5550 4600 5550 4100 +$Comp +L VPLOT8_1 U2 +U 2 1 50CEBA04 +P 5550 3000 +F 0 "U2" H 5400 3100 50 0000 C CNN +F 1 "VPLOT8_1" H 5700 3100 50 0000 C CNN + 2 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 50CEBA01 +P 3450 2950 +F 0 "U2" H 3300 3050 50 0000 C CNN +F 1 "VPLOT8_1" H 3600 3050 50 0000 C CNN + 1 3450 2950 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50862FAD +P 4550 2900 +F 0 "#FLG01" H 4550 3170 30 0001 C CNN +F 1 "PWR_FLAG" H 4550 3130 30 0000 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 50862FA6 +P 4500 4300 +F 0 "#FLG02" H 4500 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 4500 4530 30 0000 C CNN + 1 4500 4300 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50862F73 +P 5550 3850 +F 0 "R1" V 5630 3850 50 0000 C CNN +F 1 "1000" V 5550 3850 50 0000 C CNN + 1 5550 3850 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 50862F55 +P 2950 3800 +F 0 "v1" H 2750 3900 60 0000 C CNN +F 1 "PULSE" H 2750 3750 60 0000 C CNN +F 2 "R1" H 2650 3800 60 0000 C CNN + 1 2950 3800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 50862CF3 +P 2950 4800 +F 0 "#PWR03" H 2950 4800 30 0001 C CNN +F 1 "GND" H 2950 4730 30 0001 C CNN + 1 2950 4800 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 50862BA3 +P 3700 4000 +F 0 "v2" H 3500 4100 60 0000 C CNN +F 1 "5" H 3500 3950 60 0000 C CNN +F 2 "R1" H 3400 4000 60 0000 C CNN + 1 3700 4000 + 1 0 0 -1 +$EndComp +$Comp +L 7400 U1 +U 3 1 50862B5B +P 4750 3450 +F 0 "U1" H 4750 3500 60 0000 C CNN +F 1 "7400" H 4750 3350 60 0000 C CNN + 3 4750 3450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/slewRateExample/analysis b/OSCAD/Examples/slewRateExample/analysis new file mode 100644 index 0000000..f635959 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/analysis @@ -0,0 +1 @@ +.tran 1e-09 1e-06 0e-00 diff --git a/OSCAD/Examples/slewRateExample/slewRateExample-cache.bak b/OSCAD/Examples/slewRateExample/slewRateExample-cache.bak new file mode 100644 index 0000000..96fc3bb --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample-cache.bak @@ -0,0 +1,101 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 03:22:05 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/slewRateExample/slewRateExample-cache.lib b/OSCAD/Examples/slewRateExample/slewRateExample-cache.lib new file mode 100644 index 0000000..eb08e6b --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample-cache.lib @@ -0,0 +1,101 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 03:24:18 PM IST +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# uA741 +# +DEF uA741 X 0 20 Y Y 1 F N +F0 "X" 150 150 60 H V C CNN +F1 "uA741" 150 250 60 H V C CNN +$FPLIST + DIP-8__300 +$ENDFPLIST +DRAW +P 4 0 1 0 -200 200 200 0 -200 -200 -200 200 N +X - 2 -500 -100 300 R 40 40 1 1 I +X + 3 -500 100 300 R 40 40 1 1 I +X ~ 6 500 0 300 L 40 40 1 1 O +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.bak b/OSCAD/Examples/slewRateExample/slewRateExample.bak new file mode 100644 index 0000000..1f8a1ee --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.bak @@ -0,0 +1,193 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 03:22:05 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:slewRateExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PULSE v1 +U 1 1 50CEEB0C +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "PULSE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 3100 6850 3650 +Connection ~ 6850 3400 +Connection ~ 4300 4650 +Wire Wire Line + 4300 4650 4600 4650 +Wire Wire Line + 4600 4650 4600 4400 +Wire Wire Line + 6850 3400 6300 3400 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 4900 3500 5300 3500 +Wire Wire Line + 4300 3650 4300 3500 +Wire Wire Line + 4300 3500 4400 3500 +Wire Wire Line + 5300 3300 4300 3300 +Wire Wire Line + 4300 3300 4300 3400 +Wire Wire Line + 5150 3500 5150 4050 +Wire Wire Line + 5150 4050 5550 4050 +Connection ~ 5150 3500 +Wire Wire Line + 6850 4150 6850 4400 +Wire Wire Line + 6050 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 3400 +Connection ~ 6550 3400 +Wire Wire Line + 3400 3100 3400 3550 +Wire Wire Line + 3400 3550 4300 3550 +Connection ~ 4300 3550 +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 3400 2800 +F 0 "U1" H 3250 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 3550 2900 50 0000 C CNN + 1 3400 2800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG01" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 508240CB +P 4300 3400 +F 0 "#PWR02" H 4300 3400 30 0001 C CNN +F 1 "GND" H 4300 3330 30 0001 C CNN + 1 4300 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR03" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR04" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4650 3500 +F 0 "R1" V 4730 3500 50 0000 C CNN +F 1 "1000" V 4650 3500 50 0000 C CNN + 1 4650 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.cir b/OSCAD/Examples/slewRateExample/slewRateExample.cir new file mode 100644 index 0000000..67bfed1 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.cir @@ -0,0 +1,14 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 03:24:15 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 2 0 PULSE +U1 2 3 VPLOT8_1 +X1 4 0 3 UA741 +R3 3 0 10000 +R1 4 2 1000 +R2 3 4 2000 + +.end diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.cir.ckt b/OSCAD/Examples/slewRateExample/slewRateExample.cir.ckt new file mode 100644 index 0000000..99770a5 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.cir.ckt @@ -0,0 +1,13 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 03:24:15 pm ist +.include ua741.sub + +v1 2 0 pulse(0 5 0 0 0 0.5e-4 1e-4) +* Plotting option vplot8_1 +x1 4 0 3 ua741 +r3 3 0 10000 +r1 4 2 1000 +r2 3 4 2000 + +.tran 1e-09 1e-06 0e-00 +.plot v(2) v(3) +.end diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.cir.out b/OSCAD/Examples/slewRateExample/slewRateExample.cir.out new file mode 100644 index 0000000..c771986 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 03:24:15 pm ist +.include ua741.sub + +v1 2 0 pulse(0 5 0 0 0 0.5e-4 1e-4) +* Plotting option vplot8_1 +x1 4 0 3 ua741 +r3 3 0 10000 +r1 4 2 1000 +r2 3 4 2000 + +.tran 1e-09 1e-06 0e-00 + +* Control Statements +.control +run +plot v(2) v(3) +.endc +.end diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.cmp b/OSCAD/Examples/slewRateExample/slewRateExample.cmp new file mode 100644 index 0000000..c3e04af --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.cmp @@ -0,0 +1,38 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Saturday 20 October 2012 11:59:17 AM IST + +BeginCmp +TimeStamp = /50824062; +Reference = R1; +ValeurCmp = 1000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824045; +Reference = R2; +ValeurCmp = 2000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824073; +Reference = R3; +ValeurCmp = 10000; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50824091; +Reference = v1; +ValeurCmp = SINE; +IdModule = R1; +EndCmp + +BeginCmp +TimeStamp = /50823E96; +Reference = X1; +ValeurCmp = LM741; +IdModule = DIP-8__300; +EndCmp + +EndListe diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.net b/OSCAD/Examples/slewRateExample/slewRateExample.net new file mode 100644 index 0000000..938591e --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.net @@ -0,0 +1,70 @@ +# EESchema Netlist Version 1.1 created Saturday 20 October 2012 12:03:26 PM IST +( + ( /50824595 $noname X1 UA741 {Lib=UA741} + ( 2 N-000004 ) + ( 3 GND ) + ( 6 N-000001 ) + ) + ( /50824091 R1 v1 SINE {Lib=SINE} + ( 1 N-000002 ) + ( 2 GND ) + ) + ( /50824073 $noname R3 10000 {Lib=R} + ( 1 N-000001 ) + ( 2 GND ) + ) + ( /50824062 $noname R1 1000 {Lib=R} + ( 1 N-000004 ) + ( 2 N-000002 ) + ) + ( /50824045 $noname R2 2000 {Lib=R} + ( 1 N-000001 ) + ( 2 N-000004 ) + ) +) +* +{ Allowed footprints by component: +$component X1 + DIP-8__300 +$endlist +$component v1 + 1_pin +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "" "" + R2 1 + X1 6 + R3 1 +Net 2 "" "" + R1 2 + v1 1 +Net 3 "GND" "GND" + X1 3 + v1 2 + R3 2 +Net 4 "" "" + X1 2 + R1 1 + R2 2 +} +#End diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.pro b/OSCAD/Examples/slewRateExample/slewRateExample.pro new file mode 100644 index 0000000..4d957be --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.pro @@ -0,0 +1,71 @@ +update=Saturday 20 October 2012 07:46:26 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.proj b/OSCAD/Examples/slewRateExample/slewRateExample.proj new file mode 100644 index 0000000..c78c533 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.proj @@ -0,0 +1 @@ +schematicFile InvertingAmplifier.sch diff --git a/OSCAD/Examples/slewRateExample/slewRateExample.sch b/OSCAD/Examples/slewRateExample/slewRateExample.sch new file mode 100644 index 0000000..4508864 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/slewRateExample.sch @@ -0,0 +1,193 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 03:24:18 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:slewRateExample-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PULSE v1 +U 1 1 50CEEB0C +P 4300 4100 +F 0 "v1" H 4100 4200 60 0000 C CNN +F 1 "PULSE" H 4100 4050 60 0000 C CNN +F 2 "R1" H 4000 4100 60 0000 C CNN + 1 4300 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 3100 6850 3650 +Connection ~ 6850 3400 +Connection ~ 4300 4650 +Wire Wire Line + 4300 4650 4600 4650 +Wire Wire Line + 4600 4650 4600 4400 +Wire Wire Line + 6850 3400 6300 3400 +Wire Wire Line + 4300 4550 4300 4700 +Wire Wire Line + 4900 3500 5300 3500 +Wire Wire Line + 4300 3650 4300 3500 +Wire Wire Line + 4300 3500 4400 3500 +Wire Wire Line + 5300 3300 4300 3300 +Wire Wire Line + 4300 3300 4300 3400 +Wire Wire Line + 5150 3500 5150 4050 +Wire Wire Line + 5150 4050 5550 4050 +Connection ~ 5150 3500 +Wire Wire Line + 6850 4150 6850 4400 +Wire Wire Line + 6050 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 3400 +Connection ~ 6550 3400 +Wire Wire Line + 3400 3100 3400 3550 +Wire Wire Line + 3400 3550 4300 3550 +Connection ~ 4300 3550 +$Comp +L VPLOT8_1 U1 +U 2 1 50CEB089 +P 6850 2800 +F 0 "U1" H 6700 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 7000 2900 50 0000 C CNN + 2 6850 2800 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50CEB075 +P 3400 2800 +F 0 "U1" H 3250 2900 50 0000 C CNN +F 1 "VPLOT8_1" H 3550 2900 50 0000 C CNN + 1 3400 2800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 508245D2 +P 4600 4400 +F 0 "#FLG01" H 4600 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 4600 4630 30 0000 C CNN + 1 4600 4400 + 1 0 0 -1 +$EndComp +$Comp +L UA741 X1 +U 1 1 50824595 +P 5800 3400 +F 0 "X1" H 5950 3550 60 0000 C CNN +F 1 "UA741" H 5950 3650 60 0000 C CNN + 1 5800 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 508240CB +P 4300 3400 +F 0 "#PWR02" H 4300 3400 30 0001 C CNN +F 1 "GND" H 4300 3330 30 0001 C CNN + 1 4300 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 508240B7 +P 4300 4700 +F 0 "#PWR03" H 4300 4700 30 0001 C CNN +F 1 "GND" H 4300 4630 30 0001 C CNN + 1 4300 4700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 508240AD +P 6850 4400 +F 0 "#PWR04" H 6850 4400 30 0001 C CNN +F 1 "GND" H 6850 4330 30 0001 C CNN + 1 6850 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50824073 +P 6850 3900 +F 0 "R3" V 6930 3900 50 0000 C CNN +F 1 "10000" V 6850 3900 50 0000 C CNN + 1 6850 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50824062 +P 4650 3500 +F 0 "R1" V 4730 3500 50 0000 C CNN +F 1 "1000" V 4650 3500 50 0000 C CNN + 1 4650 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 50824045 +P 5800 4050 +F 0 "R2" V 5880 4050 50 0000 C CNN +F 1 "2000" V 5800 4050 50 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/slewRateExample/ua741-cache.bak b/OSCAD/Examples/slewRateExample/ua741-cache.bak new file mode 100644 index 0000000..1ac0925 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741-cache.bak @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 19 November 2012 12:14:01 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 I +X ~ 2 250 0 100 L 30 30 2 1 I +X ~ 3 250 0 100 L 30 30 3 1 I +X ~ 4 250 0 100 L 30 30 4 1 I +X ~ 5 250 0 100 L 30 30 5 1 I +X ~ 6 250 0 100 L 30 30 6 1 I +X ~ 7 250 0 100 L 30 30 7 1 I +X ~ 8 250 0 100 L 30 30 8 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/slewRateExample/ua741-cache.lib b/OSCAD/Examples/slewRateExample/ua741-cache.lib new file mode 100644 index 0000000..e2ece32 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:17:01 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/slewRateExample/ua741.bak b/OSCAD/Examples/slewRateExample/ua741.bak new file mode 100644 index 0000000..5237bd8 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 19 November 2012 12:14:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG1 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG1" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR1" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/slewRateExample/ua741.cir b/OSCAD/Examples/slewRateExample/ua741.cir new file mode 100644 index 0000000..de79742 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/OSCAD/Examples/slewRateExample/ua741.cir.ckt b/OSCAD/Examples/slewRateExample/ua741.cir.ckt new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/slewRateExample/ua741.cir.out b/OSCAD/Examples/slewRateExample/ua741.cir.out new file mode 100644 index 0000000..3661a9a --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.cir.out @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/OSCAD/Examples/slewRateExample/ua741.pro b/OSCAD/Examples/slewRateExample/ua741.pro new file mode 100644 index 0000000..a87f185 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.pro @@ -0,0 +1,71 @@ +update=Sunday 18 November 2012 03:20:54 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/OSCAD/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice diff --git a/OSCAD/Examples/slewRateExample/ua741.sch b/OSCAD/Examples/slewRateExample/ua741.sch new file mode 100644 index 0000000..6be9280 --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.sch @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/slewRateExample/ua741.sub b/OSCAD/Examples/slewRateExample/ua741.sub new file mode 100644 index 0000000..1edba9f --- /dev/null +++ b/OSCAD/Examples/slewRateExample/ua741.sub @@ -0,0 +1,11 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 + +.ends ua741
\ No newline at end of file |