initial commit

13 files changed, 762 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis
new file mode 100644
index 0000000..f74e3c8
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/analysis
@@ -0,0 +1 @@
+.dc  v1 0e-00 10e-00 1e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt
new file mode 100644
index 0000000..cb5beb4
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/cd4007.txt
@@ -0,0 +1,22 @@
+* CD4007 NMOS and PMOS transistor SPICE models
+
+* Typical - Typical Condition
+
+.model MbreakND NMOS 
++ Level=1    Gamma= 0   Xj=0
++ Tox=1200n  Phi=.6     Rs=0      Kp=111u  Vto=1.4    Lambda=0.01
++ Rd=0       Cbd=2.0p   Cbs=2.0p  Pb=.8    Cgso=0.1p
++ Cgdo=0.1p  Is=16.64p  N=1
+
+*The default W and L is 30 and 10 um respectively and AD and AS
+*should not be included.
+
+
+.model MbreakPD PMOS 
++ Level=1    Gamma= 0   Xj=0
++ Tox=1200n  Phi=.6     Rs=0      Kp=55u  Vto=-1.2   Lambda=0.04
++ Rd=0       Cbd=4.0p   Cbs=4.0p  Pb=.8   Cgso=0.2p
++ Cgdo=0.2p  Is=16.64p  N=1
+
+*The default W and L is 60 and 10 um respectively and AD and AS
+*should not be included.
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak
new file mode 100644
index 0000000..cc8bedb
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.bak
@@ -0,0 +1,118 @@
+EESchema-LIBRARY Version 2.3  Date: Friday 10 May 2013 04:54:25 PM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# MOS_N
+#
+DEF MOS_N M 0 0 N Y 1 F N
+F0 "M" 10 170 60 H V R CNN
+F1 "MOS_N" 10 -150 60 H V R CNN
+ALIAS MOSFET_N
+DRAW
+P 2 0 1 8  -50 -100  -50 100 N
+P 2 0 1 10  0 -150  0 150 N
+P 2 0 1 0  100 -100  0 -100 N
+P 2 0 1 0  100 100  0 100 N
+P 3 0 1 8  100 -100  100 0  50 0 N
+P 5 0 1 8  50 30  50 -30  0 0  50 30  50 30 N
+X D D 100 200 100 D 40 40 1 1 P
+X G G -200 0 150 R 40 40 1 1 I
+X S S 100 -200 100 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# MOS_P
+#
+DEF MOS_P M 0 40 Y N 1 F N
+F0 "M" 0 190 60 H V R CNN
+F1 "MOS_P" 0 -180 60 H V R CNN
+ALIAS MOSFET_P
+DRAW
+P 2 0 1 8  -50 -100  -50 100 N
+P 2 0 1 10  0 -150  0 150 N
+P 2 0 1 8  30 0  0 0 N
+P 2 0 1 0  100 -100  0 -100 N
+P 2 0 1 0  100 100  0 100 N
+P 3 0 1 0  80 0  100 0  100 -100 N
+P 5 0 1 8  30 40  30 -30  80 0  30 40  30 40 N
+X D D 100 200 100 D 40 40 1 1 P
+X G G -200 0 150 R 40 40 1 1 I
+X S S 100 -200 100 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.lib
new file mode 100644
index 0000000..5680002
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4-cache.lib
@@ -0,0 +1,118 @@
+EESchema-LIBRARY Version 2.3  Date: Thursday 16 May 2013 11:24:57 AM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# MOS_N
+#
+DEF MOS_N M 0 0 N Y 1 F N
+F0 "M" 10 170 60 H V R CNN
+F1 "MOS_N" 10 -150 60 H V R CNN
+ALIAS MOSFET_N
+DRAW
+P 2 0 1 8  -50 -100  -50 100 N
+P 2 0 1 10  0 -150  0 150 N
+P 2 0 1 0  100 -100  0 -100 N
+P 2 0 1 0  100 100  0 100 N
+P 3 0 1 8  100 -100  100 0  50 0 N
+P 5 0 1 8  50 30  50 -30  0 0  50 30  50 30 N
+X D D 100 200 100 D 40 40 1 1 P
+X G G -200 0 150 R 40 40 1 1 I
+X S S 100 -200 100 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# MOS_P
+#
+DEF MOS_P M 0 40 Y N 1 F N
+F0 "M" 0 190 60 H V R CNN
+F1 "MOS_P" 0 -180 60 H V R CNN
+ALIAS MOSFET_P
+DRAW
+P 2 0 1 8  -50 -100  -50 100 N
+P 2 0 1 10  0 -150  0 150 N
+P 2 0 1 8  30 0  0 0 N
+P 2 0 1 0  100 -100  0 -100 N
+P 2 0 1 0  100 100  0 100 N
+P 3 0 1 0  80 0  100 0  100 -100 N
+P 5 0 1 8  30 40  30 -30  80 0  30 40  30 40 N
+X D D 100 200 100 D 40 40 1 1 P
+X G G -200 0 150 R 40 40 1 1 I
+X S S 100 -200 100 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak
new file mode 100644
index 0000000..e14fb9e
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.bak
@@ -0,0 +1,194 @@
+EESchema Schematic File Version 2  date Friday 10 May 2013 04:54:25 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_9.4-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "10 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 5750 3600
+Wire Wire Line
+	5750 3600 5300 3600
+Wire Wire Line
+	5300 3600 5300 3850
+Connection ~ 5600 3450
+Wire Wire Line
+	5600 3650 5600 3450
+Wire Wire Line
+	6050 3450 6400 3450
+Connection ~ 6050 4300
+Wire Wire Line
+	6050 4050 6050 4350
+Wire Wire Line
+	6050 4350 5100 4350
+Wire Wire Line
+	6650 3900 6650 4300
+Wire Wire Line
+	6050 2850 6050 2700
+Wire Wire Line
+	6050 3250 6050 3650
+Wire Wire Line
+	5750 3050 5750 3850
+Connection ~ 6050 3450
+Wire Wire Line
+	6400 3450 6400 3750
+Connection ~ 6400 4300
+Wire Wire Line
+	6050 2700 6650 2700
+Wire Wire Line
+	6650 2700 6650 3000
+Wire Wire Line
+	5750 3450 5100 3450
+Connection ~ 5750 3450
+Wire Wire Line
+	5100 3450 5100 3550
+Wire Wire Line
+	6400 4400 6400 4150
+Connection ~ 5500 3450
+Wire Wire Line
+	6650 4300 6050 4300
+Connection ~ 6200 3450
+Wire Wire Line
+	5600 4050 5600 4350
+Connection ~ 5600 4350
+$Comp
+L MOS_N M3
+U 1 1 518CD8BE
+P 5500 3850
+F 0 "M3" H 5510 4020 60  0000 R CNN
+F 1 "MOS_N" H 5510 3700 60  0000 R CNN
+	1    5500 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L MOS_P M1
+U 1 1 5188E486
+P 5950 3050
+F 0 "M1" H 5950 3240 60  0000 R CNN
+F 1 "MOS_P" H 5950 2870 60  0000 R CNN
+	1    5950 3050
+	1    0    0    1   
+$EndComp
+$Comp
+L MOS_N M2
+U 1 1 5188E477
+P 5950 3850
+F 0 "M2" H 5960 4020 60  0000 R CNN
+F 1 "MOS_N" H 5960 3700 60  0000 R CNN
+	1    5950 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 2 1 5188E0A2
+P 6200 3150
+F 0 "U2" H 6050 3250 50  0000 C CNN
+F 1 "VPLOT8_1" H 6350 3250 50  0000 C CNN
+	2    6200 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5188E094
+P 6400 4300
+F 0 "#FLG01" H 6400 4570 30  0001 C CNN
+F 1 "PWR_FLAG" H 6400 4530 30  0000 C CNN
+	1    6400 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v2
+U 1 1 517F5425
+P 6650 3450
+F 0 "v2" H 6450 3550 60  0000 C CNN
+F 1 "10" H 6450 3400 60  0000 C CNN
+F 2 "R1" H 6350 3450 60  0000 C CNN
+	1    6650 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U2
+U 1 1 517F5879
+P 5500 3150
+F 0 "U2" H 5350 3250 50  0000 C CNN
+F 1 "VPLOT8_1" H 5650 3250 50  0000 C CNN
+	1    5500 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 517F5470
+P 6400 4400
+F 0 "#PWR02" H 6400 4400 30  0001 C CNN
+F 1 "GND" H 6400 4330 30  0001 C CNN
+	1    6400 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v1
+U 1 1 517F544C
+P 5100 3900
+F 0 "v1" H 4900 4000 60  0000 C CNN
+F 1 "DC" H 4900 3850 60  0000 C CNN
+F 2 "R1" H 4800 3900 60  0000 C CNN
+	1    5100 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C1
+U 1 1 517F53E7
+P 6400 3950
+F 0 "C1" H 6450 4050 50  0000 L CNN
+F 1 ".5p" H 6450 3850 50  0000 L CNN
+	1    6400 3950
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir
new file mode 100644
index 0000000..f3aa33e
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir
@@ -0,0 +1,14 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 16 May 2013 11:24:53 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+M1  4 3 1 MOS_P		
+M2  4 3 0 MOS_N		
+U2  3 4 VPLOT8_1		
+v2  1 0 10		
+v1  3 0 DC		
+C1  4 0 .5p		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt
new file mode 100644
index 0000000..0699b0a
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.ckt
@@ -0,0 +1,14 @@
+* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:24:53 am ist
+.include mos_p.lib
+.include mos_n.lib
+
+m1 4 3 1 1 mos_p
+m2 4 3 0 0 mos_n
+* Plotting option vplot8_1
+v2  1 0 10
+v1  3 0 dc 10
+c1  4 0 .5p
+
+.dc  v1 0e-00 10e-00 1e-00
+.plot v(3) v(4) 
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out
new file mode 100644
index 0000000..4fc3ec2
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.cir.out
@@ -0,0 +1,19 @@
+* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:24:53 am ist
+.include mos_p.lib
+.include mos_n.lib
+
+m1 4 3 1 1 mos_p
+m2 4 3 0 0 mos_n
+* Plotting option vplot8_1
+v2  1 0 10
+v1  3 0 dc 10
+c1  4 0 .5p
+
+.dc  v1 0e-00 10e-00 1e-00
+
+* Control Statements 
+.control
+run
+plot v(3) v(4) 
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro
new file mode 100644
index 0000000..d4ca737
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.pro
@@ -0,0 +1,74 @@
+update=Tuesday 30 April 2013 10:42:25 AM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj
new file mode 100644
index 0000000..8fac45c
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.proj
@@ -0,0 +1 @@
+schematicFile example_9.4.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch
new file mode 100644
index 0000000..de8111b
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/example_9.4.sch
@@ -0,0 +1,175 @@
+EESchema Schematic File Version 2  date Thursday 16 May 2013 11:24:57 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
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+EELAYER END
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+encoding utf-8
+Sheet 1 1
+Title ""
+Date "16 may 2013"
+Rev ""
+Comp ""
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+F 1 "MOS_P" H 5950 2870 60  0000 R CNN
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+F 1 "VPLOT8_1" H 6350 3250 50  0000 C CNN
+	2    6200 3150
+	1    0    0    -1  
+$EndComp
+$Comp
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diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib
new file mode 100644
index 0000000..23ac1f6
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_n.lib
@@ -0,0 +1,6 @@
+.model mos_n NMOS( Cgso=877.2p Tox=100n Rs=70.6m Tt=140n Vto=-3.67 
++ Pb=.8 Rg=.811 Theta=0 Phi=.6 Fc=.5 
++ Delta=0 Vmax=0 Kappa=0 Rds=444.4K Level=3 
++ L=2u Mj=.5 Uo=300 Eta=0 W=1.9 
++ Cgdo=369.3p Gamma=0 Xj=0 Rd=60.66m Cbd=2.141n 
++ Is=52.23E-18 N=2 Kp=10.15u )
diff --git a/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib
new file mode 100644
index 0000000..2c58d87
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_9/example_9.4/mos_p.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( Cgso=877.2p Tox=100n Rs=70.6m Tt=140n Vto=-3.67 
++ Pb=.8 Rg=.811 Theta=0 Phi=.6 Fc=.5 
++ Delta=0 Vmax=0 Kappa=0 Rds=444.4K Level=3 
++ L=2u Mj=.5 Uo=300 Eta=0 W=1.9 
++ Cgdo=369.3p Gamma=0 Xj=0 Rd=60.66m Cbd=2.141n 
++ Is=52.23E-18 N=2 Kp=10.15u )
\ No newline at end of file