initial commit

18 files changed, 1707 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis
new file mode 100644
index 0000000..0e8f996
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/analysis
@@ -0,0 +1 @@
+.tran  2e-03 20e-03 0e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak
new file mode 100644
index 0000000..6eed972
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.bak
@@ -0,0 +1,139 @@
+EESchema-LIBRARY Version 2.3  Date: Thursday 25 April 2013 11:20:04 AM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# Idc
+#
+DEF Idc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "Idc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# NPN
+#
+DEF NPN Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 50 H V R CNN
+F1 "NPN" 0 150 50 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
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+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
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+C 0 0 150 0 1 0 N
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+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
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+#
+DEF vplot8 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -300 0 200 R 40 40 1 1 O
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+X - 15 300 0 200 L 40 40 7 1 O
+X + 8 -300 0 200 R 40 40 8 1 O
+X - 16 300 0 200 L 40 40 8 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib
new file mode 100644
index 0000000..008a8d7
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1-cache.lib
@@ -0,0 +1,139 @@
+EESchema-LIBRARY Version 2.3  Date: Friday 26 April 2013 04:42:05 PM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# Idc
+#
+DEF Idc i 0 40 Y Y 1 F N
+F0 "i" -200 100 60 H V C CNN
+F1 "Idc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# NPN
+#
+DEF NPN Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 50 H V R CNN
+F1 "NPN" 0 150 50 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
+P 3 0 1 10  0 75  0 -75  0 -75 N
+P 3 0 1 0  50 -50  0 0  0 0 N
+P 3 0 1 0  90 -90  100 -100  100 -100 N
+P 5 0 1 0  90 -90  70 -30  30 -70  90 -90  90 -90 F
+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8
+#
+DEF vplot8 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -300 0 200 R 40 40 1 1 O
+X - 9 300 0 200 L 40 40 1 1 O
+X + 2 -300 0 200 R 40 40 2 1 O
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+X - 11 300 0 200 L 40 40 3 1 O
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+X + 7 -300 0 200 R 40 40 7 1 O
+X - 15 300 0 200 L 40 40 7 1 O
+X + 8 -300 0 200 R 40 40 8 1 O
+X - 16 300 0 200 L 40 40 8 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak
new file mode 100644
index 0000000..a480fc4
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.bak
@@ -0,0 +1,245 @@
+EESchema Schematic File Version 2  date Thursday 25 April 2013 11:20:04 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_8-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "25 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
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+Connection ~ 4700 4600
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5178C3EF
+P 4700 4600
+F 0 "#FLG01" H 4700 4870 30  0001 C CNN
+F 1 "PWR_FLAG" H 4700 4830 30  0000 C CNN
+	1    4700 4600
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5178C3E3
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+F 0 "#PWR02" H 4700 4700 30  0001 C CNN
+F 1 "GND" H 4700 4630 30  0001 C CNN
+	1    4700 4700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4700 4500 4700 4700
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+Wire Wire Line
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+Wire Wire Line
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+	6100 5000 4100 5000
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+$Comp
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+U 1 1 5178C3D2
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+F 0 "R7" V 4780 4250 50  0000 C CNN
+F 1 "150" V 4700 4250 50  0000 C CNN
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+$EndComp
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+	1    3600 3800
+	1    0    0    -1  
+$EndComp
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+F 1 "VPLOT8" H 5450 2450 50  0000 C CNN
+	1    5300 2350
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+$EndComp
+$Comp
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+F 1 "5k" V 3850 2700 50  0000 C CNN
+	1    3850 2700
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+$EndComp
+$Comp
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+U 1 1 517794EA
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+F 1 "150" V 5800 3450 50  0000 C CNN
+	1    5800 3450
+	1    0    0    -1  
+$EndComp
+$Comp
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+$EndComp
+$Comp
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+F 1 "R" V 3850 5000 50  0000 C CNN
+	1    3850 5000
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+	1    5300 4300
+	1    0    0    -1  
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diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir
new file mode 100644
index 0000000..b1cc053
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir
@@ -0,0 +1,21 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 25 April 2013 11:19:59 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+R7  9 0 150		
+v1  2 5 SINE		
+U1  1 11 VPLOT8		
+R1  8 2 5k		
+R6  3 9 150		
+R4  7 9 150		
+R5  12 11 10k		
+R3  12 1 10k		
+Q2  3 4 11 NPN		
+R2  4 5 R		
+v3  12 6 15		
+Q1  7 8 1 NPN		
+v2  9 6 1m		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt
new file mode 100644
index 0000000..d42cb97
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.ckt
@@ -0,0 +1,18 @@
+* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 11:19:59 am ist
+
+r7  9 0 150
+v1  2 5 sine( 5 50  )
+r1  8 2 5k
+r6  3 9 150
+r4  7 9 150
+r5  12 11 10k
+r3  12 1 10k
+q2 11 4 3 npn
+r2  4 5 r
+v3  12 6 15
+q1 1 8 7 npn
+v2  9 6 1m
+
+.tran  2e-03 20e-03 0e-00
+.plot v(1)-v(11) 
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out
new file mode 100644
index 0000000..95b8ceb
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.cir.out
@@ -0,0 +1,23 @@
+* eeschema netlist version 1.1 (spice format) creation date: thursday 25 april 2013 11:19:59 am ist
+
+r7  9 0 150
+v1  2 5 sine( 5 50  )
+r1  8 2 5k
+r6  3 9 150
+r4  7 9 150
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+r3  12 1 10k
+q2 11 4 3 npn
+r2  4 5 r
+v3  12 6 15
+q1 1 8 7 npn
+v2  9 6 1m
+
+.tran  2e-03 20e-03 0e-00
+
+* Control Statements 
+.control
+run
+plot v(1)-v(11) 
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro
new file mode 100644
index 0000000..71bd9f1
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.pro
@@ -0,0 +1,74 @@
+update=Thursday 18 April 2013 03:16:09 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
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+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj
new file mode 100644
index 0000000..fe0de23
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.proj
@@ -0,0 +1 @@
+schematicFile example_8.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch
new file mode 100644
index 0000000..06b9dfa
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.1/example_8.1.sch
@@ -0,0 +1,245 @@
+EESchema Schematic File Version 2  date Friday 26 April 2013 04:42:05 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_8.1-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "26 apr 2013"
+Rev ""
+Comp ""
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+Comment2 ""
+Comment3 ""
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+Connection ~ 5450 5400
+$Comp
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+F 1 "PWR_FLAG" H 5450 5630 30  0000 C CNN
+	1    5450 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5178C3E3
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+F 0 "#PWR02" H 5450 5500 30  0001 C CNN
+F 1 "GND" H 5450 5430 30  0001 C CNN
+	1    5450 5500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5450 5300 5450 5500
+Connection ~ 6550 3150
+Wire Wire Line
+	6350 3150 6550 3150
+Wire Wire Line
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+Wire Wire Line
+	6850 3500 6850 5800
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	6550 2950 6550 3300
+Wire Wire Line
+	6550 4500 5500 4500
+Wire Wire Line
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+Wire Wire Line
+	6050 4500 6050 4650
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+Wire Wire Line
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+Connection ~ 6500 2450
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+Wire Wire Line
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+Wire Wire Line
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+F 1 "VPLOT8" H 6200 3250 50  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+	1    5500 4250
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+$EndComp
+$Comp
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+F 1 "10k" V 6550 2700 50  0000 C CNN
+	1    6550 2700
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+$EndComp
+$Comp
+L R R3
+U 1 1 517794BE
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+F 0 "R3" V 5580 2700 50  0000 C CNN
+F 1 "10k" V 5500 2700 50  0000 C CNN
+	1    5500 2700
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 5177949E
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+F 0 "Q2" H 6650 3350 50  0000 R CNN
+F 1 "NPN" H 6650 3650 50  0000 R CNN
+	1    6650 3500
+	-1   0    0    -1  
+$EndComp
+$Comp
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+U 1 1 51779433
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+F 1 "R" V 4600 5800 50  0000 C CNN
+	1    4600 5800
+	0    1    1    0   
+$EndComp
+$Comp
+L DC v3
+U 1 1 51779424
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+F 1 "15" H 7150 4050 60  0000 C CNN
+F 2 "R1" H 7050 4100 60  0000 C CNN
+	1    7350 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L NPN Q1
+U 1 1 51779415
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+$EndComp
+$Comp
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diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis
new file mode 100644
index 0000000..722124c
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/analysis
@@ -0,0 +1 @@
+.dc  v1 0e-00 15e-00 1e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib
new file mode 100644
index 0000000..e93b428
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4-cache.lib
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir
new file mode 100644
index 0000000..7f3611e
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir
@@ -0,0 +1,41 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 29 April 2013 11:24:11 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U3  0 25 0 21 25 24 22 21 VPLOT8_1		
+U13  23 VPLOT8_1		
+v2  0 8 15		
+U14  12 6 IPLOT		
+U11  5 18 IPLOT		
+R7  7 8 3k		
+U15  9 7 IPLOT		
+Q9  9 23 6 NPN		
+U12  23 1 IPLOT		
+R6  1 8 15.7k		
+U9  2 8 IPLOT		
+U6  11 8 IPLOT		
+U2  10 8 IPLOT		
+Q6  2 25 4 NPN		
+U8  3 4 IPLOT		
+R5  12 5 2.3k		
+U10  19 22 IPLOT		
+U7  13 21 IPLOT		
+U4  14 24 IPLOT		
+U5  15 16 IPLOT		
+U1  17 25 IPLOT		
+Q8  23 22 18 NPN		
+R4  12 19 3k		
+Q7  3 21 22 NPN		
+Q5  3 24 12 NPN		
+R1  0 17 28.6k		
+Q1  10 25 25 NPN		
+Q3  11 25 16 NPN		
+R3  12 13 20k		
+Q4  15 0 21 NPN		
+v1  12 0 15		
+R2  12 14 20k		
+Q2  15 0 24 NPN		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt
new file mode 100644
index 0000000..14076b8
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.ckt
@@ -0,0 +1,53 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 29 april 2013 11:24:11 am ist

+

+* Plotting option vplot8_1

+* Plotting option vplot8_1

+v2  0 8 15

+V_u14 12 6 0

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+V_u15 9 7 0

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+V_u10 19 22 0

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+V_u4 14 24 0

+V_u5 15 16 0

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+q1 25 25 10 npn

+q3 16 25 11 npn

+r3  12 13 20k

+q4 21 0 15 npn

+v1  12 0 15

+r2  12 14 20k

+q2 24 0 15 npn

+

+.dc  v1 0e-00 15e-00 1e-00

+.plot v(0) v(25) v(0) v(21) v(25) v(24) v(22) v(21) 

+.plot v(23) 

+.plot i(V_u14)

+.plot i(V_u11)

+.plot i(V_u15)

+.plot i(V_u12)

+.plot i(V_u9)

+.plot i(V_u6)

+.plot i(V_u2)

+.plot i(V_u8)

+.plot i(V_u10)

+.plot i(V_u7)

+.plot i(V_u4)

+.plot i(V_u5)

+.plot i(V_u1)

+.end

diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out
new file mode 100644
index 0000000..a08c832
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.cir.out
@@ -0,0 +1,58 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 29 april 2013 11:24:11 am ist

+

+* Plotting option vplot8_1

+* Plotting option vplot8_1

+v2  0 8 15

+V_u14 12 6 0

+V_u11 5 18 0

+r7  7 8 3k

+V_u15 9 7 0

+q9 6 23 9 npn

+V_u12 23 1 0

+r6  1 8 15.7k

+V_u9 2 8 0

+V_u6 11 8 0

+V_u2 10 8 0

+q6 4 25 2 npn

+V_u8 3 4 0

+r5  12 5 2.3k

+V_u10 19 22 0

+V_u7 13 21 0

+V_u4 14 24 0

+V_u5 15 16 0

+V_u1 17 25 0

+q8 18 22 23 npn

+r4  12 19 3k

+q7 22 21 3 npn

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+q1 25 25 10 npn

+q3 16 25 11 npn

+r3  12 13 20k

+q4 21 0 15 npn

+v1  12 0 15

+r2  12 14 20k

+q2 24 0 15 npn

+

+.dc  v1 0e-00 15e-00 1e-00

+

+* Control Statements 

+.control

+run

+plot v(0) v(25) v(0) v(21) v(25) v(24) v(22) v(21) 

+plot v(23) 

+plot i(V_u14)

+plot i(V_u11)

+plot i(V_u15)

+plot i(V_u12)

+plot i(V_u9)

+plot i(V_u6)

+plot i(V_u2)

+plot i(V_u8)

+plot i(V_u10)

+plot i(V_u7)

+plot i(V_u4)

+plot i(V_u5)

+plot i(V_u1)

+.endc

+.end

diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro
new file mode 100644
index 0000000..767e17f
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.pro
@@ -0,0 +1,74 @@
+update=Monday 29 April 2013 10:50:36 AM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
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+offY_A2=0
+offX_A1=0
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+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj
new file mode 100644
index 0000000..c332699
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.proj
@@ -0,0 +1 @@
+schematicFile example_8.4.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch
new file mode 100644
index 0000000..cc68262
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_8/example_8.4/example_8.4.sch
@@ -0,0 +1,573 @@
+EESchema Schematic File Version 2  date Monday 29 April 2013 11:24:17 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+EELAYER 43  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "29 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 3450 1150
+Connection ~ 3300 5050
+Connection ~ 4900 2900
+$Comp
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+F 1 "VPLOT8_1" H 5050 2700 50  0000 C CNN
+	8    4900 2600
+	1    0    0    -1  
+$EndComp
+Connection ~ 3750 3100
+Connection ~ 3900 2550
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+Connection ~ 4750 2600
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+Connection ~ 3900 4150
+$Comp
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+F 1 "VPLOT8_1" H 4050 3950 50  0000 C CNN
+	5    3900 3850
+	1    0    0    -1  
+$EndComp
+$Comp
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+	2    2950 3850
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+$EndComp
+$Comp
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+	1    2750 2650
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+$EndComp
+$Comp
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+	3    3750 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U3
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+F 1 "VPLOT8_1" H 4150 2800 50  0000 C CNN
+	6    4000 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U3
+U 4 1 517E08E7
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+F 0 "U3" H 3750 2350 50  0000 C CNN
+F 1 "VPLOT8_1" H 4050 2350 50  0000 C CNN
+	4    3900 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U3
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+F 1 "VPLOT8_1" H 4900 2400 50  0000 C CNN
+	7    4750 2300
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+$EndComp
+$Comp
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+F 1 "VPLOT8_1" H 5650 2750 50  0000 C CNN
+	1    5500 2650
+	1    0    0    -1  
+$EndComp
+Connection ~ 4000 5050
+Wire Wire Line
+	4000 5050 4000 5550
+Wire Wire Line
+	4000 5550 3350 5550
+Connection ~ 2350 2550
+Wire Wire Line
+	2350 2550 2350 4150
+Wire Wire Line
+	2350 4150 1900 4150
+Connection ~ 3100 1150
+Connection ~ 2400 2550
+Connection ~ 2650 2750
+Wire Wire Line
+	2250 2550 2650 2550
+Wire Wire Line
+	2650 2550 2650 2950
+Connection ~ 2750 2950
+Wire Wire Line
+	2750 2950 2750 3300
+Wire Wire Line
+	2750 3300 3750 3300
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+	3750 3300 3750 2950
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+	5900 2750 5900 2450
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+	5900 3800 5900 4000
+Connection ~ 5250 2950
+Wire Wire Line
+	5250 2950 5600 2950
+Wire Wire Line
+	5250 3650 5250 4200
+Wire Wire Line
+	4500 4350 4500 4550
+Wire Wire Line
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+Connection ~ 3450 2550
+Wire Wire Line
+	3450 2550 4900 2550
+Wire Wire Line
+	4900 2550 4900 3000
+Connection ~ 4350 1150
+Wire Wire Line
+	3100 1650 3100 1950
+Wire Wire Line
+	4600 1650 4600 1950
+Wire Wire Line
+	2550 3250 2550 3350
+Wire Wire Line
+	4350 3200 4600 3200
+Wire Wire Line
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