initial commit

28 files changed, 2320 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis
new file mode 100644
index 0000000..0e8f996
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/analysis
@@ -0,0 +1 @@
+.tran  2e-03 20e-03 0e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak
new file mode 100644
index 0000000..6284625
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.bak
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 22 April 2013 12:05:40 PM IST
+#encoding utf-8
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib
new file mode 100644
index 0000000..388a263
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1-cache.lib
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 22 April 2013 12:09:56 PM IST
+#encoding utf-8
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak
new file mode 100644
index 0000000..cc13116
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.bak
@@ -0,0 +1,231 @@
+EESchema Schematic File Version 2  date Monday 22 April 2013 12:05:40 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_7.1-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 1050 3250
+$Comp
+L VPLOT8_1 U2
+U 1 1 5174D971
+P 1050 2950
+F 0 "U2" H 900 3050 50  0000 C CNN
+F 1 "VPLOT8_1" H 1200 3050 50  0000 C CNN
+	1    1050 2950
+	1    0    0    -1  
+$EndComp
+Connection ~ 2950 3200
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5174D14C
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+F 0 "#FLG01" H 2050 5620 30  0001 C CNN
+F 1 "PWR_FLAG" H 2050 5580 30  0000 C CNN
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+$EndComp
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+L VPLOT8_1 U1
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+	2    2950 2900
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+$EndComp
+$Comp
+L VPLOT8_1 U1
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+$EndComp
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+F 1 "GND" H 2050 5430 30  0001 C CNN
+	1    2050 5500
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+$EndComp
+Connection ~ 2750 5350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	1550 3200 2500 3200
+Wire Wire Line
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+Connection ~ 2050 3200
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+L R R3
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+F 0 "R3" V 2130 5050 50  0000 C CNN
+F 1 "1000" V 2050 5050 50  0000 C CNN
+	1    2050 5050
+	-1   0    0    1   
+$EndComp
+$Comp
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+U 1 1 5174CF7E
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+F 1 "100000" V 3400 4600 50  0000 C CNN
+	1    3400 4600
+	0    1    1    0   
+$EndComp
+$Comp
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+	1    4050 3600
+	-1   0    0    1   
+$EndComp
+$Comp
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+	1    3350 3200
+	0    1    1    0   
+$EndComp
+$Comp
+L VCVS E1
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+	1    2700 3650
+	0    1    1    0   
+$EndComp
+$Comp
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+F 1 "100000" V 2050 3750 50  0000 C CNN
+	1    2050 3750
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+$EndComp
+$Comp
+L SINE v1
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+F 2 "R1" H 750 3750 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+	1    1300 3200
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diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir
new file mode 100644
index 0000000..c73ab3c
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir
@@ -0,0 +1,18 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 22 April 2013 12:19:08 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+XU2  1 VPLOT8_1		
+XU1  4 3 5 VPLOT8_1		
+R3  0 6 1000		
+R5  5 6 100000		
+R6  0 5 2000		
+R4  5 3 1000		
+E1  3 0 4 6 2		
+R2  6 4 100000		
+v1  1 0 SINE		
+R1  4 1 10000		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt
new file mode 100644
index 0000000..9a79ca6
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.ckt
@@ -0,0 +1,17 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 12:09:21 pm ist
+
+* Plotting option vplot8_1
+* Plotting option vplot8_1
+r3  0 6 1000
+r5  5 6 100000
+r6  0 5 2000
+r4  5 3 1000
+e1  3 0 4 6 2
+r2  6 4 100000
+v1  1 0 sine(0 5 50 0 0)
+r1  4 1 10000
+
+.tran  2e-03 20e-03 0e-00
+.plot v(1) 
+.plot v(4) v(3) v(5) 
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out
new file mode 100644
index 0000000..222f9bd
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.cir.out
@@ -0,0 +1,22 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 12:09:21 pm ist
+
+* Plotting option vplot8_1
+* Plotting option vplot8_1
+r3  0 6 1000
+r5  5 6 100000
+r6  0 5 2000
+r4  5 3 1000
+e1  3 0 4 6 2
+r2  6 4 100000
+v1  1 0 sine(0 5 50 0 0)
+r1  4 1 10000
+
+.tran  2e-03 20e-03 0e-00
+
+* Control Statements 
+.control
+run
+plot v(1) 
+plot v(4) v(3) v(5) 
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro
new file mode 100644
index 0000000..414c8ad
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.pro
@@ -0,0 +1,74 @@
+update=Monday 22 April 2013 11:14:03 AM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj
new file mode 100644
index 0000000..dafbe48
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.proj
@@ -0,0 +1 @@
+schematicFile example_7.1.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch
new file mode 100644
index 0000000..7980439
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.1/example_7.1.sch
@@ -0,0 +1,231 @@
+EESchema Schematic File Version 2  date Monday 22 April 2013 12:09:56 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_7.1-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 apr 2013"
+Rev ""
+Comp ""
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+$Comp
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+$EndComp
+Connection ~ 2750 5350
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+$EndComp
+$Comp
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+	1    3400 4600
+	0    1    1    0   
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+$Comp
+L R R6
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+$EndComp
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+$Comp
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+$Comp
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+$Comp
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+$EndComp
+$Comp
+L R R1
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diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis
new file mode 100644
index 0000000..0e8f996
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/analysis
@@ -0,0 +1 @@
+.tran  2e-03 20e-03 0e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib
new file mode 100644
index 0000000..394db4b
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3-cache.lib
@@ -0,0 +1,115 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 22 April 2013 02:21:52 PM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# NPN
+#
+DEF NPN Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 50 H V R CNN
+F1 "NPN" 0 150 50 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
+P 3 0 1 10  0 75  0 -75  0 -75 N
+P 3 0 1 0  50 -50  0 0  0 0 N
+P 3 0 1 0  90 -90  100 -100  100 -100 N
+P 5 0 1 0  90 -90  70 -30  30 -70  90 -90  90 -90 F
+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir
new file mode 100644
index 0000000..fc9aa74
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir
@@ -0,0 +1,15 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 22 April 2013 02:21:49 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  5 4 VPLOT8_1		
+v2  2 0 12		
+R2  4 3 47000		
+R1  3 5 10000		
+v1  5 0 SINE		
+R3  2 4 4700		
+Q1  0 3 4 NPN		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt
new file mode 100644
index 0000000..421fe94
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.ckt
@@ -0,0 +1,13 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 02:21:49 pm ist
+
+* Plotting option vplot8_1
+v2  2 0 12
+r2  4 3 47000
+r1  3 5 10000
+v1  5 0 sine( 5 50  )
+r3  2 4 4700
+q1 4 3 0 npn
+
+.tran  2e-03 20e-03 0e-00
+.plot v(5) v(4) 
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out
new file mode 100644
index 0000000..db0fe26
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.cir.out
@@ -0,0 +1,18 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 22 april 2013 02:21:49 pm ist
+
+* Plotting option vplot8_1
+v2  2 0 12
+r2  4 3 47000
+r1  3 5 10000
+v1  5 0 sine( 5 50  )
+r3  2 4 4700
+q1 4 3 0 npn
+
+.tran  2e-03 20e-03 0e-00
+
+* Control Statements 
+.control
+run
+plot v(5) v(4) 
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro
new file mode 100644
index 0000000..1618111
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.pro
@@ -0,0 +1,74 @@
+update=Monday 22 April 2013 02:17:45 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
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+offX_A0=0
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+offX_A=0
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+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj
new file mode 100644
index 0000000..ff14336
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.proj
@@ -0,0 +1 @@
+schematicFile example_7.3.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch
new file mode 100644
index 0000000..fddbc06
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.3/example_7.3.sch
@@ -0,0 +1,175 @@
+EESchema Schematic File Version 2  date Monday 22 April 2013 02:21:52 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+EELAYER 43  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L VPLOT8_1 U1
+U 1 1 5174FA0E
+P 3850 3350
+F 0 "U1" H 3700 3450 50  0000 C CNN
+F 1 "VPLOT8_1" H 4000 3450 50  0000 C CNN
+	1    3850 3350
+	1    0    0    -1  
+$EndComp
+Connection ~ 3850 3650
+Wire Wire Line
+	3850 3650 3800 3650
+Connection ~ 4350 3650
+Connection ~ 5300 3350
+Wire Wire Line
+	4950 4650 4950 3850
+Wire Wire Line
+	5800 3200 5800 2800
+Wire Wire Line
+	5800 2800 4950 2800
+Wire Wire Line
+	4350 3350 4350 3650
+Wire Wire Line
+	4350 3350 4450 3350
+Wire Wire Line
+	4950 3450 4950 3300
+Wire Wire Line
+	4350 3650 4650 3650
+Wire Wire Line
+	4950 3350 5300 3350
+Connection ~ 4950 3350
+Wire Wire Line
+	5800 4100 5800 4550
+Wire Wire Line
+	5800 4550 3800 4550
+Connection ~ 4950 4550
+$Comp
+L VPLOT8_1 U1
+U 2 1 5174F9F2
+P 5300 3050
+F 0 "U1" H 5150 3150 50  0000 C CNN
+F 1 "VPLOT8_1" H 5450 3150 50  0000 C CNN
+	2    5300 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5174F9DF
+P 4950 4550
+F 0 "#FLG01" H 4950 4820 30  0001 C CNN
+F 1 "PWR_FLAG" H 4950 4780 30  0000 C CNN
+	1    4950 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5174F9D4
+P 4950 4650
+F 0 "#PWR02" H 4950 4650 30  0001 C CNN
+F 1 "GND" H 4950 4580 30  0001 C CNN
+	1    4950 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v2
+U 1 1 5174F994
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+F 1 "12" H 5600 3600 60  0000 C CNN
+F 2 "R1" H 5500 3650 60  0000 C CNN
+	1    5800 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 5174F959
+P 4700 3350
+F 0 "R2" V 4780 3350 50  0000 C CNN
+F 1 "47000" V 4700 3350 50  0000 C CNN
+	1    4700 3350
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 5174F943
+P 4100 3650
+F 0 "R1" V 4180 3650 50  0000 C CNN
+F 1 "10000" V 4100 3650 50  0000 C CNN
+	1    4100 3650
+	0    1    1    0   
+$EndComp
+$Comp
+L SINE v1
+U 1 1 5174F939
+P 3800 4100
+F 0 "v1" H 3600 4200 60  0000 C CNN
+F 1 "SINE" H 3600 4050 60  0000 C CNN
+F 2 "R1" H 3500 4100 60  0000 C CNN
+	1    3800 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 5174F90B
+P 4950 3050
+F 0 "R3" V 5030 3050 50  0000 C CNN
+F 1 "4700" V 4950 3050 50  0000 C CNN
+	1    4950 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L NPN Q1
+U 1 1 5174F8FA
+P 4850 3650
+F 0 "Q1" H 4850 3500 50  0000 R CNN
+F 1 "NPN" H 4850 3800 50  0000 R CNN
+	1    4850 3650
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis
new file mode 100644
index 0000000..0e8f996
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/analysis
@@ -0,0 +1 @@
+.tran  2e-03 20e-03 0e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak
new file mode 100644
index 0000000..61d077a
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.bak
@@ -0,0 +1,133 @@
+EESchema-LIBRARY Version 2.3  Date: Tuesday 23 April 2013 11:46:23 AM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# NPN
+#
+DEF NPN Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 50 H V R CNN
+F1 "NPN" 0 150 50 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
+P 3 0 1 10  0 75  0 -75  0 -75 N
+P 3 0 1 0  50 -50  0 0  0 0 N
+P 3 0 1 0  90 -90  100 -100  100 -100 N
+P 5 0 1 0  90 -90  70 -30  30 -70  90 -90  90 -90 F
+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib
new file mode 100644
index 0000000..b4c0e94
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4-cache.lib
@@ -0,0 +1,133 @@
+EESchema-LIBRARY Version 2.3  Date: Tuesday 23 April 2013 12:03:44 PM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# NPN
+#
+DEF NPN Q 0 0 Y Y 1 F N
+F0 "Q" 0 -150 50 H V R CNN
+F1 "NPN" 0 150 50 H V R CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  0 0  100 100 N
+P 3 0 1 10  0 75  0 -75  0 -75 N
+P 3 0 1 0  50 -50  0 0  0 0 N
+P 3 0 1 0  90 -90  100 -100  100 -100 N
+P 5 0 1 0  90 -90  70 -30  30 -70  90 -90  90 -90 F
+X E 1 100 -200 100 U 40 40 1 1 P
+X B 2 -200 0 200 R 40 40 1 1 I
+X C 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak
new file mode 100644
index 0000000..0eedc93
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.bak
@@ -0,0 +1,348 @@
+EESchema Schematic File Version 2  date Tuesday 23 April 2013 11:46:23 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_7.4-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "23 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 6350 3000
+$Comp
+L VPLOT8_1 U1
+U 1 1 517625EA
+P 6350 2700
+F 0 "U1" H 6200 2800 50  0000 C CNN
+F 1 "VPLOT8_1" H 6500 2800 50  0000 C CNN
+	1    6350 2700
+	1    0    0    -1  
+$EndComp
+Connection ~ 7000 2450
+$Comp
+L VPLOT8_1 U1
+U 2 1 517625DB
+P 7000 2150
+F 0 "U1" H 6850 2250 50  0000 C CNN
+F 1 "VPLOT8_1" H 7150 2250 50  0000 C CNN
+	2    7000 2150
+	1    0    0    -1  
+$EndComp
+Connection ~ 5800 2700
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 517625B5
+P 5800 2700
+F 0 "#FLG01" H 5800 2970 30  0001 C CNN
+F 1 "PWR_FLAG" H 5800 2930 30  0000 C CNN
+	1    5800 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 517625AE
+P 4050 3100
+F 0 "#FLG02" H 4050 3370 30  0001 C CNN
+F 1 "PWR_FLAG" H 4050 3330 30  0000 C CNN
+	1    4050 3100
+	1    0    0    -1  
+$EndComp
+Connection ~ 3250 4150
+$Comp
+L PWR_FLAG #FLG03
+U 1 1 5176256A
+P 3250 4150
+F 0 "#FLG03" H 3250 4420 30  0001 C CNN
+F 1 "PWR_FLAG" H 3250 4380 30  0000 C CNN
+	1    3250 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 5176255C
+P 3250 4300
+F 0 "#PWR04" H 3250 4300 30  0001 C CNN
+F 1 "GND" H 3250 4230 30  0001 C CNN
+	1    3250 4300
+	1    0    0    -1  
+$EndComp
+Connection ~ 3250 3950
+Wire Wire Line
+	3250 3950 3250 4300
+Wire Wire Line
+	2500 3100 2750 3100
+Connection ~ 6200 1700
+Wire Wire Line
+	7500 2400 7500 1700
+Wire Wire Line
+	7500 1700 4050 1700
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4050 3100
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	6200 3550 6200 3950
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4700 3400
+Wire Wire Line
+	5200 3400 4700 3400
+Wire Wire Line
+	4700 3300 4700 3450
+Wire Wire Line
+	6200 2500 6200 2350
+Wire Wire Line
+	4700 2600 4700 2900
+Wire Wire Line
+	5900 2700 4700 2700
+Connection ~ 4700 2700
+Wire Wire Line
+	6200 2450 6500 2450
+Connection ~ 6200 2450
+Wire Wire Line
+	6200 2900 6200 3050
+Wire Wire Line
+	5200 3950 5200 3850
+Wire Wire Line
+	7050 3950 7050 2950
+Connection ~ 5200 3950
+Wire Wire Line
+	4700 1700 4700 2100
+Wire Wire Line
+	6200 1700 6200 1850
+Connection ~ 4700 3950
+Wire Wire Line
+	3450 3100 3250 3100
+Wire Wire Line
+	6600 4350 5600 4350
+Wire Wire Line
+	4500 4350 3950 4350
+Wire Wire Line
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+Connection ~ 3950 3100
+Wire Wire Line
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+Wire Wire Line
+	7500 3950 2750 3950
+Connection ~ 7050 3950
+Wire Wire Line
+	2750 3950 2750 4000
+Wire Wire Line
+	2750 4000 2500 4000
+$Comp
+L SINE v1
+U 1 1 5176244C
+P 2500 3550
+F 0 "v1" H 2300 3650 60  0000 C CNN
+F 1 "SINE" H 2300 3500 60  0000 C CNN
+F 2 "R1" H 2200 3550 60  0000 C CNN
+	1    2500 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R6
+U 1 1 51761AB3
+P 4750 4350
+F 0 "R6" V 4830 4350 50  0000 C CNN
+F 1 "10k" V 4750 4350 50  0000 C CNN
+	1    4750 4350
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 51761A46
+P 3000 3100
+F 0 "R1" V 3080 3100 50  0000 C CNN
+F 1 "10k" V 3000 3100 50  0000 C CNN
+	1    3000 3100
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 51761A2D
+P 3650 3100
+F 0 "C1" H 3700 3200 50  0000 L CNN
+F 1 "1k" H 3700 3000 50  0000 L CNN
+	1    3650 3100
+	0    1    1    0   
+$EndComp
+$Comp
+L R R3
+U 1 1 51761A14
+P 4050 3700
+F 0 "R3" V 4130 3700 50  0000 C CNN
+F 1 "15k" V 4050 3700 50  0000 C CNN
+	1    4050 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R9
+U 1 1 517619D2
+P 7050 2700
+F 0 "R9" V 7130 2700 50  0000 C CNN
+F 1 "1k" V 7050 2700 50  0000 C CNN
+	1    7050 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C2
+U 1 1 517619B5
+P 5200 3650
+F 0 "C2" H 5250 3750 50  0000 L CNN
+F 1 "1k" H 5250 3550 50  0000 L CNN
+	1    5200 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R7
+U 1 1 517619A1
+P 6200 2100
+F 0 "R7" V 6280 2100 50  0000 C CNN
+F 1 "8k" V 6200 2100 50  0000 C CNN
+	1    6200 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R8
+U 1 1 5176198B
+P 6200 3300
+F 0 "R8" V 6280 3300 50  0000 C CNN
+F 1 "3.4k" V 6200 3300 50  0000 C CNN
+	1    6200 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C4
+U 1 1 5176197A
+P 6700 2450
+F 0 "C4" H 6750 2550 50  0000 L CNN
+F 1 "1k" H 6750 2350 50  0000 L CNN
+	1    6700 2450
+	0    1    1    0   
+$EndComp
+$Comp
+L R R5
+U 1 1 51761974
+P 4700 3700
+F 0 "R5" V 4780 3700 50  0000 C CNN
+F 1 "870" V 4700 3700 50  0000 C CNN
+	1    4700 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R4
+U 1 1 51761961
+P 4700 2350
+F 0 "R4" V 4780 2350 50  0000 C CNN
+F 1 "10k" V 4700 2350 50  0000 C CNN
+	1    4700 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v2
+U 1 1 5176195A
+P 7500 2850
+F 0 "v2" H 7300 2950 60  0000 C CNN
+F 1 "12" H 7300 2800 60  0000 C CNN
+F 2 "R1" H 7200 2850 60  0000 C CNN
+	1    7500 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C3
+U 1 1 51761951
+P 5400 4350
+F 0 "C3" H 5450 4450 50  0000 L CNN
+F 1 "1k" H 5450 4250 50  0000 L CNN
+	1    5400 4350
+	0    1    1    0   
+$EndComp
+$Comp
+L R R2
+U 1 1 5176194E
+P 4050 2400
+F 0 "R2" V 4130 2400 50  0000 C CNN
+F 1 "100k" V 4050 2400 50  0000 C CNN
+	1    4050 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L NPN Q2
+U 1 1 5176191C
+P 6100 2700
+F 0 "Q2" H 6100 2550 50  0000 R CNN
+F 1 "NPN" H 6100 2850 50  0000 R CNN
+	1    6100 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L NPN Q1
+U 1 1 517618FE
+P 4600 3100
+F 0 "Q1" H 4600 2950 50  0000 R CNN
+F 1 "NPN" H 4600 3250 50  0000 R CNN
+	1    4600 3100
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir
new file mode 100644
index 0000000..66167e8
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir
@@ -0,0 +1,26 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 23 April 2013 12:03:40 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  8 7 VPLOT8_1		
+v1  2 0 SINE		
+R6  3 6 10k		
+R1  1 2 10k		
+C1  6 1 1m		
+R3  6 0 15k		
+R9  7 0 1k		
+C2  11 0 1m		
+R7  4 9 8k		
+R8  8 0 3.4k		
+C4  7 9 1m		
+R5  11 0 870		
+R4  4 10 10k		
+v2  4 0 12		
+C3  8 3 1m		
+R2  4 6 100k		
+Q2  8 10 9 NPN		
+Q1  11 6 10 NPN		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt
new file mode 100644
index 0000000..d627f6f
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.ckt
@@ -0,0 +1,24 @@
+* eeschema netlist version 1.1 (spice format) creation date: tuesday 23 april 2013 12:03:40 pm ist
+
+* Plotting option vplot8_1
+v1  2 0 sine(0 1 50  )
+r6  3 6 10k
+r1  1 2 10k
+c1  6 1 1m
+r3  6 0 15k
+r9  7 0 1k
+c2  11 0 1m
+r7  4 9 8k
+r8  8 0 3.4k
+c4  7 9 1m
+r5  11 0 870
+r4  4 10 10k
+v2  4 0 12
+c3  8 3 1m
+r2  4 6 100k
+q2 9 10 8 npn
+q1 10 6 11 npn
+
+.tran  2e-03 20e-03 0e-00
+.plot v(8) v(7) 
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out
new file mode 100644
index 0000000..669fcbb
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.cir.out
@@ -0,0 +1,29 @@
+* eeschema netlist version 1.1 (spice format) creation date: tuesday 23 april 2013 12:03:40 pm ist
+
+* Plotting option vplot8_1
+v1  2 0 sine(0 1 50  )
+r6  3 6 10k
+r1  1 2 10k
+c1  6 1 1m
+r3  6 0 15k
+r9  7 0 1k
+c2  11 0 1m
+r7  4 9 8k
+r8  8 0 3.4k
+c4  7 9 1m
+r5  11 0 870
+r4  4 10 10k
+v2  4 0 12
+c3  8 3 1m
+r2  4 6 100k
+q2 9 10 8 npn
+q1 10 6 11 npn
+
+.tran  2e-03 20e-03 0e-00
+
+* Control Statements 
+.control
+run
+plot v(8) v(7) 
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro
new file mode 100644
index 0000000..29f504b
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.pro
@@ -0,0 +1,74 @@
+update=Tuesday 23 April 2013 10:45:01 AM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj
new file mode 100644
index 0000000..a6cb330
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.proj
@@ -0,0 +1 @@
+schematicFile example_7.4.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch
new file mode 100644
index 0000000..1f165d6
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_7/example_7.4/example_7.4.sch
@@ -0,0 +1,348 @@
+EESchema Schematic File Version 2  date Tuesday 23 April 2013 12:03:44 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
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