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| author | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
|---|---|---|
| committer | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
| commit | 8377256e7d90aa7ba1cb51f6164e99f81e2eb53c (patch) | |
| tree | 5afcc8e82d7f7d4f6fbff900520bd8f05eb343ca /OSCAD/Examples/linear1/linear1.cir.ckt.sol | |
| download | FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.gz FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.bz2 FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.zip | |
initial commit
Diffstat (limited to 'OSCAD/Examples/linear1/linear1.cir.ckt.sol')
| -rw-r--r-- | OSCAD/Examples/linear1/linear1.cir.ckt.sol | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/OSCAD/Examples/linear1/linear1.cir.ckt.sol b/OSCAD/Examples/linear1/linear1.cir.ckt.sol new file mode 100644 index 0000000..5727235 --- /dev/null +++ b/OSCAD/Examples/linear1/linear1.cir.ckt.sol @@ -0,0 +1,14 @@ +Name Source Sink Voltage Current +---------------------------------------------------------- +E 4 6 0.0000000000 0.0000000000 +I 1 2 0.0000000000 0.0000000000 +I 0 6 -0.0000000000 0.0000000000 +V 3 0 0.0000000000 0.0000000000 +G 6 1 0.0000000000 -0.0000000000 +I 0 2 -0.0000000000 0.0000000000 +R 1 0 0.0000000000 0.0000000000 +R 2 0 0.0000000000 0.0000000000 +R 1 2 0.0000000000 0.0000000000 +R 2 6 0.0000000000 0.0000000000 +R 4 0 0.0000000000 0.0000000000 +R 4 3 0.0000000000 0.0000000000 |