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| author | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
|---|---|---|
| committer | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
| commit | 8377256e7d90aa7ba1cb51f6164e99f81e2eb53c (patch) | |
| tree | 5afcc8e82d7f7d4f6fbff900520bd8f05eb343ca /OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst | |
| download | FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.gz FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.bz2 FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.zip | |
initial commit
Diffstat (limited to 'OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst')
| -rw-r--r-- | OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst new file mode 100644 index 0000000..a966a95 --- /dev/null +++ b/OSCAD/Examples/bridgeRectifier/bridgeRectifier.lst @@ -0,0 +1,25 @@ +eeschema (2011-05-25)-stable >> Creation date: Monday 15 October 2012 02:40:18 PM IST + +#Cmp ( order = Reference ) +| D1 DIODE +| D2 DIODE +| D3 DIODE +| D4 DIODE +| R1 1000 +| U1 VPLOT1 +| U2 VPLOT +| V1 SINE +#End Cmp + +#Cmp ( order = Value ) +| 1000 R1 +| DIODE D1 +| DIODE D2 +| DIODE D3 +| DIODE D4 +| SINE V1 +| VPLOT U2 +| VPLOT1 U1 +#End Cmp + +#End List |