initial commit

16 files changed, 1341 insertions, 0 deletions

diff --git a/OSCAD/Examples/RC_pcb/$savepcb.000 b/OSCAD/Examples/RC_pcb/$savepcb.000
new file mode 100644
index 0000000..8c07ce1
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/$savepcb.000
@@ -0,0 +1,203 @@
+PCBNEW-BOARD Version 1 date Thursday 16 May 2013 12:19:27 PM IST
+
+# Created by Pcbnew(2011-05-25)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 3
+NoConn 3
+Di -1875 -1494 1875 721
+Ndraw 0
+Ntrack 0
+Nzone 0
+BoardThickness 630
+Nmodule 3
+Nnets 4
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "16 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 315
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 1 "GND"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 2 "N-000001"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 3 "N-000003"
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 315
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+AddNet "GND"
+AddNet "N-000001"
+AddNet "N-000003"
+$EndNCLASS
+$MODULE SIL-2
+Po 0 0 0 15 00200000 51947CAE ~~
+Li SIL-2
+Cd Connecteurs 2 pins
+Kw CONN DEV
+Sc 51947CAE
+AR /51868B92
+Op 0 0 0
+T0 0 -1000 681 428 0 107 N V 21 N "P1"
+T1 0 -1000 600 400 0 100 N I 21 N "CONN_2"
+DS -1000 500 -1000 -500 120 21
+DS -1000 -500 1000 -500 120 21
+DS 1000 -500 1000 500 120 21
+DS 1000 500 -1000 500 120 21
+$PAD
+Sh "1" R 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000003"
+Po 500 0
+$EndPAD
+$EndMODULE  SIL-2
+$MODULE R3
+Po 0 0 0 15 00200000 51947CAF ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 51947CAF
+AR /51863417
+Op 0 A 0
+T0 0 0 550 500 0 80 N V 21 N "R1"
+T1 0 0 550 500 0 80 N I 21 N "1k"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
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+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
+DS -1300 -200 -1100 -400 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000001"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000003"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE C1
+Po 0 0 0 15 3F92C496 51947CB0 ~~
+Li C1
+Cd Condensateur e = 1 pas
+Kw C
+Sc 51947CB0
+AR /5186342E
+Op 0 0 0
+T0 100 -900 400 400 0 80 N V 21 N "C1"
+T1 0 -900 400 400 0 80 N I 21 N "1u"
+DS -980 -500 1000 -500 120 21
+DS 1000 -500 1000 500 120 21
+DS 1000 500 -1000 500 120 21
+DS -1000 500 -1000 -500 120 21
+DS -1000 -250 -750 -500 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000001"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 500 0
+$EndPAD
+$SHAPE3D
+Na "discret/capa_1_pas.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  C1
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/OSCAD/Examples/RC_pcb/$savepcb.brd b/OSCAD/Examples/RC_pcb/$savepcb.brd
new file mode 100644
index 0000000..22858c3
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/$savepcb.brd
@@ -0,0 +1,203 @@
+PCBNEW-BOARD Version 1 date Thursday 16 May 2013 12:56:45 PM IST
+
+# Created by Pcbnew(2011-05-25)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 3
+NoConn 3
+Di -1875 -1494 1875 721
+Ndraw 0
+Ntrack 0
+Nzone 0
+BoardThickness 630
+Nmodule 3
+Nnets 4
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "16 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 315
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 1 "GND"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 2 "N-000001"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 3 "N-000003"
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 315
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+AddNet "GND"
+AddNet "N-000001"
+AddNet "N-000003"
+$EndNCLASS
+$MODULE SIL-2
+Po 0 0 0 15 00200000 51947CAE ~~
+Li SIL-2
+Cd Connecteurs 2 pins
+Kw CONN DEV
+Sc 51947CAE
+AR /51868B92
+Op 0 0 0
+T0 0 -1000 681 428 0 107 N V 21 N "P1"
+T1 0 -1000 600 400 0 100 N I 21 N "CONN_2"
+DS -1000 500 -1000 -500 120 21
+DS -1000 -500 1000 -500 120 21
+DS 1000 -500 1000 500 120 21
+DS 1000 500 -1000 500 120 21
+$PAD
+Sh "1" R 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000003"
+Po 500 0
+$EndPAD
+$EndMODULE  SIL-2
+$MODULE R3
+Po 0 0 0 15 00200000 51947CAF ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 51947CAF
+AR /51863417
+Op 0 A 0
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+T1 0 0 550 500 0 80 N I 21 N "1k"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
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+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
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+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000001"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000003"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE C1
+Po 0 0 0 15 3F92C496 51947CB0 ~~
+Li C1
+Cd Condensateur e = 1 pas
+Kw C
+Sc 51947CB0
+AR /5186342E
+Op 0 0 0
+T0 100 -900 400 400 0 80 N V 21 N "C1"
+T1 0 -900 400 400 0 80 N I 21 N "1u"
+DS -980 -500 1000 -500 120 21
+DS 1000 -500 1000 500 120 21
+DS 1000 500 -1000 500 120 21
+DS -1000 500 -1000 -500 120 21
+DS -1000 -250 -750 -500 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000001"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 500 0
+$EndPAD
+$SHAPE3D
+Na "discret/capa_1_pas.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  C1
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/OSCAD/Examples/RC_pcb/RC-SilkS_Back.gbo b/OSCAD/Examples/RC_pcb/RC-SilkS_Back.gbo
new file mode 100644
index 0000000..9f1f35b
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC-SilkS_Back.gbo
@@ -0,0 +1,12 @@
+G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST*
+G01*
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+G04 Gerber Fmt 3.4, Leading zero omitted, Abs format*
+%FSLAX34Y34*%
+G04 APERTURE LIST*
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+G54D10*
+M02*
diff --git a/OSCAD/Examples/RC_pcb/RC-SilkS_Front.gto b/OSCAD/Examples/RC_pcb/RC-SilkS_Front.gto
new file mode 100644
index 0000000..95cd1a3
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC-SilkS_Front.gto
@@ -0,0 +1,113 @@
+G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST*
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diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-Back.gbl b/OSCAD/Examples/RC_pcb/RC_pcb-Back.gbl
new file mode 100644
index 0000000..020cb57
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb-Back.gbl
@@ -0,0 +1,30 @@
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diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-Front.gtl b/OSCAD/Examples/RC_pcb/RC_pcb-Front.gtl
new file mode 100644
index 0000000..3f06326
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb-Front.gtl
@@ -0,0 +1,22 @@
+G04 (created by PCBNEW-RS274X (2011-05-25)-stable) date Sunday 05 May 2013 10:21:02 PM IST*
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diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-cache.bak b/OSCAD/Examples/RC_pcb/RC_pcb-cache.bak
new file mode 100644
index 0000000..3b20495
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb-cache.bak
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3  Date: Tuesday 14 May 2013 12:09:45 AM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_2
+#
+DEF CONN_2 P 0 40 Y N 1 F N
+F0 "P" -50 0 40 V V C CNN
+F1 "CONN_2" 50 0 40 V V C CNN
+DRAW
+S -100 150 100 -150 0 1 0 N
+X P1 1 -350 100 250 R 60 60 1 1 P I
+X PM 2 -350 -100 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb-cache.lib b/OSCAD/Examples/RC_pcb/RC_pcb-cache.lib
new file mode 100644
index 0000000..a8a529e
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3  Date: Wednesday 15 May 2013 06:47:37 PM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_2
+#
+DEF CONN_2 P 0 40 Y N 1 F N
+F0 "P" -50 0 40 V V C CNN
+F1 "CONN_2" 50 0 40 V V C CNN
+DRAW
+S -100 150 100 -150 0 1 0 N
+X P1 1 -350 100 250 R 60 60 1 1 P I
+X PM 2 -350 -100 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.bak b/OSCAD/Examples/RC_pcb/RC_pcb.bak
new file mode 100644
index 0000000..7ad2473
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.bak
@@ -0,0 +1,125 @@
+EESchema Schematic File Version 2  date Tuesday 14 May 2013 12:09:45 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:RC-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "13 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	6100 2200 6100 2050
+Wire Wire Line
+	4900 2600 4900 3050
+Connection ~ 6100 2050
+Connection ~ 5550 3050
+Wire Wire Line
+	5550 3050 5550 3200
+Wire Wire Line
+	6100 2600 6100 3050
+Wire Wire Line
+	6100 3050 4900 3050
+Wire Wire Line
+	5400 2050 5400 2000
+Wire Wire Line
+	5400 2000 4900 2000
+Wire Wire Line
+	6100 2050 5900 2050
+Wire Wire Line
+	5400 2900 5400 3050
+Connection ~ 5400 3050
+Wire Wire Line
+	4900 2000 4900 2400
+$Comp
+L CONN_2 P1
+U 1 1 51868B92
+P 4550 2500
+F 0 "P1" V 4500 2500 40  0000 C CNN
+F 1 "CONN_2" V 4600 2500 40  0000 C CNN
+	1    4550 2500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 51863585
+P 5400 2900
+F 0 "#FLG01" H 5400 3170 30  0001 C CNN
+F 1 "PWR_FLAG" H 5400 3130 30  0000 C CNN
+	1    5400 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5186344D
+P 5550 3200
+F 0 "#PWR02" H 5550 3200 30  0001 C CNN
+F 1 "GND" H 5550 3130 30  0001 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C1
+U 1 1 5186342E
+P 6100 2400
+F 0 "C1" H 6150 2500 50  0000 L CNN
+F 1 "1u" H 6150 2300 50  0000 L CNN
+	1    6100 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 51863417
+P 5650 2050
+F 0 "R1" V 5730 2050 50  0000 C CNN
+F 1 "1k" V 5650 2050 50  0000 C CNN
+	1    5650 2050
+	0    1    1    0   
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.brd b/OSCAD/Examples/RC_pcb/RC_pcb.brd
new file mode 100644
index 0000000..335c0b9
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.brd
@@ -0,0 +1,225 @@
+PCBNEW-BOARD Version 1 date Sunday 05 May 2013 10:20:45 PM IST
+
+# Created by Pcbnew(2011-05-25)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 3
+NoConn 0
+Di 55424 33924 63076 39076
+Ndraw 4
+Ntrack 3
+Nzone 0
+BoardThickness 630
+Nmodule 3
+Nnets 4
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "5 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 315
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 1 "GND"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 2 "N-000001"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 3 "N-000003"
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 315
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+AddNet "GND"
+AddNet "N-000001"
+AddNet "N-000003"
+$EndNCLASS
+$MODULE SIL-2
+Po 61000 37000 900 15 00200000 51868CE1 ~~
+Li SIL-2
+Cd Connecteurs 2 pins
+Kw CONN DEV
+Sc 51868CE1
+AR /51868B92
+Op 0 0 0
+T0 0 -1000 681 428 900 107 N V 21 N "P1"
+T1 0 -1000 600 400 900 100 N I 21 N "CONN_2"
+DS -1000 500 -1000 -500 120 21
+DS -1000 -500 1000 -500 120 21
+DS 1000 -500 1000 500 120 21
+DS 1000 500 -1000 500 120 21
+$PAD
+Sh "1" R 550 550 0 0 900
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 900
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000003"
+Po 500 0
+$EndPAD
+$EndMODULE  SIL-2
+$MODULE R3
+Po 58500 35500 0 15 00200000 51868CE2 ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 51868CE2
+AR /51863417
+Op 0 A 0
+T0 0 0 550 500 0 80 N V 21 N "R1"
+T1 0 0 550 500 0 80 N I 21 N "1k"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
+DS 1300 0 1300 -400 120 21
+DS 1300 -400 -1300 -400 120 21
+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
+DS -1300 -200 -1100 -400 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000001"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000003"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE C1
+Po 57500 37500 0 15 3F92C496 51868CE3 ~~
+Li C1
+Cd Condensateur e = 1 pas
+Kw C
+Sc 51868CE3
+AR /5186342E
+Op 0 0 0
+T0 100 -900 400 400 0 80 N V 21 N "C1"
+T1 0 -900 400 400 0 80 N I 21 N "1u"
+DS -980 -500 1000 -500 120 21
+DS 1000 -500 1000 500 120 21
+DS 1000 500 -1000 500 120 21
+DS -1000 500 -1000 -500 120 21
+DS -1000 -250 -750 -500 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000001"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 500 0
+$EndPAD
+$SHAPE3D
+Na "discret/capa_1_pas.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  C1
+$DRAWSEGMENT
+Po 0 55500 39000 55500 34000 150
+De 28 0 900 0 0
+$EndDRAWSEGMENT
+$DRAWSEGMENT
+Po 0 63000 39000 55500 39000 150
+De 28 0 900 0 0
+$EndDRAWSEGMENT
+$DRAWSEGMENT
+Po 0 63000 34000 63000 39000 150
+De 28 0 900 0 0
+$EndDRAWSEGMENT
+$DRAWSEGMENT
+Po 0 55500 34000 63000 34000 150
+De 28 0 900 0 0
+$EndDRAWSEGMENT
+$TRACK
+Po 0 58000 37500 61000 37500 315 -1
+De 0 0 1 0 C00000
+Po 0 57000 35500 57000 37500 315 -1
+De 0 0 2 0 C00000
+Po 0 60000 35500 61000 36500 315 -1
+De 0 0 3 0 C00000
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.cir.ckt.sol b/OSCAD/Examples/RC_pcb/RC_pcb.cir.ckt.sol
new file mode 100644
index 0000000..29b1351
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.cir.ckt.sol
@@ -0,0 +1,6 @@
+Name	 Source	 Sink	       Voltage	       Current
+----------------------------------------------------------
+V	 1	 0	    0.0000000000    0.0000000000
+C	 3	 0	    0.0000000000    0.0000000000
+I	 0	 3	   -0.0000000000    0.0000000000
+R	 3	 1	    0.0000000000    0.0000000000
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.cmp b/OSCAD/Examples/RC_pcb/RC_pcb.cmp
new file mode 100644
index 0000000..14cc046
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.cmp
@@ -0,0 +1,24 @@
+Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Thursday 16 May 2013 01:22:40 AM IST
+
+BeginCmp
+TimeStamp = /5186342E;
+Reference = C1;
+ValeurCmp = 1u;
+IdModule  = C1;
+EndCmp
+
+BeginCmp
+TimeStamp = /51868B92;
+Reference = P1;
+ValeurCmp = CONN_2;
+IdModule  = SIL-2;
+EndCmp
+
+BeginCmp
+TimeStamp = /51863417;
+Reference = R1;
+ValeurCmp = 1k;
+IdModule  = R3;
+EndCmp
+
+EndListe
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.net b/OSCAD/Examples/RC_pcb/RC_pcb.net
new file mode 100644
index 0000000..1cda301
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.net
@@ -0,0 +1,30 @@
+# EESchema Netlist Version 1.1 created  Thursday 16 May 2013 01:22:40 AM IST
+(
+ ( /5186342E C1 C1 1u
+  ( 1 N-000001 )
+  ( 2 GND )
+ )
+ ( /51868B92 SIL-2 P1 CONN_2
+  ( 1 GND )
+  ( 2 N-000003 )
+ )
+ ( /51863417 R3 R1 1k
+  ( 1 N-000001 )
+  ( 2 N-000003 )
+ )
+)
+*
+{ Allowed footprints by component:
+$component C1
+ SM*
+ C?
+ C1-1
+$endlist
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$endfootprintlist
+}
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.pro b/OSCAD/Examples/RC_pcb/RC_pcb.pro
new file mode 100644
index 0000000..952e2e1
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.pro
@@ -0,0 +1,74 @@
+update=Monday 13 May 2013 07:10:16 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/rakhi/OSCAD/library/analogSpice
+LibName32=/home/rakhi/OSCAD/library/analogXSpice
+LibName33=/home/rakhi/OSCAD/library/convergenceAidSpice
+LibName34=/home/rakhi/OSCAD/library/converterSpice
+LibName35=/home/rakhi/OSCAD/library/digitalSpice
+LibName36=/home/rakhi/OSCAD/library/digitalXSpice
+LibName37=/home/rakhi/OSCAD/library/linearSpice
+LibName38=/home/rakhi/OSCAD/library/measurementSpice
+LibName39=/home/rakhi/OSCAD/library/portSpice
+LibName40=/home/rakhi/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.proj b/OSCAD/Examples/RC_pcb/RC_pcb.proj
new file mode 100644
index 0000000..396e6d0
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.proj
@@ -0,0 +1 @@
+schematicFile RC.sch
diff --git a/OSCAD/Examples/RC_pcb/RC_pcb.sch b/OSCAD/Examples/RC_pcb/RC_pcb.sch
new file mode 100644
index 0000000..8661fb3
--- /dev/null
+++ b/OSCAD/Examples/RC_pcb/RC_pcb.sch
@@ -0,0 +1,123 @@
+EESchema Schematic File Version 2  date Wednesday 15 May 2013 06:47:37 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:RC-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "15 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	4900 2050 5400 2050
+Wire Wire Line
+	4900 2050 4900 2400
+Connection ~ 5400 3050
+Wire Wire Line
+	5400 2900 5400 3050
+Wire Wire Line
+	5900 2050 6100 2050
+Wire Wire Line
+	6100 3050 4900 3050
+Wire Wire Line
+	6100 3050 6100 2600
+Wire Wire Line
+	5550 3050 5550 3200
+Connection ~ 5550 3050
+Connection ~ 6100 2050
+Wire Wire Line
+	4900 3050 4900 2600
+Wire Wire Line
+	6100 2050 6100 2200
+$Comp
+L CONN_2 P1
+U 1 1 51868B92
+P 4550 2500
+F 0 "P1" V 4500 2500 40  0000 C CNN
+F 1 "CONN_2" V 4600 2500 40  0000 C CNN
+	1    4550 2500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 51863585
+P 5400 2900
+F 0 "#FLG01" H 5400 3170 30  0001 C CNN
+F 1 "PWR_FLAG" H 5400 3130 30  0000 C CNN
+	1    5400 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5186344D
+P 5550 3200
+F 0 "#PWR02" H 5550 3200 30  0001 C CNN
+F 1 "GND" H 5550 3130 30  0001 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C1
+U 1 1 5186342E
+P 6100 2400
+F 0 "C1" H 6150 2500 50  0000 L CNN
+F 1 "1u" H 6150 2300 50  0000 L CNN
+	1    6100 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 51863417
+P 5650 2050
+F 0 "R1" V 5730 2050 50  0000 C CNN
+F 1 "1k" V 5650 2050 50  0000 C CNN
+	1    5650 2050
+	0    1    1    0   
+$EndComp
+$EndSCHEMATC