initial commit

10 files changed, 584 insertions, 0 deletions

diff --git a/OSCAD/Examples/RC/RC-cache.bak b/OSCAD/Examples/RC/RC-cache.bak
new file mode 100644
index 0000000..65af569
--- /dev/null
+++ b/OSCAD/Examples/RC/RC-cache.bak
@@ -0,0 +1,99 @@
+EESchema-LIBRARY Version 2.3  Date: Friday 24 May 2013 02:53:57 PM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/RC/RC-cache.lib b/OSCAD/Examples/RC/RC-cache.lib
new file mode 100644
index 0000000..e808d27
--- /dev/null
+++ b/OSCAD/Examples/RC/RC-cache.lib
@@ -0,0 +1,99 @@
+EESchema-LIBRARY Version 2.3  Date: Friday 24 May 2013 02:54:22 PM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/RC/RC.bak b/OSCAD/Examples/RC/RC.bak
new file mode 100644
index 0000000..4b41a9e
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.bak
@@ -0,0 +1,136 @@
+EESchema Schematic File Version 2  date Friday 24 May 2013 02:53:57 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:RC-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "24 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 4650 2650
+Connection ~ 5900 2650
+$Comp
+L SINE v1
+U 1 1 519F2A93
+P 4650 3100
+F 0 "v1" H 4450 3200 60  0000 C CNN
+F 1 "SINE" H 4450 3050 60  0000 C CNN
+F 2 "R1" H 4350 3100 60  0000 C CNN
+	1    4650 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5900 3300 5900 3550
+Wire Wire Line
+	5600 2650 5900 2650
+Connection ~ 5400 3550
+Wire Wire Line
+	5400 3550 5400 3800
+Wire Wire Line
+	5900 3550 4650 3550
+Wire Wire Line
+	4650 2650 5100 2650
+Wire Wire Line
+	5900 2650 5900 2900
+$Comp
+L VPLOT8_1 U1
+U 2 1 519F22B7
+P 5900 2350
+F 0 "U1" H 5750 2450 50  0000 C CNN
+F 1 "VPLOT8_1" H 6050 2450 50  0000 C CNN
+	2    5900 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG1
+U 1 1 519F229B
+P 5400 3550
+F 0 "#FLG1" H 5400 3820 30  0001 C CNN
+F 1 "PWR_FLAG" H 5400 3780 30  0000 C CNN
+	1    5400 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR1
+U 1 1 519F2294
+P 5400 3800
+F 0 "#PWR1" H 5400 3800 30  0001 C CNN
+F 1 "GND" H 5400 3730 30  0001 C CNN
+	1    5400 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 519F228E
+P 4650 2350
+F 0 "U1" H 4500 2450 50  0000 C CNN
+F 1 "VPLOT8_1" H 4800 2450 50  0000 C CNN
+	1    4650 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 519F2283
+P 5350 2650
+F 0 "R1" V 5430 2650 50  0000 C CNN
+F 1 "1k" V 5350 2650 50  0000 C CNN
+	1    5350 2650
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 519F227E
+P 5900 3100
+F 0 "C1" H 5950 3200 50  0000 L CNN
+F 1 "1u" H 5950 3000 50  0000 L CNN
+	1    5900 3100
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/RC/RC.cir b/OSCAD/Examples/RC/RC.cir
new file mode 100644
index 0000000..17738ac
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.cir
@@ -0,0 +1,12 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Friday 24 May 2013 02:23:51 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+v1  1 0 SINE		
+U1  1 3 VPLOT8_1		
+R1  3 1 1k		
+C1  0 3 1u		
+
+.end
diff --git a/OSCAD/Examples/RC/RC.cir.ckt b/OSCAD/Examples/RC/RC.cir.ckt
new file mode 100644
index 0000000..7a8138f
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.cir.ckt
@@ -0,0 +1,10 @@
+* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:23:51 pm ist

+

+v1  1 0 sine(0 5 300 0 0)

+* Plotting option vplot8_1

+r1  3 1 1k

+c1  0 3 1u

+

+.tran  5e-03 30e-03 0e-00

+.plot v(1) v(3) 

+.end

diff --git a/OSCAD/Examples/RC/RC.cir.out b/OSCAD/Examples/RC/RC.cir.out
new file mode 100644
index 0000000..01e68ad
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.cir.out
@@ -0,0 +1,15 @@
+* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:23:51 pm ist

+

+v1  1 0 sine(0 5 300 0 0)

+* Plotting option vplot8_1

+r1  3 1 1k

+c1  0 3 1u

+

+.tran  5e-03 30e-03 0e-00

+

+* Control Statements 

+.control

+run

+plot v(1) v(3) 

+.endc

+.end

diff --git a/OSCAD/Examples/RC/RC.pro b/OSCAD/Examples/RC/RC.pro
new file mode 100644
index 0000000..cfb5fa1
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.pro
@@ -0,0 +1,74 @@
+update=Friday 24 May 2013 02:22:07 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/RC/RC.proj b/OSCAD/Examples/RC/RC.proj
new file mode 100644
index 0000000..396e6d0
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.proj
@@ -0,0 +1 @@
+schematicFile RC.sch
diff --git a/OSCAD/Examples/RC/RC.sch b/OSCAD/Examples/RC/RC.sch
new file mode 100644
index 0000000..6afd4fa
--- /dev/null
+++ b/OSCAD/Examples/RC/RC.sch
@@ -0,0 +1,137 @@
+EESchema Schematic File Version 2  date Friday 24 May 2013 02:54:22 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:RC-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "24 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 5200 3550
+Connection ~ 4650 2650
+Connection ~ 5900 2650
+$Comp
+L SINE v1
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+F 2 "R1" H 4350 3100 60  0000 C CNN
+	1    4650 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	5600 2650 5900 2650
+Connection ~ 5400 3550
+Wire Wire Line
+	5400 3550 5400 3800
+Wire Wire Line
+	5900 3550 4650 3550
+Wire Wire Line
+	4650 2650 5100 2650
+Wire Wire Line
+	5900 2650 5900 2900
+$Comp
+L VPLOT8_1 U1
+U 2 1 519F22B7
+P 5900 2350
+F 0 "U1" H 5750 2450 50  0000 C CNN
+F 1 "VPLOT8_1" H 6050 2450 50  0000 C CNN
+	2    5900 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG1
+U 1 1 519F229B
+P 5200 3550
+F 0 "#FLG1" H 5200 3820 30  0001 C CNN
+F 1 "PWR_FLAG" H 5200 3780 30  0000 C CNN
+	1    5200 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR1
+U 1 1 519F2294
+P 5400 3800
+F 0 "#PWR1" H 5400 3800 30  0001 C CNN
+F 1 "GND" H 5400 3730 30  0001 C CNN
+	1    5400 3800
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+$EndComp
+$Comp
+L VPLOT8_1 U1
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+P 4650 2350
+F 0 "U1" H 4500 2450 50  0000 C CNN
+F 1 "VPLOT8_1" H 4800 2450 50  0000 C CNN
+	1    4650 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 519F2283
+P 5350 2650
+F 0 "R1" V 5430 2650 50  0000 C CNN
+F 1 "1k" V 5350 2650 50  0000 C CNN
+	1    5350 2650
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 519F227E
+P 5900 3100
+F 0 "C1" H 5950 3200 50  0000 L CNN
+F 1 "1u" H 5950 3000 50  0000 L CNN
+	1    5900 3100
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/RC/analysis b/OSCAD/Examples/RC/analysis
new file mode 100644
index 0000000..4d26811
--- /dev/null
+++ b/OSCAD/Examples/RC/analysis
@@ -0,0 +1 @@
+.tran  5e-03 30e-03 0e-00