From 871480933a1c28f8a9fed4c4d34d06c439a7a422 Mon Sep 17 00:00:00 2001 From: Srikant Patnaik Date: Sun, 11 Jan 2015 12:28:04 +0530 Subject: Moved, renamed, and deleted files The original directory structure was scattered and unorganized. Changes are basically to make it look like kernel structure. --- .../wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.c | 1561 +++ .../wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.h | 70 + .../net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.c | 11649 +++++++++++++++++++ .../net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.h | 1985 ++++ .../rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.c | 1184 ++ .../rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.h | 195 + .../rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11AC.h | 55 + .../rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11N.h | 172 + .../wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.c | 627 + .../wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.h | 905 ++ .../rtl8188E_8192E/hal/OUTSRC/odm_interface.c | 666 ++ .../rtl8188E_8192E/hal/OUTSRC/odm_interface.h | 374 + .../rtl8188E_8192E/hal/OUTSRC/odm_precomp.h | 222 + .../wireless/rtl8188E_8192E/hal/OUTSRC/odm_reg.h | 120 + .../wireless/rtl8188E_8192E/hal/OUTSRC/odm_types.h | 252 + .../hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c | 892 ++ .../hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h | 29 + .../hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c | 1105 ++ .../hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h | 108 + .../hal/OUTSRC/rtl8188e/Hal8188EReg.h | 47 + .../hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c | 891 ++ .../hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h | 56 + .../hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c | 1077 ++ .../hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h | 65 + .../hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c | 329 + .../hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h | 38 + .../hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c | 377 + .../hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h | 38 + .../hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c | 3500 ++++++ .../hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h | 135 + .../hal/OUTSRC/rtl8188e/odm_RTL8188E.c | 1290 ++ .../hal/OUTSRC/rtl8188e/odm_RTL8188E.h | 109 + .../hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c | 209 + .../hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h | 80 + 34 files changed, 30412 insertions(+) create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11AC.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11N.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_precomp.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_reg.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_types.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c create mode 100755 drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h (limited to 'drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC') diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.c new file mode 100755 index 00000000..ceed28c7 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/HalPhyRf.c @@ -0,0 +1,1561 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #include "odm_precomp.h" + +#if(DM_ODM_SUPPORT_TYPE & ODM_MP) +#include "Mp_Precomp.h" + +VOID +phy_PathAStandBy( + IN PADAPTER pAdapter + ) +{ + RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); + + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x0); + PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000); +} + +//1 7. IQK +//#define MAX_TOLERANCE 5 +//#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8192C( + IN PADAPTER pAdapter, + IN BOOLEAN configPathB + ) +{ + + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); + + //path-A IQK setting + RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); + if(pAdapter->interfaceIndex == 0) + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + } + else + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22); + } + + PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102); + + PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 : + IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502); + + //path-B IQK setting + if(configPathB) + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160206); + else + PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202); + } + + //LO calibration setting + RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + else + PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1); + + //One shot, path A LOK & IQK + RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); + PlatformStallExecution(IQK_DELAY_TIME*1000); + + // Check failed + regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); + regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); + regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); + regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8192C( + IN PADAPTER pAdapter + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; + RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); + PlatformStallExecution(IQK_DELAY_TIME*1000); + + // Check failed + regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); + regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); + regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); + regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +phy_PathAFillIQKMatrix( + IN PADAPTER pAdapter, + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT24, ((X* Oldval_0>>7) & 0x1)); + else + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //path B IQK result + 3 + if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType92D == BAND_ON_5G) + Y += 3; + + TX0_C = (Y * Oldval_0) >> 8; + RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + if(IS_HARDWARE_TYPE_8192D(pAdapter)/*&&is2T*/) + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT26, ((Y* Oldval_0>>7) & 0x1)); + else + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +phy_PathBFillIQKMatrix( + IN PADAPTER pAdapter, + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT28, ((X* Oldval_1>>7) & 0x1)); + else + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + if(pHalData->CurrentBandType92D == BAND_ON_5G) + Y += 3; //temp modify for preformance + TX1_C = (Y * Oldval_1) >> 8; + RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT30, ((Y* Oldval_1>>7) & 0x1)); + else + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + + +BOOLEAN +phy_SimularityCompare_92C( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); + + if(is2T) + bound = 8; + else + bound = 4; + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1< do IQK again +*/ +BOOLEAN +phy_SimularityCompare( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + return phy_SimularityCompare_92D(pAdapter, result, c1, c2); + else + return phy_SimularityCompare_92C(pAdapter, result, c1, c2); + +} + +VOID +phy_IQCalibrate_8192C( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u4Byte i; + u1Byte PathAOK, PathBOK; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD + }; + + u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rFPGA0_AnalogParameter4, + rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1 + }; + u4Byte retryCount; +#if MP_DRIVER + if (pAdapter->registrypriv.mp_mode == 1) + retryCount = 9; + else +#endif + retryCount = 2; + + + //Neil Chen--2011--05--19-- + //3 Path Div + u1Byte rfPathSwitch=0x0; + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + u4Byte bbvalue; + + if(t==0) + { + bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue)); + + RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + + // Save ADDA parameters, turn Path A ADDA on + phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); + phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D); + else + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); + } + + phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); + + + + if(IS_HARDWARE_TYPE_8192D(pAdapter)){ + //============================== + //3 Path Diversity + ////Neil Chen--2011--05--20 + rfPathSwitch =(u1Byte) (PHY_QueryBBReg(pAdapter, 0xB30, bMaskDWord)>>27); + //rfPathSwitch = (u1Byte) DataB30; + rfPathSwitch = rfPathSwitch&(0x01); + + if(rfPathSwitch) // Path Div On + { + phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); + //DbgPrint("=STEP= change ADDA Path from B to A Path\n"); + } + else + { + phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); + } + //3 end + //===================================== + + PHY_SetBBReg(pAdapter, rPdp_AntA, bMaskDWord, 0x01017038); + } + + if(t==0) + { + pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pHalData->bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. + phy_PIModeSwitch(pAdapter, TRUE); + } + + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00); + PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xf00000, 0x0f); + else + { + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + } + + if(is2T) + { + PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + //MAC settings + phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + { + PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x0f600000); + } + } + else + { + //Page B init + PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000); + + if(is2T) + { + PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000); + } + } + // IQ calibration setting + RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000); + PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800); + + for(i = 0 ; i < retryCount ; i++){ + PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T); + if(PathAOK == 0x03){ + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n")); + result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathAOK){ + RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); + } + + if(is2T){ + phy_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); + + for(i = 0 ; i < retryCount ; i++){ + PathBOK = phy_PathB_IQK_8192C(pAdapter); + if(PathBOK == 0x03){ + RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0); + + if(t!=0) + { + if(!pHalData->bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. + phy_PIModeSwitch(pAdapter, FALSE); + } + + // Reload ADDA power saving parameters + phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + + // Reload BB parameters + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + { + if(is2T) + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D); + else + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D -1); + } + else + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); + + if(!IS_HARDWARE_TYPE_8192D(pAdapter)) + { + // Restore RX initial gain + PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if(is2T){ + PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + } + } + //load 0xe30 IQC default value + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n")); + +} + + +VOID +phy_LCCalibrate92C( + IN PADAPTER pAdapter, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //Check continuous TX and Packet TX + tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A + RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); + + //2. Set RF mode = standby mode + //Path-A + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 + LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); + + //4. Set LC calibration begin bit15 + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + delay_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00); + } +} + + +VOID +phy_LCCalibrate( + IN PADAPTER pAdapter, + IN BOOLEAN is2T + ) +{ + if(IS_HARDWARE_TYPE_8192D(pAdapter)) + { +#if SWLCK == 1 + phy_LCCalibrate92DSW(pAdapter, is2T); +#else + phy_LCCalibrate92D(pAdapter, is2T); +#endif + } + else + { + phy_LCCalibrate92C(pAdapter, is2T); + } +} + + + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8192C( + IN PADAPTER pAdapter, + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, i, apkbound; + u1Byte path, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; +#if 0 + u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { + {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, + {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} + }; +#endif + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +if (pAdapter->registrypriv.mp_mode == 1) +{ + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; +} +#endif + + RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta)); + RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + + if (pAdapter->registrypriv.mp_mode != 1) + return; + + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); + } + + //save MAC default value + phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000); + } + + //save RF default value + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask); + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); + } + + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); + + //MAC settings + phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); + + if(path == RF_PATH_A) //Path B to standby mode + { + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000); + } + else //Path A to standby mode + { + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pHalData->bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) + PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae); + else +#endif + PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask))); + PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); + PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask))); + + // PA11+PAD01111, one shot + i = 0; + do + { + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80000000); + { + PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); + delay_ms(3); + PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); + + delay_ms(20); + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000); + + if(path == RF_PATH_A) + tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000); + else + tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value + phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value + phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]); + if(path == RF_PATH_B) + { + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + RTPRINT(FINIT, INIT_IQK, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); + + if(!IS_HARDWARE_TYPE_8723A(pAdapter)) + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); + } + + pHalData->bAPKdone = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n")); +} + + +VOID +PHY_IQCalibrate_8192C( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + +#if MP_DRIVER == 1 +if (pAdapter->registrypriv.mp_mode == 1) +{ + bStartContTx = pAdapter->MptCtx.bStartContTx; + bSingleTone = pAdapter->MptCtx.bSingleTone; + bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; +} +#endif + + //ignore IQK when continuous Tx + if(bStartContTx || bSingleTone || bCarrierSuppression) + return; + +#if DISABLE_BB_RF + return; +#endif + if(pAdapter->bSlaveOfDMSP) + return; + + if(!IS_HARDWARE_TYPE_8192D(pAdapter)) + { + if(bReCovery) + { + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); + return; + + } + } + RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n")); + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + RTPRINT(FINIT, INIT_IQK, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pAdapter->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter))); + AcquireCCKAndRWPageAControl(pAdapter); +// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n")); + for (i=0; i<3; i++) + { +// if(IS_HARDWARE_TYPE_8192C(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter)) + if(!IS_HARDWARE_TYPE_8192D(pAdapter)) + { + if(IS_92C_SERIAL( pHalData->VersionID)) + { + phy_IQCalibrate_8192C(pAdapter, result, i, TRUE); + } + else + { + // For 88C 1T1R + phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); + } + } + else/* if(IS_HARDWARE_TYPE_8192D(pAdapter))*/ + { + if(pHalData->CurrentBandType92D == BAND_ON_5G) + { + phy_IQCalibrate_5G_Normal(pAdapter, result, i); + } + else if(pHalData->CurrentBandType92D == BAND_ON_2_4G) + { + if(IS_92D_SINGLEPHY(pHalData->VersionID)) + phy_IQCalibrate_8192C(pAdapter, result, i, TRUE); + else + phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); + } + } + + if(i == 1) + { + is12simular = phy_SimularityCompare(pAdapter, result, 0, 1); + if(is12simular) + { + final_candidate = 0; + break; + } + } + + if(i == 2) + { + is13simular = phy_SimularityCompare(pAdapter, result, 0, 2); + if(is13simular) + { + final_candidate = 0; + break; + } + + is23simular = phy_SimularityCompare(pAdapter, result, 1, 2); + if(is23simular) + final_candidate = 1; + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + ReleaseCCKAndRWPageAControl(pAdapter); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pHalData->RegE94 = RegE94 = result[final_candidate][0]; + pHalData->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pHalData->RegEB4 = RegEB4 = result[final_candidate][4]; + pHalData->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate)); + RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value + RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { + if(pHalData->CurrentBandType92D == BAND_ON_5G) + phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + else + phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + + } + + if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) + { + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + { + if(pHalData->CurrentBandType92D == BAND_ON_5G) + phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + else + phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } + + if(IS_HARDWARE_TYPE_8192D(pAdapter) && final_candidate != 0xFF) + { + Indexforchannel = GetRightChnlPlaceforIQK(pHalData->CurrentChannel); + + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pHalData->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = + result[final_candidate][i]; + + pHalData->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + } + + if(!IS_HARDWARE_TYPE_8192D(pAdapter)) + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); + +} + + +VOID +PHY_LCCalibrate_8192C( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; + PMGNT_INFO pMgntInfoBuddyAdapter; + u4Byte timeout = 2000, timecount = 0; + PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; + +#if MP_DRIVER == 1 +if (pAdapter->registrypriv.mp_mode == 1) +{ + bStartContTx = pAdapter->MptCtx.bStartContTx; + bSingleTone = pAdapter->MptCtx.bSingleTone; + bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; +} +#endif + +#if DISABLE_BB_RF + return; +#endif + + //ignore LCK when continuous Tx + if(bStartContTx || bSingleTone || bCarrierSuppression) + return; + + if(BuddyAdapter != NULL && + ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType92D == BAND_ON_2_4G) || + (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType92D == BAND_ON_5G))) + { + pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo; + while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout) + { + delay_ms(50); + timecount += 50; + } + } + + while(pMgntInfo->bScanInProgress && timecount < timeout) + { + delay_ms(50); + timecount += 50; + } + + pHalData->bLCKInProgress = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + + //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) + if(IS_2T2R(pHalData->VersionID)) + { + phy_LCCalibrate(pAdapter, TRUE); + } + else{ + // For 88C 1T1R + phy_LCCalibrate(pAdapter, FALSE); + } + + pHalData->bLCKInProgress = FALSE; + + RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex)); + + +} + +VOID +PHY_APCalibrate_8192C( + IN PADAPTER pAdapter, + IN s1Byte delta + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 + return; + +#if DISABLE_BB_RF + return; +#endif + + if(IS_HARDWARE_TYPE_8192D(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter)) + return; + +#if FOR_BRAZIL_PRETEST != 1 + if(pHalData->bAPKdone) +#endif + return; + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8192C(pAdapter, delta, TRUE); + } + else{ + // For 88C 1T1R + phy_APCalibrate_8192C(pAdapter, delta, FALSE); + } +} + + +#endif + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +) +{ + u1Byte i; +#if (DM_ODM_SUPPORT_TYPE == ODM_MP || DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (!IS_HARDWARE_TYPE_8192D(Adapter)) + return; +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM)); + //0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc + + for(i = 0; i < IQK_Matrix_Settings_NUM; i++) + { + { + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] = + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][2] = + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][4] = + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][6] = 0x100; + + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][1] = + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][3] = + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][5] = + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][7] = 0x0; + + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].bIQKDone = FALSE; + + } + } + +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; place To DO modify +u4Byte EDCAParam[HT_IOT_PEER_MAX][3] = +{ // UL DL + {0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP + {0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP + {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 2:unknown AP => realtek_92SE + {0x5ea32b, 0x5ea42b, 0x5e4322}, // 3:broadcom AP + {0x5ea422, 0x00a44f, 0x00a44f}, // 4:ralink AP + {0x5ea322, 0x00a630, 0x00a44f}, // 5:atheros AP + //{0x5ea42b, 0x5ea42b, 0x5ea42b},// 6:cisco AP + {0x5e4322, 0x5e4322, 0x5e4322},// 6:cisco AP + //{0x3ea430, 0x00a630, 0x3ea44f}, // 7:cisco AP + {0x5ea44f, 0x00a44f, 0x5ea42b}, // 8:marvell AP + //{0x5ea44f, 0x5ea44f, 0x5ea44f}, // 9realtek AP + {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 10:unknown AP=> 92U AP + {0x5ea42b, 0xa630, 0x5e431c}, // 11:airgocap AP +// {0x5e4322, 0x00a44f, 0x5ea44f}, // 12:unknown AP +}; +//============================================================ +// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 +//============================================================ +#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL) +enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG }; + +static const struct ParaRecord rtl_ap_EDCA[] = +{ +//ACM,AIFSN, ECWmin, ECWmax, TXOplimit + {0, 7, 4, 10, 0}, //BK + {0, 3, 4, 6, 0}, //BE + {0, 1, 3, 4, 188}, //VI + {0, 1, 2, 3, 102}, //VO + {0, 1, 3, 4, 94}, //VI_AG + {0, 1, 2, 3, 47}, //VO_AG +}; + +static const struct ParaRecord rtl_sta_EDCA[] = +{ +//ACM,AIFSN, ECWmin, ECWmax, TXOplimit + {0, 7, 4, 10, 0}, + {0, 3, 4, 10, 0}, + {0, 2, 3, 4, 188}, + {0, 2, 2, 3, 102}, + {0, 2, 3, 4, 94}, + {0, 2, 2, 3, 47}, +}; +#endif + +//============================================================ +// Global var +//============================================================ +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { + 0x7f8001fe, // 0, +6.0dB + 0x788001e2, // 1, +5.5dB + 0x71c001c7, // 2, +5.0dB + 0x6b8001ae, // 3, +4.5dB + 0x65400195, // 4, +4.0dB + 0x5fc0017f, // 5, +3.5dB + 0x5a400169, // 6, +3.0dB + 0x55400155, // 7, +2.5dB + 0x50800142, // 8, +2.0dB + 0x4c000130, // 9, +1.5dB + 0x47c0011f, // 10, +1.0dB + 0x43c0010f, // 11, +0.5dB + 0x40000100, // 12, +0dB + 0x3c8000f2, // 13, -0.5dB + 0x390000e4, // 14, -1.0dB + 0x35c000d7, // 15, -1.5dB + 0x32c000cb, // 16, -2.0dB + 0x300000c0, // 17, -2.5dB + 0x2d4000b5, // 18, -3.0dB + 0x2ac000ab, // 19, -3.5dB + 0x288000a2, // 20, -4.0dB + 0x26000098, // 21, -4.5dB + 0x24000090, // 22, -5.0dB + 0x22000088, // 23, -5.5dB + 0x20000080, // 24, -6.0dB + 0x1e400079, // 25, -6.5dB + 0x1c800072, // 26, -7.0dB + 0x1b00006c, // 27. -7.5dB + 0x19800066, // 28, -8.0dB + 0x18000060, // 29, -8.5dB + 0x16c0005b, // 30, -9.0dB + 0x15800056, // 31, -9.5dB + 0x14400051, // 32, -10.0dB + 0x1300004c, // 33, -10.5dB + 0x12000048, // 34, -11.0dB + 0x11000044, // 35, -11.5dB + 0x10000040, // 36, -12.0dB + 0x0f00003c,// 37, -12.5dB + 0x0e400039,// 38, -13.0dB + 0x0d800036,// 39, -13.5dB + 0x0cc00033,// 40, -14.0dB + 0x0c000030,// 41, -14.5dB + 0x0b40002d,// 42, -15.0dB +}; + + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB +}; + + +u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB +}; + + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; +#endif + +//============================================================ +// Local Function predefine. +//============================================================ + +//START------------COMMON INFO RELATED---------------// +VOID +odm_CommonInfoSelfInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_CommonInfoSelfUpdate( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_CmnInfoInit_Debug( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_CmnInfoHook_Debug( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_CmnInfoUpdate_Debug( + IN PDM_ODM_T pDM_Odm + ); +/* +VOID +odm_FindMinimumRSSI( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_IsLinked( + IN PDM_ODM_T pDM_Odm + ); +*/ +//END------------COMMON INFO RELATED---------------// + +//START---------------DIG---------------------------// +VOID +odm_FalseAlarmCounterStatistics( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DIGInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DIG( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_CCKPacketDetectionThresh( + IN PDM_ODM_T pDM_Odm + ); +//END---------------DIG---------------------------// + +//START-------BB POWER SAVE-----------------------// +VOID +odm_DynamicBBPowerSavingInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicBBPowerSaving( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_1R_CCA( + IN PDM_ODM_T pDM_Odm + ); +//END---------BB POWER SAVE-----------------------// + +//START-----------------PSD-----------------------// +#if(DM_ODM_SUPPORT_TYPE & (ODM_MP)) +//============================================================ +// Function predefine. +//============================================================ +VOID odm_PathDiversityInit_92C( IN PADAPTER Adapter); +VOID odm_2TPathDiversityInit_92C( IN PADAPTER Adapter); +VOID odm_1TPathDiversityInit_92C( IN PADAPTER Adapter); +BOOLEAN odm_IsConnected_92C(IN PADAPTER Adapter); +VOID odm_PathDiversityAfterLink_92C( IN PADAPTER Adapter); + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer + ); + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ); + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer + ); + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ); + +VOID odm_SetRespPath_92C( IN PADAPTER Adapter, IN u1Byte DefaultRespPath); +VOID odm_OFDMTXPathDiversity_92C( IN PADAPTER Adapter); +VOID odm_CCKTXPathDiversity_92C( IN PADAPTER Adapter); +VOID odm_ResetPathDiversity_92C( IN PADAPTER Adapter); + +//Start-------------------- RX High Power------------------------// +VOID odm_RXHPInit( IN PDM_ODM_T pDM_Odm); +VOID odm_RXHP( IN PDM_ODM_T pDM_Odm); +VOID odm_Write_RXHP( IN PDM_ODM_T pDM_Odm); + +VOID odm_PSD_RXHP( IN PDM_ODM_T pDM_Odm); +VOID odm_PSD_RXHPCallback( PRT_TIMER pTimer); +VOID odm_PSD_RXHPWorkitemCallback( IN PVOID pContext); +//End--------------------- RX High Power -----------------------// + +VOID +odm_PathDivInit( IN PDM_ODM_T pDM_Odm); + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ); + +#endif +//END-------------------PSD-----------------------// + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicTxPowerInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicTxPowerNIC( + IN PDM_ODM_T pDM_Odm + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Value); + +VOID +odm_DynamicTxPower_92C( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicTxPower_92D( + IN PDM_ODM_T pDM_Odm + ); +#endif + + +VOID +odm_RSSIMonitorInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_RSSIMonitorCheckMP( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_RSSIMonitorCheckCE( + IN PDM_ODM_T pDM_Odm + ); +VOID +odm_RSSIMonitorCheckAP( + IN PDM_ODM_T pDM_Odm + ); + + + +VOID +odm_RSSIMonitorCheck( + IN PDM_ODM_T pDM_Odm + ); +VOID +odm_DynamicTxPower( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicTxPowerAP( + IN PDM_ODM_T pDM_Odm + ); + + +VOID +odm_SwAntDivInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_SwAntDivInit_NIC( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_SwAntDivChkAntSwitch( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Step + ); + +VOID +odm_SwAntDivChkAntSwitchNIC( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Step + ); + + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID +odm_SwAntDivChkAntSwitchCallback( + PRT_TIMER pTimer +); +VOID +odm_SwAntDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext); +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext); +#endif + + + +VOID +odm_GlobalAdapterCheck( + IN VOID + ); + +VOID +odm_RefreshRateAdaptiveMask( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_TXPowerTrackingCheck( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PDM_ODM_T pDM_Odm + ); + + + + + + + +VOID +odm_RateAdaptiveMaskInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PDM_ODM_T pDM_Odm + ); + + +VOID +odm_TXPowerTrackingInit( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PDM_ODM_T pDM_Odm + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PDM_ODM_T pDM_Odm + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_MP)) + +VOID +ODM_RateAdaptiveStateApInit( + IN PADAPTER Adapter , + IN PRT_WLAN_STA pEntry + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +VOID +odm_EdcaTurboCheck( + IN PDM_ODM_T pDM_Odm + ); +VOID +ODM_EdcaTurboInit( + IN PDM_ODM_T pDM_Odm +); + +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) +VOID +odm_EdcaTurboCheckMP( + IN PDM_ODM_T pDM_Odm + ); + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PDM_ODM_T pDM_Odm +); +//choose edca paramter for special IOT case +VOID +ODM_EdcaParaSelByIot( + IN PDM_ODM_T pDM_Odm, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ); +//check if it is UL or DL +VOID +odm_EdcaChooseTrafficIdx( + IN PDM_ODM_T pDM_Odm, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ); + +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID +odm_EdcaTurboCheckCE( + IN PDM_ODM_T pDM_Odm + ); +#else +VOID +odm_IotEngine( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_EdcaParaInit( + IN PDM_ODM_T pDM_Odm + ); +#endif + + + +#define RxDefaultAnt1 0x65a9 +#define RxDefaultAnt2 0x569a + +VOID +odm_InitHybridAntDiv( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +odm_StaDefAntSel( + IN PDM_ODM_T pDM_Odm, + IN u4Byte OFDM_Ant1_Cnt, + IN u4Byte OFDM_Ant2_Cnt, + IN u4Byte CCK_Ant1_Cnt, + IN u4Byte CCK_Ant2_Cnt, + OUT u1Byte *pDefAnt + ); + +VOID +odm_SetRxIdleAnt( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Ant, + IN BOOLEAN bDualPath +); + + + +VOID +odm_HwAntDiv( + IN PDM_ODM_T pDM_Odm +); + + + + + +#if 0 +//#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&defined(HW_ANT_SWITCH)) +VOID +odm_HW_AntennaSwitchInit( + IN PDM_ODM_T pDM_Odm +); + +VOID +odm_SetRxIdleAnt( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Ant +); + +VOID +odm_StaAntSelect( + IN PDM_ODM_T pDM_Odm, + IN struct stat_info *pstat +); + +VOID +odm_HW_IdleAntennaSelect( + IN PDM_ODM_T pDM_Odm +); + +u1Byte +ODM_Diversity_AntennaSelect( + IN PDM_ODM_T pDM_Odm, + IN u1Byte *data +); +#endif + + +//============================================================ +//3 Export Interface +//============================================================ + +// +// 2011/09/21 MH Add to describe different team necessary resource allocate?? +// +VOID +ODM_DMInit( + IN PDM_ODM_T pDM_Odm + ) +{ + +#if (FPGA_TWO_MAC_VERIFICATION == 1) + odm_RateAdaptiveMaskInit(pDM_Odm); + return; +#endif + + //2012.05.03 Luke: For all IC series + odm_CommonInfoSelfInit(pDM_Odm); + odm_CmnInfoInit_Debug(pDM_Odm); + odm_DIGInit(pDM_Odm); + odm_RateAdaptiveMaskInit(pDM_Odm); + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + + } + else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + #if (RTL8188E_SUPPORT == 1) + odm_PrimaryCCA_Init(pDM_Odm); // Gary + #endif + odm_DynamicBBPowerSavingInit(pDM_Odm); + odm_DynamicTxPowerInit(pDM_Odm); + odm_TXPowerTrackingInit(pDM_Odm); + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + odm_PSDMonitorInit(pDM_Odm); + odm_RXHPInit(pDM_Odm); + odm_PathDivInit(pDM_Odm); //92D Path Div Init //Neil Chen + #endif + ODM_EdcaTurboInit(pDM_Odm); + #if (RTL8188E_SUPPORT == 1) + ODM_RAInfo_Init_all(pDM_Odm); + #endif + if( ( pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV ) || + ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV ) || + ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV )) + { + odm_InitHybridAntDiv(pDM_Odm); + } + else if( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) + { + odm_SwAntDivInit(pDM_Odm); + } + } +} + +// +// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. +// You can not add any dummy function here, be care, you can only use DM structure +// to perform any new ODM_DM. +// +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm + ) +{ + //2012.05.03 Luke: For all IC series + odm_GlobalAdapterCheck(); + odm_CmnInfoHook_Debug(pDM_Odm); + odm_CmnInfoUpdate_Debug(pDM_Odm); + odm_CommonInfoSelfUpdate(pDM_Odm); + odm_FalseAlarmCounterStatistics(pDM_Odm); + odm_RSSIMonitorCheck(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +//#ifdef CONFIG_PLATFORM_SPRD + //For CE Platform(SPRD or Tablet) + //8723A or 8189ES platform + //NeilChen--2012--08--24-- + //Fix Leave LPS issue + if( (pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&// in LPS mode + ( + (pDM_Odm->SupportICType & (ODM_RTL8723A ) )|| + (pDM_Odm->SupportICType & (ODM_RTL8188E) &&((pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) ) + + //&&((pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) + ) + ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); + odm_DIGbyRSSI_LPS(pDM_Odm); + } + else +//#endif +#endif + { + odm_DIG(pDM_Odm); + } + + + odm_CCKPacketDetectionThresh(pDM_Odm); + + if(*(pDM_Odm->pbPowerSaving)==TRUE) + return; + + odm_RefreshRateAdaptiveMask(pDM_Odm); + + #if (RTL8192D_SUPPORT == 1) + ODM_DynamicEarlyMode(pDM_Odm); + #endif + odm_DynamicBBPowerSaving(pDM_Odm); + #if (RTL8188E_SUPPORT == 1) + odm_DynamicPrimaryCCA(pDM_Odm); + #endif + if( ( pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV ) || + ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV ) || + ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV )) + { + odm_HwAntDiv(pDM_Odm); + } + else if( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) + { + odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK); + } + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + + } + else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + ODM_TXPowerTrackingCheck(pDM_Odm); + odm_EdcaTurboCheck(pDM_Odm); + odm_DynamicTxPower(pDM_Odm); + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + odm_RXHP(pDM_Odm); + #endif + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + odm_dtc(pDM_Odm); +#endif +} + + +// +// Init /.. Fixed HW value. Only init time. +// +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ) +{ + //ODM_RT_TRACE(pDM_Odm,); + + // + // This section is used for init value + // + switch (CmnInfo) + { + // + // Fixed ODM value. + // + case ODM_CMNINFO_ABILITY: + pDM_Odm->SupportAbility = (u4Byte)Value; + break; + case ODM_CMNINFO_PLATFORM: + pDM_Odm->SupportPlatform = (u1Byte)Value; + break; + + case ODM_CMNINFO_INTERFACE: + pDM_Odm->SupportInterface = (u1Byte)Value; + break; + + case ODM_CMNINFO_MP_TEST_CHIP: + pDM_Odm->bIsMPChip= (u1Byte)Value; + break; + + case ODM_CMNINFO_IC_TYPE: + pDM_Odm->SupportICType = Value; + break; + + case ODM_CMNINFO_CUT_VER: + pDM_Odm->CutVersion = (u1Byte)Value; + break; + + case ODM_CMNINFO_FAB_VER: + pDM_Odm->FabVersion = (u1Byte)Value; + break; + + case ODM_CMNINFO_RF_TYPE: + pDM_Odm->RFType = (u1Byte)Value; + break; + + case ODM_CMNINFO_RF_ANTENNA_TYPE: + pDM_Odm->AntDivType= (u1Byte)Value; + break; + + case ODM_CMNINFO_BOARD_TYPE: + pDM_Odm->BoardType = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_LNA: + pDM_Odm->ExtLNA = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_PA: + pDM_Odm->ExtPA = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_TRSW: + pDM_Odm->ExtTRSW = (u1Byte)Value; + break; + case ODM_CMNINFO_PATCH_ID: + pDM_Odm->PatchID = (u1Byte)Value; + break; + case ODM_CMNINFO_BINHCT_TEST: + pDM_Odm->bInHctTest = (BOOLEAN)Value; + break; + case ODM_CMNINFO_BWIFI_TEST: + pDM_Odm->bWIFITest = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_SMART_CONCURRENT: + pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; + break; + + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + + } + + // + // Tx power tracking BB swing table. + // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB + // + pDM_Odm->BbSwingIdxOfdm = 12; // Set defalut value as index 12. + pDM_Odm->BbSwingIdxOfdmCurrent = 12; + pDM_Odm->BbSwingFlagOfdm = FALSE; + +} + + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ) +{ + // + // Hook call by reference pointer. + // + switch (CmnInfo) + { + // + // Dynamic call by reference pointer. + // + case ODM_CMNINFO_MAC_PHY_MODE: + pDM_Odm->pMacPhyMode = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_TX_UNI: + pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue; + break; + + case ODM_CMNINFO_RX_UNI: + pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue; + break; + + case ODM_CMNINFO_WM_MODE: + pDM_Odm->pWirelessMode = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_BAND: + pDM_Odm->pBandType = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + pDM_Odm->pSecChOffset = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_SEC_MODE: + pDM_Odm->pSecurity = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_BW: + pDM_Odm->pBandWidth = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_CHNL: + pDM_Odm->pChannel = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_DMSP_GET_VALUE: + pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_BUDDY_ADAPTOR: + pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue; + break; + + case ODM_CMNINFO_DMSP_IS_MASTER: + pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_SCAN: + pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_POWER_SAVING: + pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_ONE_PATH_CCA: + pDM_Odm->pOnePathCCA = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_DRV_STOP: + pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_PNP_IN: + pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_INIT_ON: + pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_ANT_TEST: + pDM_Odm->pAntennaTest = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_NET_CLOSED: + pDM_Odm->pbNet_closed = (BOOLEAN *)pValue; + break; + case ODM_CMNINFO_MP_MODE: + pDM_Odm->mp_mode = (u1Byte *)pValue; + break; + + //case ODM_CMNINFO_BT_COEXIST: + // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; + + //case ODM_CMNINFO_STA_STATUS: + //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; + //break; + + //case ODM_CMNINFO_PHY_STATUS: + // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; + // break; + + //case ODM_CMNINFO_MAC_STATUS: + // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; + // break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + + } + +} + + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ) +{ + // + // Hook call by reference pointer. + // + switch (CmnInfo) + { + // + // Dynamic call by reference pointer. + // + case ODM_CMNINFO_STA_STATUS: + pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; + break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + } + +} + + +// +// Update Band/CHannel/.. The values are dynamic but non-per-packet. +// +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ) +{ + // + // This init variable may be changed in run time. + // + switch (CmnInfo) + { + case ODM_CMNINFO_ABILITY: + pDM_Odm->SupportAbility = (u4Byte)Value; + break; + + case ODM_CMNINFO_RF_TYPE: + pDM_Odm->RFType = (u1Byte)Value; + break; + + case ODM_CMNINFO_WIFI_DIRECT: + pDM_Odm->bWIFI_Direct = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_WIFI_DISPLAY: + pDM_Odm->bWIFI_Display = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_LINK: + pDM_Odm->bLinked = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_RSSI_MIN: + pDM_Odm->RSSI_Min= (u1Byte)Value; + break; + + case ODM_CMNINFO_DBG_COMP: + pDM_Odm->DebugComponents = Value; + break; + + case ODM_CMNINFO_DBG_LEVEL: + pDM_Odm->DebugLevel = (u4Byte)Value; + break; + case ODM_CMNINFO_RA_THRESHOLD_HIGH: + pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value; + break; + + case ODM_CMNINFO_RA_THRESHOLD_LOW: + pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value; + break; +#if(BT_30_SUPPORT == 1) + // The following is for BT HS mode and BT coexist mechanism. + case ODM_CMNINFO_BT_DISABLED: + pDM_Odm->bBtDisabled = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_OPERATION: + pDM_Odm->bBtHsOperation = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_DIG: + pDM_Odm->btHsDigVal = (u1Byte)Value; + break; + + case ODM_CMNINFO_BT_BUSY: + pDM_Odm->bBtBusy = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_DISABLE_EDCA: + pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value; + break; +#endif + + } + + +} + +VOID +odm_CommonInfoSelfInit( + IN PDM_ODM_T pDM_Odm + ) +{ + pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x824, BIT9); + pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp; +#endif + if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D)) + { +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; +#elif (defined(CONFIG_SW_ANTENNA_DIVERSITY)) + pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; +#endif + } + if(pDM_Odm->SupportICType & (ODM_RTL8723A)) + pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; + + ODM_InitDebugSetting(pDM_Odm); +} + +VOID +odm_CommonInfoSelfUpdate( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte EntryCnt=0; + u1Byte i; + PSTA_INFO_T pEntry; + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + pEntry = pDM_Odm->pODM_StaInfo[0]; + if(pMgntInfo->mAssoc) + { + pEntry->bUsed=TRUE; + for (i=0; i<6; i++) + pEntry->MacAddr[i] = pMgntInfo->Bssid[i]; + } + else + { + pEntry->bUsed=FALSE; + for (i=0; i<6; i++) + pEntry->MacAddr[i] = 0; + } +#endif + + + if(*(pDM_Odm->pBandWidth) == ODM_BW40M) + { + if(*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) -2; + else if(*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) +2; + } + else + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + EntryCnt++; + } + if(EntryCnt == 1) + pDM_Odm->bOneEntryOnly = TRUE; + else + pDM_Odm->bOneEntryOnly = FALSE; +} + +VOID +odm_CmnInfoInit_Debug( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n",pDM_Odm->SupportPlatform) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n",pDM_Odm->SupportAbility) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n",pDM_Odm->SupportInterface) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n",pDM_Odm->SupportICType) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n",pDM_Odm->CutVersion) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n",pDM_Odm->FabVersion) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n",pDM_Odm->RFType) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n",pDM_Odm->BoardType) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n",pDM_Odm->ExtLNA) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n",pDM_Odm->ExtPA) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n",pDM_Odm->ExtTRSW) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n",pDM_Odm->PatchID) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n",pDM_Odm->bInHctTest) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n",pDM_Odm->bWIFITest) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n",pDM_Odm->bDualMacSmartConcurrent) ); + +} + +VOID +odm_CmnInfoHook_Debug( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n",*(pDM_Odm->pNumTxBytesUnicast)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n",*(pDM_Odm->pNumRxBytesUnicast)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n",*(pDM_Odm->pWirelessMode)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n",*(pDM_Odm->pSecChOffset)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n",*(pDM_Odm->pSecurity)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n",*(pDM_Odm->pBandWidth)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n",*(pDM_Odm->pChannel)) ); + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->pBandType) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandType=%d\n",*(pDM_Odm->pBandType)) ); + if(pDM_Odm->pMacPhyMode) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pMacPhyMode=%d\n",*(pDM_Odm->pMacPhyMode)) ); + if(pDM_Odm->pBuddyAdapter) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbGetValueFromOtherMac=%d\n",*(pDM_Odm->pbGetValueFromOtherMac)) ); + if(pDM_Odm->pBuddyAdapter) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBuddyAdapter=%p\n",*(pDM_Odm->pBuddyAdapter)) ); + if(pDM_Odm->pbMasterOfDMSP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbMasterOfDMSP=%d\n",*(pDM_Odm->pbMasterOfDMSP)) ); +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n",*(pDM_Odm->pbScanInProcess)) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n",*(pDM_Odm->pbPowerSaving)) ); + + if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n",*(pDM_Odm->pOnePathCCA)) ); +} + +VOID +odm_CmnInfoUpdate_Debug( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n",pDM_Odm->bWIFI_Direct) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n",pDM_Odm->bWIFI_Display) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n",pDM_Odm->bLinked) ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) ); +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID +ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ) +{ +#if USE_WORKITEM + PADAPTER pAdapter = pDM_Odm->Adapter; + + ODM_InitializeWorkItem( pDM_Odm, + &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem, + (RT_WORKITEM_CALL_BACK)odm_SwAntDivChkAntSwitchWorkitemCallback, + (PVOID)pAdapter, + "AntennaSwitchWorkitem" + ); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->PathDivSwitchWorkitem), + (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback, + (PVOID)pAdapter, + "SWAS_WorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->CCKPathDiversityWorkitem), + (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback, + (PVOID)pAdapter, + "CCKTXPathDiversityWorkItem"); +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#if (RTL8188E_SUPPORT == 1) + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->FastAntTrainingWorkitem), + (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback, + (PVOID)pAdapter, + "FastAntTrainingWorkitem"); +#endif +#endif + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem), + (RT_WORKITEM_CALL_BACK)odm_PSD_RXHPWorkitemCallback, + (PVOID)pAdapter, + "PSDRXHP_WorkItem"); +#endif +} + +VOID +ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ) +{ +#if USE_WORKITEM + ODM_FreeWorkItem( &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem)); + + ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem)); + + ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem)); + + ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem)); + + ODM_FreeWorkItem((&pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem)); +#endif + +} +#endif + +/* +VOID +odm_FindMinimumRSSI( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i; + u1Byte RSSI_Min = 0xFF; + + for(i=0; ipODM_StaInfo[i] != NULL) + if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) ) + { + if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min) + { + RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave; + } + } + } + + pDM_Odm->RSSI_Min = RSSI_Min; + +} + +VOID +odm_IsLinked( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i; + BOOLEAN Linked = FALSE; + + for(i=0; ipODM_StaInfo[i]) ) + { + Linked = TRUE; + break; + } + + } + + pDM_Odm->bLinked = Linked; +} +*/ + + +//3============================================================ +//3 DIG +//3============================================================ +/*----------------------------------------------------------------------------- + * Function: odm_DIGInit() + * + * Overview: Set DIG scheme init value. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * + *---------------------------------------------------------------------------*/ +VOID +ODM_ChangeDynamicInitGainThresh( + IN PDM_ODM_T pDM_Odm, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (DM_Type == DIG_TYPE_THRESH_HIGH) + { + pDM_DigTable->RssiHighThresh = DM_Value; + } + else if (DM_Type == DIG_TYPE_THRESH_LOW) + { + pDM_DigTable->RssiLowThresh = DM_Value; + } + else if (DM_Type == DIG_TYPE_ENABLE) + { + pDM_DigTable->Dig_Enable_Flag = TRUE; + } + else if (DM_Type == DIG_TYPE_DISABLE) + { + pDM_DigTable->Dig_Enable_Flag = FALSE; + } + else if (DM_Type == DIG_TYPE_BACKOFF) + { + if(DM_Value > 30) + DM_Value = 30; + pDM_DigTable->BackoffVal = (u1Byte)DM_Value; + } + else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) + { + if(DM_Value == 0) + DM_Value = 0x1; + pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value; + } + else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) + { + if(DM_Value > 0x50) + DM_Value = 0x50; + pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value; + } +} /* DM_ChangeDynamicInitGainThresh */ + +int getIGIForDiff(int value_IGI) +{ + #define ONERCCA_LOW_TH 0x30 + #define ONERCCA_LOW_DIFF 8 + + if (value_IGI < ONERCCA_LOW_TH) { + if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) + return ONERCCA_LOW_TH; + else + return value_IGI + ONERCCA_LOW_DIFF; + } else { + return value_IGI; + } +} + + +// Add by Neil Chen to enable edcca to MP Platform +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +VOID +odm_EnableEDCCA( + IN PDM_ODM_T pDM_Odm +) +{ + + // This should be moved out of OUTSRC + PADAPTER pAdapter = pDM_Odm->Adapter; + // Enable EDCCA. The value is suggested by SD3 Wilson. + + // + // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13. + // + if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter))) + { + //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00); + ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00); + ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD); + + } + else + { + //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03); + ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03); + ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00); + } + + //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00); +} + +VOID +odm_DisableEDCCA( + IN PDM_ODM_T pDM_Odm +) +{ + // Disable EDCCA.. + ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f); + ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f); +} + +// +// Description: According to initial gain value to determine to enable or disable EDCCA. +// +// Suggested by SD3 Wilson. Added by tynli. 2011.11.25. +// +VOID +odm_DynamicEDCCA( + IN PDM_ODM_T pDM_Odm +) +{ + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte RegC50, RegC58; + BOOLEAN bEDCCAenable = FALSE; + + RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); + RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0); + + + if((RegC50 > 0x28 && RegC58 > 0x28) || + ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) || + (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)) + { + if(!pHalData->bPreEdccaEnable) + { + odm_EnableEDCCA(pDM_Odm); + pHalData->bPreEdccaEnable = TRUE; + } + + } + else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)) + { + if(pHalData->bPreEdccaEnable) + { + odm_DisableEDCCA(pDM_Odm); + pHalData->bPreEdccaEnable = FALSE; + } + } +} + + +#endif // end MP platform support + +VOID +ODM_Write_DIG( + IN PDM_ODM_T pDM_Odm, + IN u1Byte CurrentIGI + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n", + ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); + + if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI) + { + if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) + { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if(pDM_Odm->SupportICType != ODM_RTL8188E) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + } + else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { + switch(*(pDM_Odm->pOnePathCCA)) + { + case ODM_CCA_2R: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if(pDM_Odm->SupportICType != ODM_RTL8188E) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + break; + case ODM_CCA_1R_A: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if(pDM_Odm->SupportICType != ODM_RTL8188E) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); + break; + case ODM_CCA_1R_B: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); + if(pDM_Odm->SupportICType != ODM_RTL8188E) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + break; + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI)); + //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; + pDM_DigTable->CurIGValue = CurrentIGI; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI)); + +// Add by Neil Chen to enable edcca to MP Platform +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + // Adjust EDCCA. + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + odm_DynamicEDCCA(pDM_Odm); +#endif + + +} + + +//Need LPS mode for CE platform --2012--08--24--- +//8723AS/8189ES +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +odm_DIGbyRSSI_LPS( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER pAdapter =pDM_Odm->Adapter; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; + +#if 0 //and 2.3.5 coding rule + struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; +#endif + + u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C + u1Byte bFwCurrentInPSMode = FALSE; + u1Byte CurrentIGI=pDM_Odm->RSSI_Min; + + if(! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E))) + return; + + //if((pDM_Odm->SupportInterface==ODM_ITRF_PCIE)||(pDM_Odm->SupportInterface ==ODM_ITRF_USB)) + // return; + + CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG; +#ifdef CONFIG_LPS + bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; +#endif + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG()==>\n")); + + // Using FW PS mode to make IGI + if(bFwCurrentInPSMode) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); + //Adjust by FA in LPS MODE + if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) + CurrentIGI = CurrentIGI+2; + else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) + CurrentIGI = CurrentIGI+1; + else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) + CurrentIGI = CurrentIGI-1; + } + else + { + CurrentIGI = RSSI_Lower; + } + + //Lower bound checking + + //RSSI Lower bound check + if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) + RSSI_Lower =(pDM_Odm->RSSI_Min-10); + else + RSSI_Lower =DM_DIG_MIN_NIC; + + //Upper and Lower Bound checking + if(CurrentIGI > DM_DIG_MAX_NIC) + CurrentIGI=DM_DIG_MAX_NIC; + else if(CurrentIGI < RSSI_Lower) + CurrentIGI =RSSI_Lower; + + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + +} +#endif + + +VOID +odm_DIGInit( + IN PDM_ODM_T pDM_Odm + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + //pDM_DigTable->Dig_Enable_Flag = TRUE; + //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; + pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); + //pDM_DigTable->PreIGValue = 0x0; + //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT; + //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; + pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; + pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; + pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; + pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; + if(pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + } + else + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + } + pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; + pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; + pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; + pDM_DigTable->PreCCK_CCAThres = 0xFF; + pDM_DigTable->CurCCK_CCAThres = 0x83; + pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; + pDM_DigTable->LargeFAHit = 0; + pDM_DigTable->Recover_cnt = 0; + pDM_DigTable->DIG_Dynamic_MIN_0 =DM_DIG_MIN_NIC; + pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; + pDM_DigTable->bMediaConnect_0 = FALSE; + pDM_DigTable->bMediaConnect_1 = FALSE; + + //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error + pDM_Odm->bDMInitialGainEnable = TRUE; + +} + + +VOID +odm_DIG( + IN PDM_ODM_T pDM_Odm + ) +{ + + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + u1Byte DIG_Dynamic_MIN; + u1Byte DIG_MaxOfMin; + BOOLEAN FirstConnect, FirstDisConnect; + u1Byte dm_dig_max, dm_dig_min; + u1Byte CurrentIGI = pDM_DigTable->CurIGValue; + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +// This should be moved out of OUTSRC + PADAPTER pAdapter = pDM_Odm->Adapter; +#if OS_WIN_FROM_WIN7(OS_VERSION) + if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n")); + return; + } +#endif +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtHsOperation) + { + odm_DigForBtHsMode(pDM_Odm); + return; + } +#endif + + if(pRX_HP_Table->RXHP_flag == 1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n")); + return; + } +#endif //end ODM_MP type + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) + { + printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); + ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); + return; + } +#endif +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + if (!((priv->up_time > 5) && (priv->up_time % 2)) ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Not In DIG Operation Period \n")); + return; + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); + //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) + if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) + { +#if 0 + if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { + if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1)) + CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30; + else + CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20; + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + } +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); + return; + } + + if(*(pDM_Odm->pbScanInProcess)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress \n")); + return; + } + + //add by Neil Chen to avoid PSD is processing + if(pDM_Odm->bDMInitialGainEnable == FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n")); + return; + } + + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) + { + if(*(pDM_Odm->pbMasterOfDMSP)) + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + else + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); + } + } + else + { + if(*(pDM_Odm->pBandType) == ODM_BAND_5G) + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + else + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); + } + } + } + else + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + + //1 Boundary Decision + if((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) && + ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) + { + if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { + + dm_dig_max = DM_DIG_MAX_AP_HP; + dm_dig_min = DM_DIG_MIN_AP_HP; + } + else + { + dm_dig_max = DM_DIG_MAX_NIC_HP; + dm_dig_min = DM_DIG_MIN_NIC_HP; + } + DIG_MaxOfMin = DM_DIG_MAX_AP_HP; + } + else + { + if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#ifdef DFS + if (!priv->pmib->dot11DFSEntry.disable_DFS && + (OPMODE & WIFI_AP_STATE) && + (((pDM_Odm->ControlChannel >= 52) && + (pDM_Odm->ControlChannel <= 64)) || + ((pDM_Odm->ControlChannel >= 100) && + (pDM_Odm->ControlChannel <= 140)))) + dm_dig_max = 0x24; + else +#endif + if (priv->pmib->dot11RFEntry.tx2path) { + if (*(pDM_Odm->pWirelessMode) == ODM_WM_B)//(priv->pmib->dot11BssType.net_work_type == WIRELESS_11B) + dm_dig_max = 0x2A; + else + dm_dig_max = 0x32; + } + else +#endif + dm_dig_max = DM_DIG_MAX_AP; + dm_dig_min = DM_DIG_MIN_AP; + DIG_MaxOfMin = dm_dig_max; + } + else + { + dm_dig_max = DM_DIG_MAX_NIC; + dm_dig_min = DM_DIG_MIN_NIC; + DIG_MaxOfMin = DM_DIG_MAX_AP; + } + } + + + if(pDM_Odm->bLinked) + { + //2 8723A Series, offset need to be 10 //neil + if(pDM_Odm->SupportICType==(ODM_RTL8723A)) + { + //2 Upper Bound + if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC ) + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC ) + pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC; + else + pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; + + //2 If BT is Concurrent, need to set Lower Bound + +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtBusy) + { + if(pDM_Odm->RSSI_Min>10) + { + if((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC) + DIG_Dynamic_MIN = DM_DIG_MAX_NIC; + else if((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC) + DIG_Dynamic_MIN = DM_DIG_MIN_NIC; + else + DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10; + } + else + DIG_Dynamic_MIN=DM_DIG_MIN_NIC; + } + else +#endif + { + DIG_Dynamic_MIN=DM_DIG_MIN_NIC; + } + } + else + { + //2 Modify DIG upper bound + if((pDM_Odm->RSSI_Min + 20) > dm_dig_max ) + pDM_DigTable->rx_gain_range_max = dm_dig_max; + else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min ) + pDM_DigTable->rx_gain_range_max = dm_dig_min; + else + pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; + + + //2 Modify DIG lower bound + /* + if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25)) + DIG_Dynamic_MIN++; + else if(((pFalseAlmCnt->Cnt_all < 500)||(pDM_Odm->RSSI_Min < 8))&&(DIG_Dynamic_MIN > dm_dig_min)) + DIG_Dynamic_MIN--; + */ + if(pDM_Odm->bOneEntryOnly) + { + if(pDM_Odm->RSSI_Min < dm_dig_min) + DIG_Dynamic_MIN = dm_dig_min; + else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE, DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min)); + } + //1 Lower Bound for 88E AntDiv +#if (RTL8188E_SUPPORT == 1) + else if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); + } + } +#endif + else + { + DIG_Dynamic_MIN=dm_dig_min; + } + } + } + else + { + pDM_DigTable->rx_gain_range_max = dm_dig_max; + DIG_Dynamic_MIN = dm_dig_min; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); + } + + //1 Modify DIG lower bound, deal with abnormally large false alarm + if(pFalseAlmCnt->Cnt_all > 10000) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); + + if(pDM_DigTable->LargeFAHit != 3) + pDM_DigTable->LargeFAHit++; + if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) + { + pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; + pDM_DigTable->LargeFAHit = 1; + } + + if(pDM_DigTable->LargeFAHit >= 3) + { + if((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max) + pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + else + pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); + pDM_DigTable->Recover_cnt = 3600; //3600=2hr + } + + } + else + { + //Recovery mechanism for IGI lower bound + if(pDM_DigTable->Recover_cnt != 0) + pDM_DigTable->Recover_cnt --; + else + { + if(pDM_DigTable->LargeFAHit < 3) + { + if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN) + { + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); + } + else + { + pDM_DigTable->ForbiddenIGI --; + pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); + } + } + else + { + pDM_DigTable->LargeFAHit = 0; + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit)); + + //1 Adjust initial gain by false alarm + if(pDM_Odm->bLinked) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); + if(FirstConnect) + { + CurrentIGI = pDM_Odm->RSSI_Min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); + } + else + { + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) + CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) + CurrentIGI = CurrentIGI + 1; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) + CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + } + else + { +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtBusy) + { + if(pFalseAlmCnt->Cnt_all > 0x300) + CurrentIGI = CurrentIGI + 2; + else if (pFalseAlmCnt->Cnt_all > 0x250) + CurrentIGI = CurrentIGI + 1; + else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) + CurrentIGI = CurrentIGI -1; + } + else +#endif + { + if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) + CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) + CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) + CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + + + } + } + } + } + else + { + //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); + if(FirstDisConnect) + { + CurrentIGI = pDM_DigTable->rx_gain_range_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect \n")); + } + else + { + //2012.03.30 LukeLee: enable DIG before link but with very high thresholds + if(pFalseAlmCnt->Cnt_all > 10000) + CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + else if (pFalseAlmCnt->Cnt_all > 8000) + CurrentIGI = CurrentIGI + 1;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + else if(pFalseAlmCnt->Cnt_all < 500) + CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n")); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); + //1 Check initial gain by upper/lower bound +/* + if(pDM_DigTable->CurIGValue > pDM_DigTable->rx_gain_range_max) + pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_max; + if(pDM_DigTable->CurIGValue < pDM_DigTable->rx_gain_range_min) + pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min; +*/ + if(CurrentIGI > pDM_DigTable->rx_gain_range_max) + CurrentIGI = pDM_DigTable->rx_gain_range_max; + if(CurrentIGI < pDM_DigTable->rx_gain_range_min) + CurrentIGI = pDM_DigTable->rx_gain_range_min; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", + pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); + + //2 High power RSSI threshold +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + + // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue + u8Byte curTxOkCnt=0, curRxOkCnt=0; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + + u8Byte OKCntAll=0; + //static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; + //u8Byte CurByteCnt=0, PreByteCnt=0; + + curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; + curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; + lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast; + lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast; + //----------------------------------------------------------end for LC Mocca issue + if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD)) + { + // High power IGI lower bound + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB)); + if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue)); + //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; + CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; + } + } + if((pDM_Odm->SupportICType & ODM_RTL8723A) && IS_WIRELESS_MODE_G(pAdapter)) + { + if(pHalData->UndecoratedSmoothedPWDB > 0x28) + { + if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND) + { + //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; + CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; + } + } + } +} +#endif + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + //sherry delete DualMacSmartConncurrent 20110517 + if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) + { + ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue); + if(*(pDM_Odm->pbMasterOfDMSP)) + { + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + else + { + pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; + } + } + else + { + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + if(*(pDM_Odm->pBandType) == ODM_BAND_5G) + { + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + else + { + pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; + } + } + } + else +#endif + { + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + +} + +//3============================================================ +//3 FASLE ALARM CHECK +//3============================================================ + +VOID +odm_FalseAlarmCounterStatistics( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte ret_value; + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + if( (priv->auto_channel != 0) && (priv->auto_channel != 2) ) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + if((pDM_Odm->SupportICType == ODM_RTL8192D) && + (*(pDM_Odm->pMacPhyMode)==ODM_DMSP)&& ////modify by Guo.Mingzhi 2011-12-29 + (!(*(pDM_Odm->pbMasterOfDMSP)))) + { + odm_FalseAlarmCounterStatistics_ForSlaveOfDMSP(pDM_Odm); + return; + } +#endif + + if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) + return; + +// if(pDM_Odm->SupportICType != ODM_RTL8812) + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + + //hold ofdm counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); + FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); + FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); + FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); + FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); + FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); + FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); + FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); + + FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; + +#if (RTL8188E_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); + FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); + } +#endif + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + odm_GetCCKFalseAlarm_92D(pDM_Odm); + } + else +#endif + { + //hold cck counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); + FalseAlmCnt->Cnt_Cck_fail = ret_value; + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); + FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8); + } + + FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync + + FalseAlmCnt->Cnt_SB_Search_fail + + FalseAlmCnt->Cnt_Parity_Fail + + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Cck_fail); + + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; + +#if (RTL8192C_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192C) + odm_ResetFACounter_92C(pDM_Odm); +#endif + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + odm_ResetFACounter_92D(pDM_Odm); +#endif + + if(pDM_Odm->SupportICType >=ODM_RTL8723A) + { + //reset false alarm counter registers + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); + //update ofdm counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter + + //reset CCK CCA counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); + //reset CCK FA counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", + FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", + FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", + FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); + } + else //FOR ODM_IC_11AC_SERIES + { + //read OFDM FA counter + FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); + FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); + FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; + + // reset OFDM FA coutner + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); + // reset CCK FA counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); +} + +//3============================================================ +//3 CCK Packet Detect Threshold +//3============================================================ + +VOID +odm_CCKPacketDetectionThresh( + IN PDM_ODM_T pDM_Odm + ) +{ + + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte CurCCK_CCAThres; + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +//modify by Guo.Mingzhi 2011-12-29 + if (pDM_Odm->bDualMacSmartConcurrent == TRUE) +// if (pDM_Odm->bDualMacSmartConcurrent == FALSE) + return; +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtHsOperation) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n")); + ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd); + return; + } +#endif +#endif + + if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) + return; + + if(pDM_Odm->ExtLNA) + return; + + if(pDM_Odm->bLinked) + { + if(pDM_Odm->RSSI_Min > 25) + CurCCK_CCAThres = 0xcd; + else if((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) + CurCCK_CCAThres = 0x83; + else + { + if(FalseAlmCnt->Cnt_Cck_fail > 1000) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; + } + } + else + { + if(FalseAlmCnt->Cnt_Cck_fail > 1000) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; + } + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres); + else +#endif + ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); +} + +VOID +ODM_Write_CCK_CCA_Thres( + IN PDM_ODM_T pDM_Odm, + IN u1Byte CurCCK_CCAThres + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 + { + ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); + } + pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; + pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; + +} + +//3============================================================ +//3 BB Power Save +//3============================================================ +VOID +odm_DynamicBBPowerSavingInit( + IN PDM_ODM_T pDM_Odm + ) +{ + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + + pDM_PSTable->PreCCAState = CCA_MAX; + pDM_PSTable->CurCCAState = CCA_MAX; + pDM_PSTable->PreRFState = RF_MAX; + pDM_PSTable->CurRFState = RF_MAX; + pDM_PSTable->Rssi_val_min = 0; + pDM_PSTable->initialize = 0; +} + + +VOID +odm_DynamicBBPowerSaving( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + + if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A)) + return; + if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)) + return; + if(!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) + return; + + //1 2.Power Saving for 92C + if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R)) + { + odm_1R_CCA(pDM_Odm); + } + + // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. + // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. + //1 3.Power Saving for 88C + else + { + ODM_RF_Saving(pDM_Odm, FALSE); + } +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +} + +VOID +odm_1R_CCA( + IN PDM_ODM_T pDM_Odm + ) +{ + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + + if(pDM_Odm->RSSI_Min!= 0xFF) + { + + if(pDM_PSTable->PreCCAState == CCA_2R) + { + if(pDM_Odm->RSSI_Min >= 35) + pDM_PSTable->CurCCAState = CCA_1R; + else + pDM_PSTable->CurCCAState = CCA_2R; + + } + else{ + if(pDM_Odm->RSSI_Min <= 30) + pDM_PSTable->CurCCAState = CCA_2R; + else + pDM_PSTable->CurCCAState = CCA_1R; + } + } + else{ + pDM_PSTable->CurCCAState=CCA_MAX; + } + + if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) + { + if(pDM_PSTable->CurCCAState == CCA_1R) + { + if( pDM_Odm->RFType ==ODM_2T2R ) + { + ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13); + //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); + } + else + { + ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23); + //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 + } + } + else + { + ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33); + //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); + } + pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; + } + //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA")); +} + +void +ODM_RF_Saving( + IN PDM_ODM_T pDM_Odm, + IN u1Byte bForceInNormal + ) +{ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + u1Byte Rssi_Up_bound = 30 ; + u1Byte Rssi_Low_bound = 25; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV + { + Rssi_Up_bound = 50 ; + Rssi_Low_bound = 45; + } + #endif + if(pDM_PSTable->initialize == 0){ + + pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; + pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; + pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; + pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; + //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); + pDM_PSTable->initialize = 1; + } + + if(!bForceInNormal) + { + if(pDM_Odm->RSSI_Min != 0xFF) + { + if(pDM_PSTable->PreRFState == RF_Normal) + { + if(pDM_Odm->RSSI_Min >= Rssi_Up_bound) + pDM_PSTable->CurRFState = RF_Save; + else + pDM_PSTable->CurRFState = RF_Normal; + } + else{ + if(pDM_Odm->RSSI_Min <= Rssi_Low_bound) + pDM_PSTable->CurRFState = RF_Normal; + else + pDM_PSTable->CurRFState = RF_Save; + } + } + else + pDM_PSTable->CurRFState=RF_MAX; + } + else + { + pDM_PSTable->CurRFState = RF_Normal; + } + + if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) + { + if(pDM_PSTable->CurRFState == RF_Save) + { + // 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. + // Suggested by SD3 Yu-Nan. 2011.01.20. + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); //Reg874[5]=1b'1 + } + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 + ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 + //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save")); + } + else + { + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); + ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0); + + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0 + } + //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal")); + } + pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; + } +#endif +} + + +//3============================================================ +//3 RATR MASK +//3============================================================ +//3============================================================ +//3 Rate Adaptive +//3============================================================ + +VOID +odm_RateAdaptiveMaskInit( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RATE_ADAPTIVE pOdmRA = &pDM_Odm->RateAdaptive; + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PMGNT_INFO pMgntInfo = &pDM_Odm->Adapter->MgntInfo; + PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive; + + pRA->RATRState = DM_RATR_STA_INIT; + if (pMgntInfo->DM_Type == DM_Type_ByDriver) + pMgntInfo->bUseRAMask = TRUE; + else + pMgntInfo->bUseRAMask = FALSE; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pOdmRA->Type = DM_Type_ByDriver; + if (pOdmRA->Type == DM_Type_ByDriver) + pDM_Odm->bUseRAMask = _TRUE; + else + pDM_Odm->bUseRAMask = _FALSE; + +#endif + + pOdmRA->RATRState = DM_RATR_STA_INIT; + pOdmRA->HighRSSIThresh = 50; + pOdmRA->LowRSSIThresh = 20; +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) +VOID +ODM_RateAdaptiveStateApInit( + IN PADAPTER Adapter , + IN PRT_WLAN_STA pEntry + ) +{ + PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pEntry->RateAdaptive; + pRA->RATRState = DM_RATR_STA_INIT; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +u4Byte ODM_Get_Rate_Bitmap( + IN PDM_ODM_T pDM_Odm, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level) +{ + PSTA_INFO_T pEntry; + u4Byte rate_bitmap = 0x0fffffff; + u1Byte WirelessMode; + //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode); + + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if(!IS_STA_VALID(pEntry)) + return ra_mask; + + WirelessMode = pEntry->wireless_mode; + + switch(WirelessMode) + { + case ODM_WM_B: + if(ra_mask & 0x0000000c) //11M or 5.5M enable + rate_bitmap = 0x0000000d; + else + rate_bitmap = 0x0000000f; + break; + + case (ODM_WM_A|ODM_WM_G): + if(rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else + rate_bitmap = 0x00000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if(rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else if(rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000ff0; + else + rate_bitmap = 0x00000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : + case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : + { + if ( pDM_Odm->RFType == ODM_1T2R ||pDM_Odm->RFType == ODM_1T1R) + { + if(rssi_level == DM_RATR_STA_HIGH) + { + rate_bitmap = 0x000f0000; + } + else if(rssi_level == DM_RATR_STA_MIDDLE) + { + rate_bitmap = 0x000ff000; + } + else{ + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x000ff015; + else + rate_bitmap = 0x000ff005; + } + } + else + { + if(rssi_level == DM_RATR_STA_HIGH) + { + rate_bitmap = 0x0f8f0000; + } + else if(rssi_level == DM_RATR_STA_MIDDLE) + { + rate_bitmap = 0x0f8ff000; + } + else + { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x0f8ff015; + else + rate_bitmap = 0x0f8ff005; + } + } + } + break; + default: + //case WIRELESS_11_24N: + //case WIRELESS_11_5N: + if(pDM_Odm->RFType == RF_1T2R) + rate_bitmap = 0x000fffff; + else + rate_bitmap = 0x0fffffff; + break; + + } + + //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",rssi_level,WirelessMode,rate_bitmap)); + + return rate_bitmap; + +} +#endif + +/*----------------------------------------------------------------------------- + * Function: odm_RefreshRateAdaptiveMask() + * + * Overview: Update rate table mask according to rssi + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/27/2009 hpfan Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +odm_RefreshRateAdaptiveMask( + IN PDM_ODM_T pDM_Odm + ) +{ + if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) + return; + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_MP: + odm_RefreshRateAdaptiveMaskMP(pDM_Odm); + break; + + case ODM_CE: + odm_RefreshRateAdaptiveMaskCE(pDM_Odm); + break; + + case ODM_AP: + case ODM_ADSL: + odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); + break; + } + +} + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER pAdapter = pDM_Odm->Adapter; + PADAPTER pTargetAdapter = NULL; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); + //PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive; + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + + if(pAdapter->bDriverStopped) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + return; + } + + if(!pMgntInfo->bUseRAMask) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + return; + } + + // if default port is connected, update RA table for default port (infrastructure mode only) + if(pAdapter->MgntInfo.mAssoc && (!ACTING_AS_AP(pAdapter))) + { + if( ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pRA->RATRState) ) + { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pRA->RATRState)); + pAdapter->HalFunc.UpdateHalRAMaskHandler( + pAdapter, + FALSE, + 0, + NULL, + NULL, + pRA->RATRState, + RAMask_Normal); + } + } + + // + // The following part configure AP/VWifi/IBSS rate adaptive mask. + // + + if(pMgntInfo->mIbss) + { + // Target: AP/IBSS peer. + pTargetAdapter = GetDefaultAdapter(pAdapter); + } + else + { + pTargetAdapter = GetFirstAPAdapter(pAdapter); + } + + // if extension port (softap) is started, updaet RA table for more than one clients associate + if(pTargetAdapter != NULL) + { + int i; + PRT_WLAN_STA pEntry; + PRATE_ADAPTIVE pEntryRA; + + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { +#if 0 //By YJ,120208 + if( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated) + { + pEntry = pTargetAdapter->MgntInfo.AsocEntry+i; + pEntryRA = &pEntry->RateAdaptive; + if( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) ) + { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState)); + pAdapter->HalFunc.UpdateHalRAMaskHandler( + pTargetAdapter, + FALSE, + pEntry->AID+1, + pEntry->MacAddr, + pEntry, + pEntryRA->RATRState, + RAMask_Normal); + } + } +#else + pEntry = AsocEntry_EnumStation(pTargetAdapter, i); + if(NULL != pEntry) + { + if(pEntry->bAssociated) + { + pEntryRA = &pEntry->RateAdaptive; + if( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) ) + { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState)); + pAdapter->HalFunc.UpdateHalRAMaskHandler( + pTargetAdapter, + FALSE, + pEntry->AID+1, + pEntry->MacAddr, + pEntry, + pEntryRA->RATRState, + RAMask_Normal); + } + } + } +#endif + } + } + + if(pMgntInfo->bSetTXPowerTrainingByOid) + pMgntInfo->bSetTXPowerTrainingByOid = FALSE; +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) +} + + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + u1Byte i; + PADAPTER pAdapter = pDM_Odm->Adapter; + + if(pAdapter->bDriverStopped) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + return; + } + + if(!pDM_Odm->bUseRAMask) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + return; + } + + //printk("==> %s \n",__FUNCTION__); + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) { + if( TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level) ) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); + //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); + rtw_hal_update_ra_mask(pstat, pstat->rssi_level); + } + + } + } + +#endif +} + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + struct rtl8192cd_priv *priv = pDM_Odm->priv; + struct stat_info *pstat; + + if (!priv->pmib->dot11StationConfigEntry.autoRate) + return; + + if (list_empty(&priv->asoc_list)) + return; + + list_for_each_entry(pstat, &priv->asoc_list, asoc_list) { + if(ODM_RAStateCheck(pDM_Odm, (s4Byte)pstat->rssi, FALSE, &pstat->rssi_level) ) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pstat->hwaddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi, pstat->rssi_level)); + +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv)==VERSION_8188E) { +#ifdef TXREPORT + add_RATid(priv, pstat); +#endif + } else +#endif + { +#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) + add_update_RATid(priv, pstat); +#endif + } + } + } +#endif +} + +// Return Value: BOOLEAN +// - TRUE: RATRState is changed. +BOOLEAN +ODM_RAStateCheck( + IN PDM_ODM_T pDM_Odm, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState + ) +{ + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + const u1Byte GoUpGap = 5; + u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh; + u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh; + u1Byte RATRState; + + // Threshold Adjustment: + // when RSSI state trends to go up one or two levels, make sure RSSI is high enough. + // Here GoUpGap is added to solve the boundary's level alternation issue. + switch (*pRATRState) + { + case DM_RATR_STA_INIT: + case DM_RATR_STA_HIGH: + break; + + case DM_RATR_STA_MIDDLE: + HighRSSIThreshForRA += GoUpGap; + break; + + case DM_RATR_STA_LOW: + HighRSSIThreshForRA += GoUpGap; + LowRSSIThreshForRA += GoUpGap; + break; + + default: + ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState) ); + break; + } + + // Decide RATRState by RSSI. + if(RSSI > HighRSSIThreshForRA) + RATRState = DM_RATR_STA_HIGH; + else if(RSSI > LowRSSIThreshForRA) + RATRState = DM_RATR_STA_MIDDLE; + else + RATRState = DM_RATR_STA_LOW; + //printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI); + + if( *pRATRState!=RATRState || bForceUpdate) + { + ODM_RT_TRACE( pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState) ); + *pRATRState = RATRState; + return TRUE; + } + + return FALSE; +} + + +//============================================================ + +//3============================================================ +//3 Dynamic Tx Power +//3============================================================ + +VOID +odm_DynamicTxPowerInit( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + #if DEV_BUS_TYPE==RT_USB_INTERFACE + if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power) + { + odm_DynamicTxPowerSavePowerIndex(pDM_Odm); + pMgntInfo->bDynamicTxPowerEnable = TRUE; + } + else + #else + //so 92c pci do not need dynamic tx power? vivi check it later + if(IS_HARDWARE_TYPE_8192D(Adapter)) + pMgntInfo->bDynamicTxPowerEnable = TRUE; + else + pMgntInfo->bDynamicTxPowerEnable = FALSE; + #endif + + + pHalData->LastDTPLvl = TxHighPwrLevel_Normal; + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + pdmpriv->bDynamicTxPowerEnable = _FALSE; + + #if (RTL8192C_SUPPORT==1) + #ifdef CONFIG_USB_HCI + + #ifdef CONFIG_INTEL_PROXIM + if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE)) + #else + if(pHalData->BoardType == BOARD_USB_High_PA) + #endif + + { + //odm_SavePowerIndex(Adapter); + odm_DynamicTxPowerSavePowerIndex(pDM_Odm); + pdmpriv->bDynamicTxPowerEnable = _TRUE; + } + else + #else + pdmpriv->bDynamicTxPowerEnable = _FALSE; + #endif + #endif + + pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + +#endif + +} + +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte index; + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + for(index = 0; index< 6; index++) + pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + for(index = 0; index< 6; index++) + pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]); +#endif +} + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte index; + PADAPTER Adapter = pDM_Odm->Adapter; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + for(index = 0; index< 6; index++) + PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + struct dm_priv *pdmpriv = &pHalData->dmpriv; + for(index = 0; index< 6; index++) + rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]); +#endif +#endif +} + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Value) +{ + + u1Byte index; + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + + for(index = 0; index< 6; index++) + //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); + ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); + +} + + +VOID +odm_DynamicTxPower( + IN PDM_ODM_T pDM_Odm + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + //PADAPTER pAdapter = pDM_Odm->Adapter; +// prtl8192cd_priv priv = pDM_Odm->priv; + + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + + // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. + if (pDM_Odm->ExtPA == FALSE) + return; + + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_MP: + case ODM_CE: + odm_DynamicTxPowerNIC(pDM_Odm); + break; + case ODM_AP: + odm_DynamicTxPowerAP(pDM_Odm); + break; + + case ODM_ADSL: + //odm_DIGAP(pDM_Odm); + break; + } + + +} + + +VOID +odm_DynamicTxPowerNIC( + IN PDM_ODM_T pDM_Odm + ) +{ + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + + if(pDM_Odm->SupportICType == ODM_RTL8192C) + { + odm_DynamicTxPower_92C(pDM_Odm); + } + else if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + odm_DynamicTxPower_92D(pDM_Odm); + } + else if (pDM_Odm->SupportICType & ODM_RTL8188E) + { + // Add Later. + } + else if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + // ??? + // This part need to be redefined. + } +#endif +} + +VOID +odm_DynamicTxPowerAP( + IN PDM_ODM_T pDM_Odm + + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + s4Byte i; + + if(!priv->pshare->rf_ft_var.tx_pwr_ctrl) + return; + +#ifdef HIGH_POWER_EXT_PA + if(pDM_Odm->ExtPA) + tx_power_control(priv); +#endif + + /* + * Check if station is near by to use lower tx power + */ + + if ((priv->up_time % 3) == 0 ) { + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) { + if ((pstat->hp_level == 0) && (pstat->rssi > TX_POWER_NEAR_FIELD_THRESH_AP+4)) + pstat->hp_level = 1; + else if ((pstat->hp_level == 1) && (pstat->rssi < TX_POWER_NEAR_FIELD_THRESH_AP)) + pstat->hp_level = 0; + } + } + } + +#endif +} + + +VOID +odm_DynamicTxPower_92C( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s4Byte UndecoratedSmoothedPWDB; + + + // STA not connected and AP not connected + if((!pMgntInfo->bMediaConnect) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) + { + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + + //the LastDTPlvl should reset when disconnect, + //otherwise the tx power level wouldn't change when disconnect and connect again. + // Maddest 20091220. + pHalData->LastDTPLvl=TxHighPwrLevel_Normal; + return; + } + +#if (INTEL_PROXIMITY_SUPPORT == 1) + // Intel set fixed tx power + if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0) + { + switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){ + case 1: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n")); + break; + case 2: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_70\n")); + break; + case 3: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_50\n")); + break; + case 4: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_35\n")); + break; + case 5: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_15\n")); + break; + default: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n")); + break; + } + } + else +#endif + { + if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) || + (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) || + pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + } + else + { + if(pMgntInfo->bMediaConnect) // Default port + { + if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + else + { + UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + } + else // associated entry pwdb + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + + if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + } + } + if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl ) + { + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel)); + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + if( (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) && + (pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal + odm_DynamicTxPowerRestorePowerIndex(pDM_Odm); + else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) + odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14); + else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10); + } + pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + #if (RTL8192C_SUPPORT==1) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + int UndecoratedSmoothedPWDB; + + if(!pdmpriv->bDynamicTxPowerEnable) + return; + +#ifdef CONFIG_INTEL_PROXIM + if(Adapter->proximity.proxim_on== _TRUE){ + struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv; + // Intel set fixed tx power + printk("\n %s Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output); + if(prox_priv!=NULL){ + if(prox_priv->proxim_modeinfo->power_output> 0) + { + switch(prox_priv->proxim_modeinfo->power_output) + { + case 1: + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100; + printk("TxHighPwrLevel_100\n"); + break; + case 2: + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_70; + printk("TxHighPwrLevel_70\n"); + break; + case 3: + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_50; + printk("TxHighPwrLevel_50\n"); + break; + case 4: + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_35; + printk("TxHighPwrLevel_35\n"); + break; + case 5: + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_15; + printk("TxHighPwrLevel_15\n"); + break; + default: + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100; + printk("TxHighPwrLevel_100\n"); + break; + } + } + } + } + else +#endif + { + // STA not connected and AP not connected + if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) && + (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) + { + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + + //the LastDTPlvl should reset when disconnect, + //otherwise the tx power level wouldn't change when disconnect and connect again. + // Maddest 20091220. + pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal; + return; + } + + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port + { + #if 0 + //todo: AP Mode + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + { + UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + else + { + UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + #else + UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + #endif + } + else // associated entry pwdb + { + UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + + if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + } + if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) ) + { + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal or HP2 -> Normal + odm_DynamicTxPowerRestorePowerIndex(pDM_Odm); + else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) + odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14); + else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10); + } + pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl; + #endif +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +} + + +VOID +odm_DynamicTxPower_92D( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s4Byte UndecoratedSmoothedPWDB; + + PADAPTER BuddyAdapter = Adapter->BuddyAdapter; + BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter); + u1Byte HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1; + + + // If dynamic high power is disabled. + if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) || + (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) || + pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + return; + } + + // STA not connected and AP not connected + if((!pMgntInfo->bMediaConnect) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) + { + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + + //the LastDTPlvl should reset when disconnect, + //otherwise the tx power level wouldn't change when disconnect and connect again. + // Maddest 20091220. + pHalData->LastDTPLvl=TxHighPwrLevel_Normal; + return; + } + + if(pMgntInfo->bMediaConnect) // Default port + { + if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss) + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + else + { + UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + } + else // associated entry pwdb + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + + if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType92D == 1){ + if(UndecoratedSmoothedPWDB >= 0x33) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB <0x33) && + (UndecoratedSmoothedPWDB >= 0x2b) ) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < 0x2b) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n")); + } + + } + else + + { + if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + + } + +//sherry delete flag 20110517 + if(bGetValueFromBuddyAdapter) + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n")); + if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP) + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n")); + HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl; + pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP; + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0; + Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE; + } + } + + if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) ) + { + ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel)); + if(Adapter->DualMacSmartConcurrent == TRUE) + { + if(BuddyAdapter == NULL) + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n")); + if(!Adapter->bSlaveOfDMSP) + { + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + } + else + { + if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n")); + if(Adapter->bSlaveOfDMSP) + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n")); + BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE; + BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl; + } + else + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n")); + if(!bGetValueFromBuddyAdapter) + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n")); + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + } + } + else + { + ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n")); + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + } + } + else + { + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + + } + pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#if (RTL8192D_SUPPORT==1) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + struct dm_priv *pdmpriv = &pHalData->dmpriv; + DM_ODM_T *podmpriv = &pHalData->odmpriv; + int UndecoratedSmoothedPWDB; + #if (RTL8192D_EASY_SMART_CONCURRENT == 1) + PADAPTER BuddyAdapter = Adapter->BuddyAdapter; + BOOLEAN bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter); + u8 HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1; + #endif + + // If dynamic high power is disabled. + if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) || + (!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) ) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + return; + } + + // STA not connected and AP not connected + if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) && + (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) + { + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + //the LastDTPlvl should reset when disconnect, + //otherwise the tx power level wouldn't change when disconnect and connect again. + // Maddest 20091220. + pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal; + return; + } + + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port + { + #if 0 + //todo: AP Mode + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + { + UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + else + { + UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + #else + UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + #endif + } + else // associated entry pwdb + { + UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } +#if TX_POWER_FOR_5G_BAND == 1 + if(pHalData->CurrentBandType92D == BAND_ON_5G){ + if(UndecoratedSmoothedPWDB >= 0x33) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB <0x33) && + (UndecoratedSmoothedPWDB >= 0x2b) ) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < 0x2b) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n")); + } + } + else +#endif + { + if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) + { + pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + } +#if (RTL8192D_EASY_SMART_CONCURRENT == 1) + if(bGetValueFromBuddyAdapter) + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n")); + if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP) + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n")); + HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl; + pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP; + PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); + pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0; + Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE; + } + } +#endif + + if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) ) + { + //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel)); +#if (RTL8192D_EASY_SMART_CONCURRENT == 1) + if(BuddyAdapter == NULL) + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n")); + if(!Adapter->bSlaveOfDMSP) + { + PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); + } + } + else + { + if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n")); + if(Adapter->bSlaveOfDMSP) + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n")); + BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE; + BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl; + } + else + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n")); + if(!bGetValueFromBuddyAdapter) + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n")); + PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); + } + } + } + else + { + //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n")); + PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); + } + } +#else + PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel); +#endif + } + pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl; +#endif +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +} + + +//3============================================================ +//3 RSSI Monitor +//3============================================================ + +VOID +odm_RSSIMonitorInit( + IN PDM_ODM_T pDM_Odm + ) +{ +} + +VOID +odm_RSSIMonitorCheck( + IN PDM_ODM_T pDM_Odm + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PADAPTER pAdapter = pDM_Odm->Adapter; + prtl8192cd_priv priv = pDM_Odm->priv; + + if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + return; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_MP: + odm_RSSIMonitorCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_RSSIMonitorCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_RSSIMonitorCheckAP(pDM_Odm); + break; + + case ODM_ADSL: + //odm_DIGAP(pDM_Odm); + break; + } + +} // odm_RSSIMonitorCheck + + +VOID +odm_RSSIMonitorCheckMP( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PRT_WLAN_STA pEntry; + u1Byte i; + s4Byte tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff; + + RTPRINT(FDM, DM_PWDB, ("pHalData->UndecoratedSmoothedPWDB = 0x%x( %d)\n", + pHalData->UndecoratedSmoothedPWDB, + pHalData->UndecoratedSmoothedPWDB)); + + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + { + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + } + else + { + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + } + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + RTPRINT_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr); + RTPRINT(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n", + pEntry->rssi_stat.UndecoratedSmoothedPWDB, + pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + if(pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + } + } + else + { + break; + } + } + + if(tmpEntryMaxPWDB != 0) // If associated entry is found + { + pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + RTPRINT(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", + tmpEntryMaxPWDB, tmpEntryMaxPWDB)); + } + else + { + pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + } + if(tmpEntryMinPWDB != 0xff) // If associated entry is found + { + pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + RTPRINT(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", + tmpEntryMinPWDB, tmpEntryMinPWDB)); + } + else + { + pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + } + + // Indicate Rx signal strength to FW. + if(Adapter->MgntInfo.bUseRAMask) + { + u1Byte H2C_Parameter[3] ={0}; + // DbgPrint("RxSS: %lx =%ld\n", pHalData->UndecoratedSmoothedPWDB, pHalData->UndecoratedSmoothedPWDB); + H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF); + H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 + + ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter); + } + else + { + PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB); + //DbgPrint("0x4fe write %x %d\n", pHalData->UndecoratedSmoothedPWDB, pHalData->UndecoratedSmoothedPWDB); + } +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +// +//sherry move from DUSC to here 20110517 +// +static VOID +FindMinimumRSSI_Dmsp( + IN PADAPTER pAdapter +) +{ +#if 0 + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + s32 Rssi_val_min_back_for_mac0; + BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter); + BOOLEAN bRestoreRssi = _FALSE; + PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; + + if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) + { + if(BuddyAdapter!= NULL) + { + if(pHalData->bSlaveOfDMSP) + { + //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n")); + BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM; + } + else + { + if(bGetValueFromBuddyAdapter) + { + //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n")); + bRestoreRssi = _TRUE; + Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM; + pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP; + } + } + } + + } + + if(bRestoreRssi) + { + bRestoreRssi = _FALSE; + pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0; + } +#endif +} + +static void +FindMinimumRSSI( +IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + //1 1.Determine the minimum RSSI + + if((pDM_Odm->bLinked != _TRUE) && + (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) + { + pdmpriv->MinUndecoratedPWDBForDM = 0; + //ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n")); + } + else + { + pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; + } + + //DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM); + //ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM)); +} +#endif + +VOID +odm_RSSIMonitorCheckCE( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + int i; + int tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff; + u8 sta_cnt=0; + u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi + + if(pDM_Odm->bLinked != _TRUE) + return; + + //if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) + { + #if 1 + struct sta_info *psta; + + for(i=0; ipODM_StaInfo[i])) + { + if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + + if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + + #if 0 + DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, + psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB); + #endif + + if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) { + #if(RTL8192D_SUPPORT==1) + PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8)); + #else + PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) ); + #endif + } + } + } + #else + _irqL irqL; + _list *plist, *phead; + struct sta_info *psta; + struct sta_priv *pstapriv = &Adapter->stapriv; + u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff}; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for(i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + plist = get_next(plist); + + if(_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) || + _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) + continue; + + if(psta->state & WIFI_ASOC_STATE) + { + + if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + + if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + + if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)){ + //printk("%s==> mac_id(%d),rssi(%d)\n",__FUNCTION__,psta->mac_id,psta->rssi_stat.UndecoratedSmoothedPWDB); + #if(RTL8192D_SUPPORT==1) + PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8)); + #else + PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) ); + #endif + } + } + + } + + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + #endif + + //printk("%s==> sta_cnt(%d)\n",__FUNCTION__,sta_cnt); + + for(i=0; i< sta_cnt; i++) + { + if(PWDB_rssi[i] != (0)){ + if(pHalData->fw_ractrl == _TRUE)// Report every sta's RSSI to FW + { + #if(RTL8192D_SUPPORT==1) + FillH2CCmd92D(Adapter, H2C_RSSI_REPORT, 3, (u8 *)(&PWDB_rssi[i])); + #elif((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1)) + rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]); + #endif + } + else{ + #if((RTL8188E_SUPPORT==1)&&(RATE_ADAPTIVE_SUPPORT == 1)) + ODM_RA_SetRSSI_8188E( + &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); + #endif + } + } + } + } + + if(tmpEntryMaxPWDB != 0) // If associated entry is found + { + pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + } + else + { + pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; + } + + if(tmpEntryMinPWDB != 0xff) // If associated entry is found + { + pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + } + else + { + pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; + } + + FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM + + #if(RTL8192D_SUPPORT==1) + FindMinimumRSSI_Dmsp(Adapter); + #endif + + ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); +#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE) +} +VOID +odm_RSSIMonitorCheckAP( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifdef CONFIG_RTL_92C_SUPPORT || defined(CONFIG_RTL_92D_SUPPORT) + + u4Byte i; + PSTA_INFO_T pstat; + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) + { +#ifdef STA_EXT + if (REMAP_AID(pstat) < (FW_NUM_STAT - 1)) +#endif + add_update_rssi(pDM_Odm->priv, pstat); + + } + } +#endif +#endif + +} + + + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, + (RT_TIMER_CALL_BACK)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer"); + +#if (!(DM_ODM_SUPPORT_TYPE == ODM_CE)) +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#if (RTL8188E_SUPPORT == 1) + ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, + (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer"); +#endif +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PSDTimer, + (RT_TIMER_CALL_BACK)dm_PSDMonitorCallback, NULL, "PSDTimer"); + // + //Path Diversity + //Neil Chen--2011--06--16-- / 2012/02/23 MH Revise Arch. + // + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer, + (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer"); + + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, + (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer"); + + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer, + (RT_TIMER_CALL_BACK)odm_PSD_RXHPCallback, NULL, "PSDRXHPTimer"); +#endif +} + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + // + // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in + // win7 platform. + // + HAL_ADAPTER_STS_CHK(pDM_Odm) +#endif + + ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +#if (RTL8188E_SUPPORT == 1) + ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); +#endif + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer); + // + //Path Diversity + //Neil Chen--2011--06--16-- / 2012/02/23 MH Revise Arch. + // + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); + + ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); + + ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer); +#endif +} + + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); + +#if (RTL8188E_SUPPORT == 1) + ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PSDTimer); + // + //Path Diversity + //Neil Chen--2011--06--16-- / 2012/02/23 MH Revise Arch. + // + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); + + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); + + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer); +#endif +} + + + +//#endif +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + +VOID +odm_TXPowerTrackingInit( + IN PDM_ODM_T pDM_Odm + ) +{ + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pMgntInfo->bTXPowerTracking = TRUE; + pHalData->TXPowercount = 0; + pHalData->bTXPowerTrackingInit = FALSE; + #if MP_DRIVER != 1 //for mp driver, turn off txpwrtracking as default + pHalData->TxPowerTrackControl = TRUE; + #endif//#if (MP_DRIVER != 1) + ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_RTL8188E + { + pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; + //#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default + if ( *(pDM_Odm->mp_mode) != 1) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + //#endif//#if (MP_DRIVER != 1) + MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); + } + #else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + + //if(IS_HARDWARE_TYPE_8192C(pHalData)) + { + pdmpriv->bTXPowerTracking = _TRUE; + pdmpriv->TXPowercount = 0; + pdmpriv->bTXPowerTrackingInit = _FALSE; + //#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default + + if (*(pDM_Odm->mp_mode) != 1) + pdmpriv->TxPowerTrackControl = _TRUE; + //#endif//#if (MP_DRIVER != 1) + } + MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); + + } + #endif//endif (CONFIG_RTL8188E==1) +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + #ifdef RTL8188E_SUPPORT + { + pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + } + #endif +#endif + + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PDM_ODM_T pDM_Odm + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PADAPTER pAdapter = pDM_Odm->Adapter; + prtl8192cd_priv priv = pDM_Odm->priv; + + //if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + //return; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_MP: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + + case ODM_ADSL: + //odm_DIGAP(pDM_Odm); + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + #if( (RTL8192C_SUPPORT==1) || (RTL8723A_SUPPORT==1) ) + rtl8192c_odm_CheckTXPowerTracking(Adapter); + #endif + + #if (RTL8192D_SUPPORT==1) + #if (RTL8192D_EASY_SMART_CONCURRENT == 1) + if(!Adapter->bSlaveOfDMSP) + #endif + rtl8192d_odm_CheckTXPowerTracking(Adapter); + #endif + #if(RTL8188E_SUPPORT==1) + + //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) + if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + return; + } + + if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec + { + //pHalData->TxPowerCheckCnt++; //cosa add for debug + //ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + //DBG_8192C("Trigger 92C Thermal Meter!!\n"); + + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + + } + else + { + //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); + odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + #endif + +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + return; + + if(IS_HARDWARE_TYPE_8723A(Adapter)) + return; + + if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) + odm_TXPowerTrackingThermalMeterCheck(Adapter); +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + + if ( (priv->pmib->dot11RFEntry.ther) && ((priv->up_time % priv->pshare->rf_ft_var.tpt_period) == 0)){ +#ifdef CONFIG_RTL_92D_SUPPORT + if (GET_CHIP_VER(priv)==VERSION_8192D){ + tx_power_tracking_92D(priv); + } else +#endif + { +#ifdef CONFIG_RTL_92C_SUPPORT + tx_power_tracking(priv); +#endif + } + } +#endif + +} + + + +//antenna mapping info +// 1: right-side antenna +// 2/0: left-side antenna +//PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 +//PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 +// We select left antenna as default antenna in initial process, modify it as needed +// + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND +#if (HAL_CODE_BASE==RTL8192_C) + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + static u1Byte TM_Trigger = 0; + //u1Byte TxPowerCheckCnt = 5; //10 sec + + if(!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/) + { + return; + } + + if(!TM_Trigger) //at least delay 1 sec + { + if(IS_HARDWARE_TYPE_8192D(Adapter)) + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_92D, BIT17 | BIT16, 0x03); + else if(IS_HARDWARE_TYPE_8188E(Adapter)) + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } + else + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. + TM_Trigger = 0; + } +#endif +#endif +} + +#endif + + + +//3============================================================ +//3 SW Antenna Diversity +//3============================================================ +#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) +VOID +odm_SwAntDivInit( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + odm_SwAntDivInit_NIC(pDM_Odm); +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + dm_SW_AntennaSwitchInit(pDM_Odm->priv); +#endif +} +#if (RTL8723A_SUPPORT==1) +// Only for 8723A SW ANT DIV INIT--2012--07--17 +VOID +odm_SwAntDivInit_NIC_8723A( + IN PDM_ODM_T pDM_Odm) +{ + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte btAntNum=BT_GetPGAntNum(Adapter); + + + if(IS_HARDWARE_TYPE_8723A(Adapter)) + { + pDM_SWAT_Table->ANTA_ON =TRUE; + + // Set default antenna B status by PG + if(btAntNum == Ant_x2) + pDM_SWAT_Table->ANTB_ON = TRUE; + else if(btAntNum ==Ant_x1) + pDM_SWAT_Table->ANTB_ON = FALSE; + else + pDM_SWAT_Table->ANTB_ON = TRUE; + } + +} +#endif +VOID +odm_SwAntDivInit_NIC( + IN PDM_ODM_T pDM_Odm + ) +{ + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; +// Init SW ANT DIV mechanism for 8723AE/AU/AS// Neil Chen--2012--07--17--- +// CE/AP/ADSL no using SW ANT DIV for 8723A Series IC +//#if (DM_ODM_SUPPORT_TYPE==ODM_MP) +#if (RTL8723A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + odm_SwAntDivInit_NIC_8723A(pDM_Odm); + } +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n")); + pDM_SWAT_Table->RSSI_sum_A = 0; + pDM_SWAT_Table->RSSI_cnt_A = 0; + pDM_SWAT_Table->RSSI_sum_B = 0; + pDM_SWAT_Table->RSSI_cnt_B = 0; + pDM_SWAT_Table->CurAntenna = Antenna_A; + pDM_SWAT_Table->PreAntenna = Antenna_A; + pDM_SWAT_Table->try_flag = 0xff; + pDM_SWAT_Table->PreRSSI = 0; + pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_SWAT_Table->bTriggerAntennaSwitch = 0; + pDM_SWAT_Table->SelectAntennaMap=0xAA; + pDM_SWAT_Table->lastTxOkCnt = 0; + pDM_SWAT_Table->lastRxOkCnt = 0; + pDM_SWAT_Table->TXByteCnt_A = 0; + pDM_SWAT_Table->TXByteCnt_B = 0; + pDM_SWAT_Table->RXByteCnt_A = 0; + pDM_SWAT_Table->RXByteCnt_B = 0; + pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW; + pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860); +} + +// +// 20100514 Joseph: +// Add new function to reset the state of antenna diversity before link. +// +VOID +ODM_SwAntDivResetBeforeLink( + IN PDM_ODM_T pDM_Odm + ) +{ + + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + pDM_SWAT_Table->SWAS_NoLink_State = 0; + +} + +// +// 20100514 Luke/Joseph: +// Add new function to reset antenna diversity state after link. +// +VOID +ODM_SwAntDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ) +{ + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + pDM_SWAT_Table->RSSI_cnt_A = 0; + pDM_SWAT_Table->RSSI_cnt_B = 0; + pDM_Odm->RSSI_test = FALSE; + pDM_SWAT_Table->try_flag = 0xff; + pDM_SWAT_Table->RSSI_Trying = 0; + pDM_SWAT_Table->SelectAntennaMap=0xAA; +} + +VOID +ODM_SwAntDivChkPerPktRssi( + IN PDM_ODM_T pDM_Odm, + IN u1Byte StationID, + IN PODM_PHY_INFO_T pPhyInfo + ) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + if(!(pDM_Odm->SupportAbility & (ODM_BB_ANT_DIV))) + return; + + if(StationID == pDM_SWAT_Table->RSSI_target) + { + //1 RSSI for SW Antenna Switch + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + { + pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll; + pDM_SWAT_Table->RSSI_cnt_A++; + } + else + { + pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll; + pDM_SWAT_Table->RSSI_cnt_B++; + + } + } + +} + +// +VOID +odm_SwAntDivChkAntSwitch( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Step + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PADAPTER pAdapter = pDM_Odm->Adapter; + prtl8192cd_priv priv = pDM_Odm->priv; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_MP: + case ODM_CE: + odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step); + break; + + case ODM_AP: + case ODM_ADSL: +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP |ODM_ADSL)) + if (priv->pshare->rf_ft_var.antSw_enable && (priv->up_time % 4==1)) + dm_SW_AntennaSwitch(priv, SWAW_STEP_PEAK); +#endif + break; + } + +} + +// +// 20100514 Luke/Joseph: +// Add new function for antenna diversity after link. +// This is the main function of antenna diversity after link. +// This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). +// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. +// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. +// After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just +// listened on the air with the RSSI of original antenna. +// It chooses the antenna with better RSSI. +// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting +// penalty to get next try. + + +VOID +ODM_SetAntenna( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Antenna) +{ + ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna); +} +//--------------------------------2012--09--06-- +//Note: Antenna_Main--> Antenna_A +// Antenna_Aux---> Antenna_B +//---------------------------------- +VOID +odm_SwAntDivChkAntSwitchNIC( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Step + ) +{ +#if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1)) + //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + s4Byte curRSSI=100, RSSI_A, RSSI_B; + u1Byte nextAntenna=Antenna_B; + //static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u8Byte curTxOkCnt, curRxOkCnt; + //static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; + u8Byte CurByteCnt=0, PreByteCnt=0; + //static u1Byte TrafficLoad = TRAFFIC_LOW; + u1Byte Score_A=0, Score_B=0; + u1Byte i; + + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if (pDM_Odm->SupportICType & (ODM_RTL8192D|ODM_RTL8188E)) + return; + + if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R)) + return; + + if(pDM_Odm->SupportPlatform & ODM_MP) + { + if(*(pDM_Odm->pAntennaTest)) + return; + } + + if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("odm_SwAntDivChkAntSwitch(): No AntDiv Mechanism, Antenna A or B is off\n")); + return; + } + + // Radio off: Status reset to default and return. + if(*(pDM_Odm->pbPowerSaving)==TRUE) //pHalData->eRFPowerState==eRfOff + { + ODM_SwAntDivRestAfterLink(pDM_Odm); + return; + } + + + // Handling step mismatch condition. + // Peak step is not finished at last time. Recover the variable and check again. + if( Step != pDM_SWAT_Table->try_flag ) + { + ODM_SwAntDivRestAfterLink(pDM_Odm); + } + +#if (DM_ODM_SUPPORT_TYPE &( ODM_MP| ODM_CE )) + + if(pDM_SWAT_Table->try_flag == 0xff) + { + pDM_SWAT_Table->RSSI_target = 0xff; + + #if(DM_ODM_SUPPORT_TYPE & ODM_CE) + { + u1Byte index = 0; + PSTA_INFO_T pEntry = NULL; + + + for(index=0; indexpODM_StaInfo[index]; + if(IS_STA_VALID(pEntry) ) { + break; + } + } + if(pEntry == NULL) + { + ODM_SwAntDivRestAfterLink(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); + return; + } + else + { + pDM_SWAT_Table->RSSI_target = index; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); + } + } + #elif (DM_ODM_SUPPORT_TYPE & ODM_MP) + { + PADAPTER pAdapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; + + // Select RSSI checking target + if(pMgntInfo->mAssoc && !ACTING_AS_AP(pAdapter)) + { + // Target: Infrastructure mode AP. + //pDM_SWAT_Table->RSSI_target = NULL; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): RSSI_target is DEF AP!\n")); + } + else + { + u1Byte index = 0; + PSTA_INFO_T pEntry = NULL; + PADAPTER pTargetAdapter = NULL; + + if(pMgntInfo->mIbss ) + { + // Target: AP/IBSS peer. + pTargetAdapter = pAdapter; + } + else + { + pTargetAdapter = GetFirstAPAdapter(pAdapter); + } + + if(pTargetAdapter != NULL) + { + for(index=0; indexbAssociated) + break; + } + + } + + } + + if(pEntry == NULL) + { + ODM_SwAntDivRestAfterLink(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); + return; + } + else + { + //pDM_SWAT_Table->RSSI_target = pEntry; + pDM_SWAT_Table->RSSI_target = index; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); + } + }//end if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter)) + + } + #endif + + pDM_SWAT_Table->RSSI_cnt_A = 0; + pDM_SWAT_Table->RSSI_cnt_B = 0; + pDM_SWAT_Table->try_flag = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n")); + return; + } + else + { +#if (DM_ODM_SUPPORT_TYPE &( ODM_MP)) + //PADAPTER Adapter = pDM_Odm->Adapter; + curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt; + curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt; + pDM_SWAT_Table->lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast; + pDM_SWAT_Table->lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast; +#else + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt; + pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curTxOkCnt = %lld\n",curTxOkCnt)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curRxOkCnt = %lld\n",curRxOkCnt)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastTxOkCnt = %lld\n",pDM_SWAT_Table->lastTxOkCnt)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastRxOkCnt = %lld\n",pDM_SWAT_Table->lastRxOkCnt)); + + if(pDM_SWAT_Table->try_flag == 1) + { + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + { + pDM_SWAT_Table->TXByteCnt_A += curTxOkCnt; + pDM_SWAT_Table->RXByteCnt_A += curRxOkCnt; + } + else + { + pDM_SWAT_Table->TXByteCnt_B += curTxOkCnt; + pDM_SWAT_Table->RXByteCnt_B += curRxOkCnt; + } + + nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; + pDM_SWAT_Table->RSSI_Trying--; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying)); + if(pDM_SWAT_Table->RSSI_Trying == 0) + { + CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A) : (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B); + PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B) : (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A); + + if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) + //CurByteCnt = PlatformDivision64(CurByteCnt, 9); + PreByteCnt = PreByteCnt*9; + else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) + //CurByteCnt = PlatformDivision64(CurByteCnt, 2); + PreByteCnt = PreByteCnt*2; + + if(pDM_SWAT_Table->RSSI_cnt_A > 0) + RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A; + else + RSSI_A = 0; + if(pDM_SWAT_Table->RSSI_cnt_B > 0) + RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B; + else + RSSI_B = 0; + curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; + pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", + RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B)); + } + + } + else + { + + if(pDM_SWAT_Table->RSSI_cnt_A > 0) + RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A; + else + RSSI_A = 0; + if(pDM_SWAT_Table->RSSI_cnt_B > 0) + RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B; + else + RSSI_B = 0; + curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; + pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", + RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B)); + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt)); + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt)); + } + + //1 Trying State + if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0)) + { + + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = TP_MODE")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:CurByteCnt = %lld,", CurByteCnt)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:PreByteCnt = %lld\n",PreByteCnt)); + if(CurByteCnt < PreByteCnt) + { + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; + else + pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; + } + else + { + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; + else + pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; + } + for (i= 0; i<8; i++) + { + if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1) + Score_A++; + else + Score_B++; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Score_A=%d, Score_B=%d\n", Score_A, Score_B)); + + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + { + nextAntenna = (Score_A > Score_B)?Antenna_A:Antenna_B; + } + else + { + nextAntenna = (Score_B > Score_A)?Antenna_B:Antenna_A; + } + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B")); + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n", + //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B"))); + + if(nextAntenna != pDM_SWAT_Table->CurAntenna) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna")); + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n")); + } + } + + if(pDM_SWAT_Table->TestMode == RSSI_MODE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = RSSI_MODE")); + pDM_SWAT_Table->SelectAntennaMap=0xAA; + if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna")); + nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; + } + else // current anntena is good + { + nextAntenna =pDM_SWAT_Table->CurAntenna; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n")); + } + } + pDM_SWAT_Table->try_flag = 0; + pDM_Odm->RSSI_test = FALSE; + pDM_SWAT_Table->RSSI_sum_A = 0; + pDM_SWAT_Table->RSSI_cnt_A = 0; + pDM_SWAT_Table->RSSI_sum_B = 0; + pDM_SWAT_Table->RSSI_cnt_B = 0; + pDM_SWAT_Table->TXByteCnt_A = 0; + pDM_SWAT_Table->TXByteCnt_B = 0; + pDM_SWAT_Table->RXByteCnt_A = 0; + pDM_SWAT_Table->RXByteCnt_B = 0; + + } + + //1 Normal State + else if(pDM_SWAT_Table->try_flag == 0) + { + if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) + { + if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) + pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH; + else + pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW; + } + else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) + { + if ((curTxOkCnt+curRxOkCnt) > 3750000) //if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) + pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH; + else + pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW; + } + if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) + pDM_SWAT_Table->bTriggerAntennaSwitch = 0; + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt)); + + //Prepare To Try Antenna + nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; + pDM_SWAT_Table->try_flag = 1; + pDM_Odm->RSSI_test = TRUE; + if((curRxOkCnt+curTxOkCnt) > 1000) + { + pDM_SWAT_Table->RSSI_Trying = 4; + pDM_SWAT_Table->TestMode = TP_MODE; + } + else + { + pDM_SWAT_Table->RSSI_Trying = 2; + pDM_SWAT_Table->TestMode = RSSI_MODE; + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n")); + + + pDM_SWAT_Table->RSSI_sum_A = 0; + pDM_SWAT_Table->RSSI_cnt_A = 0; + pDM_SWAT_Table->RSSI_sum_B = 0; + pDM_SWAT_Table->RSSI_cnt_B = 0; + } + } + + //1 4.Change TRX antenna + if(nextAntenna != pDM_SWAT_Table->CurAntenna) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Change TX Antenna!\n ")); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + ODM_SetAntenna(pDM_Odm,nextAntenna); + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + { + BOOLEAN bEnqueue; + bEnqueue = (pDM_Odm->SupportInterface == ODM_ITRF_PCIE)?FALSE :TRUE; + rtw_antenna_select_cmd(pDM_Odm->Adapter, nextAntenna, bEnqueue); + } + #endif + + } + + //1 5.Reset Statistics + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + pDM_SWAT_Table->CurAntenna = nextAntenna; + pDM_SWAT_Table->PreRSSI = curRSSI; + + //1 6.Set next timer + { + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + + if(pDM_SWAT_Table->RSSI_Trying == 0) + return; + + if(pDM_SWAT_Table->RSSI_Trying%2 == 0) + { + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) + { + //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 10 ); //ms + ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 10 ); //ms + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n")); + } + else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) + { + //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 50 ); //ms + ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 50 ); //ms + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n")); + } + } + else + { + //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms + ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n")); + } + } + else + { + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH) + //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 90 ); //ms + ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 90 ); //ms + else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW) + //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 100 ); //ms + ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms + } + else + //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms + ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms + } + } +#endif // #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) +#endif // #if (RTL8192C_SUPPORT==1) +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +u1Byte +odm_SwAntDivSelectChkChnl( + IN PADAPTER Adapter + ) +{ +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + u1Byte index, target_chnl=0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + u1Byte chnl_peer_cnt[14] = {0}; + + if(Adapter->MgntInfo.tmpNumBssDesc==0) + { + return 0; + } + else + { + // 20100519 Joseph: Select checking channel from current scan list. + // We just choose the channel with most APs to be the test scan channel. + for(index=0; indexMgntInfo.tmpNumBssDesc; index++) + { + // Add by hpfan: prevent access invalid channel number + // TODO: Verify channel number by channel plan + if(Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber == 0 || + Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber > 13) + continue; + + chnl_peer_cnt[Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber-1]++; + } + for(index=0; index<14; index++) + { + if(chnl_peer_cnt[index]>chnl_peer_cnt[target_chnl]) + target_chnl = index; + } + target_chnl+=1; + ODM_RT_TRACE(pDM_Odm,COMP_SWAS, DBG_LOUD, + ("odm_SwAntDivSelectChkChnl(): Channel %d is select as test channel.\n", target_chnl)); + + return target_chnl; + } +#else + return 0; +#endif +} + + +VOID +odm_SwAntDivConsructChkScanChnl( + IN PADAPTER Adapter, + IN u1Byte ChkChnl + ) +{ + + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PRT_CHANNEL_LIST pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo); + u1Byte index; + + if(ChkChnl==0) + { + // 20100519 Joseph: Original antenna scanned nothing. + // Test antenna shall scan all channel with half period in this condition. + RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, NULL, NULL); + for(index=0; indexChannelLen; index++) + pChannelList->ChannelInfo[index].ScanPeriod /= 2; + } + else + { + // The using of this CustomizedScanRequest is a trick to rescan the two channels + // under the NORMAL scanning process. It will not affect MGNT_INFO.CustomizedScanRequest. + CUSTOMIZED_SCAN_REQUEST CustomScanReq; + + CustomScanReq.bEnabled = TRUE; + CustomScanReq.Channels[0] = ChkChnl; + CustomScanReq.Channels[1] = pMgntInfo->dot11CurrentChannelNumber; + CustomScanReq.nChannels = 2; + CustomScanReq.ScanType = SCAN_ACTIVE; + CustomScanReq.Duration = DEFAULT_ACTIVE_SCAN_PERIOD; + + RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, &CustomScanReq, NULL); + } + +} +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +// +// 20100514 Luke/Joseph: +// Callback function for 500ms antenna test trying. +// +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID +odm_SwAntDivChkAntSwitchCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table; + + #if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem); + #else + odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); + #endif +#else + ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem); + #endif + +} +VOID +odm_SwAntDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ) +{ + + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); + +} +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) +{ + PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE); +} +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) +{ + PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; + odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE); +} +#endif + +#else //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) + +VOID odm_SwAntDivInit( IN PDM_ODM_T pDM_Odm ) {} +VOID ODM_SwAntDivChkPerPktRssi( + IN PDM_ODM_T pDM_Odm, + IN u1Byte StationID, + IN PODM_PHY_INFO_T pPhyInfo + ) {} +VOID odm_SwAntDivChkAntSwitch( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Step + ) {} +VOID ODM_SwAntDivResetBeforeLink( IN PDM_ODM_T pDM_Odm ){} +VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm ){} +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +u1Byte odm_SwAntDivSelectChkChnl( IN PADAPTER Adapter ){ return 0;} +VOID +odm_SwAntDivConsructChkScanChnl( + IN PADAPTER Adapter, + IN u1Byte ChkChnl + ){} +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID odm_SwAntDivChkAntSwitchCallback( PRT_TIMER pTimer){} +VOID odm_SwAntDivChkAntSwitchWorkitemCallback( IN PVOID pContext ){} +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){} +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){} +#endif + +#endif //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +#if((defined(CONFIG_SW_ANTENNA_DIVERSITY))||(defined(CONFIG_HW_ANTENNA_DIVERSITY))) +BOOLEAN +ODM_SwAntDivCheckBeforeLink8192C( + IN PDM_ODM_T pDM_Odm + ) +{ + +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData=NULL; + PMGNT_INFO pMgntInfo = NULL; + //pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + s1Byte Score = 0; + PRT_WLAN_BSS pTmpBssDesc; + PRT_WLAN_BSS pTestBssDesc; + + u1Byte target_chnl = 0; + u1Byte index; + +return FALSE; + if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 + { // The ODM structure is not initialized. + return FALSE; + } + // 2012/04/26 MH Prevent no-checked IC to execute antenna diversity. + if(pDM_Odm->SupportICType == ODM_RTL8188E && pDM_Odm->SupportInterface != ODM_ITRF_PCIE) + return FALSE; + pHalData = GET_HAL_DATA(Adapter); + pMgntInfo = &Adapter->MgntInfo; + + // Condition that does not need to use antenna diversity. + if(IS_8723_SERIES(pHalData->VersionID) || + IS_92C_SERIAL(pHalData->VersionID) || + (pHalData->AntDivCfg==0) || + pMgntInfo->AntennaTest || + Adapter->bInHctTest) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): No AntDiv Mechanism.\n")); + return FALSE; + } + + if(IS_8723_SERIES(pHalData->VersionID) || IS_92C_SERIAL(pHalData->VersionID) ) + { + if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): No AntDiv Mechanism, Antenna A or B is off\n")); + return FALSE; + } + } + + // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. + PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", + pMgntInfo->RFChangeInProgress, + pHalData->eRFPowerState)); + + pDM_SWAT_Table->SWAS_NoLink_State = 0; + + return FALSE; + } + else + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + } + + //1 Run AntDiv mechanism "Before Link" part. + if(pDM_SWAT_Table->SWAS_NoLink_State == 0) + { + //1 Prepare to do Scan again to check current antenna state. + + // Set check state to next step. + pDM_SWAT_Table->SWAS_NoLink_State = 1; + + // Copy Current Scan list. + Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc; + PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); + + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(pDM_FatTable->RxIdleAnt == MAIN_ANT) + ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT); + else + ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"))); + } + if(pDM_Odm->SupportICType != ODM_RTL8188E) + { + // Switch Antenna to another one. + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B")); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); + pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); + } + // Go back to scan function again. + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Scan one more time\n")); + pMgntInfo->ScanStep=0; + target_chnl = odm_SwAntDivSelectChkChnl(Adapter); + odm_SwAntDivConsructChkScanChnl(Adapter, target_chnl); + HTReleaseChnlOpLock(Adapter); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + + return TRUE; + } + else + { + //1 ScanComple() is called after antenna swiched. + //1 Check scan result and determine which antenna is going + //1 to be used. + + for(index=0; indexMgntInfo.tmpNumBssDesc; index++) + { + pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]); + pTestBssDesc = &(pMgntInfo->bssDesc[index]); + + if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C(): ERROR!! This shall not happen.\n")); + continue; + } + + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Compare scan entry: Score++\n")); + RT_PRINT_STR(ODM_COMP_ANT_DIV, ODM_DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + + Score++; + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Compare scan entry: Score--\n")); + RT_PRINT_STR(ODM_COMP_ANT_DIV, ODM_DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + Score--; + } + + } + + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(pMgntInfo->NumBssDesc!=0 && Score<=0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); + + if(pDM_FatTable->RxIdleAnt == MAIN_ANT) + ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT); + else + ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); + } + } + + if(pDM_Odm->SupportICType != ODM_RTL8188E) + { + if(pMgntInfo->NumBssDesc!=0 && Score<=0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): Using Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"Antenna_A":"Antenna_B")); + + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C(): Remain Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"Antenna_B":"Antenna_A")); + + pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna; + + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); + pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); + PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); + } + } + // Check state reset to default and wait for next time. + pDM_SWAT_Table->SWAS_NoLink_State = 0; + + return FALSE; + } +#else + return FALSE; +#endif + +return FALSE; +} +#else +BOOLEAN +ODM_SwAntDivCheckBeforeLink8192C( + IN PDM_ODM_T pDM_Odm + ) +{ + + return FALSE; + +} +#endif //#if((defined(CONFIG_SW_ANTENNA_DIVERSITY))||(defined(CONFIG_HW_ANTENNA_DIVERSITY))) +#endif //#if(DM_ODM_SUPPORT_TYPE==ODM_MP) + + +//3============================================================ +//3 SW Antenna Diversity +//3============================================================ + +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +VOID +odm_InitHybridAntDiv_88C_92D( + IN PDM_ODM_T pDM_Odm + ) +{ + +#if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) + struct rtl8192cd_priv *priv=pDM_Odm->priv; +#endif + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u1Byte bTxPathSel=0; //0:Path-A 1:Path-B + u1Byte i; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n")); + + //whether to do antenna diversity or not +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) + if(priv==NULL) return; + if(!priv->pshare->rf_ft_var.antHw_enable) + return; + + #ifdef SW_ANT_SWITCH + priv->pshare->rf_ft_var.antSw_enable =0; + #endif +#endif + + if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D)) + return; + + + bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?FALSE:TRUE; + + ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1 + ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna + // check HW setting: ANTSEL pin connection + #if(DM_ODM_SUPPORT_TYPE==ODM_AP) + ODM_Write2Byte(pDM_Odm,ODM_REG_RF_PIN_11N, (ODM_Read2Byte(pDM_Odm,0x804)&0xf0ff )| BIT(8) ); // b11-b8=0001,update RFPin setting + #endif + + // only AP support different path selection temperarly + if(!bTxPathSel){ //PATH-A + ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1); //select TX ANTESEL from path A + } + else { + ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0); //select ANTESEL from path B + } + + //Set OFDM HW RX Antenna Diversity + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1); // Decide final antenna by comparing 2 antennas' pwdb + + //Set CCK HW RX Antenna Diversity + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4 + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0 + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16) + + + //Enable HW Antenna Diversity + if(!bTxPathSel) //PATH-A + ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1); // Enable Hardware antenna switch + else + ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1); // Enable Hardware antenna switch + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity + + pDM_SWAT_Table->CurAntenna=0; //choose left antenna as default antenna + pDM_SWAT_Table->PreAntenna=0; + for(i=0; iCCK_Ant1_Cnt[i] = 0; + pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0; + pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0; + pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0; + pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0; + pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_InitHybridAntDiv\n")); +} + + +VOID +odm_InitHybridAntDiv( + IN PDM_ODM_T pDM_Odm + ) +{ + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n")); + return; + } + + if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) + { +#if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1)) + odm_InitHybridAntDiv_88C_92D(pDM_Odm); +#endif + } + else if(pDM_Odm->SupportICType == ODM_RTL8188E) + { +#if (RTL8188E_SUPPORT == 1) + ODM_AntennaDiversityInit_88E(pDM_Odm); +#endif + } + +} + + +BOOLEAN +odm_StaDefAntSel( + IN PDM_ODM_T pDM_Odm, + IN u4Byte OFDM_Ant1_Cnt, + IN u4Byte OFDM_Ant2_Cnt, + IN u4Byte CCK_Ant1_Cnt, + IN u4Byte CCK_Ant2_Cnt, + OUT u1Byte *pDefAnt + + ) +{ +#if 1 + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect==============>\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n",OFDM_Ant1_Cnt,OFDM_Ant2_Cnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt)); + + + if(((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)==0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n")); + return FALSE; + } + + if(OFDM_Ant1_Cnt || OFDM_Ant2_Cnt ) { + //if RX OFDM packet number larger than 0 + if(OFDM_Ant1_Cnt > OFDM_Ant2_Cnt) + (*pDefAnt)=1; + else + (*pDefAnt)=0; + } + // else if RX CCK packet number larger than 10 + else if((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 ) + { + if(CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt)) + (*pDefAnt)=1; + else if(CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt)) + (*pDefAnt)=0; + else if(CCK_Ant1_Cnt > CCK_Ant2_Cnt) + (*pDefAnt)=0; + else + (*pDefAnt)=1; + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2")); + +#endif + //u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0); + //(*pDefAnt)= (u1Byte) antsel; + + + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_StaDefAntSelect\n")); + + return TRUE; + + +} + + +VOID +odm_SetRxIdleAnt( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Ant, + IN BOOLEAN bDualPath +) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n")); + + if(Ant != pDM_SWAT_Table->RxIdleAnt) + { + //for path-A + if(Ant==1) + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9); //right-side antenna + else + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); //left-side antenna + + //for path-B + if(bDualPath){ + if(Ant==0) + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); //right-side antenna + else + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a); //left-side antenna + } + } + pDM_SWAT_Table->RxIdleAnt = Ant; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a)); + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n")); + + } + +VOID +ODM_AntselStatistics_88C( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacId, + IN u4Byte PWDBAll, + IN BOOLEAN isCCKrate +) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + if(pDM_SWAT_Table->antsel == 1) + { + if(isCCKrate) + pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++; + else + { + pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++; + pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll; + } + } + else + { + if(isCCKrate) + pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++; + else + { + pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++; + pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll; + } + } + +} + + + + +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) +VOID +ODM_SetTxAntByTxInfo_88C_92D( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u1Byte antsel; + + if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) + return; + + if(pDM_SWAT_Table->RxIdleAnt == 1) + antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?0:1; + else + antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?1:0; + + SET_TX_DESC_ANTSEL_A_92C(pDesc, antsel); + //SET_TX_DESC_ANTSEL_B_92C(pDesc, antsel); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("SET_TX_DESC_ANTSEL_A_92C=%d\n", pDM_SWAT_Table->TxAnt[macId])); +} +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID +ODM_SetTxAntByTxInfo_88C_92D( + IN PDM_ODM_T pDM_Odm +) +{ + +} +#elif(DM_ODM_SUPPORT_TYPE==ODM_AP) +VOID +ODM_SetTxAntByTxInfo_88C_92D( + IN PDM_ODM_T pDM_Odm +) +{ + +} +#endif + +VOID +odm_HwAntDiv_92C_92D( + IN PDM_ODM_T pDM_Odm +) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u4Byte RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2; + u1Byte RxIdleAnt, i; + BOOLEAN bRet=FALSE; + PSTA_INFO_T pEntry; + +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + struct rtl8192cd_priv *priv=pDM_Odm->priv; + //if test, return + if(priv->pshare->rf_ft_var.CurAntenna & 0x80) + return; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n")); + + if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) //if don't support antenna diveristy + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n")); + return; + } + + if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: IC Type is not 92C or 92D\n")); + return; + } + +#if (DM_ODM_SUPPORT_TYPE&(ODM_MP|ODM_CE)) + if(!pDM_Odm->bLinked) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: bLinked is FALSE\n")); + return; + } +#endif + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + + RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]); + RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("RSSI_Ant1=%d, RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2)); + + if(RSSI_Ant1 ||RSSI_Ant2) + { +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if(pDM_Odm->pODM_StaInfo[i]->expire_to) +#endif + { + RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2; + if((!RSSI) || ( RSSI < RSSI_Min) ) { + pDM_SWAT_Table->TargetSTA = i; + RSSI_Min = RSSI; + } + } + } + ///STA: found out default antenna + bRet=odm_StaDefAntSel(pDM_Odm, + pDM_SWAT_Table->OFDM_Ant1_Cnt[i], + pDM_SWAT_Table->OFDM_Ant2_Cnt[i], + pDM_SWAT_Table->CCK_Ant1_Cnt[i], + pDM_SWAT_Table->CCK_Ant2_Cnt[i], + &pDM_SWAT_Table->TxAnt[i]); + + //if Tx antenna selection: successful + if(bRet){ + pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0; + pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0; + pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0; + pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0; + pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0; + pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0; + } + } + } + + //set RX Idle Ant + RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA]; + odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, FALSE); + +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) +#ifdef TX_SHORTCUT + if (!priv->pmib->dot11OperationEntry.disable_txsc) { + plist = phead->next; + while(plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + if(pstat->expire_to) { + for (i=0; itx_sc_ent[i].hwdesc1); + pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); + if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) + pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); + pdesc= &(pstat->tx_sc_ent[i].hwdesc2); + pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); + if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) + pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); + } + } + + if (plist == plist->next) + break; + plist = plist->next; + }; + } +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("<==============odm_HwAntDiv\n")); + +} + +VOID +odm_HwAntDiv( + IN PDM_ODM_T pDM_Odm +) +{ + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n")); + return; + } + + if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) + { +#if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1)) + odm_HwAntDiv_92C_92D(pDM_Odm); +#endif + } + else if(pDM_Odm->SupportICType == ODM_RTL8188E) + { +#if (RTL8188E_SUPPORT == 1) + ODM_AntennaDiversity_88E(pDM_Odm); +#endif + } + +} + + +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) +#if 0 +VOID +odm_HwAntDiv( + IN PDM_ODM_T pDM_Odm +) +{ + struct rtl8192cd_priv *priv=pDM_Odm->priv; + struct stat_info *pstat, *pstat_min=NULL; + struct list_head *phead, *plist; + int rssi_min= 0xff, i; + u1Byte idleAnt=priv->pshare->rf_ft_var.CurAntenna; + u1Byte nextAnt; + BOOLEAN bRet=FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n")); + + if((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))) + return; + + //if test, return + if(priv->pshare->rf_ft_var.CurAntenna & 0x80) + return; + + phead = &priv->asoc_list; + plist = phead->next; + ////========================= + //find mimum rssi sta + ////========================= + while(plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) { + int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1]; + if((!pstat_min) || ( rssi < rssi_min) ) { + pstat_min = pstat; + rssi_min = rssi; + } + } + ///STA: found out default antenna + bRet=odm_StaDefAntSel(pDM_Odm, + pstat->hwRxAntSel[1], + pstat->hwRxAntSel[0], + pstat->cckPktCount[1], + pstat->cckPktCount[0], + &nextAnt + ); + + //if default antenna selection: successful + if(bRet){ + pstat->CurAntenna = nextAnt; + //update rssi + for(i=0; i<2; i++) { + if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0) + pstat->AntRSSI[i] = 0; + } + if(pstat->AntRSSI[idleAnt]==0) + pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1]; + // reset variables + pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0; + pstat->cckPktCount[1]= pstat->cckPktCount[0] =0; + } + + if (plist == plist->next) + break; + plist = plist->next; + + }; + ////========================= + //Choose RX Idle antenna according to minmum rssi + ////========================= + if(pstat_min) { + if(priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna) + odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE); + priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna; + } + + +#ifdef TX_SHORTCUT + if (!priv->pmib->dot11OperationEntry.disable_txsc) { + plist = phead->next; + while(plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + if(pstat->expire_to) { + for (i=0; itx_sc_ent[i].hwdesc1); + pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); + if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) + pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); + pdesc= &(pstat->tx_sc_ent[i].hwdesc2); + pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); + if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) + pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); + } + } + + if (plist == plist->next) + break; + plist = plist->next; + }; + } +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n"); +} +#endif + +u1Byte +ODM_Diversity_AntennaSelect( + IN PDM_ODM_T pDM_Odm, + IN u1Byte *data +) +{ + struct rtl8192cd_priv *priv=pDM_Odm->priv; + + int ant = _atoi(data, 16); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ODM_Diversity_AntennaSelect==============>\n")); + + #ifdef PCIE_POWER_SAVING + PCIeWakeUp(priv, POWER_DOWN_T0); + #endif + + if (ant==Antenna_B || ant==Antenna_A) + { + if ( !priv->pshare->rf_ft_var.antSw_select) { + ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(8)| BIT(9) ); // ANTSEL A as SW control + ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7))); // rx OFDM SW control + PHY_SetBBReg(priv, 0x860, 0x300, ant); + } else { + ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(24)| BIT(25) ); // ANTSEL B as HW control + PHY_SetBBReg(priv, 0x864, 0x300, ant); + ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7))); // rx OFDM SW control + } + + ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7))); // rx CCK SW control + ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc + ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a); + + priv->pshare->rf_ft_var.antHw_enable = 0; + priv->pshare->rf_ft_var.CurAntenna = (ant%2); + + #ifdef SW_ANT_SWITCH + priv->pshare->rf_ft_var.antSw_enable = 0; + priv->pshare->DM_SWAT_Table.CurAntenna = ant; + priv->pshare->RSSI_test =0; + #endif + } + else if(ant==0){ + + if ( !priv->pshare->rf_ft_var.antSw_select) { + ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(8)| BIT(9)) ); + ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) | BIT(7)); // OFDM HW control + } else { + ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(24)| BIT(25)) ); + ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) | BIT(7)); // OFDM HW control + } + + ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) | BIT(7)); // CCK HW control + ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) | BIT(21) ); // by tx desc + priv->pshare->rf_ft_var.CurAntenna = 0; + ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a); + priv->pshare->rf_ft_var.antHw_enable = 1; +#ifdef SW_ANT_SWITCH + priv->pshare->rf_ft_var.antSw_enable = 0; + priv->pshare->RSSI_test =0; +#endif + } +#ifdef SW_ANT_SWITCH + else if(ant==3) { + if(!priv->pshare->rf_ft_var.antSw_enable) { + + dm_SW_AntennaSwitchInit(priv); + ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a); + priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; + priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; + } + if ( !priv->pshare->rf_ft_var.antSw_select) + ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7))); // rx OFDM SW control + else + ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7))); // rx OFDM SW control + + ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7))); // rx CCK SW control + ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc + priv->pshare->rf_ft_var.antHw_enable = 0; + priv->pshare->rf_ft_var.antSw_enable = 1; + + } +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============ODM_Diversity_AntennaSelect\n")); + + return 1; +} +#endif + +#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) + +VOID odm_InitHybridAntDiv( IN PDM_ODM_T pDM_Odm ){} +VOID odm_HwAntDiv( IN PDM_ODM_T pDM_Odm){} +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) +VOID ODM_SetTxAntByTxInfo_88C_92D( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +){} +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID ODM_SetTxAntByTxInfo_88C_92D( IN PDM_ODM_T pDM_Odm){ } +#elif(DM_ODM_SUPPORT_TYPE==ODM_AP) +VOID ODM_SetTxAntByTxInfo_88C_92D( IN PDM_ODM_T pDM_Odm){ } +#endif + +#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) + + + +//============================================================ +//EDCA Turbo +//============================================================ +VOID +ODM_EdcaTurboInit( + IN PDM_ODM_T pDM_Odm) +{ + +#if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) + odm_EdcaParaInit(pDM_Odm); +#elif (DM_ODM_SUPPORT_TYPE==ODM_MP) + PADAPTER Adapter = NULL; + HAL_DATA_TYPE *pHalData = NULL; + + if(pDM_Odm->Adapter==NULL) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n")); + return; + } + + Adapter=pDM_Odm->Adapter; + pHalData=GET_HAL_DATA(Adapter); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; + pHalData->bIsAnyNonBEPkts = FALSE; + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; + Adapter->recvpriv.bIsAnyNonBEPkts =FALSE; + +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); + + +} // ODM_InitEdcaTurbo + +VOID +odm_EdcaTurboCheck( + IN PDM_ODM_T pDM_Odm + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PADAPTER pAdapter = pDM_Odm->Adapter; + prtl8192cd_priv priv = pDM_Odm->priv; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); + + if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) + return; + + switch (pDM_Odm->SupportPlatform) + { + case ODM_MP: + +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) + odm_EdcaTurboCheckMP(pDM_Odm); +#endif + break; + + case ODM_CE: +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + odm_EdcaTurboCheckCE(pDM_Odm); +#endif + break; + + case ODM_AP: + case ODM_ADSL: + +#if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) + odm_IotEngine(pDM_Odm); +#endif + break; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); + +} // odm_CheckEdcaTurbo + +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + + +VOID +odm_EdcaTurboCheckCE( + IN PDM_ODM_T pDM_Odm + ) +{ + +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + + PADAPTER Adapter = pDM_Odm->Adapter; + + u32 trafficIndex; + u32 edca_param; + u64 cur_tx_bytes = 0; + u64 cur_rx_bytes = 0; + u8 bbtchange = _FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct recv_priv *precvpriv = &(Adapter->recvpriv); + struct registry_priv *pregpriv = &Adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) + { + goto dm_CheckEdcaTurbo_EXIT; + } + + if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) + { + goto dm_CheckEdcaTurbo_EXIT; + } + +#ifdef CONFIG_BT_COEXIST + if (BT_DisableEDCATurbo(Adapter)) + { + goto dm_CheckEdcaTurbo_EXIT; + } +#endif + + // Check if the status needs to be changed. + if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) + { + cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; + cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; + + //traffic, TX or RX + if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK)||(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) + { + if (cur_tx_bytes > (cur_rx_bytes << 2)) + { // Uplink TP is present. + trafficIndex = UP_LINK; + } + else + { // Balance TP is present. + trafficIndex = DOWN_LINK; + } + } + else + { + if (cur_rx_bytes > (cur_tx_bytes << 2)) + { // Downlink TP is present. + trafficIndex = DOWN_LINK; + } + else + { // Balance TP is present. + trafficIndex = UP_LINK; + } + } + + if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) + { + +#if 0 + //adjust EDCA parameter for BE queue + edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; +#else + + if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + { + edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; + } + else + { + edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; + } +#endif + +#ifdef CONFIG_PCI_HCI + if(IS_92C_SERIAL(pHalData->VersionID)) + { + edca_param = 0x60a42b; + } + else + { + edca_param = 0x6ea42b; + } +#endif + rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); + + pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; + } + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE; + } + else + { + // + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + // + if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) + { + rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE; + } + } + +dm_CheckEdcaTurbo_EXIT: + // Set variables for next time. + precvpriv->bIsAnyNonBEPkts = _FALSE; + pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; + precvpriv->last_rx_bytes = precvpriv->rx_bytes; +#endif +} + + +#elif(DM_ODM_SUPPORT_TYPE==ODM_MP) +VOID +odm_EdcaTurboCheckMP( + IN PDM_ODM_T pDM_Odm + ) +{ + + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) + PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); + PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; + //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn + u8Byte Ext_curTxOkCnt = 0; + u8Byte Ext_curRxOkCnt = 0; + static u8Byte Ext_lastTxOkCnt = 0; + static u8Byte Ext_lastRxOkCnt = 0; + //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. + u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; + +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) + struct dm_priv *pdmpriv = &pHalData->dmpriv; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct recv_priv *precvpriv = &(Adapter->recvpriv); + struct registry_priv *pregpriv = &Adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + #ifdef CONFIG_BT_COEXIST + struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); + #endif + u1Byte bbtchange =FALSE; +#endif + // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. + u8Byte curTxOkCnt = 0; + u8Byte curRxOkCnt = 0; + u8Byte lastTxOkCnt = 0; + u8Byte lastRxOkCnt = 0; + u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; + u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; + u4Byte EDCA_BE = 0x5ea42b; + u4Byte IOTPeer=0; + BOOLEAN *pbIsCurRDLState=NULL; + BOOLEAN bLastIsCurRDLState=FALSE; + BOOLEAN bBiasOnRx=FALSE; + BOOLEAN bEdcaTurboOn=FALSE; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); + +////=============================== +////list paramter for different platform +////=============================== + bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState; + pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState); +#if (DM_ODM_SUPPORT_TYPE==ODM_MP) + // Caculate TX/RX TP: + curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; + curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; + if(pExtAdapter == NULL) + pExtAdapter = pDefaultAdapter; + + Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt; + Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt; + GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); + //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. + if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) + { + curTxOkCnt = Ext_curTxOkCnt ; + curRxOkCnt = Ext_curRxOkCnt ; + } + // + IOTPeer=pMgntInfo->IOTPeer; + bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE; + bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts) && (!pMgntInfo->bDisableFrameBursting))?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx bDisableFrameBursting : 0x%lx \n",pHalData->bIsAnyNonBEPkts,pMgntInfo->bDisableFrameBursting)); + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + // Caculate TX/RX TP: + curTxOkCnt = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; + curRxOkCnt = precvpriv->rx_bytes - precvpriv->last_rx_bytes; + #ifdef CONFIG_BT_COEXIST + if(pbtpriv->BT_Coexist) + { + if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0)) + bbtchange = TRUE; + } + #endif + IOTPeer=pmlmeinfo->assoc_AP_vendor; + bBiasOnRx=((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))?TRUE:FALSE; + bEdcaTurboOn=(bbtchange || (!precvpriv->bIsAnyNonBEPkts))?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bbtchange : 0x%lx bIsAnyNonBEPkts : 0x%lx \n",bbtchange,precvpriv->bIsAnyNonBEPkts)); +#endif + + +////=============================== +////check if edca turbo is disabled +////=============================== + if(odm_IsEdcaTurboDisable(pDM_Odm)) + goto dm_CheckEdcaTurbo_EXIT; + + +////=============================== +////remove iot case out +////=============================== + ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL); + + +////=============================== +////Check if the status needs to be changed. +////=============================== + if(bEdcaTurboOn) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt)); + if(bBiasOnRx) + odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState); + else + odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState); + +//modify by Guo.Mingzhi 2011-12-29 + EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE)); + +// if(((*pbIsCurRDLState)!=bLastIsCurRDLState)||(!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) +// { +// EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; +// ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + // } + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE)); + + } + else + { + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) + { +#if (DM_ODM_SUPPORT_TYPE==ODM_MP) + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) ); +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, pHalData->AcParam_BE); +#endif + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE)); + + } + } + +////=============================== +////Set variables for next time. +////=============================== +dm_CheckEdcaTurbo_EXIT: +#if (DM_ODM_SUPPORT_TYPE==ODM_MP) + pHalData->bIsAnyNonBEPkts = FALSE; + pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast; + pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast; +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) + precvpriv->bIsAnyNonBEPkts = FALSE; + pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; + precvpriv->last_rx_bytes = precvpriv->rx_bytes; +#endif + +} + + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PDM_ODM_T pDM_Odm +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + u4Byte IOTPeer=pMgntInfo->IOTPeer; +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) + struct registry_priv *pregpriv = &Adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u4Byte IOTPeer=pmlmeinfo->assoc_AP_vendor; + u1Byte WirelessMode=0xFF; //invalid value + + if(pDM_Odm->pWirelessMode!=NULL) + WirelessMode=*(pDM_Odm->pWirelessMode); + +#endif + +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtDisableEdcaTurbo) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); + return TRUE; + } +#endif + + if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))|| + (pDM_Odm->bWIFITest)|| + (IOTPeer>= HT_IOT_PEER_MAX)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n")); + return TRUE; + } + + +#if (DM_ODM_SUPPORT_TYPE ==ODM_MP) + // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue + // 2. User may disable EDCA Turbo mode with OID settings. + if((pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) ||pHalData->bForcedDisableTurboEDCA){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n")); + return TRUE; + } + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + //suggested by Jr.Luke: open TXOP for B/G/BG/A mode 2012-0215 + if((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)||(WirelessMode==ODM_WM_G)||(WirelessMode=ODM_WM_A)) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)|0x5E0000); + + if(pDM_Odm->SupportICType==ODM_RTL8192D) { + if ((pregpriv->wifi_spec == 1) || (pmlmeext->cur_wireless_mode == WIRELESS_11B)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("92D:EdcaTurboDisable\n")); + return TRUE; + } + } + else + { + if((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("Others:EdcaTurboDisable\n")); + return TRUE; + } + } +#ifdef CONFIG_BT_COEXIST + if (BT_DisableEDCATurbo(Adapter)) + { + goto dm_CheckEdcaTurbo_EXIT; + } +#endif + +#endif + + return FALSE; + + +} + +//add iot case here: for MP/CE +VOID +ODM_EdcaParaSelByIot( + IN PDM_ODM_T pDM_Odm, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ) +{ + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte IOTPeer=0; + u4Byte ICType=pDM_Odm->SupportICType; + u1Byte WirelessMode=0xFF; //invalid value + u4Byte RFType=pDM_Odm->RFType; + +#if(DM_ODM_SUPPORT_TYPE==ODM_MP) + PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); + PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + #ifdef CONFIG_BT_COEXIST + struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); + #endif + u1Byte bbtchange =FALSE; +#endif + + if(pDM_Odm->pWirelessMode!=NULL) + WirelessMode=*(pDM_Odm->pWirelessMode); + +/////////////////////////////////////////////////////////// +////list paramter for different platform +#if (DM_ODM_SUPPORT_TYPE==ODM_MP) + IOTPeer=pMgntInfo->IOTPeer; + GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + IOTPeer=pmlmeinfo->assoc_AP_vendor; + #ifdef CONFIG_BT_COEXIST + if(pbtpriv->BT_Coexist) + { + if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0)) + bbtchange = TRUE; + } + #endif + +#endif + + if(ICType==ODM_RTL8192D) + { + // Single PHY + if(pDM_Odm->RFType==ODM_2T2R) + { + (*EDCA_BE_UL) = 0x60a42b; //0x5ea42b; + (*EDCA_BE_DL) = 0x60a42b; //0x5ea42b; + + } + else + { + (*EDCA_BE_UL) = 0x6ea42b; + (*EDCA_BE_DL) = 0x6ea42b; + } + + } +////============================ +/// IOT case for MP +////============================ +#if (DM_ODM_SUPPORT_TYPE==ODM_MP) + else + { + + if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){ + if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) { + (*EDCA_BE_UL) = 0x60a42b; + (*EDCA_BE_DL) = 0x60a42b; + } + else + { + (*EDCA_BE_UL) = 0x6ea42b; + (*EDCA_BE_DL) = 0x6ea42b; + } + } + } + + if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) + { + (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer]; + (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer]; + } + + #if (INTEL_PROXIMITY_SUPPORT == 1) + if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE) + { + (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f; + } + else + #endif + { + if((!pMgntInfo->bDisableFrameBursting) && + (pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE))) + {// To check whether we shall force turn on TXOP configuration. + if(!((*EDCA_BE_UL) & 0xffff0000)) + (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL. + if(!((*EDCA_BE_DL) & 0xffff0000)) + (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL. + } + + //92D txop can't be set to 0x3e for cisco1250 + if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) + { + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; + } + //merge from 92s_92c_merge temp brunch v2445 20120215 + else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) + { + (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; + } + else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) + { + (*EDCA_BE_DL) = 0xa630; + } + + else if(IOTPeer == HT_IOT_PEER_MARVELL) + { + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; + } + else if(IOTPeer == HT_IOT_PEER_ATHEROS) + { + // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + } + } +////============================ +/// IOT case for CE +////============================ +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) + + if(RFType==ODM_RTL8192D) + { + if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) + { + (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK]; + (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK]; + } + else if((IOTPeer == HT_IOT_PEER_AIRGO) && + ((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)))) + (*EDCA_BE_DL)=0x00a630; + + else if((IOTPeer== HT_IOT_PEER_ATHEROS) && + (WirelessMode&ODM_WM_N5G) && + (Adapter->securitypriv.dot11PrivacyAlgrthm == _AES_ )) + (*EDCA_BE_DL)=0xa42b; + + } + //92C IOT case: + else + { + #ifdef CONFIG_BT_COEXIST + if(bbtchange) + { + (*EDCA_BE_UL) = pbtpriv->BT_EDCA[UP_LINK]; + (*EDCA_BE_DL) = pbtpriv->BT_EDCA[DOWN_LINK]; + } + else + #endif + { + if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) + { + (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK]; + (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK]; + } + else + { + (*EDCA_BE_UL)=EDCAParam[HT_IOT_PEER_UNKNOWN][UP_LINK]; + (*EDCA_BE_DL)=EDCAParam[HT_IOT_PEER_UNKNOWN][DOWN_LINK]; + } + } + if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){ + if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) + { + (*EDCA_BE_UL) = 0x60a42b; + (*EDCA_BE_DL) = 0x60a42b; + } + else + { + (*EDCA_BE_UL) = 0x6ea42b; + (*EDCA_BE_DL) = 0x6ea42b; + } + } + + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL))); + +} + + +VOID +odm_EdcaChooseTrafficIdx( + IN PDM_ODM_T pDM_Odm, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ) +{ + + + if(bBiasOnRx) + { + + if(cur_tx_bytes>(cur_rx_bytes*4)) + { + *pbIsCurRDLState=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n ")); + + } + else + { + *pbIsCurRDLState=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); + + } + } + else + { + if(cur_rx_bytes>(cur_tx_bytes*4)) + { + *pbIsCurRDLState=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n")); + + } + else + { + *pbIsCurRDLState=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); + } + } + + return ; +} + +#endif + +#if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL)) + +void odm_EdcaParaInit( + IN PDM_ODM_T pDM_Odm + ) +{ + prtl8192cd_priv priv = pDM_Odm->priv; + int mode=priv->pmib->dot11BssType.net_work_type; + + static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time; + struct ParaRecord EDCA[4]; + + memset(EDCA, 0, 4*sizeof(struct ParaRecord)); + + sifs_time = 10; + slot_time = 20; + + if (mode & (ODM_WM_N24G|ODM_WM_N5G)) + sifs_time = 16; + + if (mode & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G|ODM_WM_A)) + slot_time = 9; + + +#if((defined(RTL_MANUAL_EDCA))&&(DM_ODM_SUPPORT_TYPE==ODM_AP)) + if( priv->pmib->dot11QosEntry.ManualEDCA ) { + if( OPMODE & WIFI_AP_STATE ) + memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord)); + else + memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord)); + + #ifdef WIFI_WMM + if (QOS_ENABLE) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); + else + #endif + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); + + }else + #endif //RTL_MANUAL_EDCA + { + + if(OPMODE & WIFI_AP_STATE) + { + memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord)); + + if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G)) + memcpy(&EDCA[VI], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); + else + memcpy(&EDCA[VI], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord)); + } + else + { + memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord)); + + if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G)) + memcpy(&EDCA[VI], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); + else + memcpy(&EDCA[VI], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord)); + } + + #ifdef WIFI_WMM + if (QOS_ENABLE) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); + else + #endif + +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time)); +#elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + 2* slot_time)); +#endif + + + } + + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VO_PARAM, (EDCA[VO].TXOPlimit<< 16) | (EDCA[VO].ECWmax<< 12) | (EDCA[VO].ECWmin<< 8) | (sifs_time + EDCA[VO].AIFSN* slot_time)); + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[BE].AIFSN* slot_time)); + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BK_PARAM, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[BK].AIFSN* slot_time)); +// ODM_Write1Byte(pDM_Odm,ACMHWCTRL, 0x00); + + priv->pshare->iot_mode_enable = 0; +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) + if (priv->pshare->rf_ft_var.wifi_beq_iot) + priv->pshare->iot_mode_VI_exist = 0; + + #ifdef WMM_VIBE_PRI + priv->pshare->iot_mode_BE_exist = 0; + #endif + + #ifdef LOW_TP_TXOP + priv->pshare->BE_cwmax_enhance = 0; + #endif + +#elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL) + priv->pshare->iot_mode_BE_exist = 0; +#endif + priv->pshare->iot_mode_VO_exist = 0; +} + +BOOLEAN +ODM_ChooseIotMainSTA( + IN PDM_ODM_T pDM_Odm, + IN PSTA_INFO_T pstat + ) +{ + prtl8192cd_priv priv = pDM_Odm->priv; + BOOLEAN bhighTP_found_pstat=FALSE; + + if ((GET_ROOT(priv)->up_time % 2) == 0) { + unsigned int tx_2s_avg = 0; + unsigned int rx_2s_avg = 0; + int i=0, aggReady=0; + unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes); + + pstat->current_tx_bytes += pstat->tx_byte_cnt; + pstat->current_rx_bytes += pstat->rx_byte_cnt; + + if (total_sum != 0) { + if (total_sum <= 100) { + tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum); + rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum); + } else { + tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100)); + rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100)); + } + + } + +#if(DM_ODM_SUPPORT_TYPE==ODM_ADSL) + if (pstat->ht_cap_len) { + if ((tx_2s_avg + rx_2s_avg) >=25 /*50*/) { + + priv->pshare->highTP_found_pstat = pstat; + bhighTP_found_pstat=TRUE; + } + } +#elif(DM_ODM_SUPPORT_TYPE==ODM_AP) + for(i=0; i<8; i++) + aggReady += (pstat->ADDBA_ready[i]); + if (pstat->ht_cap_len && aggReady) + { + if ((tx_2s_avg + rx_2s_avg >= 25)) { + priv->pshare->highTP_found_pstat = pstat; + } + + #ifdef CLIENT_MODE + if (OPMODE & WIFI_STATION_STATE) { +#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) + if ((pstat->IOTPeer==HT_IOT_PEER_RALINK) && ((tx_2s_avg + rx_2s_avg) >= 45)) +#else + if(pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45)) +#endif + priv->pshare->highTP_found_pstat = pstat; + } + #endif + } +#endif + } else { + pstat->current_tx_bytes = pstat->tx_byte_cnt; + pstat->current_rx_bytes = pstat->rx_byte_cnt; + } + + return bhighTP_found_pstat; +} + + +#ifdef WIFI_WMM +VOID +ODM_IotEdcaSwitch( + IN PDM_ODM_T pDM_Odm, + IN unsigned char enable + ) +{ + prtl8192cd_priv priv = pDM_Odm->priv; + int mode=priv->pmib->dot11BssType.net_work_type; + unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94; + unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs; + +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if (!(!priv->pmib->dot11OperationEntry.wifi_specific || + ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + #ifdef CLIENT_MODE + || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + #endif + )) + return; +#endif + + if ((mode & (ODM_WM_N24G|ODM_WM_N5G)) && (priv->pshare->ht_sta_num + #ifdef WDS + || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) + #endif + )) + sifs_time = 16; + + if (mode & (ODM_WM_N24G|ODM_WM_N5G|ODM_WM_G|ODM_WM_A)) { + slot_time = 9; + } + else + { + BE_TXOP = 94; + VI_TXOP = 188; + } + +#if (DM_ODM_SUPPORT_TYPE==ODM_ADSL) + if (priv->pshare->iot_mode_VO_exist) { + // to separate AC_VI and AC_BE to avoid using the same EDCA settings + if (priv->pshare->iot_mode_BE_exist) { + vi_cw_max = 5; + vi_cw_min = 3; + } else { + vi_cw_max = 6; + vi_cw_min = 4; + } + } + vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); + + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs); + + +#elif (DM_ODM_SUPPORT_TYPE==ODM_AP) + if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) { + if (priv->pshare->iot_mode_VO_exist) { + #ifdef WMM_VIBE_PRI + if (priv->pshare->iot_mode_BE_exist) + { + vi_cw_max = 5; + vi_cw_min = 3; + vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); + } + else + #endif + { + vi_cw_max = 6; + vi_cw_min = 4; + vi_aifs = 0x2b; + } + } + else { + vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); + } + + ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16) + | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs); + } +#endif + + + +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (10 << 12) | (4 << 8) | 0x4f); + else if(!enable) +#elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL) + if(!enable) //if iot is disable ,maintain original BEQ PARAM +#endif + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8) + | (sifs_time + 3 * slot_time)); + else + { + int txop_enlarge; + int txop; + unsigned int cw_max; + unsigned int txop_close; + + #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)) + cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6); + txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0); + + if(priv->pshare->txop_enlarge == 0xe) //if intel case + txop = (txop_close ? 0 : (BE_TXOP*2)); + else //if other case + txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge)); + #else + cw_max=6; + if((priv->pshare->txop_enlarge==0xe)||(priv->pshare->txop_enlarge==0xd)) + txop=BE_TXOP*2; + else + txop=BE_TXOP*priv->pshare->txop_enlarge; + + #endif + + if (priv->pshare->ht_sta_num + #ifdef WDS + || ((OPMODE & WIFI_AP_STATE) && (mode & (ODM_WM_N24G|ODM_WM_N5G)) && + priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) + #endif + ) + { + + if (priv->pshare->txop_enlarge == 0xe) { + // is intel client, use a different edca value + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop<< 16) | (cw_max<< 12) | (4 << 8) | 0x1f); + priv->pshare->txop_enlarge = 2; + } +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) + #ifndef LOW_TP_TXOP + else if (priv->pshare->txop_enlarge == 0xd) { + // is intel ralink, use a different edca value + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | (4 << 12) | (3 << 8) | 0x19); + priv->pshare->txop_enlarge = 2; + } + #endif +#endif + else + { + if (pDM_Odm->RFType==ODM_2T2R) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | + (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); + else + #if(DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | + (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time)); + #else + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | + (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time)); + + #endif + } + } + else + { + #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); + #else + #if defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP*2 << 16) | (cw_max << 12) | (5 << 8) | (sifs_time + 3 * slot_time)); + #else + ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP*2 << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); + #endif + + #endif + } + + } +} +#endif + +VOID +odm_IotEngine( + IN PDM_ODM_T pDM_Odm + ) +{ + + struct rtl8192cd_priv *priv=pDM_Odm->priv; + PSTA_INFO_T pstat = NULL; + u4Byte i; + +#ifdef WIFI_WMM + unsigned int switch_turbo = 0; +#endif +//////////////////////////////////////////////////////// +// if EDCA Turbo function is not supported or Manual EDCA Setting +// then return +//////////////////////////////////////////////////////// + if(!(pDM_Odm->SupportAbility&ODM_MAC_EDCA_TURBO)){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO NOT SUPPORTED\n")); + return; + } + +#if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM)) + if(priv->pmib->dot11QosEntry.ManualEDCA){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: MANUAL SETTING\n")); + return ; + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE &ODM_AP) + ////////////////////////////////////////////////////// + //find high TP STA every 2s +////////////////////////////////////////////////////// + if ((GET_ROOT(priv)->up_time % 2) == 0) + priv->pshare->highTP_found_pstat==NULL; + +#if 0 + phead = &priv->asoc_list; + plist = phead->next; + while(plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + + if(ODM_ChooseIotMainSTA(pDM_Odm, pstat)); //find the correct station + break; + if (plist == plist->next) //the last plist + break; + plist = plist->next; + }; +#endif + + //find highTP STA + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) && (ODM_ChooseIotMainSTA(pDM_Odm, pstat))) //find the correct station + break; + } + + ////////////////////////////////////////////////////// + //if highTP STA is not found, then return + ////////////////////////////////////////////////////// + if(priv->pshare->highTP_found_pstat==NULL) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: NO HT STA FOUND\n")); + return; + } +#endif + + pstat=priv->pshare->highTP_found_pstat; + + +#ifdef WIFI_WMM + if (QOS_ENABLE) { + if (!priv->pmib->dot11OperationEntry.wifi_specific + #if(DM_ODM_SUPPORT_TYPE==ODM_AP) + ||((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL) + || (priv->pmib->dot11OperationEntry.wifi_specific == 2) + #endif + ) { + if (priv->pshare->iot_mode_enable && + ((priv->pshare->phw->VO_pkt_count > 50) || + (priv->pshare->phw->VI_pkt_count > 50) || + (priv->pshare->phw->BK_pkt_count > 50))) { + priv->pshare->iot_mode_enable = 0; + switch_turbo++; + } else if ((!priv->pshare->iot_mode_enable) && + ((priv->pshare->phw->VO_pkt_count < 50) && + (priv->pshare->phw->VI_pkt_count < 50) && + (priv->pshare->phw->BK_pkt_count < 50))) { + priv->pshare->iot_mode_enable++; + switch_turbo++; + } + } + + + #if(DM_ODM_SUPPORT_TYPE==ODM_AP) + if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) + #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL) + if (priv->pmib->dot11OperationEntry.wifi_specific) + #endif + { + if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) { + priv->pshare->iot_mode_VO_exist++; + switch_turbo++; + } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) { + priv->pshare->iot_mode_VO_exist = 0; + switch_turbo++; + } +#if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI))) + if (priv->pshare->iot_mode_VO_exist) { + //printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count); + if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) { + priv->pshare->iot_mode_BE_exist++; + switch_turbo++; + } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) { + priv->pshare->iot_mode_BE_exist = 0; + switch_turbo++; + } + } +#endif + +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if (priv->pshare->rf_ft_var.wifi_beq_iot) + { + if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) { + priv->pshare->iot_mode_VI_exist++; + switch_turbo++; + } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) { + priv->pshare->iot_mode_VI_exist = 0; + switch_turbo++; + } + } +#endif + + } + else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) { + if (priv->pshare->txop_enlarge) { + priv->pshare->txop_enlarge = 0; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } + } + +#if(defined(CLIENT_MODE) && (DM_ODM_SUPPORT_TYPE==ODM_AP)) + if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + { + if (priv->pshare->iot_mode_enable && + (((priv->pshare->phw->VO_pkt_count > 50) || + (priv->pshare->phw->VI_pkt_count > 50) || + (priv->pshare->phw->BK_pkt_count > 50)) || + (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3])))) + { + priv->pshare->iot_mode_enable = 0; + switch_turbo++; + } + else if ((!priv->pshare->iot_mode_enable) && + (((priv->pshare->phw->VO_pkt_count < 50) && + (priv->pshare->phw->VI_pkt_count < 50) && + (priv->pshare->phw->BK_pkt_count < 50)) && + (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3])))) + { + priv->pshare->iot_mode_enable++; + switch_turbo++; + } + } +#endif + + priv->pshare->phw->VO_pkt_count = 0; + priv->pshare->phw->VI_pkt_count = 0; + priv->pshare->phw->BK_pkt_count = 0; + + #if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI))) + priv->pshare->phw->BE_pkt_count = 0; + #endif + + #if(DM_ODM_SUPPORT_TYPE==ODM_AP) + if (priv->pshare->rf_ft_var.wifi_beq_iot) + priv->pshare->phw->VI_rx_pkt_count = 0; + #endif + + } +#endif + + if ((priv->up_time % 2) == 0) { + /* + * decide EDCA content for different chip vendor + */ +#ifdef WIFI_WMM + #if(DM_ODM_SUPPORT_TYPE==ODM_ADSL) + if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2) + + #elif(DM_ODM_SUPPORT_TYPE==ODM_AP) + if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || + ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + #ifdef CLIENT_MODE + || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + #endif + #endif + )) + + { + + if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) { +#ifdef LOW_TP_TXOP +#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) + if (pstat->IOTPeer==HT_IOT_PEER_INTEL) +#else + if (pstat->is_intel_sta) +#endif + { + if (priv->pshare->txop_enlarge != 0xe) + { + priv->pshare->txop_enlarge = 0xe; + + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } + } + else if (priv->pshare->txop_enlarge != 2) + { + priv->pshare->txop_enlarge = 2; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } +#else + if (priv->pshare->txop_enlarge != 2) + { +#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) + if (pstat->IOTPeer==HT_IOT_PEER_INTEL) +#else + if (pstat->is_intel_sta) +#endif + priv->pshare->txop_enlarge = 0xe; +#if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC) + else if (pstat->IOTPeer==HT_IOT_PEER_RALINK) +#else + else if (pstat->is_ralink_sta) +#endif + priv->pshare->txop_enlarge = 0xd; + else + priv->pshare->txop_enlarge = 2; + + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } +#endif +#if 0 + if (priv->pshare->txop_enlarge != 2) + { + #if(DM_ODM_SUPPORT_TYPE==ODM_AP) + if (pstat->IOTPeer==HT_IOT_PEER_INTEL) + #else + if (pstat->is_intel_sta) + #endif + priv->pshare->txop_enlarge = 0xe; + #if(DM_ODM_SUPPORT_TYPE==ODM_AP) + else if (pstat->IOTPeer==HT_IOT_PEER_RALINK) + priv->pshare->txop_enlarge = 0xd; + #endif + else + priv->pshare->txop_enlarge = 2; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } +#endif + } + else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) + { + if (priv->pshare->txop_enlarge) { + priv->pshare->txop_enlarge = 0; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } + } + +#if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&( defined LOW_TP_TXOP)) + // for Intel IOT, need to enlarge CW MAX from 6 to 10 + if (pstat && pstat->is_intel_sta && (((pstat->tx_avarage+pstat->rx_avarage)>>10) < + priv->pshare->rf_ft_var.cwmax_enhance_thd)) + { + if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable) + { + priv->pshare->BE_cwmax_enhance = 1; + switch_turbo++; + } + } else { + if (priv->pshare->BE_cwmax_enhance) { + priv->pshare->BE_cwmax_enhance = 0; + switch_turbo++; + } + } +#endif + } +#endif + priv->pshare->current_tx_bytes = 0; + priv->pshare->current_rx_bytes = 0; + } + +#if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined( SW_TX_QUEUE)) + if ((priv->assoc_num > 1) && (AMPDU_ENABLE)) + { + if (priv->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd){ + if ((priv->swq_en == 0)){ + switch_turbo++; + if (priv->pshare->txop_enlarge == 0) + priv->pshare->txop_enlarge = 2; + priv->swq_en = 1; + } + else + { + if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) + { + priv->pshare->txop_enlarge = 2; + switch_turbo--; + } + } + } + else if(priv->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd){ + priv->swq_en = 0; + } + else if ((priv->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) { + priv->pshare->txop_enlarge = 2; + switch_turbo--; + } + } +#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined CONFIG_RTL_819XD)) + else if( (priv->assoc_num == 1) && (AMPDU_ENABLE)) { + if (pstat) { + int en_thd = 14417920>>(priv->up_time % 2); + if ((priv->swq_en == 0) && (pstat->current_tx_bytes > en_thd) && (pstat->current_rx_bytes > en_thd) ) { //50Mbps + priv->swq_en = 1; + priv->swqen_keeptime = priv->up_time; + } + else if ((priv->swq_en == 1) && ((pstat->tx_avarage < 4587520) || (pstat->rx_avarage < 4587520))) { //35Mbps + priv->swq_en = 0; + priv->swqen_keeptime = 0; + } + } + else { + priv->swq_en = 0; + priv->swqen_keeptime = 0; + } + } +#endif +#endif + +#ifdef WIFI_WMM +#ifdef LOW_TP_TXOP + if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + && QOS_ENABLE) { + if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) { + unsigned int thd_tp; + unsigned char under_thd; + unsigned int curr_tp; + + if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G)) + { + // Determine the upper bound throughput threshold. + if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G)) { + if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num) + thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; + else + thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n; + } + else + thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; + + // Determine to close txop. + curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17); + if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low) + under_thd = 1; + else + under_thd = 0; + } + else + { + under_thd = 0; + } + + if (switch_turbo) + { + priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; + priv->pshare->rf_ft_var.low_tp_txop_count = 0; + } + else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) { + priv->pshare->rf_ft_var.low_tp_txop_count++; + if (priv->pshare->rf_ft_var.low_tp_txop_close) { + priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay;; + } + if (priv->pshare->rf_ft_var.low_tp_txop_count ==priv->pshare->rf_ft_var.low_tp_txop_delay) + + { + priv->pshare->rf_ft_var.low_tp_txop_count = 0; + priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; + switch_turbo++; + } + } + else + { + priv->pshare->rf_ft_var.low_tp_txop_count = 0; + } + } + } +#endif + + if (switch_turbo) + ODM_IotEdcaSwitch( pDM_Odm, priv->pshare->iot_mode_enable ); +#endif +} +#endif + + +#if( DM_ODM_SUPPORT_TYPE == ODM_MP) +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + return TRUE; +} +#endif + +// need to ODM CE Platform +//move to here for ANT detection mechanism using + +#if ((DM_ODM_SUPPORT_TYPE == ODM_MP)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) +u4Byte +GetPSDData( + IN PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd) +{ + //unsigned int val, rfval; + //int psd_report; + u4Byte psd_report; + + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //Debug Message + //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord); + //DbgPrint("Reg908 = 0x%x\n",val); + //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord); + //rfval = PHY_QueryRFReg(Adapter, RF_PATH_A, 0x00, bRFRegOffsetMask); + //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval); + //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n", + //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval); + + //Set DCO frequency index, offset=(40MHz/SamplePts)*point + ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); + + //Start PSD calculation, Reg808[22]=0->1 + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); + //Need to wait for HW PSD report + ODM_StallExecution(30); + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); + //Read PSD report, Reg8B4[15:0] + psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; + +#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX)) + psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c); +#else + psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c); +#endif + + return psd_report; + +} + +u4Byte +ConvertTo_dB( + u4Byte Value) +{ + u1Byte i; + u1Byte j; + u4Byte dB; + + Value = Value & 0xFFFF; + + for (i=0;i<8;i++) + { + if (Value <= dB_Invert_Table[i][11]) + { + break; + } + } + + if (i >= 8) + { + return (96); // maximum 96 dB + } + + for (j=0;j<12;j++) + { + if (Value <= dB_Invert_Table[i][j]) + { + break; + } + } + + dB = i*12 + j + 1; + + return (dB); +} + +#endif + +// +// LukeLee: +// PSD function will be moved to FW in future IC, but now is only implemented in MP platform +// So PSD function will not be incorporated to common ODM +// +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +//#if(RTL8723_FPGA_VERIFICATION == 1) +//#define PSD_RESCAN 1 +//#else +//#define PSD_RESCAN 4 +//#endif +#define SCAN_INTERVAL 700 //ms +#define SYN_Length 5 // for 92D + +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define pw_th_10dB 0x0 +#define pw_th_16dB 0x3 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +#define Idle_Mode 0 +#define High_TP_Mode 1 +#define Low_TP_Mode 2 + + +VOID +odm_PSDMonitorInit( + IN PDM_ODM_T pDM_Odm) +{ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PSD Monitor Setting + //Which path in ADC/DAC is turnned on for PSD: both I/Q + ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3); + //Ageraged number: 8 + ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1); + pDM_Odm->bPSDinProcess = FALSE; + pDM_Odm->bUserAssignLevel = FALSE; + + //pDM_Odm->bDMInitialGainEnable=TRUE; //change the initialization to DIGinit + //Set Debug Port + //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803); + //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD + //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan + //PHY_SetBBReg(Adapter, 0xB38, bMaskByte1, 0x32); // PSDDelay + //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval + + //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms +#endif +} + +VOID +PatchDCTone( + IN PDM_ODM_T pDM_Odm, + pu4Byte PSD_report, + u1Byte initial_gain_psd +) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PADAPTER pAdapter; + + u4Byte psd_report; + + //2 Switch to CH11 to patch CH9 and CH13 DC tone + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, 11); + + if(pDM_Odm->SupportICType== ODM_RTL8192D) + { + if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, 11); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x25, 0xfffff, 0x643BC); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, 0xfffff, 0x77C1A); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2B, 0xfffff, 0x41289); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2C, 0xfffff, 0x01840); + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x25, 0xfffff, 0x643BC); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, 0xfffff, 0x77C1A); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2B, 0xfffff, 0x41289); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2C, 0xfffff, 0x01840); + } + } + + //Ch9 DC tone patch + psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd); + PSD_report[50] = psd_report; + //Ch13 DC tone patch + psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd); + PSD_report[70] = psd_report; + + //2 Switch to CH3 to patch CH1 and CH5 DC tone + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, 3); + + + if(pDM_Odm->SupportICType==ODM_RTL8192D) + { + if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, 3); + //PHY_SetRFReg(Adapter, RF_PATH_B, 0x25, 0xfffff, 0x643BC); + //PHY_SetRFReg(Adapter, RF_PATH_B, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, 0xfffff, 0x07C1A); + //PHY_SetRFReg(Adapter, RF_PATH_B, 0x2B, 0xfffff, 0x61289); + //PHY_SetRFReg(Adapter, RF_PATH_B, 0x2C, 0xfffff, 0x01C41); + } + else + { + //PHY_SetRFReg(Adapter, RF_PATH_A, 0x25, 0xfffff, 0x643BC); + //PHY_SetRFReg(Adapter, RF_PATH_A, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, 0xfffff, 0x07C1A); + //PHY_SetRFReg(Adapter, RF_PATH_A, 0x2B, 0xfffff, 0x61289); + //PHY_SetRFReg(Adapter, RF_PATH_A, 0x2C, 0xfffff, 0x01C41); + } + } + + //Ch1 DC tone patch + psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd); + PSD_report[10] = psd_report; + //Ch5 DC tone patch + psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd); + PSD_report[30] = psd_report; + +} + + +VOID +GoodChannelDecision( + PDM_ODM_T pDM_Odm, + ps4Byte PSD_report, + pu1Byte PSD_bitmap, + u1Byte RSSI_BT, + pu1Byte PSD_bitmap_memory) +{ + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + //s4Byte TH1 = SSBT-0x15; // modify TH by Neil Chen + s4Byte TH1= RSSI_BT+0x14; + s4Byte TH2 = RSSI_BT+85; + //u2Byte TH3; +// s4Byte RegB34; + u1Byte bitmap, Smooth_size[3], Smooth_TH[3]; + //u1Byte psd_bit; + u4Byte i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3]; + int start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ; + +// RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF; + + if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D)) + { + TH1 = RSSI_BT + 0x14; + } + + Smooth_size[0]=Smooth_Size_1; + Smooth_size[1]=Smooth_Size_2; + Smooth_size[2]=Smooth_Size_3; + Smooth_TH[0]=Smooth_TH_1; + Smooth_TH[1]=Smooth_TH_2; + Smooth_TH[2]=Smooth_TH_3; + Smooth_Interval[0]=16; + Smooth_Interval[1]=15; + Smooth_Interval[2]=13; + good_cnt = 0; + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + //2 Threshold + + if(RSSI_BT >=41) + TH1 = 113; + else if(RSSI_BT >=38) // >= -15dBm + TH1 = 105; //0x69 + else if((RSSI_BT >=33)&(RSSI_BT <38)) + TH1 = 99+(RSSI_BT-33); //0x63 + else if((RSSI_BT >=26)&(RSSI_BT<33)) + TH1 = 99-(33-RSSI_BT)+2; //0x5e + else if((RSSI_BT >=24)&(RSSI_BT<26)) + TH1 = 88-((RSSI_BT-24)*3); //0x58 + else if((RSSI_BT >=18)&(RSSI_BT<24)) + TH1 = 77+((RSSI_BT-18)*2); + else if((RSSI_BT >=14)&(RSSI_BT<18)) + TH1 = 63+((RSSI_BT-14)*2); + else if((RSSI_BT >=8)&(RSSI_BT<14)) + TH1 = 58+((RSSI_BT-8)*2); + else if((RSSI_BT >=3)&(RSSI_BT<8)) + TH1 = 52+(RSSI_BT-3); + else + TH1 = 51; + } + + for (i = 0; i< 10; i++) + PSD_bitmap[i] = 0; + + + // Add By Gary + for (i=0; i<80; i++) + pRX_HP_Table->PSD_bitmap_RXHP[i] = 0; + // End + + + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + TH1 =TH1-SIR_STEP_SIZE; + } + while (good_cnt < PSD_CHMIN) + { + good_cnt = 0; + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + if(TH1 ==TH2) + break; + if((TH1+SIR_STEP_SIZE) < TH2) + TH1 += SIR_STEP_SIZE; + else + TH1 = TH2; + } + else + { + if(TH1==(RSSI_BT+0x1E)) + break; + if((TH1+2) < (RSSI_BT+0x1E)) + TH1+=3; + else + TH1 = RSSI_BT+0x1E; + + } + ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1)); + + for (i = 0; i< 80; i++) + { + if(PSD_report[i] < TH1) + { + byte_idx = i / 8; + bit_idx = i -8*byte_idx; + bitmap = PSD_bitmap[byte_idx]; + PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx); + } + } + +#if DBG + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: before smoothing\n")); + for(n=0;n<10;n++) + { + //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]); + for (i = 0; i<8; i++) + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i)); + } +#endif + + //1 Start of smoothing function + + for (j=0;j<3;j++) + { + start_byte_idx=0; + start_bit_idx=0; + for(n=0; n 7 ) + { + start_byte_idx= start_byte_idx+start_bit_idx/8; + start_bit_idx = start_bit_idx%8; + } + } + + ODM_RT_TRACE( pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1)); + for(n=0;n<10;n++) + { + for (i = 0; i<8; i++) + { + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i)); + + if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1) //----- Add By Gary + { + pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1; + } // ------end by Gary + } + } + + } + + + good_cnt = 0; + for ( i = 0; i < 10; i++) + { + for (n = 0; n < 8; n++) + if((PSD_bitmap[i]& BIT(n)) != 0) + good_cnt++; + } + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: good channel cnt = %u",good_cnt)); + } + + //RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1)); + for (i = 0; i <10; i++) + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i])); +/* + //Update bitmap memory + for(i = 0; i < 80; i++) + { + byte_idx = i / 8; + bit_idx = i -8*byte_idx; + psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx; + bitmap = PSD_bitmap_memory[i]; + PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit; + } +*/ +} + + + +VOID +odm_PSD_Monitor( + PDM_ODM_T pDM_Odm +) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + + unsigned int pts, start_point, stop_point, initial_gain ; + static u1Byte PSD_bitmap_memory[80], init_memory = 0; + static u1Byte psd_cnt=0; + static u4Byte PSD_report[80], PSD_report_tmp; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u1Byte H2C_PSD_DATA[5]={0,0,0,0,0}; + static u1Byte H2C_PSD_DATA_last[5] ={0,0,0,0,0}; + u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125, + 0,3,6,10,13,16,19,22,26,29}; + u1Byte n, i, channel, BBReset,tone_idx; + u1Byte PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper; + s4Byte PSD_skip_start, PSD_skip_stop; + u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel; + u4Byte ReScan, Interval, Is40MHz; + u8Byte curTxOkCnt, curRxOkCnt; + int cur_byte_idx, cur_bit_idx; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + //--------------2G band synthesizer for 92D switch RF channel using----------------- + u1Byte group_idx=0; + u4Byte SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0; + u4Byte SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C}; // synthesizer RF register for 2G channel + u4Byte SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, // For CH1,2,4,9,10.11.12 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840} + {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, // For CH3,13,14 + {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}}; // For Ch5,6,7,8 + //--------------------- Add by Gary for Debug setting ---------------------- + s4Byte psd_result = 0; + u1Byte RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF); + u1Byte rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF); + //--------------------------------------------------------------------- + + if(*(pDM_Odm->pbScanInProcess)) + { + if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)) + { + //pHalData->bPSDactive=FALSE; + //ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ) + ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 900); //ms + //psd_cnt=0; + } + return; + } + + ReScan = PSD_RESCAN; + Interval = SCAN_INTERVAL; + + + //1 Initialization + if(init_memory == 0) + { + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Init memory\n")); + for(i = 0; i < 80; i++) + PSD_bitmap_memory[i] = 0xFF; // channel is always good + init_memory = 1; + } + if(psd_cnt == 0) + { + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n")); + for(i = 0; i < 80; i++) + PSD_report[i] = 0; + } +#if 0 //for test only + DbgPrint("cosa odm_PSD_Monitor call()\n"); + DbgPrint("cosa pHalData->RSSI_BT = %d\n", pHalData->RSSI_BT); + DbgPrint("cosa pHalData->bUserAssignLevel = %d\n", pHalData->bUserAssignLevel); +#if 0 + psd_cnt++; + if (psd_cnt < ReScan) + PlatformSetTimer( Adapter, &pHalData->PSDTimer, Interval); //ms + else + psd_cnt = 0; + return; +#endif +#endif + //1 Backup Current Settings + CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); +/* + if(pDM_Odm->SupportICType==ODM_RTL8192D) + { + //2 Record Current synthesizer parameters based on current channel + if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY)) + { + SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord); + } + else // DualMAC_DualPHY 2G + { + SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord); + } + } +*/ + //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord); + RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord); + + //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28; + RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28; + + //2??? + Is40MHz = pMgntInfo->pHTInfo->bCurBW40MHz; + + ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n")); + //1 Turn off CCK + //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0); + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); + //1 Turn off TX + //Pause TX Queue + //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF); + ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF); + + //Force RX to stop TX immediately + //PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); + + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); + //1 Turn off RX + //Rx AGC off RegC70[0]=0, RegC7C[20]=0 + //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0); + //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0); + + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0); + + + //Turn off CCA + //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0); + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); + + //BB Reset + //BBReset = PlatformEFIORead1Byte(Adapter, 0x02); + BBReset = ODM_Read1Byte(pDM_Odm, 0x02); + + //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0)); + //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0); + + ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0)); + ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0); + + //1 Leave RX idle low power + //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0); + + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); + //1 Fix initial gain + //if (IS_HARDWARE_TYPE_8723AE(Adapter)) + //RSSI_BT = pHalData->RSSI_BT; + //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary + // RSSI_BT = RSSI_BT_new; + + if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)) + RSSI_BT=pDM_Odm->RSSI_BT; //need to check C2H to pDM_Odm RSSI BT + + else if((pDM_Odm->SupportICType==ODM_RTL8192C)||(pDM_Odm->SupportICType==ODM_RTL8192D)) + RSSI_BT = RSSI_BT_new; + + + + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + //Neil add--2011--10--12 + //2 Initial Gain index + if(RSSI_BT >=35) // >= -15dBm + initial_gain_psd = RSSI_BT*2; + else if((RSSI_BT >=33)&(RSSI_BT<35)) + initial_gain_psd = RSSI_BT*2+6; + else if((RSSI_BT >=24)&(RSSI_BT<33)) + initial_gain_psd = 70-(31-RSSI_BT); + else if((RSSI_BT >=19)&(RSSI_BT<24)) + initial_gain_psd = 64-((24-RSSI_BT)*4); + else if((RSSI_BT >=14)&(RSSI_BT<19)) + initial_gain_psd = 44-((18-RSSI_BT)*2); + else if((RSSI_BT >=8)&(RSSI_BT<14)) + initial_gain_psd = 35-(14-RSSI_BT); + else + initial_gain_psd = 0x1B; + } + else + { + if(rssi_ctrl == 1) // just for debug!! + initial_gain_psd = RSSI_BT_new ; + else + { + //need to do + initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI + } + } + //if(RSSI_BT<0x17) + // RSSI_BT +=3; + //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT); + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + //initialGainUpper = 0x5E; //Modify by neil chen + + if(pDM_Odm->bUserAssignLevel) + { + pDM_Odm->bUserAssignLevel = FALSE; + initialGainUpper = 0x7f; + } + else + { + initialGainUpper = 0x5E; + } + + /* + if (initial_gain_psd < 0x1a) + initial_gain_psd = 0x1a; + if (initial_gain_psd > initialGainUpper) + initial_gain_psd = initialGainUpper; + */ + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + SSBT = RSSI_BT * 2 +0x3E; + else if((pDM_Odm->SupportICType==ODM_RTL8192C)||(pDM_Odm->SupportICType==ODM_RTL8192D)) + { + RSSI_BT = initial_gain_psd; + SSBT = RSSI_BT; + } + + //if(IS_HARDWARE_TYPE_8723AE(Adapter)) + // SSBT = RSSI_BT * 2 +0x3E; + //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary + //{ + // RSSI_BT = initial_gain_psd; + // SSBT = RSSI_BT; + //} + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT)); + ODM_RT_TRACE( pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd)); + //DbgPrint("PSD: SSBT= %d", SSBT); + //need to do + //pMgntInfo->bDMInitialGainEnable = FALSE; + pDM_Odm->bDMInitialGainEnable = FALSE; + initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F; + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); + //1 Turn off 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF); + + //pts value = 128, 256, 512, 1024 + pts = 128; + + if(pts == 128) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); + start_point = 64; + stop_point = 192; + } + else if(pts == 256) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1); + start_point = 128; + stop_point = 384; + } + else if(pts == 512) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2); + start_point = 256; + stop_point = 768; + } + else + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3); + start_point = 512; + stop_point = 1536; + } + + +//3 Skip WLAN channels if WLAN busy + + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + PSD_skip_start=80; + PSD_skip_stop = 0; + wlan_channel = CurrentChannel & 0x0f; + + ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz)); + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtHsOperation) + { + if(pDM_Odm->bLinked) + { + if(Is40MHz) + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; + } + else + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; + } + } + else + { + // mask for 40MHz + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; + } + if(PSD_skip_start < 0) + PSD_skip_start = 0; + if(PSD_skip_stop >80) + PSD_skip_stop = 80; + } + else +#endif + { + if((curRxOkCnt+curTxOkCnt) > 5) + { + if(Is40MHz) + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; + } + else + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; + } + + if(PSD_skip_start < 0) + PSD_skip_start = 0; + if(PSD_skip_stop >80) + PSD_skip_stop = 80; + } + } + } + else + { + if((curRxOkCnt+curTxOkCnt) > 1000) + { + PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10; + PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20; + } + } + + ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop)); + + for (n=0;n<80;n++) + { + if((n%20)==0) + { + channel = (n/20)*4 + 1; + /* + if(pDM_Odm->SupportICType==ODM_RTL8192D) + { + switch(channel) + { + case 1: + case 9: + group_idx = 0; + break; + case 5: + group_idx = 2; + break; + case 13: + group_idx = 1; + break; + } + + if((pHalData->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)) + { + for(i = 0; i < SYN_Length; i++) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]); + + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, channel); + } + else // DualMAC_DualPHY 2G + { + for(i = 0; i < SYN_Length; i++) + ODM_SetRFReg(pDM_Odm, RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]); + + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + } + else */ + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + tone_idx = n%20; + if ((n>=PSD_skip_start) && (n PSD_report[n]) + PSD_report[n] = PSD_report_tmp; + + } + } + + PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd); + + //----end + //1 Turn on RX + //Rx AGC on + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1); + //CCK on + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); + //1 Turn on TX + //Resume TX Queue + + ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00); + //Turn on 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0); + //1 Restore Current Settings + //Resume DIG + pDM_Odm->bDMInitialGainEnable = TRUE; + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain); + // restore originl center frequency + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); + + /* + if(pDM_Odm->SupportICType==ODM_RTL8192D) + { + if((pHalData->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)) + { + PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel); + PHY_SetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord, SYN_RF25); + PHY_SetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord, SYN_RF26); + PHY_SetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord, SYN_RF27); + PHY_SetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B); + PHY_SetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C); + } + else // DualMAC_DualPHY + { + PHY_SetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord, SYN_RF25); + PHY_SetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord, SYN_RF26); + PHY_SetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord, SYN_RF27); + PHY_SetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B); + PHY_SetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C); + } + }*/ + //Turn on CCA + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI); + //Restore RX idle low power + if(RxIdleLowPwr == TRUE) + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1); + + psd_cnt++; + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt)); + if (psd_cnt < ReScan) + ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval); + else + { + psd_cnt = 0; + for(i=0;i<80;i++) + //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]); + RT_TRACE( COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i])); + + + GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory); + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + cur_byte_idx=0; + cur_bit_idx=0; + + //2 Restore H2C PSD Data to Last Data + H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0]; + H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1]; + H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2]; + H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3]; + H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4]; + + + //2 Translate 80bit channel map to 40bit channel + for ( i=0;i<5;i++) + { + for(n=0;n<8;n++) + { + cur_byte_idx = i*2 + n/4; + cur_bit_idx = (n%4)*2; + if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0)) + H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n); + } + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i])); + } + + //3 To Compare the difference + for ( i=0;i<5;i++) + { + if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i]) + { + FillH2CCmd(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA); + ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n")); + break; + } + else + { + if(i==5) + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Not need to Update\n")); + } + } + //pHalData->bPSDactive=FALSE; + ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 900); + ODM_RT_TRACE( pDM_Odm,COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n")); + } + } +} +/* +//Neil for Get BT RSSI +// Be Triggered by BT C2H CMD +VOID +ODM_PSDGetRSSI( + IN u1Byte RSSI_BT) +{ + + +} + +*/ + +VOID +ODM_PSDMonitor( + IN PDM_ODM_T pDM_Odm + ) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + //if(IS_HARDWARE_TYPE_8723AE(Adapter)) + + if(pDM_Odm->SupportICType == ODM_RTL8723A) //may need to add other IC type + { + if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE) + { +#if(BT_30_SUPPORT == 1) + if(pDM_Odm->bBtDisabled) //need to check upper layer connection + { + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n")); + return; + } +#endif + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n")); + //if(pHalData->bPSDactive ==FALSE) + //{ + pDM_Odm->bPSDinProcess = TRUE; + //pHalData->bPSDactive=TRUE; + odm_PSD_Monitor(pDM_Odm); + pDM_Odm->bPSDinProcess = FALSE; + } + } + +} +VOID +odm_PSDMonitorCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + +#if USE_WORKITEM + PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem); +#else + ODM_PSDMonitor(pDM_Odm); +#endif +} + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + + ODM_PSDMonitor(pDM_Odm); +} + + + + //cosa debug tool need to modify + +VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ) +{ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi)); + if(mode) + { + pDM_Odm->RSSI_BT = (u1Byte)btRssi; + pDM_Odm->bUserAssignLevel = TRUE; + ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms + } + else + { + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer); + } +#endif +} + + +//#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) + +void odm_RXHPInit( + IN PDM_ODM_T pDM_Odm) +{ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + u1Byte index; + + pRX_HP_Table->RXHP_enable = TRUE; + pRX_HP_Table->RXHP_flag = 0; + pRX_HP_Table->PSD_func_trigger = 0; + pRX_HP_Table->Pre_IGI = 0x20; + pRX_HP_Table->Cur_IGI = 0x20; + pRX_HP_Table->Cur_pw_th = pw_th_10dB; + pRX_HP_Table->Pre_pw_th = pw_th_10dB; + for(index=0; index<80; index++) + pRX_HP_Table->PSD_bitmap_RXHP[index] = 1; + +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + pRX_HP_Table->TP_Mode = Idle_Mode; +#endif +#endif +} + +void odm_RXHP( + IN PDM_ODM_T pDM_Odm) +{ +#if( DM_ODM_SUPPORT_TYPE & (ODM_MP)) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); + + u1Byte i, j, sum; + u1Byte Is40MHz; + s1Byte Intf_diff_idx, MIN_Intf_diff_idx = 16; + s4Byte cur_channel; + u1Byte ch_map_intf_5M[17] = {0}; + static u4Byte FA_TH = 0; + static u1Byte psd_intf_flag = 0; + static s4Byte curRssi = 0; + static s4Byte preRssi = 0; + static u1Byte PSDTriggerCnt = 1; + + u1Byte RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31); // for debug!! + +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + static s8Byte lastTxOkCnt = 0, lastRxOkCnt = 0; + s8Byte curTxOkCnt, curRxOkCnt; + s8Byte curTPOkCnt; + s8Byte TP_Acc3, TP_Acc5; + static s8Byte TP_Buff[5] = {0}; + static u1Byte pre_state = 0, pre_state_flag = 0; + static u1Byte Intf_HighTP_flag = 0, De_counter = 16; + static u1Byte TP_Degrade_flag = 0; +#endif + static u1Byte LatchCnt = 0; + + if((pDM_Odm->SupportICType == ODM_RTL8723A)||(pDM_Odm->SupportICType == ODM_RTL8188E)) + return; + //AGC RX High Power Mode is only applied on 2G band in 92D!!! + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G) + return; + } + + if(!(pDM_Odm->SupportAbility==ODM_BB_RXHP)) + return; + + + //RX HP ON/OFF + if(RX_HP_enable == 1) + pRX_HP_Table->RXHP_enable = FALSE; + else + pRX_HP_Table->RXHP_enable = TRUE; + + if(pRX_HP_Table->RXHP_enable == FALSE) + { + if(pRX_HP_Table->RXHP_flag == 1) + { + pRX_HP_Table->RXHP_flag = 0; + psd_intf_flag = 0; + } + return; + } + +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + //2 Record current TP for USB interface + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + curTPOkCnt = curTxOkCnt+curRxOkCnt; + TP_Buff[0] = curTPOkCnt; // current TP + TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3); + TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5); + + if(TP_Acc5 < 1000) + pRX_HP_Table->TP_Mode = Idle_Mode; + else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000)) + pRX_HP_Table->TP_Mode = Low_TP_Mode; + else + pRX_HP_Table->TP_Mode = High_TP_Mode; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode)); + // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing. + // When LatchCnt = 0, we would Get PSD result. + if(TP_Degrade_flag == 1) + { + LatchCnt--; + if(LatchCnt == 0) + { + TP_Degrade_flag = 0; + } + } + // When PSD function triggered by TP degrade 20%, and Interference Flag = 1 + // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down. + if(Intf_HighTP_flag == 1) + { + De_counter--; + if(De_counter == 0) + { + Intf_HighTP_flag = 0; + psd_intf_flag = 0; + } + } +#endif + + //2 AGC RX High Power Mode by PSD only applied to STA Mode + //3 NOT applied 1. Ad Hoc Mode. + //3 NOT applied 2. AP Mode + if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter))) + { + Is40MHz = *(pDM_Odm->pBandWidth); + curRssi = pDM_Odm->RSSI_Min; + cur_channel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz)); + //2 PSD function would be triggered + //3 1. Every 4 sec for PCIE + //3 2. Before TP Mode (Idle TP<4kbps) for USB + //3 3. After TP Mode (High TP) for USB + if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0)) // Only RSSI>TH and RX_HP_flag=0 will Do PSD process + { +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + //2 Before TP Mode ==> PSD would be trigger every 4 sec + if(pRX_HP_Table->TP_Mode == Idle_Mode) //2.1 less wlan traffic <4kbps + { +#endif + if(PSDTriggerCnt == 1) + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + PSDTriggerCnt = 0; + } + else + { + PSDTriggerCnt++; + } +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + } + //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function + if(pRX_HP_Table->TP_Mode == High_TP_Mode) + { + if((pre_state_flag == 0)&&(LatchCnt == 0)) + { + // TP var < 5% + if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3))) + { + pre_state++; + if(pre_state == 3) // hit pre_state condition => consecutive 3 times + { + pre_state_flag = 1; + pre_state = 0; + } + + } + else + { + pre_state = 0; + } + } + //3 If pre_state_flag=1 ==> start to monitor TP degrade 20% + if(pre_state_flag == 1) + { + if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3)) // degrade 20% + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + TP_Degrade_flag = 1; + LatchCnt = 2; + pre_state_flag = 0; + } + else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2]) + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + TP_Degrade_flag = 1; + LatchCnt = 2; + pre_state_flag = 0; + } + else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3]) + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + TP_Degrade_flag = 1; + LatchCnt = 2; + pre_state_flag = 0; + } + } + } +#endif +} + +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + for (i=0;i<4;i++) + { + TP_Buff[4-i] = TP_Buff[3-i]; + } +#endif + //2 Update PSD bitmap according to PSD report + if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0)) + { + //2 Separate 80M bandwidth into 16 group with smaller 5M BW. + for (i = 0 ; i < 16 ; i++) + { + sum = 0; + for(j = 0; j < 5 ; j++) + sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j]; + + if(sum < 5) + { + ch_map_intf_5M[i] = 1; // interference flag + } + } + //=============just for debug========================= + //for(i=0;i<16;i++) + //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]); + //=============================================== + //2 Mask target channel 5M index + for(i = 0; i < (4+4*Is40MHz) ; i++) + { + ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0; + } + + psd_intf_flag = 0; + for(i = 0; i < 16; i++) + { + if(ch_map_intf_5M[i] == 1) + { + psd_intf_flag = 1; // interference is detected!!! + break; + } + } + +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + if(pRX_HP_Table->TP_Mode!=Idle_Mode) + { + if(psd_intf_flag == 1) // to avoid psd_intf_flag always 1 + { + Intf_HighTP_flag = 1; + De_counter = 32; // 0x1E -> 0x3E needs 32 times by each IGI step =1 + } + } +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag)); + //2 Distance between target channel and interference + for(i = 0; i < 16; i++) + { + if(ch_map_intf_5M[i] == 1) + { + Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz)); + if(Intf_diff_idx < MIN_Intf_diff_idx) + MIN_Intf_diff_idx = Intf_diff_idx; // the min difference index between interference and target + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx)); + //2 Choose False Alarm Threshold + switch (MIN_Intf_diff_idx){ + case 0: + case 1: + case 2: + case 3: + FA_TH = FA_RXHP_TH1; + break; + case 4: // CH5 + case 5: // CH6 + FA_TH = FA_RXHP_TH2; + break; + case 6: // CH7 + case 7: // CH8 + FA_TH = FA_RXHP_TH3; + break; + case 8: // CH9 + case 9: //CH10 + FA_TH = FA_RXHP_TH4; + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + FA_TH = FA_RXHP_TH5; + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH)); + pRX_HP_Table->PSD_func_trigger = 0; + } + //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode + if(pRX_HP_Table->RXHP_flag == 1) + { + if ((curRssi > 80)&&(preRssi < 80)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1; + } + else if ((curRssi < 80)&&(preRssi > 80)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; + } + else if ((curRssi > 72)&&(preRssi < 72)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; + } + else if ((curRssi < 72)&&( preRssi > 72)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3; + } + else if (curRssi < 68) //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode + { + pRX_HP_Table->Cur_pw_th = pw_th_10dB; + pRX_HP_Table->RXHP_flag = 0; // Back to Normal DIG Mode + psd_intf_flag = 0; + } + } + else // pRX_HP_Table->RXHP_flag == 0 + { + //1 Decide whether to enter AGC RX High Power Mode + if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) && + (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max)) + { + if (curRssi > 80) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1; + } + else if (curRssi > 72) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; + } + else + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3; + } + pRX_HP_Table->Cur_pw_th = pw_th_16dB; //RegC54[9:8]=2'b11: to enter AGC Flow 3 + pRX_HP_Table->First_time_enter = TRUE; + pRX_HP_Table->RXHP_flag = 1; // RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode + } + } + preRssi = curRssi; + odm_Write_RXHP(pDM_Odm); + } +#endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_MP)) +#endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE) +} + +void odm_Write_RXHP( + IN PDM_ODM_T pDM_Odm) +{ + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + u4Byte currentIGI; + + if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI) + { + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + } + + if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th) +{ + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th); // RegC54[9:8]=2'b11: AGC Flow 3 + } + + if(pRX_HP_Table->RXHP_flag == 0) + { + pRX_HP_Table->Cur_IGI = 0x20; + } + else + { + currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); + if(currentIGI<0x50) + { + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + } + } + pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI; + pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th; + +} + +VOID +odm_PSD_RXHP( + IN PDM_ODM_T pDM_Odm +) +{ + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + unsigned int pts, start_point, stop_point, initial_gain ; + static u1Byte PSD_bitmap_memory[80], init_memory = 0; + static u1Byte psd_cnt=0; + static u4Byte PSD_report[80], PSD_report_tmp; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125, + 0,3,6,10,13,16,19,22,26,29}; + u1Byte n, i, channel, BBReset,tone_idx; + u1Byte PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper; + s4Byte PSD_skip_start, PSD_skip_stop; + u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel; + u4Byte ReScan, Interval, Is40MHz; + u8Byte curTxOkCnt, curRxOkCnt; + //--------------2G band synthesizer for 92D switch RF channel using----------------- + u1Byte group_idx=0; + u4Byte SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0; + u4Byte SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C}; // synthesizer RF register for 2G channel + u4Byte SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, // For CH1,2,4,9,10.11.12 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840} + {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, // For CH3,13,14 + {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}}; // For Ch5,6,7,8 + //--------------------- Add by Gary for Debug setting ---------------------- + s4Byte psd_result = 0; + u1Byte RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF); + u1Byte rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF); + //--------------------------------------------------------------------- + + if(pMgntInfo->bScanInProgress) + { + return; + } + + ReScan = PSD_RESCAN; + Interval = SCAN_INTERVAL; + + + //1 Initialization + if(init_memory == 0) + { + RT_TRACE( COMP_PSD, DBG_LOUD,("Init memory\n")); + for(i = 0; i < 80; i++) + PSD_bitmap_memory[i] = 0xFF; // channel is always good + init_memory = 1; + } + if(psd_cnt == 0) + { + RT_TRACE(COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n")); + for(i = 0; i < 80; i++) + PSD_report[i] = 0; + } + + //1 Backup Current Settings + CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + //2 Record Current synthesizer parameters based on current channel + if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) + { + SYN_RF25 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x2C, bMaskDWord); + } + else // DualMAC_DualPHY 2G + { + SYN_RF25 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x2C, bMaskDWord); + } + } + RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord); + RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28; + Is40MHz = *(pDM_Odm->pBandWidth); + ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n")); + //1 Turn off CCK + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); + //1 Turn off TX + //Pause TX Queue + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); + //Force RX to stop TX immediately + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); + //1 Turn off RX + //Rx AGC off RegC70[0]=0, RegC7C[20]=0 + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0); + //Turn off CCA + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); + //BB Reset + BBReset = ODM_Read1Byte(pDM_Odm, 0x02); + ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0)); + ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0); + //1 Leave RX idle low power + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); + //1 Fix initial gain + RSSI_BT = RSSI_BT_new; + RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + if(rssi_ctrl == 1) // just for debug!! + initial_gain_psd = RSSI_BT_new; + else + initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI + + RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + initialGainUpper = 0x54; + + RSSI_BT = initial_gain_psd; + //SSBT = RSSI_BT; + + //RT_TRACE( COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT)); + RT_TRACE( COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd)); + + pDM_Odm->bDMInitialGainEnable = FALSE; + initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F; + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); + //1 Turn off 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF); + + //pts value = 128, 256, 512, 1024 + pts = 128; + + if(pts == 128) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); + start_point = 64; + stop_point = 192; + } + else if(pts == 256) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1); + start_point = 128; + stop_point = 384; + } + else if(pts == 512) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2); + start_point = 256; + stop_point = 768; + } + else + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3); + start_point = 512; + stop_point = 1536; + } + + +//3 Skip WLAN channels if WLAN busy + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + PSD_skip_start=80; + PSD_skip_stop = 0; + wlan_channel = CurrentChannel & 0x0f; + + RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz)); + + if((curRxOkCnt+curTxOkCnt) > 1000) + { + PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10; + PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20; + } + + RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop)); + + for (n=0;n<80;n++) + { + if((n%20)==0) + { + channel = (n/20)*4 + 1; + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + switch(channel) + { + case 1: + case 9: + group_idx = 0; + break; + case 5: + group_idx = 2; + break; + case 13: + group_idx = 1; + break; + } + if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) + { + for(i = 0; i < SYN_Length; i++) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]); + + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, channel); + } + else // DualMAC_DualPHY 2G + { + for(i = 0; i < SYN_Length; i++) + ODM_SetRFReg(pDM_Odm, RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]); + + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + } + else + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + tone_idx = n%20; + if ((n>=PSD_skip_start) && (n PSD_report[n]) + PSD_report[n] = PSD_report_tmp; + + } + } + + PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd); + + //----end + //1 Turn on RX + //Rx AGC on + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1); + //CCK on + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); + //1 Turn on TX + //Resume TX Queue + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + //Turn on 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0); + //1 Restore Current Settings + //Resume DIG + pDM_Odm->bDMInitialGainEnable= TRUE; + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain); + // restore originl center frequency + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x25, bMaskDWord, SYN_RF25); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x26, bMaskDWord, SYN_RF26); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, bMaskDWord, SYN_RF27); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C); + } + else // DualMAC_DualPHY + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x25, bMaskDWord, SYN_RF25); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x26, bMaskDWord, SYN_RF26); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, bMaskDWord, SYN_RF27); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C); + } + } + //Turn on CCA + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI); + //Restore RX idle low power + if(RxIdleLowPwr == TRUE) + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1); + + psd_cnt++; + //gPrint("psd cnt=%d\n", psd_cnt); + ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt)); + if (psd_cnt < ReScan) + { + ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval); //ms + } + else + { + psd_cnt = 0; + for(i=0;i<80;i++) + RT_TRACE( COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i])); + //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]); + + GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory); + + } + } + +VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem); + #else + odm_PSD_RXHP(pDM_Odm); + #endif +#else + ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem); +#endif + + } + +VOID +odm_PSD_RXHPWorkitemCallback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + odm_PSD_RXHP(pDM_Odm); +} + +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +// +// 2011/09/22 MH Add for 92D global spin lock utilization. +// +VOID +odm_GlobalAdapterCheck( + IN VOID + ) +{ + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + + //sherry delete flag 20110517 +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + ACQUIRE_GLOBAL_SPINLOCK(&GlobalSpinlockForGlobalAdapterList); +#else + ACQUIRE_GLOBAL_MUTEX(GlobalMutexForGlobalAdapterList); +#endif + +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + RELEASE_GLOBAL_SPINLOCK(&GlobalSpinlockForGlobalAdapterList); +#else + RELEASE_GLOBAL_MUTEX(GlobalMutexForGlobalAdapterList); +#endif + +#endif + +} // odm_GlobalAdapterCheck + + + +// +// 2011/12/02 MH Copy from MP oursrc for temporarily test. +// +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID +odm_OFDMTXPathDiversity_92C( + IN PADAPTER Adapter) +{ +// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_WLAN_STA pEntry; + u1Byte i, DefaultRespPath = 0; + s4Byte MinRSSI = 0xFF; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + pDM_PDTable->OFDMTXPath = 0; + + //1 Default Port + if(pMgntInfo->mAssoc) + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port RSSI[0]=%d, RSSI[1]=%d\n", + Adapter->RxStats.RxRSSIPercentage[0], Adapter->RxStats.RxRSSIPercentage[1])); + if(Adapter->RxStats.RxRSSIPercentage[0] > Adapter->RxStats.RxRSSIPercentage[1]) + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & (~BIT0); + MinRSSI = Adapter->RxStats.RxRSSIPercentage[1]; + DefaultRespPath = 0; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-0\n")); + } + else + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT0; + MinRSSI = Adapter->RxStats.RxRSSIPercentage[0]; + DefaultRespPath = 1; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-1\n")); + } + //RT_TRACE( COMP_SWAS, DBG_LOUD, ("pDM_PDTable->OFDMTXPath =0x%x\n",pDM_PDTable->OFDMTXPath)); + } + //1 Extension Port + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d, RSSI_0=%d, RSSI_1=%d\n", + pEntry->AID+1, pEntry->rssi_stat.RxRSSIPercentage[0], pEntry->rssi_stat.RxRSSIPercentage[1])); + + if(pEntry->rssi_stat.RxRSSIPercentage[0] > pEntry->rssi_stat.RxRSSIPercentage[1]) + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & ~(BIT(pEntry->AID+1)); + //pHalData->TXPath = pHalData->TXPath & ~(1<<(pEntry->AID+1)); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-0\n", pEntry->AID+1)); + if(pEntry->rssi_stat.RxRSSIPercentage[1] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[1]; + DefaultRespPath = 0; + } + } + else + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT(pEntry->AID+1); + //pHalData->TXPath = pHalData->TXPath | (1 << (pEntry->AID+1)); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-1\n", pEntry->AID+1)); + if(pEntry->rssi_stat.RxRSSIPercentage[0] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[0]; + DefaultRespPath = 1; + } + } + } + } + else + { + break; + } + } + + pDM_PDTable->OFDMDefaultRespPath = DefaultRespPath; +} + + +BOOLEAN +odm_IsConnected_92C( + IN PADAPTER Adapter +) +{ + PRT_WLAN_STA pEntry; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + u4Byte i; + BOOLEAN bConnected=FALSE; + + if(pMgntInfo->mAssoc) + { + bConnected = TRUE; + } + else + { + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + bConnected = TRUE; + break; + } + } + else + { + break; + } + } + } + return bConnected; +} + + +VOID +odm_ResetPathDiversity_92C( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + PRT_WLAN_STA pEntry; + u4Byte i; + + pHalData->RSSI_test = FALSE; + pDM_PDTable->CCK_Pkt_Cnt = 0; + pDM_PDTable->OFDM_Pkt_Cnt = 0; + pHalData->CCK_Pkt_Cnt =0; + pHalData->OFDM_Pkt_Cnt =0; + + if(pDM_PDTable->CCKPathDivEnable == TRUE) + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); //RX path = PathAB + + for(i=0; i<2; i++) + { + pDM_PDTable->RSSI_CCK_Path_cnt[i]=0; + pDM_PDTable->RSSI_CCK_Path[i] = 0; + } + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + pEntry->rssi_stat.CCK_Pkt_Cnt = 0; + pEntry->rssi_stat.OFDM_Pkt_Cnt = 0; + for(i=0; i<2; i++) + { + pEntry->rssi_stat.RSSI_CCK_Path_cnt[i] = 0; + pEntry->rssi_stat.RSSI_CCK_Path[i] = 0; + } + } + else + break; + } +} + + +VOID +odm_CCKTXPathDiversity_92C( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_WLAN_STA pEntry; + s4Byte MinRSSI = 0xFF; + u1Byte i, DefaultRespPath = 0; +// BOOLEAN bBModePathDiv = FALSE; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + + //1 Default Port + if(pMgntInfo->mAssoc) + { + if(pHalData->OFDM_Pkt_Cnt == 0) + { + for(i=0; i<2; i++) + { + if(pDM_PDTable->RSSI_CCK_Path_cnt[i] > 1) //Because the first packet is discarded + pDM_PDTable->RSSI_CCK_Path[i] = pDM_PDTable->RSSI_CCK_Path[i] / (pDM_PDTable->RSSI_CCK_Path_cnt[i]-1); + else + pDM_PDTable->RSSI_CCK_Path[i] = 0; + } + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path[0]=%d, pDM_PDTable->RSSI_CCK_Path[1]=%d\n", + pDM_PDTable->RSSI_CCK_Path[0], pDM_PDTable->RSSI_CCK_Path[1])); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path_cnt[0]=%d, pDM_PDTable->RSSI_CCK_Path_cnt[1]=%d\n", + pDM_PDTable->RSSI_CCK_Path_cnt[0], pDM_PDTable->RSSI_CCK_Path_cnt[1])); + + if(pDM_PDTable->RSSI_CCK_Path[0] > pDM_PDTable->RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0); + MinRSSI = pDM_PDTable->RSSI_CCK_Path[1]; + DefaultRespPath = 0; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n")); + } + else if(pDM_PDTable->RSSI_CCK_Path[0] < pDM_PDTable->RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT0; + MinRSSI = pDM_PDTable->RSSI_CCK_Path[0]; + DefaultRespPath = 1; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-1\n")); + } + else + { + if((pDM_PDTable->RSSI_CCK_Path[0] != 0) && (pDM_PDTable->RSSI_CCK_Path[0] < MinRSSI)) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n")); + MinRSSI = pDM_PDTable->RSSI_CCK_Path[1]; + DefaultRespPath = 0; + } + else + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port unchange CCK Path\n")); + } + } + } + else //Follow OFDM decision + { + pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~BIT0)) | (pDM_PDTable->OFDMTXPath &BIT0); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, Default port Select CCK Path-%d\n", + pDM_PDTable->CCKTXPath &BIT0)); + } + } + //1 Extension Port + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + if(pEntry->rssi_stat.OFDM_Pkt_Cnt == 0) + { + for(i=0; i<2; i++) + { + if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[i] > 1) + pEntry->rssi_stat.RSSI_CCK_Path[i] = pEntry->rssi_stat.RSSI_CCK_Path[i] / (pEntry->rssi_stat.RSSI_CCK_Path_cnt[i]-1); + else + pEntry->rssi_stat.RSSI_CCK_Path[i] = 0; + } + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d, RSSI_CCK0=%d, RSSI_CCK1=%d\n", + pEntry->AID+1, pEntry->rssi_stat.RSSI_CCK_Path[0], pEntry->rssi_stat.RSSI_CCK_Path[1])); + + if(pEntry->rssi_stat.RSSI_CCK_Path[0] >pEntry->rssi_stat.RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AID+1)); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AID+1)); + if(pEntry->rssi_stat.RSSI_CCK_Path[1] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1]; + DefaultRespPath = 0; + } + } + else if(pEntry->rssi_stat.RSSI_CCK_Path[0] rssi_stat.RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT(pEntry->AID+1); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-1\n", pEntry->AID+1)); + if(pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[0]; + DefaultRespPath = 1; + } + } + else + { + if((pEntry->rssi_stat.RSSI_CCK_Path[0] != 0) && (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI)) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AID+1)); + MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1]; + DefaultRespPath = 0; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AID+1)); + } + else + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d unchange CCK Path\n", pEntry->AID+1)); + } + } + } + else //Follow OFDM decision + { + pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~(BIT(pEntry->AID+1)))) | (pDM_PDTable->OFDMTXPath & BIT(pEntry->AID+1)); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, MACID=%d Select CCK Path-%d\n", + pEntry->AID+1, (pDM_PDTable->CCKTXPath & BIT(pEntry->AID+1))>>(pEntry->AID+1))); + } + } + } + else + { + break; + } + } + + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C:MinRSSI=%d\n",MinRSSI)); + + if(MinRSSI == 0xFF) + DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; + + pDM_PDTable->CCKDefaultRespPath = DefaultRespPath; +} + + + +VOID +odm_PathDiversityAfterLink_92C( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + u1Byte DefaultRespPath=0; + + if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff)) + { + if(pHalData->PathDivCfg == 0) + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("No ODM_TXPathDiversity()\n")); + } + else + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("2T ODM_TXPathDiversity()\n")); + } + return; + } + if(!odm_IsConnected_92C(Adapter)) + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n")); + return; + } + + + if(pDM_PDTable->TrainingState == 0) + { + RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n")); + odm_OFDMTXPathDiversity_92C(Adapter); + + if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100)) + { + //RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n")); + + if(pDM_PDTable->CCK_Pkt_Cnt > 300) + pDM_PDTable->Timer = 20; + else if(pDM_PDTable->CCK_Pkt_Cnt > 100) + pDM_PDTable->Timer = 60; + else + pDM_PDTable->Timer = 250; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer)); + + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // RX path = PathA + pDM_PDTable->TrainingState = 1; + pHalData->RSSI_test = TRUE; + ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms + } + else + { + pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath; + DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n")); + odm_SetRespPath_92C(Adapter, DefaultRespPath); + odm_ResetPathDiversity_92C(Adapter); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); + } + } + else if(pDM_PDTable->TrainingState == 1) + { + //RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n")); + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // RX path = PathB + pDM_PDTable->TrainingState = 2; + ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms + } + else + { + //RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n")); + pDM_PDTable->TrainingState = 0; + odm_CCKTXPathDiversity_92C(Adapter); + if(pDM_PDTable->OFDM_Pkt_Cnt != 0) + { + DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n")); + } + else + { + DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n")); + } + odm_SetRespPath_92C(Adapter, DefaultRespPath); + odm_ResetPathDiversity_92C(Adapter); + RT_TRACE( COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); + } + +} + + + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer +) +{ +#if USE_WORKITEM + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; +#endif + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem); +#else + odm_PathDiversityAfterLink_92C(Adapter); +#endif +#else + PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem); +#endif + +} + + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + + odm_CCKTXPathDiversity_92C(Adapter); +} + + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bCount = FALSE; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + //BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE_92C(pDesc); +#if DEV_BUS_TYPE != RT_SDIO_INTERFACE + BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE(Adapter, pDesc); +#else //below code would be removed if we have verified SDIO + BOOLEAN isCCKrate = IS_HARDWARE_TYPE_8188E(Adapter) ? RX_HAL_IS_CCK_RATE_88E(pDesc) : RX_HAL_IS_CCK_RATE_92C(pDesc); +#endif + + if((pHalData->PathDivCfg != 1) || (pHalData->RSSI_test == FALSE)) + return; + + if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID) + bCount = TRUE; + else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry) + bCount = TRUE; + + if(bCount && isCCKrate) + { + if(pDM_PDTable->TrainingState == 1 ) + { + if(pEntry) + { + if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[0] != 0) + pEntry->rssi_stat.RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll; + pEntry->rssi_stat.RSSI_CCK_Path_cnt[0]++; + } + else + { + if(pDM_PDTable->RSSI_CCK_Path_cnt[0] != 0) + pDM_PDTable->RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll; + pDM_PDTable->RSSI_CCK_Path_cnt[0]++; + } + } + else if(pDM_PDTable->TrainingState == 2 ) + { + if(pEntry) + { + if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[1] != 0) + pEntry->rssi_stat.RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll; + pEntry->rssi_stat.RSSI_CCK_Path_cnt[1]++; + } + else + { + if(pDM_PDTable->RSSI_CCK_Path_cnt[1] != 0) + pDM_PDTable->RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll; + pDM_PDTable->RSSI_CCK_Path_cnt[1]++; + } + } + } +} + + +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ) +{ +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE* pHalData = NULL; + PMGNT_INFO pMgntInfo = NULL; + //pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table; + pPD_T pDM_PDTable = NULL; + + s1Byte Score = 0; + PRT_WLAN_BSS pTmpBssDesc; + PRT_WLAN_BSS pTestBssDesc; + + u1Byte target_chnl = 0; + u1Byte index; + + if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 + { // The ODM structure is not initialized. + return FALSE; + } + pHalData = GET_HAL_DATA(Adapter); + pMgntInfo = &Adapter->MgntInfo; + pDM_PDTable = &Adapter->DM_PDTable; + + // Condition that does not need to use path diversity. + if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest ) + { + RT_TRACE(COMP_SWAS, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n")); + return FALSE; + } + + // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. + PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + + RT_TRACE(COMP_SWAS, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", + pMgntInfo->RFChangeInProgress, + pHalData->eRFPowerState)); + + //pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_PDTable->PathDiv_NoLink_State = 0; + + return FALSE; + } + else + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + } + + //1 Run AntDiv mechanism "Before Link" part. + //if(pDM_SWAT_Table->SWAS_NoLink_State == 0) + if(pDM_PDTable->PathDiv_NoLink_State == 0) + { + //1 Prepare to do Scan again to check current antenna state. + + // Set check state to next step. + //pDM_SWAT_Table->SWAS_NoLink_State = 1; + pDM_PDTable->PathDiv_NoLink_State = 1; + + // Copy Current Scan list. + Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc; + PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); + + // Switch Antenna to another one. + if(pDM_PDTable->DefaultRespPath == 0) + { + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // TRX path = PathB + odm_SetRespPath_92C(Adapter, 1); + pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; + pDM_PDTable->CCKTXPath = 0xFFFFFFFF; + } + else + { + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // TRX path = PathA + odm_SetRespPath_92C(Adapter, 0); + pDM_PDTable->OFDMTXPath = 0x0; + pDM_PDTable->CCKTXPath = 0x0; + } +#if 0 + + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; + + RT_TRACE(COMP_SWAS, DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B")); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); + pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); + PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); +#endif + + // Go back to scan function again. + RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n")); + pMgntInfo->ScanStep=0; + target_chnl = odm_SwAntDivSelectChkChnl(Adapter); + odm_SwAntDivConsructChkScanChnl(Adapter, target_chnl); + HTReleaseChnlOpLock(Adapter); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + + return TRUE; + } + else + { + //1 ScanComple() is called after antenna swiched. + //1 Check scan result and determine which antenna is going + //1 to be used. + + for(index=0; indexMgntInfo.tmpNumBssDesc; index++) + { + pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]); + pTestBssDesc = &(pMgntInfo->bssDesc[index]); + + if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) + { + RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n")); + continue; + } + + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) + { + RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n")); + RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); + RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + + Score++; + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) + { + RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n")); + RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); + RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + Score--; + } + + } + + if(pMgntInfo->NumBssDesc!=0 && Score<=0) + { + RT_TRACE(COMP_SWAS, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); + + //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + } + else + { + RT_TRACE(COMP_SWAS, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); + + if(pDM_PDTable->DefaultRespPath == 0) + { + pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; + pDM_PDTable->CCKTXPath = 0xFFFFFFFF; + odm_SetRespPath_92C(Adapter, 1); + } + else + { + pDM_PDTable->OFDMTXPath = 0x0; + pDM_PDTable->CCKTXPath = 0x0; + odm_SetRespPath_92C(Adapter, 0); + } + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); // RX path = PathAB + + //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna; + + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); + //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); + } + + // Check state reset to default and wait for next time. + //pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_PDTable->PathDiv_NoLink_State = 0; + + return FALSE; + } +#else + return FALSE; +#endif + +} + + +//Neil Chen---2011--06--22 +//----92D Path Diversity----// +//#ifdef PathDiv92D +//================================== +//3 Path Diversity +//================================== +// +// 20100514 Luke/Joseph: +// Add new function for antenna diversity after link. +// This is the main function of antenna diversity after link. +// This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). +// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. +// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. +// After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just +// listened on the air with the RSSI of original antenna. +// It chooses the antenna with better RSSI. +// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting +// penalty to get next try. +// +// +// 20100503 Joseph: +// Add new function SwAntDivCheck8192C(). +// This is the main function of Antenna diversity function before link. +// Mainly, it just retains last scan result and scan again. +// After that, it compares the scan result to see which one gets better RSSI. +// It selects antenna with better receiving power and returns better scan result. +// + + +// +// 20100514 Luke/Joseph: +// This function is used to gather the RSSI information for antenna testing. +// It selects the RSSI of the peer STA that we want to know. +// +VOID +ODM_PathDivChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bCount = FALSE; + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID) + bCount = TRUE; + else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry) + bCount = TRUE; + + if(bCount) + { + //1 RSSI for SW Antenna Switch + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + { + pHalData->RSSI_sum_A += pRfd->Status.RxPWDBAll; + pHalData->RSSI_cnt_A++; + } + else + { + pHalData->RSSI_sum_B += pRfd->Status.RxPWDBAll; + pHalData->RSSI_cnt_B++; + + } + } +} + + + +// +// 20100514 Luke/Joseph: +// Add new function to reset antenna diversity state after link. +// +VOID +ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER Adapter=pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_cnt_B = 0; + pHalData->RSSI_test = FALSE; + pDM_SWAT_Table->try_flag = 0x0; // NOT 0xff + pDM_SWAT_Table->RSSI_Trying = 0; + pDM_SWAT_Table->SelectAntennaMap=0xAA; + pDM_SWAT_Table->CurAntenna = Antenna_A; +} + + +// +// 20100514 Luke/Joseph: +// Callback function for 500ms antenna test trying. +// +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem); +#else + odm_PathDivChkAntSwitch(pDM_Odm); +#endif +#else + PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem); +#endif + +//odm_SwAntDivChkAntSwitch(Adapter, SWAW_STEP_DETERMINE); + +} + + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + odm_PathDivChkAntSwitch(pDM_Odm); +} + + + //MAC0_ACCESS_PHY1 + +// 2011-06-22 Neil Chen & Gary Hsin +// Refer to Jr.Luke's SW ANT DIV +// 92D Path Diversity Main function +// refer to 88C software antenna diversity +// +VOID +odm_PathDivChkAntSwitch( + PDM_ODM_T pDM_Odm + //PADAPTER Adapter, + //u1Byte Step +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + s4Byte curRSSI=100, RSSI_A, RSSI_B; + u1Byte nextAntenna=Antenna_B; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u8Byte curTxOkCnt, curRxOkCnt; + static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; + u8Byte CurByteCnt=0, PreByteCnt=0; + static u1Byte TrafficLoad = TRAFFIC_LOW; + u1Byte Score_A=0, Score_B=0; + u1Byte i=0x0; + // Neil Chen + static u1Byte pathdiv_para=0x0; + static u1Byte switchfirsttime=0x00; + // u1Byte regB33 = (u1Byte) PHY_QueryBBReg(Adapter, 0xB30,BIT27); + u1Byte regB33 = (u1Byte)ODM_GetBBReg(pDM_Odm, PATHDIV_REG, BIT27); + + + //u1Byte reg637 =0x0; + static u1Byte fw_value=0x0; + u1Byte n=0; + static u8Byte lastTxOkCnt_tmp=0, lastRxOkCnt_tmp=0; + //u8Byte curTxOkCnt_tmp, curRxOkCnt_tmp; + PADAPTER BuddyAdapter = Adapter->BuddyAdapter; // another adapter MAC + // Path Diversity //Neil Chen--2011--06--22 + + //u1Byte PathDiv_Trigger = (u1Byte) PHY_QueryBBReg(Adapter, 0xBA0,BIT31); + u1Byte PathDiv_Trigger = (u1Byte) ODM_GetBBReg(pDM_Odm, PATHDIV_TRI,BIT31); + u1Byte PathDiv_Enable = pHalData->bPathDiv_Enable; + + + //DbgPrint("Path Div PG Value:%x \n",PathDiv_Enable); + if((BuddyAdapter==NULL)||(!PathDiv_Enable)||(PathDiv_Trigger)||(pHalData->CurrentBandType92D == BAND_ON_2_4G)) + { + return; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD,("===================>odm_PathDivChkAntSwitch()\n")); + + // The first time to switch path excluding 2nd, 3rd, ....etc.... + if(switchfirsttime==0) + { + if(regB33==0) + { + pDM_SWAT_Table->CurAntenna = Antenna_A; // Default MAC0_5G-->Path A (current antenna) + } + } + + // Condition that does not need to use antenna diversity. + if(pDM_Odm->SupportICType != ODM_RTL8192D) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDiversityMechanims(): No PathDiv Mechanism.\n")); + return; + } + + // Radio off: Status reset to default and return. + if(pHalData->eRFPowerState==eRfOff) + { + //ODM_SwAntDivRestAfterLink(Adapter); + return; + } + + /* + // Handling step mismatch condition. + // Peak step is not finished at last time. Recover the variable and check again. + if( Step != pDM_SWAT_Table->try_flag ) + { + ODM_SwAntDivRestAfterLink(Adapter); + } */ + + if(pDM_SWAT_Table->try_flag == 0xff) + { + // Select RSSI checking target + if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter)) + { + // Target: Infrastructure mode AP. + pHalData->RSSI_target = NULL; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDivMechanism(): RSSI_target is DEF AP!\n")); + } + else + { + u1Byte index = 0; + PRT_WLAN_STA pEntry = NULL; + PADAPTER pTargetAdapter = NULL; + + if( pMgntInfo->mIbss || ACTING_AS_AP(Adapter) ) + { + // Target: AP/IBSS peer. + pTargetAdapter = Adapter; + } + else if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + { + // Target: VWIFI peer. + pTargetAdapter = GetFirstExtAdapter(Adapter); + } + + if(pTargetAdapter != NULL) + { + for(index=0; indexbAssociated) + break; + } + } + } + + if(pEntry == NULL) + { + ODM_PathDivRestAfterLink(pDM_Odm); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); + return; + } + else + { + pHalData->RSSI_target = pEntry; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); + } + } + + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_cnt_B = 0; + pDM_SWAT_Table->try_flag = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n")); + return; + } + else + { + // 1st step + curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; + curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; + lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + + if(pDM_SWAT_Table->try_flag == 1) // Training State + { + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + { + TXByteCnt_A += curTxOkCnt; + RXByteCnt_A += curRxOkCnt; + } + else + { + TXByteCnt_B += curTxOkCnt; + RXByteCnt_B += curRxOkCnt; + } + + nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; + pDM_SWAT_Table->RSSI_Trying--; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying)); + if(pDM_SWAT_Table->RSSI_Trying == 0) + { + CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (TXByteCnt_A+RXByteCnt_A) : (TXByteCnt_B+RXByteCnt_B); + PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (TXByteCnt_B+RXByteCnt_B) : (TXByteCnt_A+RXByteCnt_A); + + if(TrafficLoad == TRAFFIC_HIGH) + { + //CurByteCnt = PlatformDivision64(CurByteCnt, 9); + PreByteCnt =PreByteCnt*9; + } + else if(TrafficLoad == TRAFFIC_LOW) + { + //CurByteCnt = PlatformDivision64(CurByteCnt, 2); + PreByteCnt =PreByteCnt*2; + } + if(pHalData->RSSI_cnt_A > 0) + RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; + else + RSSI_A = 0; + if(pHalData->RSSI_cnt_B > 0) + RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; + else + RSSI_B = 0; + curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; + pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", + RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B)); + } + + } + else // try_flag=0 + { + + if(pHalData->RSSI_cnt_A > 0) + RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; + else + RSSI_A = 0; + if(pHalData->RSSI_cnt_B > 0) + RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; + else + RSSI_B = 0; + curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; + pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", + RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B)); + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt)); + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt)); + } + + //1 Trying State + if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0)) + { + + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = TP_MODE")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:CurByteCnt = %"i64fmt"d,", CurByteCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:PreByteCnt = %"i64fmt"d\n",PreByteCnt)); + if(CurByteCnt < PreByteCnt) + { + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; + else + pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; + } + else + { + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; + else + pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; + } + for (i= 0; i<8; i++) + { + if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1) + Score_A++; + else + Score_B++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Score_A=%d, Score_B=%d\n", Score_A, Score_B)); + + if(pDM_SWAT_Table->CurAntenna == Antenna_A) + { + nextAntenna = (Score_A >= Score_B)?Antenna_A:Antenna_B; + } + else + { + nextAntenna = (Score_B >= Score_A)?Antenna_B:Antenna_A; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B"))); + + if(nextAntenna != pDM_SWAT_Table->CurAntenna) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Switch back to another antenna")); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: current anntena is good\n")); + } + } + + + if(pDM_SWAT_Table->TestMode == RSSI_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = RSSI_MODE")); + pDM_SWAT_Table->SelectAntennaMap=0xAA; + if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna + { + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Switch back to another antenna")); + nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; + } + else // current anntena is good + { + nextAntenna =pDM_SWAT_Table->CurAntenna; + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: current anntena is good\n")); + } + } + + pDM_SWAT_Table->try_flag = 0; + pHalData->RSSI_test = FALSE; + pHalData->RSSI_sum_A = 0; + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_sum_B = 0; + pHalData->RSSI_cnt_B = 0; + TXByteCnt_A = 0; + TXByteCnt_B = 0; + RXByteCnt_A = 0; + RXByteCnt_B = 0; + + } + + //1 Normal State + else if(pDM_SWAT_Table->try_flag == 0) + { + if(TrafficLoad == TRAFFIC_HIGH) + { + if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) + TrafficLoad = TRAFFIC_HIGH; + else + TrafficLoad = TRAFFIC_LOW; + } + else if(TrafficLoad == TRAFFIC_LOW) + { + if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) + TrafficLoad = TRAFFIC_HIGH; + else + TrafficLoad = TRAFFIC_LOW; + } + if(TrafficLoad == TRAFFIC_HIGH) + pDM_SWAT_Table->bTriggerAntennaSwitch = 0; + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt)); + + //Prepare To Try Antenna + nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; + pDM_SWAT_Table->try_flag = 1; + pHalData->RSSI_test = TRUE; + if((curRxOkCnt+curTxOkCnt) > 1000) + { +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + pDM_SWAT_Table->RSSI_Trying = 4; +#else + pDM_SWAT_Table->RSSI_Trying = 2; +#endif + pDM_SWAT_Table->TestMode = TP_MODE; + } + else + { + pDM_SWAT_Table->RSSI_Trying = 2; + pDM_SWAT_Table->TestMode = RSSI_MODE; + + } + + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n")); + pHalData->RSSI_sum_A = 0; + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_sum_B = 0; + pHalData->RSSI_cnt_B = 0; + } // end of try_flag=0 + } + + //1 4.Change TRX antenna + if(nextAntenna != pDM_SWAT_Table->CurAntenna) + { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Change TX Antenna!\n ")); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); for 88C + if(nextAntenna==Antenna_A) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH A\n ")); + pathdiv_para = 0x02; //02 to switchback to RF path A + fw_value = 0x03; +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); +#else + ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); +#endif + } + else if(nextAntenna==Antenna_B) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH B\n ")); + if(switchfirsttime==0) // First Time To Enter Path Diversity + { + switchfirsttime=0x01; + pathdiv_para = 0x00; + fw_value=0x00; // to backup RF Path A Releated Registers + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); +#else + ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); + //for(u1Byte n=0; n<80,n++) + //{ + //delay_us(500); + ODM_delay_ms(500); + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); + + fw_value=0x01; // to backup RF Path A Releated Registers + ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: FIRST TIME To DO PATH SWITCH!\n ")); + } + else + { + pathdiv_para = 0x01; + fw_value = 0x02; +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); +#else + ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); +#endif + } + } + // odm_PathDiversity_8192D(Adapter, pathdiv_para); + } + + //1 5.Reset Statistics + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + pDM_SWAT_Table->CurAntenna = nextAntenna; + pDM_SWAT_Table->PreRSSI = curRSSI; + //lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + //lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + + //1 6.Set next timer + + if(pDM_SWAT_Table->RSSI_Trying == 0) + return; + + if(pDM_SWAT_Table->RSSI_Trying%2 == 0) + { + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + if(TrafficLoad == TRAFFIC_HIGH) + { +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 10 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 10 ms\n")); +#else + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 20 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 20 ms\n")); +#endif + } + else if(TrafficLoad == TRAFFIC_LOW) + { + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 50 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 50 ms\n")); + } + } + else // TestMode == RSSI_MODE + { + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 500 ms\n")); + } + } + else + { + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + if(TrafficLoad == TRAFFIC_HIGH) + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 90 ); //ms + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 90 ms\n")); +#else + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 180); //ms +#endif + else if(TrafficLoad == TRAFFIC_LOW) + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 100 ); //ms + } + else + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms + } +} + +//================================================== +//3 PathDiv End +//================================================== + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ) +{ + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + + RT_TRACE( COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Select Response Path=%d\n",DefaultRespPath)); + if(DefaultRespPath != pDM_PDTable->DefaultRespPath) + { + if(DefaultRespPath == 0) + { + PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x15); + } + else + { + PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x2A); + } + } + pDM_PDTable->DefaultRespPath = DefaultRespPath; +} + + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte TXPath; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + + //2011.09.05 Add by Luke Lee for path diversity + if(pHalData->PathDivCfg == 1) + { + TXPath = (pDM_PDTable->OFDMTXPath >> pTcb->macId) & BIT0; + //RT_TRACE( COMP_SWAS, DBG_LOUD, ("Fill TXDESC: macID=%d, TXPath=%d\n", pTcb->macId, TXPath)); + //SET_TX_DESC_TX_ANT_CCK(pDesc,TXPath); + if(TXPath == 0) + { + SET_TX_DESC_TX_ANTL_92C(pDesc,1); + SET_TX_DESC_TX_ANT_HT_92C(pDesc,1); + } + else + { + SET_TX_DESC_TX_ANTL_92C(pDesc,2); + SET_TX_DESC_TX_ANT_HT_92C(pDesc,2); + } + TXPath = (pDM_PDTable->CCKTXPath >> pTcb->macId) & BIT0; + if(TXPath == 0) + { + SET_TX_DESC_TX_ANT_CCK_92C(pDesc,1); + } + else + { + SET_TX_DESC_TX_ANT_CCK_92C(pDesc,2); + } + } +} + +//Only for MP //Neil Chen--2012--0502-- +VOID +odm_PathDivInit( +IN PDM_ODM_T pDM_Odm) +{ + pPATHDIV_PARA pathIQK = &pDM_Odm->pathIQK; + + pathIQK->org_2g_RegC14=0x0; + pathIQK->org_2g_RegC4C=0x0; + pathIQK->org_2g_RegC80=0x0; + pathIQK->org_2g_RegC94=0x0; + pathIQK->org_2g_RegCA0=0x0; + pathIQK->org_5g_RegC14=0x0; + pathIQK->org_5g_RegCA0=0x0; + pathIQK->org_5g_RegE30=0x0; + pathIQK->swt_2g_RegC14=0x0; + pathIQK->swt_2g_RegC4C=0x0; + pathIQK->swt_2g_RegC80=0x0; + pathIQK->swt_2g_RegC94=0x0; + pathIQK->swt_2g_RegCA0=0x0; + pathIQK->swt_5g_RegC14=0x0; + pathIQK->swt_5g_RegCA0=0x0; + pathIQK->swt_5g_RegE30=0x0; + +} +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + +#if ((DM_ODM_SUPPORT_TYPE == ODM_MP)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) + + +// +// Description: +// Set Single/Dual Antenna default setting for products that do not do detection in advance. +// +// Added by Joseph, 2012.03.22 +// +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PDM_ODM_T pDM_Odm + ) +{ + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=TRUE; +} + + +//2 8723A ANT DETECT + + +VOID +odm_PHY_SaveAFERegisters( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFEReg, + IN pu4Byte AFEBackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; + + //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord); + } +} + +VOID +odm_PHY_ReloadAFERegisters( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFEReg, + IN pu4Byte AFEBackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; + + //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + + ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]); + } +} + +//2 8723A ANT DETECT +// +// Description: +// Implement IQK single tone for RF DPK loopback and BB PSD scanning. +// This function is cooperated with BB team Neil. +// +// Added by Roger, 2011.12.15 +// +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PDM_ODM_T pDM_Odm, + IN u1Byte mode + ) +{ + + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u4Byte CurrentChannel,RfLoopReg; + u1Byte n; + u4Byte Reg88c, Regc08, Reg874, Regc50; + u1Byte initial_gain = 0x5a; + u4Byte PSD_report_tmp; + u4Byte AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0; + BOOLEAN bResult = TRUE; + u4Byte AFE_Backup[16]; + u4Byte AFE_REG_8723A[16] = { + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN, + rFPGA0_XCD_SwitchControl, rBlue_Tooth}; + + if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))) + return bResult; + + if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) + return bResult; + + if(pDM_Odm->SupportICType == ODM_RTL8192C) + { + //Which path in ADC/DAC is turnned on for PSD: both I/Q + ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3); + //Ageraged number: 8 + ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1); + //pts = 128; + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); + } + + //1 Backup Current RF/BB Settings + + CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); + RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask); + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); // change to Antenna A + // Step 1: USE IQK to transmitter single tone + + ODM_StallExecution(10); + + //Store A Path Register 88c, c08, 874, c50 + Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); + Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); + Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); + Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); + + // Store AFE Registers + odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); + + //Set PSD 128 pts + ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts + + // To SET CH1 to do + ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); //Channel 1 + + // AFE all on step + ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4); + ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4); + + // 3 wire Disable + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); + + //BB IQK Setting + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); + + //IQK setting tone@ 4.34Mhz + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + + + //Page B init + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); + + //RF loop Setting + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008); + + //IQK Single tone start + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + ODM_StallExecution(1000); + PSD_report_tmp=0x0; + + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp >AntA_report) + AntA_report=PSD_report_tmp; + } + + PSD_report_tmp=0x0; + + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); // change to Antenna B + ODM_StallExecution(10); + + + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp > AntB_report) + AntB_report=PSD_report_tmp; + } + + // change to open case + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); // change to Ant A and B all open case + ODM_StallExecution(10); + + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp > AntO_report) + AntO_report=PSD_report_tmp; + } + + //Close IQK Single Tone function + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + PSD_report_tmp = 0x0; + + //1 Return to antanna A + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); + + //Reload AFE Registers + odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report)); + + + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + //2 Test Ant B based on Ant A is ON + if(mode==ANTTESTB) + { + if(AntA_report >= 100) + { + if(AntB_report > (AntA_report+1)) + { + pDM_SWAT_Table->ANTB_ON=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); + } + else + { + pDM_SWAT_Table->ANTB_ON=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n")); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); + pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default + bResult = FALSE; + } + } + //2 Test Ant A and B based on DPDT Open + else if(mode==ANTTESTALL) + { + if((AntO_report >=100)&(AntO_report <118)) + { + if(AntA_report > (AntO_report+1)) + { + pDM_SWAT_Table->ANTA_ON=FALSE; + //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF")); + } + else + { + pDM_SWAT_Table->ANTA_ON=TRUE; + //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON")); + } + + if(AntB_report > (AntO_report+2)) + { + pDM_SWAT_Table->ANTB_ON=FALSE; + //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF")); + } + else + { + pDM_SWAT_Table->ANTB_ON=TRUE; + //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON")); + } + } + } + } + else if(pDM_Odm->SupportICType == ODM_RTL8192C) + { + if(AntA_report >= 100) + { + if(AntB_report > (AntA_report+2)) + { + pDM_SWAT_Table->ANTA_ON=FALSE; + pDM_SWAT_Table->ANTB_ON=TRUE; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n")); + } + else if(AntA_report > (AntB_report+2)) + { + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=FALSE; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); + } + else + { + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=TRUE; + RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna \n")); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); + pDM_SWAT_Table->ANTA_ON=TRUE; // Set Antenna A on as default + pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default + bResult = FALSE; + } + } + return bResult; + +} + + +#endif // end odm_CE + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ +void odm_dtc(PDM_ODM_T pDM_Odm) +{ +#ifdef CONFIG_DM_RESP_TXAGC + #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ + #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ + + /* RSSI vs TX power step mapping: decade TX power */ + static const u8 dtc_table_down[]={ + DTC_BASE, + (DTC_BASE+5), + (DTC_BASE+10), + (DTC_BASE+15), + (DTC_BASE+20), + (DTC_BASE+25) + }; + + /* RSSI vs TX power step mapping: increase TX power */ + static const u8 dtc_table_up[]={ + DTC_DWN_BASE, + (DTC_DWN_BASE-5), + (DTC_DWN_BASE-10), + (DTC_DWN_BASE-15), + (DTC_DWN_BASE-15), + (DTC_DWN_BASE-20), + (DTC_DWN_BASE-20), + (DTC_DWN_BASE-25), + (DTC_DWN_BASE-25), + (DTC_DWN_BASE-30), + (DTC_DWN_BASE-35) + }; + + u8 i; + u8 dtc_steps=0; + u8 sign; + u8 resp_txagc=0; + + #if 0 + /* As DIG is disabled, DTC is also disable */ + if(!(pDM_Odm->SupportAbility & ODM_XXXXXX)) + return; + #endif + + if (DTC_BASE < pDM_Odm->RSSI_Min) { + /* need to decade the CTS TX power */ + sign = 1; + for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6)) + break; + else + dtc_steps++; + } + } +#if 0 + else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min) + { + /* needs to increase the CTS TX power */ + sign = 0; + dtc_steps = 1; + for (i=0;iRSSI_Min) || (dtc_steps>=10)) + break; + else + dtc_steps++; + } + } +#endif + else + { + sign = 0; + dtc_steps = 0; + } + + resp_txagc = dtc_steps | (sign << 4); + resp_txagc = resp_txagc | (resp_txagc << 5); + ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc); + + DBG_871X("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n", + __func__, pDM_Odm->RSSI_Min, sign?"minus":"plus", dtc_steps); +#endif /* CONFIG_RESP_TXAGC_ADJUST */ +} + +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.h new file mode 100755 index 00000000..748c90b8 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm.h @@ -0,0 +1,1985 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +//============================================================ +// Definition +//============================================================ +// +// 2011/09/22 MH Define all team supprt ability. +// + +// +// 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. +// +//#define DM_ODM_SUPPORT_AP 0 +//#define DM_ODM_SUPPORT_ADSL 0 +//#define DM_ODM_SUPPORT_CE 0 +//#define DM_ODM_SUPPORT_MP 1 + +// +// 2011/09/28 MH Define ODM SW team support flag. +// + + + +// +// Antenna Switch Relative Definition. +// + +// +// 20100503 Joseph: +// Add new function SwAntDivCheck8192C(). +// This is the main function of Antenna diversity function before link. +// Mainly, it just retains last scan result and scan again. +// After that, it compares the scan result to see which one gets better RSSI. +// It selects antenna with better receiving power and returns better scan result. +// +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + + +//============================================================ +//3 Tx Power Tracking +//3============================================================ +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 + + +//============================================================ +//3 PSD Handler +//3============================================================ + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#if(RTL8723_FPGA_VERIFICATION == 1) +#define PSD_RESCAN 1 +#else +#define PSD_RESCAN 4 +#endif +#define PSD_SCAN_INTERVAL 700 //ms + + + +//8723A High Power IGI Setting +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a + +// LPS define +#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps +#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps +#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps +#define RSSI_OFFSET_DIG 0x05; + +//ANT Test +#define ANTTESTALL 0x00 //Ant A or B will be Testing +#define ANTTESTA 0x01 //Ant A will be Testing +#define ANTTESTB 0x02 //Ant B will be testing + + +//============================================================ +// structure and define +//============================================================ + +// +// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. +// We need to remove to other position??? +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) +typedef struct rtl8192cd_priv { + u1Byte temp; + +}rtl8192cd_priv, *prtl8192cd_priv; +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +typedef struct _ADAPTER{ + u1Byte temp; + #ifdef AP_BUILD_WORKAROUND + HAL_DATA_TYPE* temp2; + prtl8192cd_priv priv; + #endif +}ADAPTER, *PADAPTER; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +typedef struct _WLAN_STA{ + u1Byte temp; +} WLAN_STA, *PRT_WLAN_STA; + +#endif + +typedef struct _Dynamic_Initial_Gain_Threshold_ +{ + u1Byte Dig_Enable_Flag; + u1Byte Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u4Byte FALowThresh; + u4Byte FAHighThresh; + + u1Byte CurSTAConnectState; + u1Byte PreSTAConnectState; + u1Byte CurMultiSTAConnectState; + + u1Byte PreIGValue; + u1Byte CurIGValue; + u1Byte BackupIGValue; + + s1Byte BackoffVal; + s1Byte BackoffVal_range_max; + s1Byte BackoffVal_range_min; + u1Byte rx_gain_range_max; + u1Byte rx_gain_range_min; + u1Byte Rssi_val_min; + + u1Byte PreCCK_CCAThres; + u1Byte CurCCK_CCAThres; + u1Byte PreCCKPDState; + u1Byte CurCCKPDState; + + u1Byte LargeFAHit; + u1Byte ForbiddenIGI; + u4Byte Recover_cnt; + + u1Byte DIG_Dynamic_MIN_0; + u1Byte DIG_Dynamic_MIN_1; + BOOLEAN bMediaConnect_0; + BOOLEAN bMediaConnect_1; + + u4Byte AntDiv_RSSI_max; + u4Byte RSSI_max; +}DIG_T,*pDIG_T; + +typedef struct _Dynamic_Power_Saving_ +{ + u1Byte PreCCAState; + u1Byte CurCCAState; + + u1Byte PreRFState; + u1Byte CurRFState; + + int Rssi_val_min; + + u1Byte initialize; + u4Byte Reg874,RegC70,Reg85C,RegA74; + +}PS_T,*pPS_T; + +typedef struct _FALSE_ALARM_STATISTICS{ + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte Cnt_Mcs_fail; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; //Gary + u4Byte Cnt_BW_LSC; //Gary +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + +typedef struct _Dynamic_Primary_CCA{ + u1Byte PriCCA_flag; + u1Byte intf_flag; + u1Byte intf_type; + u1Byte DupRTS_flag; + u1Byte Monitor_flag; +}Pri_CCA_T, *pPri_CCA_T; + +typedef struct _RX_High_Power_ +{ + u1Byte RXHP_flag; + u1Byte PSD_func_trigger; + u1Byte PSD_bitmap_RXHP[80]; + u1Byte Pre_IGI; + u1Byte Cur_IGI; + u1Byte Pre_pw_th; + u1Byte Cur_pw_th; + BOOLEAN First_time_enter; + BOOLEAN RXHP_enable; + u1Byte TP_Mode; + RT_TIMER PSDTimer; +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + #if USE_WORKITEM + RT_WORK_ITEM PSDTimeWorkitem; + #endif +#endif + +}RXHP_T, *pRXHP_T; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[]. +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM + +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define ASSOCIATE_ENTRY_NUM NUM_STAT +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1 + +#else +// +// 2012/01/12 MH Revise for compatiable with other SW team. +// 0 is for STA 1-n is for AP clients. +// +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1// Default port only one +#endif + +//#ifdef CONFIG_ANTENNA_DIVERSITY +// This indicates two different the steps. +// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. +// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK +// with original RSSI to determine if it is necessary to switch antenna. +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +typedef struct _SW_Antenna_Switch_ +{ + u1Byte try_flag; + s4Byte PreRSSI; + u1Byte CurAntenna; + u1Byte PreAntenna; + u1Byte RSSI_Trying; + u1Byte TestMode; + u1Byte bTriggerAntennaSwitch; + u1Byte SelectAntennaMap; + u1Byte RSSI_target; + + // Before link Antenna Switch check + u1Byte SWAS_NoLink_State; + u4Byte SWAS_NoLink_BK_Reg860; + BOOLEAN ANTA_ON; //To indicate Ant A is or not + BOOLEAN ANTB_ON; //To indicate Ant B is on or not + + s4Byte RSSI_sum_A; + s4Byte RSSI_sum_B; + s4Byte RSSI_cnt_A; + s4Byte RSSI_cnt_B; + + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte TrafficLoad; + RT_TIMER SwAntennaSwitchTimer; +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + #if USE_WORKITEM + RT_WORK_ITEM SwAntennaSwitchWorkitem; + #endif +#endif +/* CE Platform use +#ifdef CONFIG_SW_ANTENNA_DIVERSITY + _timer SwAntennaSwitchTimer; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte DoubleComfirm; + u1Byte TrafficLoad; + //SW Antenna Switch + + +#endif +*/ +#ifdef CONFIG_HW_ANTENNA_DIVERSITY + //Hybrid Antenna Diversity + u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; + u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; + u1Byte TxAnt[ASSOCIATE_ENTRY_NUM]; + u1Byte TargetSTA; + u1Byte antsel; + u1Byte RxIdleAnt; + +#endif + +}SWAT_T, *pSWAT_T; +//#endif + +typedef struct _EDCA_TURBO_ +{ + BOOLEAN bCurrentTurboEDCA; + BOOLEAN bIsCurRDLState; + #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) + u4Byte prv_traffic_idx; // edca turbo + #endif + +}EDCA_T,*pEDCA_T; + +typedef struct _ODM_RATE_ADAPTIVE +{ + u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver + u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH + u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW + u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW + u4Byte LastRATR; // RATR Register Content + +} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + + +#ifdef ADSL_AP_BUILD_WORKAROUND +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms +#endif + +// +// Indicate different AP vendor for IOT issue. +// +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 + HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_MAX = 16 +}HT_IOT_PEER_E, *PHTIOT_PEER_E; +#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + + + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#if (RTL8192D_SUPPORT==1) +#define IQK_BB_REG_NUM 10 +#else +#define IQK_BB_REG_NUM 9 +#endif +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +#define IQK_Matrix_Settings_NUM 1+24+21 + +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +// +// Declare for common info +// +// Declare for common info +// +#define MAX_PATH_NUM_92CS 2 + +typedef struct _ODM_Phy_Status_Info_ +{ + u1Byte RxPWDBAll; + u1Byte SignalQuality; // in 0-100 index. + u1Byte RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM + u1Byte RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + s1Byte RxPower; // in dBm Translate from PWdB + s1Byte RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; // in 0-100 index. + u1Byte RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb +#endif + u1Byte RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR +}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; + + +typedef struct _ODM_Phy_Dbg_Info_ +{ + //ODM Write,debug info + s1Byte RxSNRdB[MAX_PATH_NUM_92CS]; + u8Byte NumQryPhyStatus; + u8Byte NumQryPhyStatusCCK; + u8Byte NumQryPhyStatusOFDM; + //Others + s4Byte RxEVM[MAX_PATH_NUM_92CS]; + +}ODM_PHY_DBG_INFO_T; + +typedef struct _ODM_Per_Pkt_Info_ +{ + u1Byte Rate; + u1Byte StationID; + BOOLEAN bPacketMatchBSSID; + BOOLEAN bPacketToSelf; + BOOLEAN bPacketBeacon; +}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; + +typedef struct _ODM_Mac_Status_Info_ +{ + u1Byte test; + +}ODM_MAC_INFO; + + +typedef enum tag_Dynamic_ODM_Support_Ability_Type +{ + // BB Team + ODM_DIG = 0x00000001, + ODM_HIGH_POWER = 0x00000002, + ODM_CCK_CCA_TH = 0x00000004, + ODM_FA_STATISTICS = 0x00000008, + ODM_RAMASK = 0x00000010, + ODM_RSSI_MONITOR = 0x00000020, + ODM_SW_ANTDIV = 0x00000040, + ODM_HW_ANTDIV = 0x00000080, + ODM_BB_PWRSV = 0x00000100, + ODM_2TPATHDIV = 0x00000200, + ODM_1TPATHDIV = 0x00000400, + ODM_PSD2AFH = 0x00000800 +}ODM_Ability_E; + +// +// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T +// Please declare below ODM relative info in your STA info structure. +// +#if 1 +typedef struct _ODM_STA_INFO{ + // Driver Write + BOOLEAN bUsed; // record the sta status link or not? + //u1Byte WirelessMode; // + u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E + + // ODM Write + //1 PHY_STATUS_INFO + u1Byte RSSI_Path[4]; // + u1Byte RSSI_Ave; + u1Byte RXEVM[4]; + u1Byte RXSNR[4]; + + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. +#if 0 + u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_C; //only in Jagar: 4bit + u1Byte ANTSEL_D; //only in Jagar: 4bit + u1Byte TX_ANTL; //not in Jagar: 2bit + u1Byte TX_ANT_HT; //not in Jagar: 2bit + u1Byte TX_ANT_CCK; //not in Jagar: 2bit + u1Byte TXAGC_A; //not in Jagar: 4bit + u1Byte TXAGC_B; //not in Jagar: 4bit + u1Byte TXPWR_OFFSET; //only in Jagar: 3bit + u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK +#endif + + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // Move To lower layer. + // + // ODM Write Wilson will handle this part(said by Luke.Lee) + //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. +#if 0 + //1 For 88E RA (don't redefine the naming) + u1Byte rate_id; + u1Byte rate_SGI; + u1Byte rssi_sta_ra; + u1Byte SGI_enable; + u1Byte Decision_rate; + u1Byte Pre_rate; + u1Byte Active; + + // Driver write Wilson handle. + //1 TX_RPT (don't redefine the naming) + u2Byte RTY[4]; // ??? + u2Byte TOTAL; // ??? + u2Byte DROP; // ??? + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // +#endif + +}ODM_STA_INFO_T, *PODM_STA_INFO_T; +#endif + +// +// 2011/10/20 MH Define Common info enum for all team. +// +typedef enum _ODM_Common_Info_Definition +{ +//-------------REMOVED CASE-----------// + //ODM_CMNINFO_CCK_HP, + //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? + //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E + //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E +//-------------REMOVED CASE-----------// + + // + // Fixed value: + // + + //-----------HOOK BEFORE REG INIT-----------// + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, // ODM_ABILITY_E + ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E + ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E + ODM_CMNINFO_FAB_VER, // ODM_FAB_E + ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? + ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E + ODM_CMNINFO_EXT_LNA, // TRUE + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + //-----------HOOK BEFORE REG INIT-----------// + + + // + // Dynamic value: + // +//--------- POINTER REFERENCE-----------// + ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E + ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E + ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E + ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E + ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_CHNL, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + ODM_CMNINFO_MP_MODE, +//--------- POINTER REFERENCE-----------// + +//------------CALL BY VALUE-------------// + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, // u8Byte + ODM_CMNINFO_DBG_LEVEL, // u4Byte + ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte + ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte + ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte + ODM_CMNINFO_BT_DISABLED, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil + ODM_CMNINFO_BT_DISABLE_EDCA, +//------------CALL BY VALUE-------------// + + // + // Dynamic ptr array hook itms. + // + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + + ODM_CMNINFO_MAX, + + +}ODM_CMNINFO_E; + +// +// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY +// +typedef enum _ODM_Support_Ability_Definition +{ + // + // BB ODM section BIT 0-15 + // + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, + ODM_BB_DYNAMIC_TXPWR = BIT2, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_SAVE = BIT7, + ODM_BB_PWR_TRAIN = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_PSD = BIT11, + ODM_BB_RXHP = BIT12, + + // + // MAC DM section BIT 16-23 + // + ODM_MAC_EDCA_TURBO = BIT16, + ODM_MAC_EARLY_MODE = BIT17, + + // + // RF ODM section BIT 24-31 + // + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, + +}ODM_ABILITY_E; + +// ODM_CMNINFO_INTERFACE +typedef enum tag_ODM_Support_Interface_Definition +{ + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}ODM_INTERFACE_E; + +// ODM_CMNINFO_IC_TYPE +typedef enum tag_ODM_Support_IC_Type_Definition +{ + ODM_RTL8192S = BIT0, + ODM_RTL8192C = BIT1, + ODM_RTL8192D = BIT2, + ODM_RTL8723A = BIT3, + ODM_RTL8188E = BIT4, + ODM_RTL8812 = BIT5, + ODM_RTL8821 = BIT6, +}ODM_IC_TYPE_E; + +#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E) +#define ODM_IC_11AC_SERIES (ODM_RTL8812) + +//ODM_CMNINFO_CUT_VER +typedef enum tag_ODM_Cut_Version_Definition +{ + ODM_CUT_A = 1, + ODM_CUT_B = 2, + ODM_CUT_C = 3, + ODM_CUT_D = 4, + ODM_CUT_E = 5, + ODM_CUT_F = 6, + ODM_CUT_TEST = 7, +}ODM_CUT_VERSION_E; + +// ODM_CMNINFO_FAB_VER +typedef enum tag_ODM_Fab_Version_Definition +{ + ODM_TSMC = 0, + ODM_UMC = 1, +}ODM_FAB_E; + +// ODM_CMNINFO_RF_TYPE +// +// For example 1T2R (A+AB = BIT0|BIT4|BIT5) +// +typedef enum tag_ODM_RF_Path_Bit_Definition +{ + ODM_RF_TX_A = BIT0, + ODM_RF_TX_B = BIT1, + ODM_RF_TX_C = BIT2, + ODM_RF_TX_D = BIT3, + ODM_RF_RX_A = BIT4, + ODM_RF_RX_B = BIT5, + ODM_RF_RX_C = BIT6, + ODM_RF_RX_D = BIT7, +}ODM_RF_PATH_E; + + +typedef enum tag_ODM_RF_Type_Definition +{ + ODM_1T1R = 0, + ODM_1T2R = 1, + ODM_2T2R = 2, + ODM_2T3R = 3, + ODM_2T4R = 4, + ODM_3T3R = 5, + ODM_3T4R = 6, + ODM_4T4R = 7, +}ODM_RF_TYPE_E; + + +// +// ODM Dynamic common info value definition +// + +//typedef enum _MACPHY_MODE_8192D{ +// SINGLEMAC_SINGLEPHY, +// DUALMAC_DUALPHY, +// DUALMAC_SINGLEPHY, +//}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; +// Above is the original define in MP driver. Please use the same define. THX. +typedef enum tag_ODM_MAC_PHY_Mode_Definition +{ + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}ODM_MAC_PHY_MODE_E; + + +typedef enum tag_BT_Coexist_Definition +{ + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}ODM_BT_COEXIST_E; + +// ODM_CMNINFO_OP_MODE +typedef enum tag_Operation_Mode_Definition +{ + ODM_NO_LINK = BIT0, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, + ODM_AP_MODE = BIT4, + ODM_CLIENT_MODE = BIT5, + ODM_AD_HOC = BIT6, + ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DISPLAY = BIT8, +}ODM_OPERATION_MODE_E; + +// ODM_CMNINFO_WM_MODE +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT0, + ODM_WM_G = BIT1, + ODM_WM_A = BIT2, + ODM_WM_N24G = BIT3, + ODM_WM_N5G = BIT4, + ODM_WM_AUTO = BIT5, + ODM_WM_AC = BIT6, +}ODM_WIRELESS_MODE_E; + +// ODM_CMNINFO_BAND +typedef enum tag_Band_Type_Definition +{ + ODM_BAND_2_4G = BIT0, + ODM_BAND_5G = BIT1, + +}ODM_BAND_TYPE_E; + +// ODM_CMNINFO_SEC_CHNL_OFFSET +typedef enum tag_Secondary_Channel_Offset_Definition +{ + ODM_DONT_CARE = 0, + ODM_BELOW = 1, + ODM_ABOVE = 2 +}ODM_SEC_CHNL_OFFSET_E; + +// ODM_CMNINFO_SEC_MODE +typedef enum tag_Security_Definition +{ + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, // WEP + WPA + ODM_SEC_SMS4 = 7, +}ODM_SECURITY_E; + +// ODM_CMNINFO_BW +typedef enum tag_Bandwidth_Definition +{ + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW10M = 4, +}ODM_BW_E; + +// ODM_CMNINFO_CHNL + +// ODM_CMNINFO_BOARD_TYPE +typedef enum tag_Board_Definition +{ + ODM_BOARD_NORMAL = 0, + ODM_BOARD_HIGHPWR = 1, + ODM_BOARD_MINICARD = 2, + ODM_BOARD_SLIM = 3, + ODM_BOARD_COMBO = 4, + +}ODM_BOARD_TYPE_E; + +// ODM_CMNINFO_ONE_PATH_CCA +typedef enum tag_CCA_Path +{ + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}ODM_CCA_PATH_E; + + +typedef struct _ODM_RA_Info_ +{ + u1Byte RateID; + u4Byte RateMask; + u4Byte RAUseRate; + u1Byte RateSGI; + u1Byte RssiStaRA; + u1Byte PreRssiStaRA; + u1Byte SGIEnable; + u1Byte DecisionRate; + u1Byte PreRate; + u1Byte HighestRate; + u1Byte LowestRate; + u4Byte NscUp; + u4Byte NscDown; + u2Byte RTY[5]; + u4Byte TOTAL; + u2Byte DROP; + u1Byte Active; + u2Byte RptTime; + u1Byte RAWaitingCounter; + u1Byte RAPendingCounter; +#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! + u1Byte PTActive; // on or off + u1Byte PTTryState; // 0 trying state, 1 for decision state + u1Byte PTStage; // 0~6 + u1Byte PTStopCount; //Stop PT counter + u1Byte PTPreRate; // if rate change do PT + u1Byte PTPreRssi; // if RSSI change 5% do PT + u1Byte PTModeSS; // decide whitch rate should do PT + u1Byte RAstage; // StageRA, decide how many times RA will be done between PT + u1Byte PTSmoothFactor; +#endif +} ODM_RA_INFO_T,*PODM_RA_INFO_T; + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[1][IQK_Matrix_REG_NUM]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) +typedef struct _PathDiv_Parameter_define_ +{ + u4Byte org_5g_RegE30; + u4Byte org_5g_RegC14; + u4Byte org_5g_RegCA0; + u4Byte swt_5g_RegE30; + u4Byte swt_5g_RegC14; + u4Byte swt_5g_RegCA0; + //for 2G IQK information + u4Byte org_2g_RegC80; + u4Byte org_2g_RegC4C; + u4Byte org_2g_RegC94; + u4Byte org_2g_RegC14; + u4Byte org_2g_RegCA0; + + u4Byte swt_2g_RegC80; + u4Byte swt_2g_RegC4C; + u4Byte swt_2g_RegC94; + u4Byte swt_2g_RegC14; + u4Byte swt_2g_RegCA0; +}PATHDIV_PARA,*pPATHDIV_PARA; +#endif + + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + BOOLEAN bDPKenable; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[2]; + BOOLEAN bDoneTxpower; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + + u1Byte Delta_IQK; + u1Byte Delta_LCK; + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; +// +// ODM Dynamic common info value definition +// + +typedef struct _FAST_ANTENNA_TRAINNING_ +{ + u1Byte Bssid[6]; + u1Byte antsel_rx_keep_0; + u1Byte antsel_rx_keep_1; + u1Byte antsel_rx_keep_2; + u4Byte antSumRSSI[7]; + u4Byte antRSSIcnt[7]; + u4Byte antAveRSSI[7]; + u1Byte FAT_State; + u4Byte TrainIdx; + u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte RxIdleAnt; + BOOLEAN bBecomeLinked; + +}FAT_T,*pFAT_T; + +typedef enum _FAT_STATE +{ + FAT_NORMAL_STATE = 0, + FAT_TRAINING_STATE = 1, +}FAT_STATE_E, *PFAT_STATE_E; + +typedef enum _ANT_DIV_TYPE +{ + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, + +}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; + + + + + + + + + + + + + +// +// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. +// +#if(DM_ODM_SUPPORT_TYPE & ODM_MP) +#if (RT_PLATFORM != PLATFORM_LINUX) +typedef +#endif +struct DM_Out_Source_Dynamic_Mechanism_Structure +#else// for AP,ADSL,CE Team +typedef struct DM_Out_Source_Dynamic_Mechanism_Structure +#endif +{ + //RT_TIMER FastAntTrainingTimer; + // + // Add for different team use temporarily + // + PADAPTER Adapter; // For CE/NIC team + prtl8192cd_priv priv; // For AP/ADSL team + // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. + BOOLEAN odm_ready; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + rtl8192cd_priv fake_priv; +#endif +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + // ADSL_AP_BUILD_WORKAROUND + ADAPTER fake_adapter; +#endif + + u8Byte DebugComponents; + u4Byte DebugLevel; + +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + BOOLEAN bCckHighPower; + u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE + u1Byte ControlChannel; +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + +//--------REMOVED COMMON INFO----------// + //u1Byte PseudoMacPhyMode; + //BOOLEAN *BTCoexist; + //BOOLEAN PseudoBtCoexist; + //u1Byte OPMode; + //BOOLEAN bAPMode; + //BOOLEAN bClientMode; + //BOOLEAN bAdHocMode; + //BOOLEAN bSlaveOfDMSP; +//--------REMOVED COMMON INFO----------// + + +//1 COMMON INFORMATION + + // + // Init Value + // +//-----------HOOK BEFORE REG INIT-----------// + // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 + u1Byte SupportPlatform; + // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K + u4Byte SupportAbility; + // ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 + u1Byte SupportInterface; + // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... + u4Byte SupportICType; + // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... + u1Byte CutVersion; + // Fab Version TSMC/UMC = 0/1 + u1Byte FabVersion; + // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... + u1Byte RFType; + // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... + u1Byte BoardType; + // with external LNA NO/Yes = 0/1 + u1Byte ExtLNA; + // with external PA NO/Yes = 0/1 + u1Byte ExtPA; + // with external TRSW NO/Yes = 0/1 + u1Byte ExtTRSW; + u1Byte PatchID; //Customer ID + BOOLEAN bInHctTest; + BOOLEAN bWIFITest; + + BOOLEAN bDualMacSmartConcurrent; + u4Byte BK_SupportAbility; + u1Byte AntDivType; +//-----------HOOK BEFORE REG INIT-----------// + + // + // Dynamic Value + // +//--------- POINTER REFERENCE-----------// + + u1Byte u1Byte_temp; + BOOLEAN BOOLEAN_temp; + PADAPTER PADAPTER_temp; + + // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 + u1Byte *pMacPhyMode; + //TX Unicast byte count + u8Byte *pNumTxBytesUnicast; + //RX Unicast byte count + u8Byte *pNumRxBytesUnicast; + // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 + u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E + // Frequence band 2.4G/5G = 0/1 + u1Byte *pBandType; + // Secondary channel offset don't_care/below/above = 0/1/2 + u1Byte *pSecChOffset; + // Security mode Open/WEP/AES/TKIP = 0/1/2/3 + u1Byte *pSecurity; + // BW info 20M/40M/80M = 0/1/2 + u1Byte *pBandWidth; + // Central channel location Ch1/Ch2/.... + u1Byte *pChannel; //central channel number + // Common info for 92D DMSP + + BOOLEAN *pbGetValueFromOtherMac; + PADAPTER *pBuddyAdapter; + BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave + // Common info for Status + BOOLEAN *pbScanInProcess; + BOOLEAN *pbPowerSaving; + // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. + u1Byte *pOnePathCCA; + //pMgntInfo->AntennaTest + u1Byte *pAntennaTest; + BOOLEAN *pbNet_closed; +//--------- POINTER REFERENCE-----------// + // +//------------CALL BY VALUE-------------// + BOOLEAN bWIFI_Direct; + BOOLEAN bWIFI_Display; + BOOLEAN bLinked; + u1Byte RSSI_Min; + u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1 + BOOLEAN bIsMPChip; + BOOLEAN bOneEntryOnly; + // Common info for BTDM + BOOLEAN bBtDisabled; // BT is disabled + BOOLEAN bBtHsOperation; // BT HS mode is under progress + u1Byte btHsDigVal; // use BT rssi to decide the DIG value + BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo + BOOLEAN bBtBusy; // BT is busy. +//------------CALL BY VALUE-------------// + + //2 Define STA info. + // _ODM_STA_INFO + // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? + PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + +#if (RATE_ADAPTIVE_SUPPORT == 1) + u2Byte CurrminRptTime; + ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 +#endif + // + // 2012/02/14 MH Add to share 88E ra with other SW team. + // We need to colelct all support abilit to a proper area. + // + BOOLEAN RaSupport88E; + + // Define ........... + + // Latest packet phy info (ODM write) + ODM_PHY_DBG_INFO_T PhyDbgInfo; + //PHY_INFO_88E PhyInfo; + + // Latest packet phy info (ODM write) + ODM_MAC_INFO *pMacInfo; + //MAC_INFO_88E MacInfo; + + // Different Team independt structure?? + + // + //TX_RTP_CMN TX_retrpo; + //TX_RTP_88E TX_retrpo; + //TX_RTP_8195 TX_retrpo; + + // + //ODM Structure + // + FAT_T DM_FatTable; + DIG_T DM_DigTable; + PS_T DM_PSTable; + Pri_CCA_T DM_PriCCA; + RXHP_T DM_RXHP_Table; + FALSE_ALARM_STATISTICS FalseAlmCnt; + FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; + //#ifdef CONFIG_ANTENNA_DIVERSITY + SWAT_T DM_SWAT_Table; + BOOLEAN RSSI_test; + //#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) + //Path Div Struct + PATHDIV_PARA pathIQK; +#endif + + EDCA_T DM_EDCA_Table; + u4Byte WMMEDCA_BE; + // Copy from SD4 structure + // + // ================================================== + // + + //common + //u1Byte DM_Type; + //u1Byte PSD_Report_RXHP[80]; // Add By Gary + //u1Byte PSD_func_flag; // Add By Gary + //for DIG + //u1Byte bDMInitialGainEnable; + //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. + //for Antenna diversity + //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse + //PSTA_INFO_T RSSI_target; + + BOOLEAN *pbDriverStopped; + BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; + BOOLEAN *pinit_adpt_in_progress; + + //PSD + BOOLEAN bUserAssignLevel; + RT_TIMER PSDTimer; + u1Byte RSSI_BT; //come from BT + BOOLEAN bPSDinProcess; + BOOLEAN bDMInitialGainEnable; + + //for rate adaptive, in fact, 88c/92c fw will handle this + u1Byte bUseRAMask; + + ODM_RATE_ADAPTIVE RateAdaptive; + + + ODM_RF_CAL_T RFCalibrateInfo; + + // + // TX power tracking + // + u1Byte BbSwingIdxOfdm; + u1Byte BbSwingIdxOfdmCurrent; + u1Byte BbSwingIdxOfdmBase; + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + BOOLEAN BbSwingFlagCck; + u1Byte *mp_mode; + // + // ODM system resource. + // + + // ODM relative time. + RT_TIMER PathDivSwitchTimer; + //2011.09.27 add for Path Diversity + RT_TIMER CCKPathDiversityTimer; + RT_TIMER FastAntTrainingTimer; + + // ODM relative workitem. +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + #if USE_WORKITEM + RT_WORK_ITEM PathDivSwitchWorkitem; + RT_WORK_ITEM CCKPathDiversityWorkitem; + RT_WORK_ITEM FastAntTrainingWorkitem; + #endif +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_MP) + +#if (RT_PLATFORM != PLATFORM_LINUX) +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#else +}; +#endif + +#else// for AP,ADSL,CE Team +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#endif + + + +#if 1 //92c-series +#define ODM_RF_PATH_MAX 2 +#else //jaguar - series +#define ODM_RF_PATH_MAX 4 +#endif + +typedef enum _ODM_RF_RADIO_PATH { + ODM_RF_PATH_A = 0, //Radio Path A + ODM_RF_PATH_B = 1, //Radio Path B + ODM_RF_PATH_C = 2, //Radio Path C + ODM_RF_PATH_D = 3, //Radio Path D + // ODM_RF_PATH_MAX, //Max RF number 90 support +} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; + + typedef enum _ODM_RF_CONTENT{ + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +} ODM_RF_CONTENT; + +typedef enum _ODM_BB_Config_Type{ + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, +} ODM_BB_Config_Type, *PODM_BB_Config_Type; + +// Status code +#if (DM_ODM_SUPPORT_TYPE != ODM_MP) +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}RT_STATUS,*PRT_STATUS; +#endif // end of RT_STATUS definition + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +//#include "odm_function.h" + +//3=========================================================== +//3 DIG +//3=========================================================== + +typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition +{ + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_BACKOFF = 2, + DIG_TYPE_RX_GAIN_MIN = 3, + DIG_TYPE_RX_GAIN_MAX = 4, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}DM_DIG_OP_E; +/* +typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition +{ + CCK_PD_STAGE_LowRssi = 0, + CCK_PD_STAGE_HighRssi = 1, + CCK_PD_STAGE_MAX = 3, +}DM_CCK_PDTH_E; + +typedef enum tag_DIG_EXT_PORT_ALGO_Definition +{ + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}DM_DIG_EXT_PORT_ALG_E; + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} + +#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) + +#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) +*/ +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_SCAN_RSSI_TH 0x14 //scan return issue for LC + + +#define DM_FALSEALARM_THRESH_LOW 400 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c + +#define DM_DIG_MAX_AP 0x32 +#define DM_DIG_MIN_AP 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +//vivi 92c&92d has different definition, 20110504 +//this is for 92c +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV +#define DM_DIG_FA_TH0 0x80//0x20 +#else +#define DM_DIG_FA_TH0 0x200//0x20 +#endif +#define DM_DIG_FA_TH1 0x300//0x100 +#define DM_DIG_FA_TH2 0x400//0x200 +//this is for 92d +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +//3=========================================================== +//3 AGC RX High Power Mode +//3=========================================================== +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +//3=========================================================== +//3 EDCA +//3=========================================================== + +//3=========================================================== +//3 Dynamic Tx Power +//3=========================================================== +//Dynamic Tx Power Control Threshold +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +//3=========================================================== +//3 Tx Power Tracking +//3=========================================================== +#if 0 //mask this, since these have been defined in typdef.h, vivi +#define OFDM_TABLE_SIZE 37 +#define OFDM_TABLE_SIZE_92D 43 +#define CCK_TABLE_SIZE 33 +#endif + + +//3=========================================================== +//3 Rate Adaptive +//3=========================================================== +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 + +//3=========================================================== +//3 BB Power Save +//3=========================================================== + + +typedef enum tag_1R_CCA_Type_Definition +{ + CCA_1R =0, + CCA_2R = 1, + CCA_MAX = 2, +}DM_1R_CCA_E; + +typedef enum tag_RF_Type_Definition +{ + RF_Save =0, + RF_Normal = 1, + RF_MAX = 2, +}DM_RF_E; + +//3=========================================================== +//3 Antenna Diversity +//3=========================================================== +typedef enum tag_SW_Antenna_Switch_Definition +{ + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}DM_SWAS_E; + + +// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. +#define MAX_ANTENNA_DETECTION_CNT 10 + +// +// Extern Global Variables. +// +#define OFDM_TABLE_SIZE_92C 37 +#define OFDM_TABLE_SIZE_92D 43 +#define CCK_TABLE_SIZE 33 + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + + + +// +// check Sta pointer valid or not +// +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) +#elif (DM_ODM_SUPPORT_TYPE & ODM_MP) +#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) +#else +#define IS_STA_VALID(pSta) (pSta) +#endif +// 20100514 Joseph: Add definition for antenna switching test after link. +// This indicates two different the steps. +// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. +// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK +// with original RSSI to determine if it is necessary to switch antenna. +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +VOID ODM_Write_DIG(IN PDM_ODM_T pDM_Odm, IN u1Byte CurrentIGI); +VOID ODM_Write_CCK_CCA_Thres(IN PDM_ODM_T pDM_Odm, IN u1Byte CurCCK_CCAThres); + +VOID +ODM_SetAntenna( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Antenna); + + +#define dm_RF_Saving ODM_RF_Saving +void ODM_RF_Saving( IN PDM_ODM_T pDM_Odm, + IN u1Byte bForceInNormal ); + +#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink +VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm); + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck +VOID +ODM_TXPowerTrackingCheck( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +ODM_RAStateCheck( + IN PDM_ODM_T pDM_Odm, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_AP|ODM_ADSL)) +//============================================================ +// function prototype +//============================================================ +//#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); +VOID +ODM_ChangeDynamicInitGainThresh( + IN PDM_ODM_T pDM_Odm, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ); + +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter + ); + + +#if (DM_ODM_SUPPORT_TYPE != ODM_ADSL) +VOID +ODM_RateAdaptiveStateApInit( + IN PADAPTER Adapter , + IN PRT_WLAN_STA pEntry + ); +#endif +#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#ifdef WIFI_WMM +VOID +ODM_IotEdcaSwitch( + IN PDM_ODM_T pDM_Odm, + IN unsigned char enable + ); +#endif + +BOOLEAN +ODM_ChooseIotMainSTA( + IN PDM_ODM_T pDM_Odm, + IN PSTA_INFO_T pstat + ); +#endif + +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) +#ifdef HW_ANT_SWITCH +u1Byte +ODM_Diversity_AntennaSelect( + IN PDM_ODM_T pDM_Odm, + IN u1Byte *data +); +#endif +#endif + +#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink +VOID ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm); + +//#define SwAntDivCheckBeforeLink8192C ODM_SwAntDivCheckBeforeLink8192C +#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink8192C +BOOLEAN +ODM_SwAntDivCheckBeforeLink8192C( + IN PDM_ODM_T pDM_Odm + ); + + +#endif + +#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi +VOID ODM_SwAntDivChkPerPktRssi( + IN PDM_ODM_T pDM_Odm, + IN u1Byte StationID, + IN PODM_PHY_INFO_T pPhyInfo + ); + +#if((DM_ODM_SUPPORT_TYPE==ODM_MP)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) + +u4Byte ConvertTo_dB(u4Byte Value); + +u4Byte +GetPSDData( + PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd); + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +odm_DIGbyRSSI_LPS( + IN PDM_ODM_T pDM_Odm + ); + +u4Byte ODM_Get_Rate_Bitmap( + IN PDM_ODM_T pDM_Odm, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level); +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_MP)) +#define dm_PSDMonitorCallback odm_PSDMonitorCallback +VOID odm_PSDMonitorCallback(PRT_TIMER pTimer); + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ); + + +VOID +PatchDCTone( + IN PDM_ODM_T pDM_Odm, + pu4Byte PSD_report, + u1Byte initial_gain_psd +); +VOID +ODM_PSDMonitor( + IN PDM_ODM_T pDM_Odm + ); +VOID odm_PSD_Monitor(PDM_ODM_T pDM_Odm); +VOID odm_PSDMonitorInit(PDM_ODM_T pDM_Odm); + +VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ); + +#endif // DM_ODM_SUPPORT_TYPE + + + +VOID ODM_DMInit( IN PDM_ODM_T pDM_Odm); + +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm // For common use in the future + ); + +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ); + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ); + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm + ); + + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); +VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); + +VOID odm_PathDivChkAntSwitch(PDM_ODM_T pDM_Odm); +VOID ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ); + + +//===========================================// +// Neil Chen----2011--06--15-- + +//3 Path Diversity +//=========================================================== + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +//#define PATHDIV_ENABLE 1 + +//VOID odm_PathDivChkAntSwitch(PADAPTER Adapter,u1Byte Step); +VOID ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ); + +#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi +VOID ODM_PathDivChkPerPktRssi(PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd ); + +u8Byte +PlatformDivision64( + IN u8Byte x, + IN u8Byte y +); + + +// 20100514 Joseph: Add definition for antenna switching test after link. +// This indicates two different the steps. +// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. +// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK +// with original RSSI to determine if it is necessary to switch antenna. +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +//==================================================== +//3 PathDiV End +//==================================================== + +#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ); + +#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); +// + + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ); + + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc +); + + +#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi + +// +// 2012/01/12 MH Check afapter status. Temp fix BSOD. +// +#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ + if (pDM_Odm->Adapter == NULL)\ + {\ + return;\ + }\ + + +// +// For new definition in MP temporarily fro power tracking, +// +#define odm_TXPowerTrackingDirectCall(_Adapter) \ + IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \ + IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \ + IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\ + odm_TXPowerTrackingCallback_ThermalMeter_8188E(_Adapter) + +VOID +ODM_SetTxAntByTxInfo_88C_92D( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId + ); +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID +ODM_AntselStatistics_88C( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacId, + IN u4Byte PWDBAll, + IN BOOLEAN isCCKrate +); + +#if( DM_ODM_SUPPORT_TYPE & (ODM_MP |ODM_CE)) + +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PDM_ODM_T pDM_Odm, + IN u1Byte mode + ); + +#endif // #if((DM_ODM_SUPPORT_TYPE==ODM_MP)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void odm_dtc(PDM_ODM_T pDM_Odm); +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.c new file mode 100755 index 00000000..1d054e41 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.c @@ -0,0 +1,1184 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "odm_precomp.h" + +#if (RTL8188E_FOR_TEST_CHIP > 1) + #define READ_AND_CONFIG(ic, txt) do {\ + if (pDM_Odm->bIsMPChip)\ + READ_AND_CONFIG_MP(ic,txt);\ + else\ + READ_AND_CONFIG_TC(ic,txt);\ + } while(0) +#elif (RTL8188E_FOR_TEST_CHIP == 1) + #define READ_AND_CONFIG READ_AND_CONFIG_TC +#else + #define READ_AND_CONFIG READ_AND_CONFIG_MP +#endif + +#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm)) +#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm)) + +u1Byte +odm_QueryRxPwrPercentage( + IN s1Byte AntPower + ) +{ + if ((AntPower <= -100) || (AntPower >= 20)) + { + return 0; + } + else if (AntPower >= 0) + { + return 100; + } + else + { + return (100+AntPower); + } + +} + +#if (DM_ODM_SUPPORT_TYPE != ODM_MP) +// +// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. +// IF other SW team do not support the feature, remove this section.?? +// +s4Byte +odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( + IN OUT PDM_ODM_T pDM_Odm, + s4Byte CurrSig +) +{ + s4Byte RetSig; +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + //if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + { + // Step 1. Scale mapping. + // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. + // 20100426 Joseph: Modify Signal strength mapping. + // This modification makes the RSSI indication similar to Intel solution. + // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. + if(CurrSig >= 54 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig>=42 && CurrSig <= 53 ) + { + RetSig = 95; + } + else if(CurrSig>=36 && CurrSig <= 41 ) + { + RetSig = 74 + ((CurrSig - 36) *20)/6; + } + else if(CurrSig>=33 && CurrSig <= 35 ) + { + RetSig = 65 + ((CurrSig - 33) *8)/2; + } + else if(CurrSig>=18 && CurrSig <= 32 ) + { + RetSig = 62 + ((CurrSig - 18) *2)/15; + } + else if(CurrSig>=15 && CurrSig <= 17 ) + { + RetSig = 33 + ((CurrSig - 15) *28)/2; + } + else if(CurrSig>=10 && CurrSig <= 14 ) + { + RetSig = 39; + } + else if(CurrSig>=8 && CurrSig <= 9 ) + { + RetSig = 33; + } + else if(CurrSig <= 8 ) + { + RetSig = 19; + } + } +#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP) + return RetSig; +} + +s4Byte +odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore( + IN OUT PDM_ODM_T pDM_Odm, + s4Byte CurrSig +) +{ + s4Byte RetSig; +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + //if(pDM_Odm->SupportInterface == ODM_ITRF_USB) + { + // Netcore request this modification because 2009.04.13 SU driver use it. + if(CurrSig >= 31 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 90 + ((CurrSig - 20) / 1); + } + else if(CurrSig >= 11 && CurrSig <= 20) + { + RetSig = 80 + ((CurrSig - 10) / 1); + } + else if(CurrSig >= 7 && CurrSig <= 10) + { + RetSig = 69 + (CurrSig - 7); + } + else if(CurrSig == 6) + { + RetSig = 54; + } + else if(CurrSig == 5) + { + RetSig = 45; + } + else if(CurrSig == 4) + { + RetSig = 36; + } + else if(CurrSig == 3) + { + RetSig = 27; + } + else if(CurrSig == 2) + { + RetSig = 18; + } + else if(CurrSig == 1) + { + RetSig = 9; + } + else + { + RetSig = CurrSig; + } + } +#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP) + return RetSig; +} + + +s4Byte +odm_SignalScaleMapping_92CSeries( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig +) +{ + s4Byte RetSig; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + { + // Step 1. Scale mapping. + if(CurrSig >= 61 && CurrSig <= 100) + { + RetSig = 90 + ((CurrSig - 60) / 4); + } + else if(CurrSig >= 41 && CurrSig <= 60) + { + RetSig = 78 + ((CurrSig - 40) / 2); + } + else if(CurrSig >= 31 && CurrSig <= 40) + { + RetSig = 66 + (CurrSig - 30); + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 54 + (CurrSig - 20); + } + else if(CurrSig >= 5 && CurrSig <= 20) + { + RetSig = 42 + (((CurrSig - 5) * 2) / 3); + } + else if(CurrSig == 4) + { + RetSig = 36; + } + else if(CurrSig == 3) + { + RetSig = 27; + } + else if(CurrSig == 2) + { + RetSig = 18; + } + else if(CurrSig == 1) + { + RetSig = 9; + } + else + { + RetSig = CurrSig; + } + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) ) + { + if(CurrSig >= 51 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig >= 41 && CurrSig <= 50) + { + RetSig = 80 + ((CurrSig - 40)*2); + } + else if(CurrSig >= 31 && CurrSig <= 40) + { + RetSig = 66 + (CurrSig - 30); + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 54 + (CurrSig - 20); + } + else if(CurrSig >= 10 && CurrSig <= 20) + { + RetSig = 42 + (((CurrSig - 10) * 2) / 3); + } + else if(CurrSig >= 5 && CurrSig <= 9) + { + RetSig = 22 + (((CurrSig - 5) * 3) / 2); + } + else if(CurrSig >= 1 && CurrSig <= 4) + { + RetSig = 6 + (((CurrSig - 1) * 3) / 2); + } + else + { + RetSig = CurrSig; + } + } +#endif + return RetSig; +} +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig +) +{ + if( (pDM_Odm->SupportPlatform == ODM_MP) && + (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO + (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore + { + return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); + } + else if( (pDM_Odm->SupportPlatform == ODM_MP) && + (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && + (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) + { + return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); + } + else{ + return odm_SignalScaleMapping_92CSeries(pDM_Odm,CurrSig); + } + +} +#endif + +//pMgntInfo->CustomerID == RT_CID_819x_Lenovo +static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( + IN PDM_ODM_T pDM_Odm, + IN u1Byte isCCKrate, + IN u1Byte PWDB_ALL, + IN u1Byte path, + IN u1Byte RSSI +) +{ + u1Byte SQ; +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) + // mapping to 5 bars for vista signal strength + // signal quality in driver will be displayed to signal strength + if(isCCKrate){ + // in vista. + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 22 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 18 && PWDB_ALL < 22) + SQ = 40; + else + SQ = 20; + } + else{//OFDM rate + + // mapping to 5 bars for vista signal strength + // signal quality in driver will be displayed to signal strength + // in vista. + if(RSSI >= 50) + SQ = 100; + else if(RSSI >= 35 && RSSI < 50) + SQ = 80; + else if(RSSI >= 22 && RSSI < 35) + SQ = 60; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } +#endif + return SQ; +} + +static u1Byte +odm_EVMdbToPercentage( + IN s1Byte Value + ) +{ + // + // -33dB~0dB to 0%~99% + // + s1Byte ret_val; + + ret_val = Value; + //ret_val /= 2; + + //ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x \n", ret_val, ret_val)); + + if(ret_val >= 0) + ret_val = 0; + if(ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val*=3; + + if(ret_val == 99) + ret_val = 100; + + return(ret_val); +} + + + +VOID +odm_RxPhyStatus92CSeries_Parsing( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u1Byte i, Max_spatial_stream; + s1Byte rx_pwr[4], rx_pwr_all=0; + u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT; + u1Byte RSSI, total_rssi=0; + u1Byte isCCKrate=0; + u1Byte rf_rx_num = 0; + u1Byte cck_highpwr = 0; + u1Byte LNA_idx, VGA_idx; + + PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus; + + isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE; + + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + + + if(isCCKrate) + { + u1Byte report; + u1Byte cck_agc_rpt; + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + // + // (1)Hardware does not provide RSSI for CCK + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + + //if(pHalData->eRFPowerState == eRfOn) + cck_highpwr = pDM_Odm->bCckHighPower; + //else + // cck_highpwr = FALSE; + + cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; + + //2011.11.28 LukeLee: 88E use different LNA & VGA gain table + //The RSSI formula should be modified according to the gain table + //In 88E, cck_highpwr is always set to 1 + if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) + { + LNA_idx = ((cck_agc_rpt & 0xE0) >>5); + VGA_idx = (cck_agc_rpt & 0x1F); + switch(LNA_idx) + { + case 7: + if(VGA_idx <= 27) + rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2 + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0 + break; + case 5: + rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5 + break; + case 4: + rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4 + break; + case 3: + //rx_pwr_all = -28 + 2*(7-VGA_idx); //VGA_idx = 7~0 + rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0 + break; + case 2: + if(cck_highpwr) + rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0 + else + rx_pwr_all = -6+ 2*(5-VGA_idx); + break; + case 1: + rx_pwr_all = 8-2*VGA_idx; + break; + case 0: + rx_pwr_all = 14-2*VGA_idx; + break; + default: + //DbgPrint("CCK Exception default\n"); + break; + } + rx_pwr_all += 6; + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + if(cck_highpwr == FALSE) + { + if(PWDB_ALL >= 80) + PWDB_ALL = ((PWDB_ALL-80)<<1)+((PWDB_ALL-80)>>1)+80; + else if((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) + PWDB_ALL += 3; + if(PWDB_ALL>100) + PWDB_ALL = 100; + } + } + else + { + if(!cck_highpwr) + { + report =( cck_agc_rpt & 0xc0 )>>6; + switch(report) + { + // 03312009 modified by cosa + // Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion + // Note: different RF with the different RNA gain. + case 0x3: + rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); + break; + case 0x2: + rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); + break; + case 0x1: + rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); + break; + case 0x0: + rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); + break; + } + } + else + { + //report = pDrvInfo->cfosho[0] & 0x60; + //report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; + + report = (cck_agc_rpt & 0x60)>>5; + switch(report) + { + case 0x3: + rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x2: + rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f)<<1); + break; + case 0x1: + rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x0: + rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f)<<1) ; + break; + } + } + + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + //Modification for ext-LNA board + if(pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) + { + if((cck_agc_rpt>>7) == 0){ + PWDB_ALL = (PWDB_ALL>94)?100:(PWDB_ALL +6); + } + else + { + if(PWDB_ALL > 38) + PWDB_ALL -= 16; + else + PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12); + } + + //CCK modification + if(PWDB_ALL > 25 && PWDB_ALL <= 60) + PWDB_ALL += 6; + //else if (PWDB_ALL <= 25) + // PWDB_ALL += 8; + } + else//Modification for int-LNA board + { + if(PWDB_ALL > 99) + PWDB_ALL -= 8; + else if(PWDB_ALL > 50 && PWDB_ALL <= 68) + PWDB_ALL += 4; + } + } + + pPhyInfo->RxPWDBAll = PWDB_ALL; +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + // + // (3) Get Signal Quality (EVM) + // + if(pPktinfo->bPacketMatchBSSID) + { + u1Byte SQ,SQ_rpt; + + if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo + SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); + } + else if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ + SQ = 100; + } + else{ + SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; + + if(SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64-SQ_rpt) * 100) / 44; + + } + + //DbgPrint("cck SQ = %d\n", SQ); + pPhyInfo->SignalQuality = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + } + } + else //is OFDM rate + { + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + // + // (1)Get RSSI for HT rate + // + + for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) + { + // 2008/01/30 MH we will judge RF RX path now. + if (pDM_Odm->RFPathRxEnable & BIT(i)) + rf_rx_num++; + //else + //continue; + + rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + pPhyInfo->RxPwr[i] = rx_pwr[i]; + #endif + + /* Translate DBM to percentage. */ + RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); + total_rssi += RSSI; + //RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); + + //Modification for ext-LNA board + if(pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) + { + if((pPhyStaRpt->path_agc[i].trsw) == 1) + RSSI = (RSSI>94)?100:(RSSI +6); + else + RSSI = (RSSI<=16)?(RSSI>>3):(RSSI -16); + + if((RSSI <= 34) && (RSSI >=4)) + RSSI -= 4; + } + + pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI; + + #if (DM_ODM_SUPPORT_TYPE & (/*ODM_MP|*/ODM_CE|ODM_AP|ODM_ADSL)) + //Get Rx snr value in DB + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2); + #endif + + /* Record Signal Strength for next packet */ + if(pPktinfo->bPacketMatchBSSID) + { + if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)) + { + if(i==ODM_RF_PATH_A) + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI); + + } + + } + } + + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; + //RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n", PWDB_ALL)); + + PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + //RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n",PWDB_ALL)); + + pPhyInfo->RxPWDBAll = PWDB_ALL; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); + #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; + pPhyInfo->RxPower = rx_pwr_all; + pPhyInfo->RecvSignalPower = rx_pwr_all; + #endif + + if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){ + //do nothing + } + else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo + // + // (3)EVM of HT rate + // + if(pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15) + Max_spatial_stream = 2; //both spatial stream make sense + else + Max_spatial_stream = 1; //only spatial stream 1 makes sense + + for(i=0; i>= 1" because the compilor of free build environment + // fill most significant bit to "zero" when doing shifting operation which may change a negative + // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. + EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm + + //RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", + //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); + + if(pPktinfo->bPacketMatchBSSID) + { + if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only + { + pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff); + } + pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff); + } + } + } + + } +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + //UI BSS List signal strength(in percentage), make it good looking, from 0~100. + //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). + if(isCCKrate) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ + pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, PWDB_ALL));//PWDB_ALL; +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL; +#endif + } + else + { + if (rf_rx_num != 0) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ + pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, total_rssi/=rf_rx_num));//PWDB_ALL; +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num)); +#endif + } + } +#endif + + //For 92C/92D HW (Hybrid) Antenna Diversity +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) + pDM_SWAT_Table->antsel = pPhyStaRpt->ant_sel; + //For 88E HW Antenna Diversity + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; +#endif +} + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ) +{ + +} + +VOID +odm_Process_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm, + IN PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + + s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave; + u1Byte isCCKrate=0; + u1Byte RSSI_max, RSSI_min, i; + u4Byte OFDM_pkt=0; + u4Byte Weighting=0; + + PSTA_INFO_T pEntry; + + if(pPktinfo->StationID == 0xFF) + return; + + // 2011/11/17 MH Need to debug + //if (pDM_Odm->SupportPlatform == ODM_MP) + { + + } + + pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; + if(!IS_STA_VALID(pEntry) ){ + return; + } + if((!pPktinfo->bPacketMatchBSSID) ) + { + return; + } + + isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE; + +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1)) + if(pDM_Odm->SupportICType & ODM_RTL8192C|ODM_RTL8192D) + { + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) + { + //if(pPktinfo->bPacketBeacon) + //{ + // DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate); + //} + ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID, pPhyInfo->RxPWDBAll, isCCKrate); + } + } +#endif + //-----------------Smart Antenna Debug Message------------------// +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + u1Byte antsel_tr_mux; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + { + if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) + { + if(pPktinfo->bPacketToSelf) //(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) + { + antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; + pDM_FatTable->antSumRSSI[antsel_tr_mux] += pPhyInfo->RxPWDBAll; + pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", + //pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); + + } + } + } + else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) + { + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) + { + antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", + // pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); + + ODM_AntselStatistics_88E(pDM_Odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); + } + } + + } +#endif +#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) + //-----------------Smart Antenna Debug Message------------------// + + UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; + UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; + UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) + { + + if(!isCCKrate)//ofdm rate + { + if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){ + RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + } + else + { + //DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d \n", + //pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); + + + if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]) + { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + } + else + { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + } + if((RSSI_max -RSSI_min) < 3) + RSSI_Ave = RSSI_max; + else if((RSSI_max -RSSI_min) < 6) + RSSI_Ave = RSSI_max - 1; + else if((RSSI_max -RSSI_min) < 10) + RSSI_Ave = RSSI_max - 2; + else + RSSI_Ave = RSSI_max - 3; + } + + //1 Process OFDM RSSI + if(UndecoratedSmoothedOFDM <= 0) // initialize + { + UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; + } + else + { + if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM) + { + UndecoratedSmoothedOFDM = + ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + + (RSSI_Ave)) /(Rx_Smooth_Factor); + UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; + } + else + { + UndecoratedSmoothedOFDM = + ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + + (RSSI_Ave)) /(Rx_Smooth_Factor); + } + } + + pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; + + } + else + { + RSSI_Ave = pPhyInfo->RxPWDBAll; + + //1 Process CCK RSSI + if(UndecoratedSmoothedCCK <= 0) // initialize + { + UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; + } + else + { + if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK) + { + UndecoratedSmoothedCCK = + ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + + (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); + UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; + } + else + { + UndecoratedSmoothedCCK = + ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + + (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); + } + } + pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; + } + + //if(pEntry) + { + //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI + if(pEntry->rssi_stat.ValidBit >= 64) + pEntry->rssi_stat.ValidBit = 64; + else + pEntry->rssi_stat.ValidBit++; + + for(i=0; irssi_stat.ValidBit; i++) + OFDM_pkt += (u1Byte)(pEntry->rssi_stat.PacketMap>>i)&BIT0; + + if(pEntry->rssi_stat.ValidBit == 64) + { + Weighting = ((OFDM_pkt<<4) > 64)?64:(OFDM_pkt<<4); + UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; + } + else + { + if(pEntry->rssi_stat.ValidBit != 0) + UndecoratedSmoothedPWDB = (OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit; + else + UndecoratedSmoothedPWDB = 0; + } + + pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; + pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; + pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + + //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); + //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", + // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); + + } + + } +} + + +// +// Endianness before calling this API +// +VOID +ODM_PhyStatusQuery_92CSeries( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + + odm_RxPhyStatus92CSeries_Parsing( + pDM_Odm, + pPhyInfo, + pPhyStatus, + pPktinfo); + + if( pDM_Odm->RSSI_test == TRUE) + { + // Select the packets to do RSSI checking for antenna switching. + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon ) + { + /* + #if 0//(DM_ODM_SUPPORT_TYPE == ODM_MP) + dm_SWAW_RSSI_Check( + Adapter, + (tmppAdapter!=NULL)?(tmppAdapter==Adapter):TRUE, + bPacketMatchBSSID, + pEntry, + pRfd); + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + // Select the packets to do RSSI checking for antenna switching. + //odm_SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll); + #endif + */ + ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo); + } + } + else + { + odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo); + } + +} + + + +// +// Endianness before calling this API +// +VOID +ODM_PhyStatusQuery_JaguarSeries( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + + +} + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ +#if 0 // How to jaguar jugar series?? + if(pDM_Odm->SupportICType >= ODM_RTL8195 ) + { + ODM_PhyStatusQuery_JaguarSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); + } + else +#endif + { + ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); + } +} + +// For future use. +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ) +{ + // 2011/10/19 Driver team will handle in the future. + +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP)) + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Content, + IN ODM_RF_RADIO_PATH_E eRFPath + ) +{ + //RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n")); +#if (RTL8723A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723A) + { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8723A,_RadioA_1T_); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8723RadioA_1TArray\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8723RadioB_1TArray\n")); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); + //rtStatus = RT_STATUS_SUCCESS; +#endif +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG(8188E,_RadioA_1T_); + //else if(eRFPath == ODM_RF_PATH_B) + // READ_AND_CONFIG(8188E,_RadioB_1T_); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); + //rtStatus = RT_STATUS_SUCCESS; +#endif + return HAL_STATUS_SUCCESS; +} + + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ) +{ +#if (RTL8723A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + + if(ConfigType == CONFIG_BB_PHY_REG) + { + READ_AND_CONFIG_MP(8723A,_PHY_REG_1T_); + } + else if(ConfigType == CONFIG_BB_AGC_TAB) + { + READ_AND_CONFIG_MP(8723A,_AGC_TAB_1T_); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n")); + } +#endif + +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + + if(ConfigType == CONFIG_BB_PHY_REG) + { + READ_AND_CONFIG(8188E,_PHY_REG_1T_); + } +// else if(ConfigType == ODM_BaseBand_Config_PHY_REG_MP) +// { + //READ_AND_CONFIG(8188E,_PHY_REG_MP_); +// } + else if(ConfigType == CONFIG_BB_AGC_TAB) + { + READ_AND_CONFIG(8188E,_AGC_TAB_1T_); + } + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + { + READ_AND_CONFIG(8188E,_PHY_REG_PG_); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n")); + } + } +#endif + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte result = HAL_STATUS_SUCCESS; +#if (RTL8723A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723A) + { + READ_AND_CONFIG_MP(8723A,_MAC_REG_); + } +#endif +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + result = READ_AND_CONFIG(8188E,_MAC_REG_); + } +#endif + + return result; +} + + +#endif // end of (#if DM_ODM_SUPPORT_TYPE) + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.h new file mode 100755 index 00000000..9b53a8aa --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_HWConfig.h @@ -0,0 +1,195 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + +//============================================================ +// Definition +//============================================================ +// +//----------------------------------------------------------- +// CCK Rates, TxHT = 0 +#define DESC92C_RATE1M 0x00 +#define DESC92C_RATE2M 0x01 +#define DESC92C_RATE5_5M 0x02 +#define DESC92C_RATE11M 0x03 + +// OFDM Rates, TxHT = 0 +#define DESC92C_RATE6M 0x04 +#define DESC92C_RATE9M 0x05 +#define DESC92C_RATE12M 0x06 +#define DESC92C_RATE18M 0x07 +#define DESC92C_RATE24M 0x08 +#define DESC92C_RATE36M 0x09 +#define DESC92C_RATE48M 0x0a +#define DESC92C_RATE54M 0x0b + +// MCS Rates, TxHT = 1 +#define DESC92C_RATEMCS0 0x0c +#define DESC92C_RATEMCS1 0x0d +#define DESC92C_RATEMCS2 0x0e +#define DESC92C_RATEMCS3 0x0f +#define DESC92C_RATEMCS4 0x10 +#define DESC92C_RATEMCS5 0x11 +#define DESC92C_RATEMCS6 0x12 +#define DESC92C_RATEMCS7 0x13 +#define DESC92C_RATEMCS8 0x14 +#define DESC92C_RATEMCS9 0x15 +#define DESC92C_RATEMCS10 0x16 +#define DESC92C_RATEMCS11 0x17 +#define DESC92C_RATEMCS12 0x18 +#define DESC92C_RATEMCS13 0x19 +#define DESC92C_RATEMCS14 0x1a +#define DESC92C_RATEMCS15 0x1b +#define DESC92C_RATEMCS15_SG 0x1c +#define DESC92C_RATEMCS32 0x20 + + +//============================================================ +// structure and define +//============================================================ + +typedef struct _Phy_Rx_AGC_Info +{ + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain:7,trsw:1; + #else + u1Byte trsw:1,gain:7; + #endif +} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T; + +typedef struct _Phy_Status_Rpt_8192cd +{ + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_corr[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_rpt_b_ofdm_cfosho_b; + u1Byte rsvd_1;//ch_corr_msb; + u1Byte noise_power_db_msb; + u1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte noise_power_db_lsb; + u1Byte rsvd_2[3]; + u1Byte stream_csi[2]; + u1Byte stream_target_csi[2]; + s1Byte sig_evm; + u1Byte rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1; + u1Byte sgi_en:1; + u1Byte rxsc:2; + u1Byte idle_long:1; + u1Byte r_ant_train_en:1; + u1Byte ant_sel_b:1; + u1Byte ant_sel:1; +#else // _BIG_ENDIAN_ + u1Byte ant_sel:1; + u1Byte ant_sel_b:1; + u1Byte r_ant_train_en:1; + u1Byte idle_long:1; + u1Byte rxsc:2; + u1Byte sgi_en:1; + u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1; +#endif +} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T; + + +typedef struct _Phy_Status_Rpt_8195 +{ + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_num[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_bb_pwr_ofdm_cfosho_b; + u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition) + u1Byte rsvd_1; + u1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte rsvd_2[2]; + u1Byte stream_snr[2]; + u1Byte stream_csi[2]; + u1Byte rsvd_3[2]; + s1Byte sig_evm; + u1Byte rsvd_4; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_anta:3; + u1Byte antidx_antb:3; + u1Byte rsvd_5:2; +#else // _BIG_ENDIAN_ + u1Byte rsvd_5:2; + u1Byte antidx_antb:3; + u1Byte antidx_anta:3; +#endif +} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T; + + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ); + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ); + +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ); +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP)) +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Content, + IN ODM_RF_RADIO_PATH_E eRFPath + ); + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ); + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ); +#endif + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11AC.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11AC.h new file mode 100755 index 00000000..b2a318a9 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11AC.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +//2 RF REG LIST + + + +//2 BB REG LIST +//PAGE 8 +//PAGE 9 +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +//PAGE A +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +//PAGE C +#define ODM_REG_IGI_A_11AC 0xC50 +//PAGE E +#define ODM_REG_IGI_B_11AC 0xE50 +//PAGE F +#define ODM_REG_OFDM_FA_11AC 0xF48 + + +//2 MAC REG LIST + + + + +//DIG Related +#define ODM_BIT_IGI_11AC 0xFFFFFFFF + + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11N.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11N.h new file mode 100755 index 00000000..841b1b42 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_RegDefine11N.h @@ -0,0 +1,172 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + + +//2 RF REG LIST +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +//PAGE 9 +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +//PAGE A +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +//PAGE B +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +//PAGE C +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +//PAGE D +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +//PAGE E +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC + + + + + + + +//2 MAC REG LIST +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +//DIG Related +#define ODM_BIT_IGI_11N 0x0000007F + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.c new file mode 100755 index 00000000..7db60cf5 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.c @@ -0,0 +1,627 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "odm_precomp.h" + +VOID +ODM_InitDebugSetting( + IN PDM_ODM_T pDM_Odm + ) +{ +pDM_Odm->DebugLevel = ODM_DBG_TRACE; + +pDM_Odm->DebugComponents = +\ +#if DBG +//BB Functions +// ODM_COMP_DIG | +// ODM_COMP_RA_MASK | +// ODM_COMP_DYNAMIC_TXPWR | +// ODM_COMP_FA_CNT | +// ODM_COMP_RSSI_MONITOR | +// ODM_COMP_CCK_PD | +// ODM_COMP_ANT_DIV | +// ODM_COMP_PWR_SAVE | +// ODM_COMP_PWR_TRAIN | +// ODM_COMP_RATE_ADAPTIVE | +// ODM_COMP_PATH_DIV | +// ODM_COMP_DYNAMIC_PRICCA | +// ODM_COMP_RXHP | + +//MAC Functions +// ODM_COMP_EDCA_TURBO | +// ODM_COMP_EARLY_MODE | +//RF Functions +// ODM_COMP_TX_PWR_TRACK | +// ODM_COMP_RX_GAIN_TRACK | +// ODM_COMP_CALIBRATION | +//Common +// ODM_COMP_COMMON | +// ODM_COMP_INIT | +#endif + 0; +} + +#if 0 +/*------------------Declare variable----------------------- +// Define debug flag array for common debug print macro. */ +u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX]; + +/* Define debug print header for every service module. */ +ODM_DBGP_HEAD_T ODM_DBGP_Head; + + +/*----------------------------------------------------------------------------- + * Function: DBGP_Flag_Init + * + * Overview: Refresh all debug print control flag content to zero. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 10/20/2006 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void ODM_DBGP_Flag_Init(void) +{ + u1Byte i; + + for (i = 0; i < ODM_DBGP_TYPE_MAX; i++) + { + ODM_DBGP_Type[i] = 0; + } + +#ifndef ADSL_AP_BUILD_WORKAROUND +#if DBG + // 2010/06/02 MH Free build driver can not out any debug message!!! + // Init Debug flag enable condition + + ODM_DBGP_Type[FINIT] = \ +// INIT_EEPROM | +// INIT_TxPower | +// INIT_IQK | +// INIT_RF | + 0; + + ODM_DBGP_Type[FDM] = \ +// WA_IOT | +// DM_PWDB | +// DM_Monitor | +// DM_DIG | +// DM_EDCA_Turbo | +// DM_BT30 | + 0; + + ODM_DBGP_Type[FIOCTL] = \ +// IOCTL_IRP | +// IOCTL_IRP_DETAIL | +// IOCTL_IRP_STATISTICS | +// IOCTL_IRP_HANDLE | +// IOCTL_BT_HCICMD | +// IOCTL_BT_HCICMD_DETAIL | +// IOCTL_BT_HCICMD_EXT | +// IOCTL_BT_EVENT | +// IOCTL_BT_EVENT_DETAIL | +// IOCTL_BT_EVENT_PERIODICAL | +// IOCTL_BT_TX_ACLDATA | +// IOCTL_BT_TX_ACLDATA_DETAIL | +// IOCTL_BT_RX_ACLDATA | +// IOCTL_BT_RX_ACLDATA_DETAIL | +// IOCTL_BT_TP | +// IOCTL_STATE | +// IOCTL_BT_LOGO | +// IOCTL_CALLBACK_FUN | +// IOCTL_PARSE_BT_PKT | + 0; + + ODM_DBGP_Type[FBT] = \ +// BT_TRACE | + 0; + + ODM_DBGP_Type[FEEPROM] = \ +// EEPROM_W | +// EFUSE_PG | +// EFUSE_READ_ALL | +// EFUSE_ANALYSIS | +// EFUSE_PG_DETAIL | + 0; + + ODM_DBGP_Type[FDBG_CTRL] = \ +// DBG_CTRL_TRACE | +// DBG_CTRL_INBAND_NOISE | + 0; + + // 2011/07/20 MH Add for short cut + ODM_DBGP_Type[FSHORT_CUT] = \ +// SHCUT_TX | +// SHCUT_RX | + 0; + +#endif +#endif + /* Define debug header of every service module. */ + //ODM_DBGP_Head.pMANS = "\n\r[MANS] "; + //ODM_DBGP_Head.pRTOS = "\n\r[RTOS] "; + //ODM_DBGP_Head.pALM = "\n\r[ALM] "; + //ODM_DBGP_Head.pPEM = "\n\r[PEM] "; + //ODM_DBGP_Head.pCMPK = "\n\r[CMPK] "; + //ODM_DBGP_Head.pRAPD = "\n\r[RAPD] "; + //ODM_DBGP_Head.pTXPB = "\n\r[TXPB] "; + //ODM_DBGP_Head.pQUMG = "\n\r[QUMG] "; + +} /* DBGP_Flag_Init */ + +#endif + + +#if 0 +u4Byte GlobalDebugLevel = DBG_LOUD; +// +// 2009/06/22 MH Allow Fre build to print none debug info at init time. +// +#if DBG +u8Byte GlobalDebugComponents = \ +// COMP_TRACE | +// COMP_DBG | +// COMP_INIT | +// COMP_OID_QUERY | +// COMP_OID_SET | +// COMP_RECV | +// COMP_SEND | +// COMP_IO | +// COMP_POWER | +// COMP_MLME | +// COMP_SCAN | +// COMP_SYSTEM | +// COMP_SEC | +// COMP_AP | +// COMP_TURBO | +// COMP_QOS | +// COMP_AUTHENTICATOR | +// COMP_BEACON | +// COMP_ANTENNA | +// COMP_RATE | +// COMP_EVENTS | +// COMP_FPGA | +// COMP_RM | +// COMP_MP | +// COMP_RXDESC | +// COMP_CKIP | +// COMP_DIG | +// COMP_TXAGC | +// COMP_HIPWR | +// COMP_HALDM | +// COMP_RSNA | +// COMP_INDIC | +// COMP_LED | +// COMP_RF | +// COMP_DUALMACSWITCH | +// COMP_EASY_CONCURRENT | + +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! +//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! + +// COMP_HT | +// COMP_POWER_TRACKING | +// COMP_RX_REORDER | +// COMP_AMSDU | +// COMP_WPS | +// COMP_RATR | +// COMP_RESET | +// COMP_CMD | +// COMP_EFUSE | +// COMP_MESH_INTERWORKING | +// COMP_CCX | +// COMP_IOCTL | +// COMP_GP | +// COMP_TXAGG | +// COMP_BB_POWERSAVING | +// COMP_SWAS | +// COMP_P2P | +// COMP_MUX | +// COMP_FUNC | +// COMP_TDLS | +// COMP_OMNIPEEK | +// COMP_PSD | + 0; + + +#else +#define FuncEntry +#define FuncExit +u8Byte GlobalDebugComponents = 0; +#endif + +#if (RT_PLATFORM==PLATFORM_LINUX) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) +EXPORT_SYMBOL(GlobalDebugComponents); +EXPORT_SYMBOL(GlobalDebugLevel); +#endif +#endif + +/*------------------Declare variable----------------------- +// Define debug flag array for common debug print macro. */ +u4Byte DBGP_Type[DBGP_TYPE_MAX]; + +/* Define debug print header for every service module. */ +DBGP_HEAD_T DBGP_Head; + + +/*----------------------------------------------------------------------------- + * Function: DBGP_Flag_Init + * + * Overview: Refresh all debug print control flag content to zero. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 10/20/2006 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void DBGP_Flag_Init(void) +{ + u1Byte i; + + for (i = 0; i < DBGP_TYPE_MAX; i++) + { + DBGP_Type[i] = 0; + } + +#if DBG + // 2010/06/02 MH Free build driver can not out any debug message!!! + // Init Debug flag enable condition + + DBGP_Type[FINIT] = \ +// INIT_EEPROM | +// INIT_TxPower | +// INIT_IQK | +// INIT_RF | + 0; + + DBGP_Type[FDM] = \ +// WA_IOT | +// DM_PWDB | +// DM_Monitor | +// DM_DIG | +// DM_EDCA_Turbo | +// DM_BT30 | + 0; + + DBGP_Type[FIOCTL] = \ +// IOCTL_IRP | +// IOCTL_IRP_DETAIL | +// IOCTL_IRP_STATISTICS | +// IOCTL_IRP_HANDLE | +// IOCTL_BT_HCICMD | +// IOCTL_BT_HCICMD_DETAIL | +// IOCTL_BT_HCICMD_EXT | +// IOCTL_BT_EVENT | +// IOCTL_BT_EVENT_DETAIL | +// IOCTL_BT_EVENT_PERIODICAL | +// IOCTL_BT_TX_ACLDATA | +// IOCTL_BT_TX_ACLDATA_DETAIL | +// IOCTL_BT_RX_ACLDATA | +// IOCTL_BT_RX_ACLDATA_DETAIL | +// IOCTL_BT_TP | +// IOCTL_STATE | +// IOCTL_BT_LOGO | +// IOCTL_CALLBACK_FUN | +// IOCTL_PARSE_BT_PKT | + 0; + + DBGP_Type[FBT] = \ +// BT_TRACE | + 0; + + DBGP_Type[FEEPROM] = \ +// EEPROM_W | +// EFUSE_PG | +// EFUSE_READ_ALL | +// EFUSE_ANALYSIS | +// EFUSE_PG_DETAIL | + 0; + + DBGP_Type[FDBG_CTRL] = \ +// DBG_CTRL_TRACE | +// DBG_CTRL_INBAND_NOISE | + 0; + + // 2011/07/20 MH Add for short cut + DBGP_Type[FSHORT_CUT] = \ +// SHCUT_TX | +// SHCUT_RX | + 0; + +#endif + /* Define debug header of every service module. */ + DBGP_Head.pMANS = "\n\r[MANS] "; + DBGP_Head.pRTOS = "\n\r[RTOS] "; + DBGP_Head.pALM = "\n\r[ALM] "; + DBGP_Head.pPEM = "\n\r[PEM] "; + DBGP_Head.pCMPK = "\n\r[CMPK] "; + DBGP_Head.pRAPD = "\n\r[RAPD] "; + DBGP_Head.pTXPB = "\n\r[TXPB] "; + DBGP_Head.pQUMG = "\n\r[QUMG] "; + +} /* DBGP_Flag_Init */ + + +/*----------------------------------------------------------------------------- + * Function: DBG_PrintAllFlag + * + * Overview: Print All debug flag + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 12/10/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void DBG_PrintAllFlag(void) +{ + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n")); +} // DBG_PrintAllFlag + + +extern void DBG_PrintAllComp(void) +{ + u1Byte i; + + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n")); + + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents)); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP =")); + for (i = 0; i < 64; i++) + { + if (GlobalDebugComponents & ((u8Byte)0x1 << i) ) + { + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i)); + } + } + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n")); + +} // DBG_PrintAllComp + + +/*----------------------------------------------------------------------------- + * Function: DBG_PrintFlagEvent + * + * Overview: Print dedicated debug flag event + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 12/10/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void DBG_PrintFlagEvent(u1Byte DbgFlag) +{ + switch(DbgFlag) + { + case FQoS: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n")); + break; + + case FTX: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n")); + break; + + case FRX: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n")); + break; + + case FSEC: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n")); + break; + + case FMGNT: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n")); + break; + + case FMLME: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n")); + break; + + case FRESOURCE: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n")); + break; + + case FBEACON: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n")); + break; + + case FISR: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n")); + break; + + case FPHY: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n")); + break; + + case FMP: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n")); + break; + + case FEEPROM: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n")); + break; + + case FPWR: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n")); + break; + + case FDM: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n")); + break; + + case FDBG_CTRL: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n")); + break; + + case FC2H: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n")); + break; + + case FBT: + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n")); + ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n")); + break; + + default: + break; + } + +} // DBG_PrintFlagEvent + + +extern void DBG_DumpMem(const u1Byte DbgComp, + const u1Byte DbgLevel, + pu1Byte pMem, + u2Byte Len) +{ + u2Byte i; + + for (i=0;i<((Len>>3) + 1);i++) + { + ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n", + *(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)), + *(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7)))); + + } +} + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.h new file mode 100755 index 00000000..f8670c9a --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_debug.h @@ -0,0 +1,905 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + + +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE()! +// +#define ODM_DBG_OFF 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define ODM_DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define ODM_DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define ODM_DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define ODM_DBG_TRACE 5 + +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +//BB Functions +#define ODM_COMP_DIG BIT0 +#define ODM_COMP_RA_MASK BIT1 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_CCK_PD BIT5 +#define ODM_COMP_ANT_DIV BIT6 +#define ODM_COMP_PWR_SAVE BIT7 +#define ODM_COMP_PWR_TRAIN BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PATH_DIV BIT10 +#define ODM_COMP_PSD BIT11 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_RXHP BIT13 +//MAC Functions +#define ODM_COMP_EDCA_TURBO BIT16 +#define ODM_COMP_EARLY_MODE BIT17 +//RF Functions +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_RX_GAIN_TRACK BIT25 +#define ODM_COMP_CALIBRATION BIT26 +//Common Functions +#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_INIT BIT31 + +/*------------------------Export Marco Definition---------------------------*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +#define RT_PRINTK DbgPrint +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define DbgPrint printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); +#else + #define DbgPrint panic_printk +#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); +#endif + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#if DBG +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + if(pDM_Odm->SupportICType == ODM_RTL8192C) \ + DbgPrint("[ODM-92C] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8192D) \ + DbgPrint("[ODM-92D] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8723A) \ + DbgPrint("[ODM-8723A] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8188E) \ + DbgPrint("[ODM-8188E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8812) \ + DbgPrint("[ODM-8812] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8821) \ + DbgPrint("[ODM-8821] "); \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if(!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + RT_PRINTK fmt; \ + ASSERT(FALSE); \ + } +#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + int __i; \ + pu1Byte __ptr = (pu1Byte)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + } +#else +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) +#define ODM_dbg_enter() +#define ODM_dbg_exit() +#define ODM_dbg_trace(str) +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) +#endif + + +VOID +ODM_InitDebugSetting( + IN PDM_ODM_T pDM_Odm + ); + + + +#if 0 +#if DBG +#define DbgPrint printk + +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \ + { \ + char *szTitle = _TitleString; \ + pu1Byte pbtHexData = _HexData; \ + u4Byte u4bHexDataLen = _HexDataLen; \ + u4Byte __i; \ + DbgPrint("%s", szTitle); \ + for (__i=0;__i=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22. + +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \ + if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \ + { \ + int __i; \ + u1Byte buffer[MAX_STR_LEN]; \ + int length = (_Len\n", _Len, buffer); \ + } + +#else // of #if DBG +#define DbgPrint(...) +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) +#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) +#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) +#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) +#endif // of #if DBG + +#endif + + +#if 0 +/* Define debug print header for every service module.*/ +typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure +{ + const char *pMANS; + const char *pRTOS; + const char *pALM; + const char *pPEM; + const char *pCMPK; + const char *pRAPD; + const char *pTXPB; + const char *pQUMG; +}ODM_DBGP_HEAD_T; + + +/* Define different debug flag for dedicated service modules in debug flag array. */ +// Each module has independt 32 bit debug flag you cnn define the flag as yout require. +typedef enum tag_ODM_DBGP_Flag_Type_Definition +{ + ODM_FTX = 0, + ODM_FRX , + ODM_FPHY , + ODM_FPWR , + ODM_FDM , + ODM_FC2H , + ODM_FBT , + ODM_DBGP_TYPE_MAX +}ODM_DBGP_FLAG_E; + + +// Define TX relative debug bit --> FTX +#define ODM_TX_DESC BIT0 +#define ODM_TX_DESC_TID BIT1 +#define ODM_TX_PATH BIT2 + +// Define RX relative debug bit --> FRX +#define ODM_RX_DATA BIT0 +#define ODM_RX_PHY_STS BIT1 +#define ODM_RX_PHY_SS BIT2 +#define ODM_RX_PHY_SQ BIT3 +#define ODM_RX_PHY_ASTS BIT4 +#define ODM_RX_ERR_LEN BIT5 +#define ODM_RX_DEFRAG BIT6 +#define ODM_RX_ERR_RATE BIT7 +#define ODM_RX_PATH BIT8 +#define ODM_RX_BEACON BIT9 + +// Define PHY-BB/RF/MAC check module bit --> FPHY +#define ODM_PHY_BBR BIT0 +#define ODM_PHY_BBW BIT1 +#define ODM_PHY_RFR BIT2 +#define ODM_PHY_RFW BIT3 +#define ODM_PHY_MACR BIT4 +#define ODM_PHY_MACW BIT5 +#define ODM_PHY_ALLR BIT6 +#define ODM_PHY_ALLW BIT7 +#define ODM_PHY_TXPWR BIT8 +#define ODM_PHY_PWRDIFF BIT9 +#define ODM_PHY_SICR BIT10 +#define ODM_PHY_SICW BIT11 + + + + +extern u4Byte ODM_GlobalDebugLevel; + + +#if DBG +extern u8Byte ODM_GlobalDebugComponents; +#endif +#endif +#if 0 + +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE(pDM_Odm,)! +// +#define DBG_OFF 0 + +// +// Deprecated! Don't use it! +// TODO: fix related debug message! +// +//#define DBG_SEC 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define DBG_TRACE 5 + + + +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +#define COMP_TRACE BIT0 // For function call tracing. +#define COMP_DBG BIT1 // Only for temporary debug message. +#define COMP_INIT BIT2 // during driver initialization / halt / reset. +#define COMP_OID_QUERY BIT3 // Query OID. +#define COMP_OID_SET BIT4 // Set OID. +#define COMP_RECV BIT5 // Reveive part data path. +#define COMP_SEND BIT6 // Send part path. +#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02. +#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related. +#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS. +#define COMP_SCAN BIT10 // For site survey. +#define COMP_SYSTEM BIT11 // For general platform function. +#define COMP_SEC BIT12 // For Security. +#define COMP_AP BIT13 // For AP mode related. +#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21. +#define COMP_QOS BIT15 // For QoS. +#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30. +#define COMP_BEACON BIT17 // For Beacon related, by rcnjko. +#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko. +#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling +#define COMP_EVENTS BIT20 // Event handling +#define COMP_FPGA BIT21 // For FPGA verfication +#define COMP_RM BIT22 // For Radio Measurement. +#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13 +#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. +#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14. +#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko. +#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko. +#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko. +#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko. +#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW. +#define COMP_INDIC BIT31 // For link indication +#define COMP_LED BIT32 // For LED. +#define COMP_RF BIT33 // For RF. +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! +//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! + +#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11 +#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING +#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder +#define COMP_AMSDU BIT37 // For A-MSDU Debugging +#define COMP_WPS BIT38 //WPS Debug Message +#define COMP_RATR BIT39 +#define COMP_RESET BIT40 +// For debug command to print on dbgview!! +#define COMP_CMD BIT41 +#define COMP_EFUSE BIT42 +#define COMP_MESH_INTERWORKING BIT43 +#define COMP_CCX BIT44 //CCX Debug Flag +#define COMP_IOCTL BIT45 // IO Control +#define COMP_GP BIT46 // For generic parser. +#define COMP_TXAGG BIT47 +#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer +#define COMP_TEST BIT49 +#define COMP_BB_POWERSAVING BIT50 +#define COMP_SWAS BIT51 // For SW Antenna Switch +#define COMP_P2P BIT52 +#define COMP_MUX BIT53 +#define COMP_FUNC BIT54 +#define COMP_TDLS BIT55 +#define COMP_OMNIPEEK BIT56 +#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug +#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug +#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH + +#define COMP_DFS BIT62 + +#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components +// For debug print flag to use +/*------------------------------Define structure----------------------------*/ +/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/ + +/* Defnie structure to store different debug flag variable. Every debug flag + is a UINT32 integer and you can assign 32 different events. */ +typedef struct tag_DBGP_Debug_Flag_Structure +{ + u4Byte Mans; /* Main Scheduler module. */ + u4Byte Rtos; /* RTOS module. */ + u4Byte Alarm; /* Alarm module. */ + u4Byte Pm; /* Performance monitor module. */ +}DBGP_FLAG_T; + +/* Define debug print header for every service module.*/ +typedef struct tag_DBGP_Service_Module_Header_Name_Structure +{ + const char *pMANS; + const char *pRTOS; + const char *pALM; + const char *pPEM; + const char *pCMPK; + const char *pRAPD; + const char *pTXPB; + const char *pQUMG; +}DBGP_HEAD_T; + + +/* Define different debug flag for dedicated service modules in debug flag array. */ +// Each module has independt 32 bit debug flag you cnn define the flag as yout require. +typedef enum tag_DBGP_Flag_Type_Definition +{ + FQoS = 0, + FTX = 1, + FRX = 2, + FSEC = 3, + FMGNT = 4, + FMLME = 5, + FRESOURCE = 6, + FBEACON = 7, + FISR = 8, + FPHY = 9, + FMP = 10, + FEEPROM = 11, + FPWR = 12, + FDM = 13, + FDBG_CTRL = 14, + FC2H = 15, + FBT = 16, + FINIT = 17, + FIOCTL = 18, + FSHORT_CUT = 19, + DBGP_TYPE_MAX +}DBGP_FLAG_E; + + +// Define Qos Relative debug flag bit --> FQoS +#define QoS_INIT BIT0 +#define QoS_VISTA BIT1 + +// Define TX relative debug bit --> FTX +#define TX_DESC BIT0 +#define TX_DESC_TID BIT1 +#define TX_PATH BIT2 + +// Define RX relative debug bit --> FRX +#define RX_DATA BIT0 +#define RX_PHY_STS BIT1 +#define RX_PHY_SS BIT2 +#define RX_PHY_SQ BIT3 +#define RX_PHY_ASTS BIT4 +#define RX_ERR_LEN BIT5 +#define RX_DEFRAG BIT6 +#define RX_ERR_RATE BIT7 +#define RX_PATH BIT8 +#define RX_BEACON BIT9 + +// Define Security relative debug bit --> FSEC + +// Define MGNT relative debug bit --> FMGNT + +// Define MLME relative debug bit --> FMLME +#define MEDIA_STS BIT0 +#define LINK_STS BIT1 + +// Define OS resource check module bit --> FRESOURCE +#define OS_CHK BIT0 + +// Define beacon content check module bit --> FBEACON +#define BCN_SHOW BIT0 +#define BCN_PEER BIT1 + +// Define ISR/IMR check module bit --> FISR +#define ISR_CHK BIT0 + +// Define PHY-BB/RF/MAC check module bit --> FPHY +#define PHY_BBR BIT0 +#define PHY_BBW BIT1 +#define PHY_RFR BIT2 +#define PHY_RFW BIT3 +#define PHY_MACR BIT4 +#define PHY_MACW BIT5 +#define PHY_ALLR BIT6 +#define PHY_ALLW BIT7 +#define PHY_TXPWR BIT8 +#define PHY_PWRDIFF BIT9 +#define PHY_SICR BIT10 +#define PHY_SICW BIT11 + +// Define MPT driver check module bit --> FMP +#define MP_RX BIT0 +#define MP_SWICH_CH BIT1 + +// Define EEPROM and EFUSE check module bit --> FEEPROM +#define EEPROM_W BIT0 +#define EFUSE_PG BIT1 +#define EFUSE_READ_ALL BIT2 +#define EFUSE_ANALYSIS BIT3 +#define EFUSE_PG_DETAIL BIT4 + +// Define power save check module bit --> FPWR +#define LPS BIT0 +#define IPS BIT1 +#define PWRSW BIT2 +#define PWRHW BIT3 +#define PWRHAL BIT4 + +// Define Dynamic Mechanism check module bit --> FDM +#define WA_IOT BIT0 +#define DM_PWDB BIT1 +#define DM_Monitor BIT2 +#define DM_DIG BIT3 +#define DM_EDCA_Turbo BIT4 +#define DM_BT30 BIT5 + +// Define Dbg Control module bit --> FDBG_CTRL +#define DBG_CTRL_TRACE BIT0 +#define DBG_CTRL_INBAND_NOISE BIT1 + +// Define FW C2H Cmd check module bit --> FC2H +#define C2H_Summary BIT0 +#define C2H_PacketData BIT1 +#define C2H_ContentData BIT2 +// Define BT Cmd check module bit --> FBT +#define BT_TRACE BIT0 +#define BT_RFPoll BIT1 + +// Define init check for module bit --> FINIT +#define INIT_EEPROM BIT0 +#define INIT_TxPower BIT1 +#define INIT_IQK BIT2 +#define INIT_RF BIT3 + +// Define IOCTL Cmd check module bit --> FIOCTL +// section 1 : IRP related +#define IOCTL_IRP BIT0 +#define IOCTL_IRP_DETAIL BIT1 +#define IOCTL_IRP_STATISTICS BIT2 +#define IOCTL_IRP_HANDLE BIT3 +// section 2 : HCI command/event +#define IOCTL_BT_HCICMD BIT8 +#define IOCTL_BT_HCICMD_DETAIL BIT9 +#define IOCTL_BT_HCICMD_EXT BIT10 +#define IOCTL_BT_EVENT BIT11 +#define IOCTL_BT_EVENT_DETAIL BIT12 +#define IOCTL_BT_EVENT_PERIODICAL BIT13 +// section 3 : BT tx/rx data and throughput +#define IOCTL_BT_TX_ACLDATA BIT16 +#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17 +#define IOCTL_BT_RX_ACLDATA BIT18 +#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19 +#define IOCTL_BT_TP BIT20 +// section 4 : BT connection state machine. +#define IOCTL_STATE BIT21 +#define IOCTL_BT_LOGO BIT22 +// section 5 : BT function trace +#define IOCTL_CALLBACK_FUN BIT24 +#define IOCTL_PARSE_BT_PKT BIT25 +#define IOCTL_BT_TX_PKT BIT26 +#define IOCTL_BT_FLAG_MON BIT27 + +// +// Define init check for module bit --> FSHORT_CUT +// 2011/07/20 MH Add for short but definition. +// +#define SHCUT_TX BIT0 +#define SHCUT_RX BIT1 + + +/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/ +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +#if (DM_ODM_SUPPORT_TYPE != ODM_MP) +#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args); + +#if DBG +#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \ + if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define RT_TRACE_F(comp, level, fmt) \ + if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define RT_ASSERT(expr,fmt) \ + if(!(expr)) { \ + printk( "Assertion failed! %s at ......\n", #expr); \ + printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + } +#define dbg_enter() { printk("==> %s\n", __FUNCTION__); } +#define dbg_exit() { printk("<== %s\n", __FUNCTION__); } +#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); } +#else +#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) +#define RT_TRACE_F(comp, level, fmt) +#define RT_ASSERT(expr, fmt) +#define dbg_enter() +#define dbg_exit() +#define dbg_trace(str) +#endif + +#if DBG +#define DbgPrint printk + +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \ + { \ + char *szTitle = _TitleString; \ + pu1Byte pbtHexData = _HexData; \ + u4Byte u4bHexDataLen = _HexDataLen; \ + u4Byte __i; \ + DbgPrint("%s", szTitle); \ + for (__i=0;__i=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22. + +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \ + if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \ + { \ + int __i; \ + u1Byte buffer[MAX_STR_LEN]; \ + int length = (_Len\n", _Len, buffer); \ + } + +#else // of #if DBG +#define DbgPrint(...) +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) +#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) +#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) +#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) +#endif // of #if DBG + + + +#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_MP) + +#define DEBUG_PRINT 1 + +// Please add new OS's print API by yourself + +//#if (RT_PLATFORM==PLATFORM_WINDOWS) +#if (DEBUG_PRINT == 1) && DBG +#define RTPRINT(dbgtype, dbgflag, printstr)\ +{\ + if (DBGP_Type[dbgtype] & dbgflag)\ + {\ + DbgPrint printstr;\ + }\ +} + +#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\ +{\ + if (DBGP_Type[dbgtype] & dbgflag)\ + {\ + int __i; \ + pu1Byte ptr = (pu1Byte)_Ptr; \ + DbgPrint printstr; \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + }\ +} + +#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\ +{\ + if (DBGP_Type[dbgtype] & dbgflag)\ + {\ + int __i; \ + pu1Byte ptr = (pu1Byte)_HexData; \ + DbgPrint(_TitleString); \ + for( __i=0; __i<(int)_HexDataLen; __i++ ) \ + { \ + DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\ + if (((__i + 1) % 16) == 0) DbgPrint("\n");\ + } \ + DbgPrint("\n"); \ + }\ +} +#define FuncEntry FunctionIn(COMP_FUNC) +#define FuncExit FunctionOut(COMP_FUNC) + +#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__)) +#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__)) + + +#else + +#define DBGP(dbgtype, dbgflag, printstr) +#define RTPRINT(dbgtype, dbgflag, printstr) +#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr) +#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen) +#define FuncEntry +#define FuncExit +#define FunctionIn(_comp) +#define FunctionOut(_comp) +#endif +/*------------------------Export Marco Definition---------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +extern u4Byte DBGP_Type[DBGP_TYPE_MAX]; +extern DBGP_HEAD_T DBGP_Head; + +/*------------------------Export global variable----------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +extern void DBGP_Flag_Init(void); +extern void DBG_PrintAllFlag(void); +extern void DBG_PrintAllComp(void); +extern void DBG_PrintFlagEvent(u1Byte DbgFlag); +extern void DBG_DumpMem(const u1Byte DbgComp, + const u1Byte DbgLevel, + pu1Byte pMem, + u2Byte Len); + +/*--------------------------Exported Function prototype---------------------*/ + + + + + + + + + +extern u4Byte GlobalDebugLevel; +extern u8Byte GlobalDebugComponents; + + +#endif + + +#endif // __ODM_DBG_H__ + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.c new file mode 100755 index 00000000..7f6dd58b --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.c @@ -0,0 +1,666 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "odm_precomp.h" +// +// ODM IO Relative API. +// + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R8(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read8(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead1Byte(Adapter, RegAddr); +#endif + +} + + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R16(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read16(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead2Byte(Adapter, RegAddr); +#endif + +} + + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R32(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read32(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead4Byte(Adapter, RegAddr); +#endif + +} + + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W8(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write8(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite1Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W16(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write16(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite2Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W32(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write32(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryBBReg(Adapter, RegAddr, BitMask); +#endif +} + + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryBBReg(Adapter, RegAddr, BitMask); +#endif +} + + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); +#endif +} + + + + +// +// ODM Memory relative API. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + *pPtr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + *pPtr = rtw_zvmalloc(length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformAllocateMemory(Adapter, pPtr, length); +#endif +} + +// length could be ignored, used to detect memory leakage. +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + kfree(pPtr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + rtw_vmfree(pPtr, length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + //PADAPTER Adapter = pDM_Odm->Adapter; + PlatformFreeMemory(pPtr, length); +#endif +} +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return memcmp(pBuf1,pBuf2,length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + return _rtw_memcmp(pBuf1,pBuf2,length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + return PlatformCompareMemory(pBuf1,pBuf2,length); +#endif +} + + + +// +// ODM MISC relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformAcquireSpinLock(Adapter, type); +#endif +} +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformReleaseSpinLock(Adapter, type); +#endif +} + +// +// Work item relative API. FOr MP driver only~! +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID); +#endif +} + + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformStartWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformStopWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformFreeWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformScheduleWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformIsWorkItemScheduled(pRtWorkItem); +#endif +} + + + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(usDelay); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformStallExecution(usDelay); +#endif +} + +VOID +ODM_delay_ms(IN u4Byte ms) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + delay_ms(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_mdelay_os(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + delay_ms(ms); +#endif +} + +VOID +ODM_delay_us(IN u4Byte us) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + delay_us(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PlatformStallExecution(us); +#endif +} + +VOID +ODM_sleep_ms(IN u4Byte ms) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_msleep_os(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) +#endif +} + +VOID +ODM_sleep_us(IN u4Byte us) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_usleep_os(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) +#endif +} + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + mod_timer(pTimer, jiffies + (msDelay+9)/10); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + _set_timer(pTimer,msDelay ); //ms +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformSetTimer(Adapter, pTimer, msDelay); +#endif + +} + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + pTimer->function = CallBackFunc; + pTimer->data = (unsigned long)pDM_Odm; + init_timer(pTimer); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + _init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID); +#endif +} + + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + del_timer_sync(pTimer); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + _cancel_timer_ex(pTimer); +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformCancelTimer(Adapter, pTimer); +#endif +} + + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + + PADAPTER Adapter = pDM_Odm->Adapter; + + // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. + // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. + if (pTimer == 0) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); + return; + } + + PlatformReleaseTimer(Adapter, pTimer); +#endif +} + + +// +// ODM FW relative API. +// +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) +VOID +ODM_FillH2CCmd( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +) +{ + if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) + { + switch(ElementID) + { + case ODM_H2C_RSSI_REPORT: + FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer); + default: + break; + } + + } + else if(IS_HARDWARE_TYPE_8188E(Adapter)) + { + switch(ElementID) + { + case ODM_H2C_PSD_RESULT: + FillH2CCmd88E(Adapter, H2C_88E_PSD_RESULT, CmdLen, pCmdBuffer); + default: + break; + } + } + else + { + switch(ElementID) + { + case ODM_H2C_RSSI_REPORT: + FillH2CCmd92C(Adapter, H2C_RSSI_REPORT, CmdLen, pCmdBuffer); + case ODM_H2C_PSD_RESULT: + FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, CmdLen, pCmdBuffer); + default: + break; + } + } +} +#else +u4Byte +ODM_FillH2CCmd( + IN pu1Byte pH2CBuffer, + IN u4Byte H2CBufferLen, + IN u4Byte CmdNum, + IN pu4Byte pElementID, + IN pu4Byte pCmdLen, + IN pu1Byte* pCmbBuffer, + IN pu1Byte CmdStartSeq + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_MP) + //FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq); + return FALSE; +#endif + + return TRUE; +} +#endif + + + + + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.h new file mode 100755 index 00000000..a5e86801 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_interface.h @@ -0,0 +1,374 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + + + +// +// =========== Constant/Structure/Enum/... Define +// + + + +// +// =========== Macro Define +// + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +// _cat: implemented by Token-Pasting Operator. +#if 0 +#define _cat(_name, _ic_type, _func) \ + ( \ + _func##_all(_name) \ + ) +#endif + +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pDM_Odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES. +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#endif +#if 0 // only sample code +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \ + ((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \ + ((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \ + ((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \ + ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ + _func##_ic(_name, _8195) \ + ) +#endif + +// _name: name of register or bit. +// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" +// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) + +typedef enum _ODM_H2C_CMD +{ + ODM_H2C_RSSI_REPORT = 0, + ODM_H2C_PSD_RESULT=1, + ODM_H2C_PathDiv = 2, + ODM_MAX_H2CCMD +}ODM_H2C_CMD; + + +// +// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. +// Suggest HW team to use thread instead of workitem. Windows also support the feature. +// +#if (DM_ODM_SUPPORT_TYPE != ODM_MP) +typedef void *PRT_WORK_ITEM ; +typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; +typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); + +#if 0 +typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; + +typedef struct _RT_WORK_ITEM +{ + + RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. + PVOID Adapter; // Pointer to Adapter object. + PVOID pContext; // Parameter to passed to CallBackFunc(). + RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. + u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. + PVOID pPlatformExt; // Pointer to platform-dependent extension. + BOOLEAN bFree; + char szID[36]; // An identity string of this workitem. +}RT_WORK_ITEM, *PRT_WORK_ITEM; + +#endif + + +#endif + +// +// =========== Extern Variable ??? It should be forbidden. +// + + +// +// =========== EXtern Function Prototype +// + + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ); + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ); + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ); + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + + +// +// Memory Relative Function. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ); +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ); + +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ); + +// +// ODM MISC-spin lock relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + + +// +// ODM MISC-workitem relative API. +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ); + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ); + +VOID +ODM_delay_ms(IN u4Byte ms); + + +VOID +ODM_delay_us(IN u4Byte us); + +VOID +ODM_sleep_ms(IN u4Byte ms); + +VOID +ODM_sleep_us(IN u4Byte us); + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ); + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + + +// +// ODM FW relative API. +// +#if (DM_ODM_SUPPORT_TYPE & ODM_MP) +VOID +ODM_FillH2CCmd( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); +#else +u4Byte +ODM_FillH2CCmd( + IN pu1Byte pH2CBuffer, + IN u4Byte H2CBufferLen, + IN u4Byte CmdNum, + IN pu4Byte pElementID, + IN pu4Byte pCmdLen, + IN pu1Byte* pCmbBuffer, + IN pu1Byte CmdStartSeq + ); +#endif +#endif // __ODM_INTERFACE_H__ + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_precomp.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_precomp.h new file mode 100755 index 00000000..f40a1277 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_precomp.h @@ -0,0 +1,222 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "odm_types.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. + +#else + +#define TEST_FALG___ 1 + +#endif + +//2 Config Flags and Structs - defined by each ODM Type + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../8192cd_cfg.h" + #include "../odm_inc.h" + + #include "../8192cd.h" + #include "../8192cd_util.h" + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef AP_BUILD_WORKAROUND + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + // Flags + #include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags. + #include "../odm_inc.h" // OUTSRC needs some extra flags. + // Data Structure + #include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0. + #include "../8192cd.h" // OUTSRC needs basic ADSL struct definition. + #include "../8192cd_util.h" // OUTSRC needs basic I/O function. + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef ADSL_AP_BUILD_WORKAROUND + // NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14. + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) + #include + #include + #include + #include + #include + +#elif (DM_ODM_SUPPORT_TYPE == ODM_MP) + #include "Mp_Precomp.h" + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE +#endif + + +//2 Hardware Parameter Files + + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (RTL8192C_SUPPORT==1) + #include "rtl8192c/Hal8192CEFWImg_AP.h" + #include "rtl8192c/Hal8192CEPHYImg_AP.h" + #include "rtl8192c/Hal8192CEMACImg_AP.h" +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + #include "rtl8192c/Hal8192CEFWImg_ADSL.h" + #include "rtl8192c/Hal8192CEPHYImg_ADSL.h" + #include "rtl8192c/Hal8192CEMACImg_ADSL.h" + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #if(RTL8192CE_SUPPORT ==1) + #include "rtl8192c/Hal8192CEFWImg_CE.h" + #include "rtl8192c/Hal8192CEPHYImg_CE.h" + #include "rtl8192c/Hal8192CEMACImg_CE.h" + #elif(RTL8192CU_SUPPORT ==1) + #include "rtl8192c/Hal8192CUFWImg_CE.h" + #include "rtl8192c/Hal8192CUPHYImg_CE.h" + #include "rtl8192c/Hal8192CUMACImg_CE.h" + #elif(RTL8192DE_SUPPORT ==1) + #include "rtl8192d/Hal8192DEFWImg_CE.h" + #include "rtl8192d/Hal8192DEPHYImg_CE.h" + #include "rtl8192d/Hal8192DEMACImg_CE.h" + #elif(RTL8192DU_SUPPORT ==1) + #include "rtl8192d/Hal8192DUFWImg_CE.h" + #include "rtl8192d/Hal8192DUPHYImg_CE.h" + #include "rtl8192d/Hal8192DUMACImg_CE.h" + #elif(RTL8723AS_SUPPORT==1) + #include "rtl8723a/Hal8723SHWImg_CE.h" + #elif(RTL8723AU_SUPPORT==1) + #include "rtl8723a/Hal8723UHWImg_CE.h" + #elif(RTL8188E_SUPPORT==1) + #include "rtl8188e/Hal8188EFWImg_CE.h" + #endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_MP) + +#endif + + +//2 OutSrc Header Files + +#include "odm.h" +#include "odm_HWConfig.h" +#include "odm_debug.h" +#include "odm_RegDefine11AC.h" +#include "odm_RegDefine11N.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (RTL8192C_SUPPORT==1) + #include "rtl8192c/HalDMOutSrc8192C_AP.h" +#endif +#if (RTL8188E_SUPPORT==1) + #include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training +#endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + #include "rtl8192c/HalDMOutSrc8192C_ADSL.h" + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "HalPhyRf.h" + #if (RTL8192C_SUPPORT==1) + #ifdef CONFIG_INTEL_PROXIM + #include "../proxim/intel_proxim.h" + #endif + #include "rtl8192c/HalDMOutSrc8192C_CE.h" + #include + #elif (RTL8192D_SUPPORT==1) + #include "rtl8192d/HalDMOutSrc8192D_CE.h" + #include "rtl8192d_hal.h" + #elif (RTL8723A_SUPPORT==1) + #include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking + #include "rtl8723a_hal.h" + #elif (RTL8188E_SUPPORT==1) + #include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking + #include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training + #include "rtl8188e_hal.h" + #endif + +#endif + +#include "odm_interface.h" +#include "odm_reg.h" + +#if (RTL8192C_SUPPORT==1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#include "rtl8192c/Hal8192CHWImg_MAC.h" +#include "rtl8192c/Hal8192CHWImg_RF.h" +#include "rtl8192c/Hal8192CHWImg_BB.h" +#include "rtl8192c/Hal8192CHWImg_FW.h" +#endif +#include "rtl8192c/odm_RTL8192C.h" +#endif +#if (RTL8192D_SUPPORT==1) +#include "rtl8192d/odm_RTL8192D.h" +#endif + +#if (RTL8723A_SUPPORT==1) +#include "rtl8723a/HalHWImg8723A_MAC.h" +#include "rtl8723a/HalHWImg8723A_RF.h" +#include "rtl8723a/HalHWImg8723A_BB.h" +#include "rtl8723a/HalHWImg8723A_FW.h" +#include "rtl8723a/odm_RegConfig8723A.h" +#endif + +#if (RTL8188E_SUPPORT==1) +#include "rtl8188e/HalHWImg8188E_MAC.h" +#include "rtl8188e/HalHWImg8188E_RF.h" +#include "rtl8188e/HalHWImg8188E_BB.h" +#include "rtl8188e/Hal8188EReg.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#include "rtl8188e/HalPhyRf_8188e.h" +#endif + +#if (RTL8188E_FOR_TEST_CHIP >= 1) +#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h" +#include "rtl8188e/HalHWImg8188E_TestChip_RF.h" +#include "rtl8188e/HalHWImg8188E_TestChip_BB.h" +#endif + +#ifdef CONFIG_WOWLAN +#if (RTL8188E_SUPPORT==1) +#include "rtl8188e/HalHWImg8188E_FW.h" +#endif +#endif //CONFIG_WOWLAN + +#include "rtl8188e/odm_RegConfig8188E.h" +#include "rtl8188e/odm_RTL8188E.h" +#endif + +#endif // __ODM_PRECOMP_H__ + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_reg.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_reg.h new file mode 100755 index 00000000..361ac79c --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_reg.h @@ -0,0 +1,120 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: odm_reg.h +// +// Description: +// +// This file is for general register definition. +// +// +//============================================================ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +// +// Register Definition +// + +//MAC REG +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +//BB REG +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +//RF REG +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 + +//Ant Detect Reg +#define ODM_DPDT 0x300 + +//PSD Init +#define ODM_PSDREG 0x808 + +//92D Path Div +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +// +// Bitmap Definition +// + +#define BIT_FA_RESET BIT0 + + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_types.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_types.h new file mode 100755 index 00000000..b243d74d --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/odm_types.h @@ -0,0 +1,252 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +// +// Define Different SW team support +// +#define ODM_AP 0x01 //BIT0 +#define ODM_ADSL 0x02 //BIT1 +#define ODM_CE 0x04 //BIT2 +#define ODM_MP 0x08 //BIT3 + +#define DM_ODM_SUPPORT_TYPE ODM_CE + +// Deifne HW endian support +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#if (DM_ODM_SUPPORT_TYPE != ODM_MP) +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 +#endif + +typedef enum _HAL_STATUS{ + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, + /*RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED,*/ +}HAL_STATUS,*PHAL_STATUS; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +typedef enum _RT_SPINLOCK_TYPE{ + RT_TEMP =1, +}RT_SPINLOCK_TYPE; +#elif( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL)) + +#define VISTA_USB_RX_REVISE 0 + +// +// Declare for ODM spin lock defintion temporarily fro compile pass. +// +typedef enum _RT_SPINLOCK_TYPE{ + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. +#if VISTA_USB_RX_REVISE + RT_USBRX_CONTEXT_SPINLOCK = 13, + RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR +#endif + //Shall we define Ndis 6.2 SpinLock Here ? + RT_PORT_SPINLOCK=16, + RT_VNIC_SPINLOCK=17, + RT_HVL_SPINLOCK=18, + RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. + + RT_BTData_SPINLOCK=25, + + RT_WAPI_OPTION_SPINLOCK=26, + RT_WAPI_RX_SPINLOCK=27, + + // add for 92D CCK control issue + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35 +}RT_SPINLOCK_TYPE; + +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + #define STA_INFO_T RT_WLAN_STA + #define PSTA_INFO_T PRT_WLAN_STA + +// typedef unsigned long u4Byte,*pu4Byte; + #define CONFIG_HW_ANTENNA_DIVERSITY +#define CONFIG_SW_ANTENNA_DIVERSITY + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define AP_BUILD_WORKAROUND + // + + #ifdef AP_BUILD_WORKAROUND + #include "../typedef.h" + #else + typedef void VOID,*PVOID; + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; + typedef char s1Byte,*ps1Byte; + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + #endif + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + + #define DEV_BUS_TYPE RT_PCI_INTERFACE + + #define _TRUE 1 + #define _FALSE 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define ADSL_BUILD_WORKAROUND + // + + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; + typedef char s1Byte,*ps1Byte; + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + + #define DEV_BUS_TYPE RT_PCI_INTERFACE + + #define _TRUE 1 + #define _FALSE 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include + +#if 0 + typedef u8 u1Byte, *pu1Byte; + typedef u16 u2Byte,*pu2Byte; + typedef u32 u4Byte,*pu4Byte; + typedef u64 u8Byte,*pu8Byte; + typedef s8 s1Byte,*ps1Byte; + typedef s16 s2Byte,*ps2Byte; + typedef s32 s4Byte,*ps4Byte; + typedef s64 s8Byte,*ps8Byte; +#else + #define u1Byte u8 + #define pu1Byte u8* + + #define u2Byte u16 + #define pu2Byte u16* + + #define u4Byte u32 + #define pu4Byte u32* + + #define u8Byte u64 + #define pu8Byte u64* + + #define s1Byte s8 + #define ps1Byte s8* + + #define s2Byte s16 + #define ps2Byte s16* + + #define s4Byte s32 + #define ps4Byte s32* + + #define s8Byte s64 + #define ps8Byte s64* + +#endif + #ifdef CONFIG_USB_HCI + #define DEV_BUS_TYPE RT_USB_INTERFACE + #elif defined(CONFIG_PCI_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #elif defined(CONFIG_SDIO_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #endif + + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined (CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + #define STA_INFO_T struct sta_info + #define PSTA_INFO_T struct sta_info * + + + + #define TRUE _TRUE + #define FALSE _FALSE + + + #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) + #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) + #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + + //define useless flag to avoid compile warning + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define BT_30_SUPPORT 0 + #define FPGA_TWO_MAC_VERIFICATION 0 +#endif + + +#endif // __ODM_TYPES_H__ + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c new file mode 100755 index 00000000..815a357b --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c @@ -0,0 +1,892 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ +#include "../odm_precomp.h" + +const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength] = { +0xE1, 0x88, 0x10, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01, 0x21, 0x11, 0x27, 0x30, 0x36, 0x00, 0x00, +0x2D, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x45, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xC1, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xA1, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x56, 0xF7, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x42, 0x04, 0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0, +0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A, 0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C, +0xEC, 0x24, 0x89, 0xF8, 0xE6, 0xBC, 0x03, 0x02, 0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00, +0x40, 0xCE, 0x79, 0x04, 0x78, 0x80, 0x16, 0xE6, 0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1, +0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9, 0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF, +0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF, 0x04, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30, +0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50, 0x20, 0x05, 0x0C, 0x74, 0x88, 0x25, 0x0C, 0xF8, +0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8, +0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80, 0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5, +0x0C, 0x24, 0x89, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD, +0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0, 0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x88, +0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C, 0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF, +0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F, 0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F, +0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x88, 0xA6, +0x81, 0x74, 0x03, 0x60, 0x06, 0xFF, 0x08, 0x76, 0xFF, 0xDF, 0xFB, 0x7F, 0x04, 0xE4, 0x78, 0x80, +0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81, 0x76, 0x30, 0x90, 0x45, 0xDE, 0x74, 0x01, 0x93, +0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89, 0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2, +0x8C, 0xD2, 0xAF, 0x22, 0x03, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81, +0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE, +0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74, 0x88, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18, +0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09, +0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE, 0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81, +0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x88, 0x2E, 0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02, +0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09, +0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF, 0x24, 0x88, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F, +0x04, 0x90, 0x45, 0xDE, 0x93, 0xF6, 0x08, 0xEF, 0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3, +0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4, +0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF, 0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x88, 0x2F, +0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x42, 0x4D, 0x50, 0x2E, 0x74, 0x89, 0x2F, 0xF8, 0xE6, 0xBF, 0x03, +0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74, 0x88, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C, +0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19, 0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5, +0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74, 0x89, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01, +0x0F, 0x74, 0x88, 0x2F, 0xF8, 0xA6, 0x01, 0x08, 0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC, +0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8, 0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5, +0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, +0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6, 0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4, +0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30, 0xE2, 0x01, 0x0F, 0x02, 0x42, 0x4C, 0x8F, 0xF0, +0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80, 0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08, +0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50, 0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6, +0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30, +0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC, +0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x42, 0x4D, 0x7F, 0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF, +0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF, 0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0, +0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xEF, +0x5B, 0xFF, 0xEE, 0x5A, 0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, +0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, +0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xE2, 0xFC, 0x08, 0xE2, 0xFD, 0x08, 0xE2, 0xFE, 0x08, 0xE2, 0xFF, +0x22, 0xE2, 0xFB, 0x08, 0xE2, 0xF9, 0x08, 0xE2, 0xFA, 0x08, 0xE2, 0xCB, 0xF8, 0x22, 0xEC, 0xF2, +0x08, 0xED, 0xF2, 0x08, 0xEE, 0xF2, 0x08, 0xEF, 0xF2, 0x22, 0xA4, 0x25, 0x82, 0xF5, 0x82, 0xE5, +0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB, +0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, +0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, +0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0x02, 0x45, +0x8C, 0x02, 0x42, 0xDD, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03, 0xF6, 0x80, 0x01, +0xF2, 0x08, 0xDF, 0xF4, 0x80, 0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, +0x33, 0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, +0xDF, 0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90, 0x45, 0xD1, 0xE4, +0x7E, 0x01, 0x93, 0x60, 0xBC, 0xA3, 0xFF, 0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, +0x93, 0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40, 0xB8, 0xE4, 0x93, +0xA3, 0xFA, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, +0xCA, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, +0xBE, 0x00, 0x41, 0x82, 0x09, 0x00, 0x41, 0x82, 0x0A, 0x00, 0x41, 0x82, 0x17, 0x00, 0x59, 0xE2, +0x5C, 0x24, 0x5E, 0x5D, 0x5F, 0xA1, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, +0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, +0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xE6, 0xF0, 0x74, 0x45, 0xA3, 0xF0, 0xD1, 0x35, 0x74, +0xE6, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x45, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, +0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, +0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x00, 0x54, 0xE0, 0x55, 0x35, 0xF5, 0x39, 0xA3, 0xE0, 0x55, +0x36, 0xF5, 0x3A, 0xA3, 0xE0, 0x55, 0x37, 0xF5, 0x3B, 0xA3, 0xE0, 0x55, 0x38, 0xF5, 0x3C, 0xAD, +0x39, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0xAD, 0x3A, 0x7F, 0x55, 0x12, 0x32, 0x1E, 0xAD, 0x3B, 0x7F, +0x56, 0x12, 0x32, 0x1E, 0xAD, 0x3C, 0x7F, 0x57, 0x12, 0x32, 0x1E, 0x53, 0x91, 0xEF, 0x22, 0xC0, +0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, +0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, +0x6F, 0xF0, 0x74, 0x46, 0xA3, 0xF0, 0x12, 0x6C, 0x78, 0xE5, 0x41, 0x30, 0xE4, 0x04, 0x7F, 0x02, +0x91, 0x27, 0xE5, 0x41, 0x30, 0xE6, 0x03, 0x12, 0x6C, 0xD5, 0xE5, 0x43, 0x30, 0xE0, 0x03, 0x12, +0x51, 0xC2, 0xE5, 0x43, 0x30, 0xE1, 0x03, 0x12, 0x4D, 0x0C, 0xE5, 0x43, 0x30, 0xE2, 0x03, 0x12, +0x4C, 0xC1, 0xE5, 0x43, 0x30, 0xE3, 0x03, 0x12, 0x6C, 0xE2, 0xE5, 0x43, 0x30, 0xE4, 0x03, 0x12, +0x6D, 0x04, 0xE5, 0x43, 0x30, 0xE5, 0x03, 0x12, 0x6D, 0x33, 0xE5, 0x43, 0x30, 0xE6, 0x02, 0xF1, +0x0F, 0xE5, 0x44, 0x30, 0xE1, 0x03, 0x12, 0x51, 0x7F, 0x74, 0x6F, 0x04, 0x90, 0x01, 0xC4, 0xF0, +0x74, 0x46, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, +0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, +0x80, 0xDE, 0xE0, 0xB4, 0x01, 0x13, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x0D, 0x90, 0x81, 0x2B, 0xE0, +0x54, 0xFE, 0xF0, 0x54, 0x07, 0x70, 0x02, 0xF1, 0x2A, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0x90, 0x81, +0x29, 0x30, 0xE0, 0x05, 0xE0, 0xFF, 0x02, 0x74, 0x8F, 0xE0, 0xFF, 0x7D, 0x01, 0xD3, 0x10, 0xAF, +0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, 0x13, 0xED, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x90, 0x82, 0x14, +0xF0, 0x90, 0x81, 0x24, 0xE0, 0xFE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, 0x03, 0x02, 0x48, +0xA0, 0xEE, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x03, 0x02, 0x48, 0xA0, 0x90, 0x82, +0x14, 0xE0, 0xFE, 0x6F, 0x70, 0x03, 0x02, 0x48, 0xA0, 0xEF, 0x70, 0x03, 0x02, 0x48, 0x17, 0x24, +0xFE, 0x70, 0x03, 0x02, 0x48, 0x50, 0x24, 0xFE, 0x60, 0x51, 0x24, 0xFC, 0x70, 0x03, 0x02, 0x48, +0x8B, 0x24, 0xFC, 0x60, 0x03, 0x02, 0x48, 0xA0, 0xEE, 0xB4, 0x0E, 0x03, 0x12, 0x49, 0x5E, 0x90, +0x82, 0x14, 0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0x49, 0x93, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x06, +0x03, 0x12, 0x49, 0x34, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x04, 0x0F, 0x90, 0x82, 0x13, 0xE0, 0xFF, +0x60, 0x05, 0x12, 0x73, 0x75, 0x80, 0x03, 0x12, 0x66, 0x26, 0x90, 0x82, 0x14, 0xE0, 0x64, 0x08, +0x60, 0x03, 0x02, 0x48, 0xA0, 0x12, 0x73, 0xD3, 0x02, 0x48, 0xA0, 0x90, 0x82, 0x14, 0xE0, 0x70, +0x05, 0x7F, 0x01, 0x12, 0x49, 0x93, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x49, 0x34, +0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0E, 0x09, 0x12, 0x48, 0xA5, 0xBF, 0x01, 0x03, 0x12, 0x49, 0x5E, +0x90, 0x82, 0x14, 0xE0, 0x64, 0x0C, 0x60, 0x02, 0x01, 0xA0, 0x11, 0xA5, 0xEF, 0x64, 0x01, 0x60, +0x02, 0x01, 0xA0, 0x11, 0xFA, 0x01, 0xA0, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0E, 0x07, 0x11, 0xA5, +0xBF, 0x01, 0x02, 0x31, 0x5E, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x06, 0x02, 0x31, 0x34, 0x90, 0x82, +0x14, 0xE0, 0xB4, 0x0C, 0x07, 0x11, 0xA5, 0xBF, 0x01, 0x02, 0x11, 0xFA, 0x90, 0x82, 0x14, 0xE0, +0x64, 0x04, 0x70, 0x5C, 0x12, 0x72, 0xF5, 0xEF, 0x64, 0x01, 0x70, 0x54, 0x31, 0xBE, 0x80, 0x50, +0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0E, 0x07, 0x11, 0xA5, 0xBF, 0x01, 0x02, 0x31, 0x5E, 0x90, 0x82, +0x14, 0xE0, 0xB4, 0x06, 0x02, 0x31, 0x34, 0x90, 0x82, 0x14, 0xE0, 0xB4, 0x0C, 0x07, 0x11, 0xA5, +0xBF, 0x01, 0x02, 0x11, 0xFA, 0x90, 0x82, 0x14, 0xE0, 0x70, 0x04, 0x7F, 0x01, 0x31, 0x93, 0x90, +0x82, 0x14, 0xE0, 0xB4, 0x04, 0x1A, 0x12, 0x73, 0xBB, 0x80, 0x15, 0x90, 0x82, 0x14, 0xE0, 0xB4, +0x0C, 0x0E, 0x90, 0x81, 0x25, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x02, 0x31, 0xB1, +0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD1, 0xAB, 0xEF, 0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, +0x01, 0xF0, 0x80, 0x3D, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, +0x08, 0x90, 0x01, 0xB8, 0x74, 0x02, 0xF0, 0x80, 0x28, 0xEF, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x08, +0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x19, 0x90, 0x81, 0x29, 0xE0, 0xD3, 0x94, 0x04, 0x40, +0x08, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, +0x22, 0x90, 0x01, 0xB9, 0x74, 0x02, 0xF0, 0x7F, 0x00, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, +0x70, 0x31, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x7F, +0x01, 0xF1, 0x0D, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x2A, +0x74, 0x0E, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, +0xB8, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x25, 0xE0, 0x90, 0x06, 0x04, 0x20, 0xE0, 0x0C, 0xE0, 0x44, +0x40, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x04, 0xF0, 0x80, 0x0E, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x81, +0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, 0x81, +0x25, 0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x08, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x80, 0x1E, 0x90, +0x06, 0x04, 0xE0, 0x44, 0x40, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x04, 0xF0, +0x90, 0x05, 0x27, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x23, 0x74, 0x04, 0xF0, 0x90, 0x05, 0x22, +0xE4, 0xF0, 0x22, 0x90, 0x82, 0x15, 0xEF, 0xF0, 0x12, 0x54, 0x65, 0x90, 0x82, 0x15, 0xE0, 0x60, +0x05, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x04, 0xF0, 0x90, 0x81, 0x23, 0xF0, +0x22, 0x31, 0xE3, 0x90, 0x81, 0x2A, 0x74, 0x08, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x05, +0x22, 0x74, 0xFF, 0xF0, 0xF1, 0x3A, 0x90, 0x01, 0x37, 0x74, 0x02, 0xF0, 0xFD, 0x7F, 0x03, 0x51, +0x57, 0x31, 0xE3, 0xE4, 0x90, 0x81, 0x2A, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x05, 0x22, +0x74, 0xFF, 0xF0, 0xF1, 0x3A, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0xCC, 0xF0, 0x00, 0xC0, 0x7F, +0x8C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x14, +0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xF9, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, +0x00, 0xE4, 0xFD, 0xFF, 0x12, 0x55, 0x1C, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x44, +0x80, 0xFC, 0x90, 0x82, 0x05, 0x12, 0x20, 0xCE, 0x90, 0x82, 0x05, 0x12, 0x44, 0xD9, 0x90, 0x85, +0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x01, 0x00, 0x74, 0x3F, +0xF0, 0xA3, 0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x20, 0xF0, 0x22, 0x90, 0x01, +0x34, 0x74, 0x40, 0xF0, 0xFD, 0xE4, 0xFF, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0x4D, 0xFE, 0xF6, 0x74, +0x30, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0xE4, 0x90, 0x81, 0xCB, 0xF0, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, +0x81, 0x1F, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, +0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90, 0x81, +0x1F, 0xF0, 0xEE, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, +0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0xFF, 0x90, 0x81, 0x1F, 0xF0, 0xEE, 0x54, 0x20, 0xFE, +0xEF, 0x54, 0xDF, 0x4E, 0xF0, 0x12, 0x1F, 0xA4, 0xC3, 0x13, 0x20, 0xE0, 0x02, 0x61, 0x5E, 0x90, +0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x6D, 0x90, 0x81, 0xCB, 0x74, 0x21, 0xF0, 0xEF, 0x13, 0x13, +0x54, 0x3F, 0x30, 0xE0, 0x0B, 0x51, 0x4E, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x08, 0xF0, 0x80, 0x0C, +0xE4, 0x90, 0x81, 0x20, 0xF0, 0xA3, 0xF0, 0x7D, 0x40, 0xFF, 0x91, 0x26, 0x90, 0x81, 0x1F, 0xE0, +0xFD, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x12, 0xF0, +0xED, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x14, 0xF0, 0x90, 0x81, +0x1F, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x80, 0xF0, +0x90, 0x81, 0xCB, 0xE0, 0x90, 0x05, 0x27, 0xF0, 0x90, 0x81, 0x22, 0xE0, 0x60, 0x02, 0x81, 0x17, +0x7F, 0x01, 0x80, 0x15, 0x90, 0x81, 0xCB, 0x74, 0x01, 0xF0, 0x90, 0x05, 0x27, 0xF0, 0x90, 0x81, +0x22, 0xE0, 0x64, 0x04, 0x60, 0x02, 0x81, 0x17, 0xFF, 0x12, 0x53, 0x0E, 0x81, 0x17, 0x90, 0x81, +0x1F, 0xE0, 0xFF, 0x20, 0xE0, 0x02, 0x61, 0xE7, 0x90, 0x81, 0xCB, 0x74, 0x31, 0xF0, 0xEF, 0x13, +0x13, 0x54, 0x3F, 0x30, 0xE0, 0x0B, 0x51, 0x4E, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x08, 0xF0, 0x80, +0x06, 0x7D, 0x40, 0xE4, 0xFF, 0x91, 0x26, 0x90, 0x81, 0x1F, 0xE0, 0xFD, 0x13, 0x13, 0x13, 0x54, +0x1F, 0x30, 0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x02, 0xF0, 0xED, 0xC4, 0x54, 0x0F, 0x30, +0xE0, 0x07, 0x90, 0x81, 0xCB, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x81, 0xCB, 0xE0, 0x90, 0x05, 0x27, +0xF0, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x70, 0x1D, 0xFD, 0x7F, 0x04, 0x12, 0x47, 0x3D, 0x12, +0x51, 0x73, 0xBF, 0x01, 0x09, 0x90, 0x81, 0x29, 0xE0, 0xFF, 0x7D, 0x01, 0x80, 0x03, 0xE4, 0xFD, +0xFF, 0x12, 0x47, 0x3D, 0x80, 0x41, 0x90, 0x81, 0x2A, 0xE0, 0x90, 0x81, 0x23, 0xF0, 0x90, 0x05, +0x27, 0xE0, 0x44, 0x40, 0xF0, 0x80, 0x30, 0x90, 0x81, 0xCB, 0x74, 0x01, 0xF0, 0x90, 0x05, 0x27, +0xF0, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x02, 0x06, 0x7D, 0x01, 0x7F, 0x04, 0x80, 0x0B, 0x90, 0x81, +0x23, 0xE0, 0xB4, 0x08, 0x07, 0x7D, 0x01, 0x7F, 0x0C, 0x12, 0x47, 0x3D, 0xD1, 0x34, 0x90, 0x81, +0x29, 0x12, 0x47, 0x39, 0x12, 0x5A, 0xA7, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x7D, 0x02, 0x7F, 0x02, +0x91, 0x26, 0x7D, 0x01, 0x7F, 0x02, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, +0xF6, 0x74, 0x30, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xEF, 0x70, +0x37, 0x7D, 0x78, 0x7F, 0x02, 0x91, 0x26, 0x7D, 0x02, 0x7F, 0x03, 0x91, 0x26, 0x7D, 0xC8, 0x7F, +0x02, 0x12, 0x71, 0x8F, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x7D, +0x01, 0x7F, 0x0C, 0x12, 0x47, 0x3D, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, +0x90, 0x06, 0x0A, 0xE0, 0x54, 0xF8, 0xF0, 0x22, 0x90, 0x01, 0x36, 0x74, 0x78, 0xF0, 0xA3, 0x74, +0x02, 0xF0, 0x7D, 0x78, 0xFF, 0x51, 0x57, 0x7D, 0x02, 0x7F, 0x03, 0x51, 0x57, 0x90, 0x06, 0x0A, +0xE0, 0x44, 0x07, 0xF0, 0x90, 0x81, 0x32, 0xA3, 0xE0, 0x90, 0x05, 0x58, 0xF0, 0x90, 0x80, 0xDE, +0xE0, 0xB4, 0x01, 0x15, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x20, +0xE2, 0x0E, 0x7D, 0x01, 0x7F, 0x04, 0x02, 0x47, 0x3D, 0x90, 0x81, 0x25, 0xE0, 0x44, 0x04, 0xF0, +0x22, 0x90, 0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x08, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x60, +0x3A, 0x90, 0x81, 0x27, 0xE0, 0x70, 0x04, 0xEF, 0x30, 0xE0, 0x0A, 0x90, 0x81, 0x2A, 0xE0, 0x64, +0x02, 0x60, 0x28, 0xB1, 0x83, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, +0x14, 0x90, 0x81, 0x2D, 0xE0, 0xFF, 0xA3, 0xE0, 0x6F, 0x70, 0x0A, 0xF1, 0xCD, 0x91, 0x1C, 0x90, +0x81, 0x2E, 0xE0, 0x14, 0xF0, 0x90, 0x01, 0xE6, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x1F, 0xE0, +0x30, 0xE0, 0x06, 0x90, 0x81, 0x21, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x45, 0x90, +0x81, 0x25, 0xE0, 0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x12, 0x90, 0x01, 0x3B, 0xE0, +0x30, 0xE4, 0x0B, 0x91, 0x1C, 0x90, 0x81, 0x2D, 0xE0, 0x14, 0x90, 0x05, 0x73, 0xF0, 0x90, 0x82, +0x0B, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, 0xC3, 0x90, 0x82, 0x0C, 0xE0, 0x94, 0x80, 0x90, +0x82, 0x0B, 0xE0, 0x64, 0x80, 0x94, 0x80, 0x40, 0x0B, 0x90, 0x01, 0x98, 0xE0, 0x54, 0xFE, 0xF0, +0xE0, 0x44, 0x01, 0xF0, 0x12, 0x75, 0xF8, 0xD1, 0xD6, 0x90, 0x81, 0x3F, 0xE0, 0x30, 0xE0, 0x0C, +0xE4, 0xF5, 0x1D, 0xA3, 0xF1, 0xFB, 0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x01, 0xBE, 0xE0, +0x04, 0xF0, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x60, 0x02, 0xC1, 0x23, 0x90, 0x81, 0x27, +0xE0, 0x70, 0x02, 0xC1, 0x23, 0x90, 0x81, 0x26, 0xE0, 0xC4, 0x54, 0x0F, 0x64, 0x01, 0x70, 0x22, +0x90, 0x06, 0xAB, 0xE0, 0x90, 0x81, 0x2E, 0xF0, 0x90, 0x06, 0xAA, 0xE0, 0x90, 0x81, 0x2D, 0xF0, +0xA3, 0xE0, 0xFF, 0x70, 0x08, 0x90, 0x81, 0x2D, 0xE0, 0xFE, 0xFF, 0x80, 0x00, 0x90, 0x81, 0x2E, +0xEF, 0xF0, 0x90, 0x81, 0x25, 0xE0, 0x44, 0x04, 0xF0, 0xE4, 0x90, 0x81, 0x30, 0xF0, 0x90, 0x81, +0x32, 0xA3, 0xE0, 0x90, 0x05, 0x58, 0xF0, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, +0x02, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x26, 0xE0, +0xFF, 0xC4, 0x54, 0x0F, 0x24, 0xFD, 0x50, 0x02, 0x80, 0x0F, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, +0x05, 0x12, 0x6D, 0xF2, 0x80, 0x03, 0x12, 0x6E, 0xC9, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x13, +0x54, 0x1F, 0x30, 0xE0, 0x0E, 0x90, 0x81, 0x2D, 0xE0, 0xFF, 0xA3, 0xE0, 0xB5, 0x07, 0x04, 0xF1, +0xCD, 0x91, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x07, 0x90, 0x81, 0x25, 0xE0, +0x44, 0x04, 0xF0, 0x22, 0xD1, 0xAB, 0xEF, 0x70, 0x02, 0xD1, 0x3C, 0x22, 0x90, 0x81, 0x27, 0xE0, +0x64, 0x01, 0x70, 0x66, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x60, 0x51, 0x90, 0x81, 0x2A, 0xE0, +0x70, 0x03, 0xFF, 0x31, 0x93, 0x90, 0x81, 0x2A, 0xE0, 0x64, 0x0C, 0x60, 0x03, 0x12, 0x66, 0x26, +0x90, 0x01, 0x5B, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0xD1, 0xAB, 0xEF, 0x64, 0x01, +0x60, 0x38, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, +0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x12, 0x50, 0x05, 0x90, 0x01, 0x5B, 0x74, 0x05, 0xF0, 0x90, +0x06, 0x92, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0x90, 0x81, 0x2A, +0xE0, 0x70, 0x07, 0x7D, 0x01, 0x7F, 0x04, 0x12, 0x47, 0x3D, 0x22, 0x90, 0x04, 0x1A, 0xE0, 0xF4, +0x60, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x04, 0x1B, 0xE0, 0x54, 0x07, 0x64, 0x07, 0x7F, 0x01, 0x60, +0x02, 0x7F, 0x00, 0x22, 0x12, 0x50, 0x60, 0x90, 0x81, 0x2D, 0xE0, 0x14, 0x90, 0x05, 0x73, 0xF0, +0x7D, 0x02, 0x7F, 0x02, 0x51, 0x57, 0x90, 0x81, 0x42, 0xE0, 0x30, 0xE0, 0x2D, 0x90, 0x80, 0xDE, +0xE0, 0xB4, 0x01, 0x26, 0x90, 0x82, 0x17, 0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x0A, 0x0B, 0x90, 0x81, +0x44, 0xE0, 0x04, 0xF0, 0xE4, 0x90, 0x82, 0x17, 0xF0, 0x90, 0x81, 0x44, 0xE0, 0xFF, 0x90, 0x81, +0x43, 0xE0, 0xB5, 0x07, 0x05, 0xE4, 0xA3, 0xF0, 0xF1, 0x0B, 0x22, 0xE4, 0xFF, 0x8F, 0x53, 0x90, +0x04, 0x1D, 0xE0, 0x60, 0x19, 0x90, 0x05, 0x22, 0xE0, 0xF5, 0x56, 0x74, 0xFF, 0xF0, 0xF1, 0x3A, +0xBF, 0x01, 0x03, 0x12, 0x74, 0xFB, 0x90, 0x05, 0x22, 0xE5, 0x56, 0xF0, 0x80, 0x03, 0x12, 0x74, +0xFB, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x7F, 0x01, 0x22, 0xE4, 0x90, 0x82, 0x0F, 0xF0, 0xA3, +0xF0, 0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, 0xA3, 0xE0, 0x70, 0x07, 0xA3, +0xE0, 0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x82, 0x10, 0xE0, 0x94, 0xE8, 0x90, 0x82, 0x0F, +0xE0, 0x94, 0x03, 0x40, 0x0A, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x20, 0xF0, 0x7F, 0x00, 0x22, 0x7F, +0x32, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x82, 0x0F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, +0x80, 0xBF, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0x3F, 0xF0, +0xEF, 0x60, 0x1D, 0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x10, +0xF0, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0x22, +0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xEF, 0xF0, 0x74, 0x1F, +0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x40, 0xF0, 0x22, 0xEF, 0x14, 0x90, +0x05, 0x73, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10, 0xF0, 0xFD, 0x7F, 0x03, 0x74, 0x45, 0x2F, 0xF8, +0xE6, 0x4D, 0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, +0x22, 0xE0, 0x44, 0x02, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x39, 0xE0, 0xF5, 0x1E, 0xE4, 0xFB, +0xFD, 0x7F, 0x54, 0x7E, 0x01, 0x8E, 0x19, 0x8F, 0x1A, 0xE5, 0x1E, 0x54, 0x07, 0xC4, 0x33, 0x54, +0xE0, 0x85, 0x19, 0x83, 0x85, 0x1A, 0x82, 0xF0, 0xE5, 0x1D, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, +0xFF, 0xE5, 0x1E, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x4F, 0xA3, 0xF0, 0xEB, 0x54, 0x07, 0xC4, 0x33, +0x54, 0xE0, 0xFF, 0xE5, 0x1D, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x4F, 0x85, 0x1A, 0x82, 0x85, 0x19, +0x83, 0xA3, 0xA3, 0xF0, 0xBD, 0x01, 0x0C, 0x85, 0x1A, 0x82, 0x8E, 0x83, 0xA3, 0xA3, 0xA3, 0x74, +0x03, 0xF0, 0x22, 0x85, 0x1A, 0x82, 0x85, 0x19, 0x83, 0xA3, 0xA3, 0xA3, 0x74, 0x01, 0xF0, 0x22, +0xE4, 0x90, 0x81, 0x4D, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x58, 0x90, 0x80, 0xDE, 0xE0, 0x64, +0x01, 0x70, 0x50, 0x90, 0x81, 0x4D, 0x04, 0xF0, 0xE4, 0x90, 0x81, 0x2E, 0xF0, 0x90, 0x81, 0x1F, +0xE0, 0x30, 0xE0, 0x15, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x02, 0x05, 0xE4, 0x90, 0x81, 0x4D, 0xF0, +0x31, 0x73, 0xEF, 0x70, 0x04, 0x90, 0x81, 0x4D, 0xF0, 0x90, 0x81, 0x4D, 0xE0, 0x60, 0x24, 0x90, +0x81, 0x2B, 0xE0, 0x44, 0x10, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x2F, 0x12, 0x4F, 0xFB, 0x90, +0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x20, 0xE2, 0x07, 0x7D, 0x01, 0x7F, 0x04, +0x12, 0x47, 0x3D, 0x22, 0xE4, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x70, 0x02, 0x21, +0x72, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x60, 0x02, 0x21, 0x72, 0x90, 0x81, 0x26, 0xE0, 0xFF, +0xC4, 0x54, 0x0F, 0x60, 0x22, 0x24, 0xFE, 0x60, 0x03, 0x04, 0x70, 0x21, 0x90, 0x81, 0x2E, 0xE0, +0x14, 0xF0, 0xE0, 0xFF, 0x60, 0x06, 0x90, 0x81, 0x30, 0xE0, 0x60, 0x11, 0xEF, 0x70, 0x08, 0x90, +0x81, 0x2D, 0xE0, 0xA3, 0xF0, 0x80, 0x00, 0x90, 0x81, 0x4C, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x1F, +0xE0, 0x30, 0xE0, 0x15, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x02, 0x05, 0xE4, 0x90, 0x81, 0x4C, 0xF0, +0x31, 0x73, 0xEF, 0x70, 0x04, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x81, 0x4C, 0xE0, 0x60, 0x43, 0x90, +0x81, 0x2B, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x81, 0x30, 0xE0, 0x60, 0x03, 0xB4, 0x01, 0x09, 0xE4, +0xF5, 0x1D, 0x90, 0x81, 0x30, 0xE0, 0x80, 0x0D, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x30, 0xE0, 0x75, +0xF0, 0x03, 0xA4, 0x24, 0xFE, 0xFF, 0x90, 0x81, 0x2F, 0xE0, 0x2F, 0x12, 0x4F, 0xFC, 0x90, 0x01, +0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x20, 0xE2, 0x07, 0x7D, 0x01, 0x7F, 0x04, 0x12, +0x47, 0x3D, 0x22, 0x90, 0x05, 0x43, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0x22, 0x90, +0x81, 0x27, 0xE0, 0x70, 0x07, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, 0x11, 0x90, 0x81, 0x1F, 0xE0, +0x30, 0xE0, 0x07, 0x31, 0x73, 0xBF, 0x01, 0x05, 0x41, 0x5B, 0x12, 0x4E, 0x3C, 0x22, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0x1E, 0xE0, 0xB4, 0x01, 0x04, 0x7F, 0x04, 0x80, 0x0B, +0x31, 0x73, 0xBF, 0x01, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x02, 0x71, 0x0E, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x90, 0x81, 0x4B, 0xE0, 0x60, 0x0F, 0xE4, 0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x02, +0xF0, 0x90, 0x05, 0xFC, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, 0x10, 0xA3, 0x74, +0x01, 0xF0, 0x90, 0x81, 0x1F, 0xE0, 0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x02, 0x31, 0x9E, 0x11, 0xC4, +0x90, 0x81, 0x3F, 0xE0, 0x30, 0xE0, 0x07, 0x91, 0x65, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, +0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x3D, 0x90, 0x81, 0x23, 0xE0, 0x7E, 0x00, 0xB4, 0x02, 0x02, +0x7E, 0x01, 0x90, 0x81, 0x22, 0xE0, 0x7D, 0x00, 0xB4, 0x04, 0x02, 0x7D, 0x01, 0xED, 0x4E, 0x70, +0x23, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x02, 0x21, 0x9E, 0x51, 0x45, 0x90, 0x81, 0x23, 0xE0, 0xB4, +0x08, 0x06, 0xE4, 0xFD, 0x7F, 0x0C, 0x80, 0x09, 0x90, 0x81, 0x23, 0xE0, 0x70, 0x06, 0xFD, 0x7F, +0x04, 0x12, 0x47, 0x3D, 0x22, 0x90, 0x81, 0x1E, 0xE0, 0xB4, 0x01, 0x0F, 0x90, 0x81, 0x23, 0xE0, +0x64, 0x02, 0x60, 0x07, 0x7D, 0x01, 0x7F, 0x02, 0x12, 0x47, 0x3D, 0x90, 0x81, 0x27, 0xE0, 0x64, +0x02, 0x60, 0x14, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x60, 0x0C, 0x12, 0x4E, 0xAB, 0xEF, 0x70, +0x06, 0xFD, 0x7F, 0x0C, 0x12, 0x47, 0x3D, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0xFF, 0x30, 0xE0, 0x3F, +0x90, 0x81, 0x23, 0xE0, 0x7E, 0x00, 0xB4, 0x02, 0x02, 0x7E, 0x01, 0x90, 0x81, 0x22, 0xE0, 0x7D, +0x00, 0xB4, 0x04, 0x02, 0x7D, 0x01, 0xED, 0x4E, 0x70, 0x25, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x02, +0x21, 0x9E, 0x12, 0x74, 0xAC, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x0C, 0x06, 0xE4, 0xFD, 0x7F, 0x08, +0x80, 0x0A, 0x90, 0x81, 0x23, 0xE0, 0xB4, 0x04, 0x06, 0xE4, 0xFD, 0xFF, 0x12, 0x47, 0x3D, 0x22, +0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x1F, 0x12, 0x1F, 0xA4, +0xFF, 0x90, 0x81, 0x1E, 0xF0, 0xBF, 0x01, 0x12, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, 0x90, 0x00, +0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x21, 0x80, 0x1D, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, +0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x0F, 0x90, 0x81, 0x1F, 0xE0, 0x20, 0xE0, +0x06, 0xE4, 0xFF, 0x71, 0x0E, 0x80, 0x02, 0x31, 0x9E, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0x22, 0xE0, 0x90, 0x82, 0x16, 0xF0, 0x6F, 0x70, 0x02, +0x81, 0x04, 0xEF, 0x14, 0x60, 0x3E, 0x14, 0x60, 0x62, 0x14, 0x70, 0x02, 0x61, 0xB8, 0x14, 0x70, +0x02, 0x61, 0xDF, 0x24, 0x04, 0x60, 0x02, 0x81, 0x04, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x04, +0x04, 0x91, 0x41, 0x81, 0x04, 0xEF, 0xB4, 0x02, 0x04, 0x91, 0x50, 0x81, 0x04, 0x90, 0x82, 0x16, +0xE0, 0xFF, 0xB4, 0x03, 0x04, 0x91, 0x54, 0x81, 0x04, 0xEF, 0x64, 0x01, 0x60, 0x02, 0x81, 0x04, +0x91, 0x43, 0x81, 0x04, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x04, 0x04, 0x91, 0xF3, 0x81, 0x04, +0xEF, 0xB4, 0x02, 0x04, 0x91, 0x58, 0x81, 0x04, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x03, 0x04, +0x91, 0xE8, 0x81, 0x04, 0xEF, 0x70, 0x7D, 0x91, 0x2B, 0x80, 0x79, 0x90, 0x82, 0x16, 0xE0, 0xB4, +0x04, 0x05, 0x12, 0x74, 0x60, 0x80, 0x6D, 0x90, 0x82, 0x16, 0xE0, 0xB4, 0x01, 0x04, 0x91, 0x21, +0x80, 0x62, 0x90, 0x82, 0x16, 0xE0, 0xB4, 0x03, 0x05, 0x12, 0x74, 0x71, 0x80, 0x56, 0x90, 0x82, +0x16, 0xE0, 0x70, 0x50, 0x91, 0x1F, 0x80, 0x4C, 0x90, 0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x04, 0x05, +0x12, 0x74, 0x4C, 0x80, 0x3F, 0xEF, 0xB4, 0x01, 0x04, 0x91, 0x34, 0x80, 0x37, 0xEF, 0xB4, 0x02, +0x04, 0x91, 0xDF, 0x80, 0x2F, 0x90, 0x82, 0x16, 0xE0, 0x70, 0x29, 0x91, 0x32, 0x80, 0x25, 0x90, +0x82, 0x16, 0xE0, 0xFF, 0xB4, 0x03, 0x05, 0x12, 0x74, 0x7B, 0x80, 0x18, 0xEF, 0xB4, 0x01, 0x04, +0x91, 0x0B, 0x80, 0x10, 0xEF, 0xB4, 0x02, 0x04, 0xB1, 0x06, 0x80, 0x08, 0x90, 0x82, 0x16, 0xE0, +0x70, 0x02, 0x91, 0x09, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x91, 0x2B, 0x90, 0x05, 0x22, 0x74, 0x6F, +0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0x91, +0x2B, 0x12, 0x49, 0xDD, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x81, 0x22, 0x74, 0x01, +0xF0, 0x22, 0x91, 0x2B, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, +0x22, 0x91, 0xF3, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0x90, 0x81, 0x22, 0xF0, 0x22, +0x91, 0x58, 0x80, 0xEF, 0x91, 0xE8, 0x80, 0xEB, 0x91, 0x65, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, +0x81, 0x22, 0x04, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x01, 0x01, 0xE0, +0x44, 0x02, 0xF0, 0x90, 0x01, 0x00, 0x74, 0xFF, 0xF0, 0x90, 0x06, 0xB7, 0x74, 0x09, 0xF0, 0x90, +0x06, 0xB4, 0x74, 0x86, 0xF0, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x54, 0x7F, 0xFC, +0x90, 0x82, 0x01, 0x12, 0x20, 0xCE, 0x90, 0x82, 0x01, 0x12, 0x44, 0xD9, 0x90, 0x85, 0xBB, 0x12, +0x20, 0xCE, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0xCC, +0xC0, 0x00, 0xC0, 0x7F, 0x8C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, +0x00, 0xC0, 0x00, 0x14, 0x7F, 0x70, 0x7E, 0x0E, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xF9, 0x12, 0x20, +0xDA, 0x00, 0x03, 0x3E, 0x60, 0xE4, 0xFD, 0xFF, 0xB1, 0x1C, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x91, +0x65, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, 0x22, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x22, +0x04, 0xF0, 0x22, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x90, +0x81, 0x22, 0x74, 0x01, 0xF0, 0x22, 0x91, 0x65, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x90, 0x05, +0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0xC0, 0x07, 0xC0, 0x05, 0x90, 0x81, 0xF9, 0x12, 0x44, 0xD9, 0x90, 0x81, 0xE5, +0x12, 0x20, 0xCE, 0xD0, 0x05, 0xD0, 0x07, 0x12, 0x60, 0xF5, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, +0x81, 0xC8, 0x12, 0x45, 0x1F, 0xEF, 0x12, 0x45, 0x28, 0x55, 0x71, 0x00, 0x55, 0x7A, 0x01, 0x55, +0x83, 0x02, 0x55, 0x8B, 0x03, 0x55, 0x94, 0x04, 0x55, 0x9C, 0x20, 0x55, 0xA4, 0x21, 0x55, 0xAD, +0x23, 0x55, 0xB5, 0x24, 0x55, 0xBE, 0x25, 0x55, 0xC7, 0x26, 0x55, 0xCF, 0xC0, 0x00, 0x00, 0x55, +0xD8, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x6A, 0xB0, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, +0x02, 0x65, 0x81, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x41, 0xC0, 0x90, 0x81, 0xC8, 0x12, 0x45, +0x16, 0x02, 0x75, 0xD8, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x80, 0x44, 0x90, 0x81, 0xC8, 0x12, +0x45, 0x16, 0xC1, 0x4B, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x6A, 0xF8, 0x90, 0x81, 0xC8, +0x12, 0x45, 0x16, 0xE1, 0xE1, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x4A, 0x6C, 0x90, 0x81, +0xC8, 0x12, 0x45, 0x16, 0x02, 0x6B, 0x3E, 0x90, 0x81, 0xC8, 0x12, 0x45, 0x16, 0x80, 0x3E, 0x90, +0x81, 0xC8, 0x12, 0x45, 0x16, 0x02, 0x6B, 0x4E, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x01, 0xF0, 0x22, +0x12, 0x5A, 0x4B, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x45, 0xE0, 0x54, 0xFE, +0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x14, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, +0x46, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x47, 0xF0, 0x22, 0x12, 0x1F, 0xA4, +0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0x90, 0x00, 0x01, 0x12, +0x1F, 0xBD, 0xFE, 0x90, 0x05, 0x54, 0xE0, 0xC3, 0x9E, 0x90, 0x81, 0x40, 0xF0, 0xEF, 0x20, 0xE0, +0x07, 0x91, 0x65, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0x01, 0x90, 0x01, +0xBC, 0xF0, 0x90, 0x81, 0x40, 0xE0, 0x90, 0x01, 0xBD, 0xF0, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, +0x7F, 0x90, 0x81, 0x27, 0xF0, 0xEF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0xA3, 0xF0, 0x90, 0x00, +0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x54, 0xF0, 0xC4, 0x54, 0x0F, 0xFE, 0x90, 0x81, 0x26, 0xE0, 0x54, +0xF0, 0x4E, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x54, 0x01, 0x25, 0xE0, 0xFE, 0x90, 0x81, +0x24, 0xE0, 0x54, 0xFD, 0x4E, 0xF0, 0xEF, 0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFF, 0x90, 0x81, 0x26, +0xE0, 0x54, 0x0F, 0x4F, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x29, 0xF0, 0xD1, +0xC6, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0xF0, 0x90, 0x81, 0x27, 0xE0, 0x90, +0x01, 0xBA, 0xF0, 0x90, 0x81, 0x29, 0xE0, 0x90, 0x01, 0xBB, 0xF0, 0x90, 0x81, 0x26, 0xE0, 0x54, +0x0F, 0x90, 0x01, 0xBE, 0xF0, 0x22, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x1F, 0x12, 0x72, 0xB3, 0x90, +0x81, 0x27, 0xE0, 0xFF, 0x12, 0x4C, 0x3E, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x19, 0x90, 0x81, 0xCB, +0x12, 0x45, 0x16, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x54, 0x0F, 0xFF, 0x90, 0x00, 0x02, 0x12, +0x1F, 0xBD, 0xFD, 0x12, 0x72, 0xC4, 0x22, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, +0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, +0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xF7, 0xF0, 0x74, 0x56, 0xA3, 0xF0, 0x12, 0x6C, +0xA5, 0xE5, 0x49, 0x30, 0xE1, 0x03, 0x12, 0x6F, 0x79, 0xE5, 0x49, 0x30, 0xE2, 0x02, 0xF1, 0xA5, +0xE5, 0x49, 0x30, 0xE3, 0x03, 0x12, 0x6F, 0x8D, 0xE5, 0x4A, 0x30, 0xE0, 0x03, 0x12, 0x6F, 0xC9, +0xE5, 0x4A, 0x30, 0xE4, 0x03, 0x12, 0x70, 0x22, 0xE5, 0x4B, 0x30, 0xE1, 0x02, 0x51, 0x78, 0xE5, +0x4B, 0x30, 0xE0, 0x02, 0x31, 0xFF, 0xE5, 0x4B, 0x30, 0xE3, 0x02, 0xF1, 0xE0, 0xE5, 0x4C, 0x30, +0xE1, 0x05, 0x7F, 0x03, 0x12, 0x44, 0x27, 0xE5, 0x4C, 0x30, 0xE4, 0x03, 0x12, 0x4E, 0xC4, 0xE5, +0x4C, 0x30, 0xE5, 0x03, 0x12, 0x70, 0x38, 0xE5, 0x4C, 0x30, 0xE6, 0x03, 0x12, 0x70, 0xCE, 0x74, +0xF7, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x56, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, +0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, +0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x34, 0x90, 0x06, 0x92, 0xE0, 0x30, +0xE0, 0x23, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, +0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x11, 0x05, 0x90, 0x01, 0x5B, 0x74, 0x05, 0xF0, 0x90, 0x06, +0x92, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xF7, 0xF0, 0x12, 0x47, 0x2A, 0x22, +0x22, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x31, 0xF0, 0x22, 0x90, 0x01, 0xC8, 0xE4, 0xF0, 0xA3, 0xF0, +0xA3, 0xF0, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x51, 0x7F, 0xFF, 0xFE, 0x12, 0x2B, 0x27, 0xBF, 0x01, +0x09, 0x90, 0x81, 0x51, 0xE0, 0x64, 0x03, 0x60, 0x03, 0x22, 0x01, 0xAB, 0xE4, 0x90, 0x81, 0x56, +0xF0, 0x90, 0x81, 0x56, 0xE0, 0xFF, 0xC3, 0x94, 0x02, 0x40, 0x02, 0x01, 0xE6, 0xC3, 0x74, 0xFE, +0x9F, 0xFF, 0xE4, 0x94, 0x00, 0xFE, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x52, 0x12, 0x2B, 0x27, 0xEF, +0x64, 0x01, 0x70, 0x77, 0x90, 0x81, 0x52, 0xE0, 0xFF, 0x54, 0xC0, 0xFE, 0x60, 0x05, 0xEF, 0x54, +0x0C, 0x70, 0x16, 0x90, 0x81, 0x52, 0xE0, 0xFF, 0x54, 0x30, 0x60, 0x67, 0xEF, 0x54, 0x03, 0x60, +0x62, 0x90, 0x81, 0x53, 0x74, 0x01, 0xF0, 0x80, 0x05, 0xE4, 0x90, 0x81, 0x53, 0xF0, 0x90, 0x81, +0x53, 0xE0, 0x90, 0x81, 0x52, 0x70, 0x16, 0xE0, 0xFF, 0xEE, 0x13, 0x13, 0x54, 0x3F, 0x90, 0x81, +0x54, 0xF0, 0xEF, 0x54, 0x0C, 0x13, 0x13, 0x54, 0x3F, 0xA3, 0xF0, 0x80, 0x0D, 0xE0, 0xFE, 0x54, +0x30, 0x90, 0x81, 0x54, 0xF0, 0xEE, 0x54, 0x03, 0xA3, 0xF0, 0x90, 0x81, 0x54, 0xE0, 0x64, 0x30, +0x70, 0x54, 0xA3, 0xE0, 0x64, 0x02, 0x70, 0x4E, 0x90, 0x00, 0xF5, 0xE0, 0x54, 0x40, 0x90, 0x81, +0x57, 0xF0, 0xE0, 0x70, 0x41, 0xA3, 0x74, 0x02, 0xF0, 0x80, 0x10, 0x90, 0x81, 0x58, 0x74, 0x01, +0xF0, 0x80, 0x08, 0x90, 0x81, 0x56, 0xE0, 0x04, 0xF0, 0x01, 0x11, 0x90, 0x01, 0xC4, 0x74, 0xE9, +0xF0, 0x74, 0x57, 0xA3, 0xF0, 0x90, 0x81, 0x58, 0xE0, 0x90, 0x01, 0xC8, 0xF0, 0x90, 0x81, 0x52, +0xE0, 0x90, 0x01, 0xC9, 0xF0, 0x90, 0x81, 0x53, 0xE0, 0x90, 0x01, 0xCA, 0xF0, 0xE4, 0xFD, 0x7F, +0x1F, 0x12, 0x32, 0x1E, 0x80, 0xD5, 0x22, 0x90, 0x00, 0xF7, 0xE0, 0x20, 0xE7, 0x09, 0xE0, 0x7F, +0x01, 0x20, 0xE6, 0x0C, 0x7F, 0x02, 0x22, 0x90, 0x00, 0xF7, 0xE0, 0x30, 0xE6, 0x02, 0x7F, 0x03, +0x22, 0x11, 0xE7, 0x90, 0x80, 0x3C, 0xEF, 0xF0, 0x31, 0x13, 0x90, 0x01, 0x64, 0x74, 0x01, 0xF0, +0x02, 0x2D, 0xA7, 0x31, 0x81, 0x31, 0xB1, 0x31, 0x40, 0x31, 0x5F, 0xE4, 0xF5, 0x35, 0xF5, 0x36, +0xF5, 0x37, 0xF5, 0x38, 0xAD, 0x35, 0x7F, 0x50, 0x12, 0x32, 0x1E, 0xAD, 0x36, 0x7F, 0x51, 0x12, +0x32, 0x1E, 0xAD, 0x37, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xAD, 0x38, 0x7F, 0x53, 0x02, 0x32, 0x1E, +0x75, 0x3D, 0x10, 0xE4, 0xF5, 0x3E, 0x75, 0x3F, 0x07, 0x75, 0x40, 0x02, 0x90, 0x01, 0x30, 0xE5, +0x3D, 0xF0, 0xA3, 0xE5, 0x3E, 0xF0, 0xA3, 0xE5, 0x3F, 0xF0, 0xA3, 0xE5, 0x40, 0xF0, 0x22, 0x75, +0x45, 0x0E, 0x75, 0x46, 0x01, 0x43, 0x46, 0x10, 0x75, 0x47, 0x03, 0x75, 0x48, 0x62, 0x90, 0x01, +0x38, 0xE5, 0x45, 0xF0, 0xA3, 0xE5, 0x46, 0xF0, 0xA3, 0xE5, 0x47, 0xF0, 0xA3, 0xE5, 0x48, 0xF0, +0x22, 0x90, 0x01, 0x30, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x38, 0xF0, +0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x50, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x51, +0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x53, 0x02, 0x32, +0x1E, 0x90, 0x01, 0x34, 0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x3C, +0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, +0x55, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x56, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x57, 0x02, +0x32, 0x1E, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x80, 0xFD, 0x7F, 0x80, 0x12, 0x32, 0x1E, 0x90, 0xFD, +0x00, 0xE0, 0x54, 0xBF, 0xF0, 0x12, 0x57, 0xE9, 0x51, 0x77, 0x12, 0x32, 0x77, 0x51, 0xC9, 0x51, +0x5E, 0x7F, 0x01, 0x12, 0x43, 0x15, 0x90, 0x81, 0x41, 0x74, 0x02, 0xF0, 0xFF, 0x12, 0x43, 0x15, +0x90, 0x81, 0x41, 0xE0, 0x04, 0xF0, 0x7F, 0x03, 0x12, 0x43, 0x15, 0x90, 0x81, 0x41, 0xE0, 0x04, +0xF0, 0x31, 0x01, 0x51, 0x3F, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x40, 0xFD, 0x7F, 0x80, 0x12, 0x32, +0x1E, 0x75, 0x20, 0xFF, 0x51, 0x68, 0x51, 0xF9, 0x51, 0x7F, 0xE4, 0xFF, 0x02, 0x43, 0x9E, 0x51, +0x62, 0x51, 0x6F, 0x51, 0xA7, 0x71, 0x4F, 0x51, 0x8A, 0x51, 0x95, 0x90, 0x81, 0x45, 0xE0, 0x54, +0xFE, 0xF0, 0xA3, 0x74, 0x03, 0xF0, 0xA3, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0xE4, 0xF5, +0x4D, 0x22, 0xE4, 0x90, 0x80, 0xDE, 0xF0, 0x22, 0x75, 0xE8, 0x03, 0x75, 0xA8, 0x84, 0x22, 0xE4, +0x90, 0x80, 0xD8, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x01, 0x94, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, +0x01, 0xE4, 0x74, 0x0B, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x81, 0x3F, 0xE0, 0x54, 0xFE, +0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x42, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, +0x74, 0x0A, 0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0xFD, +0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0xE4, 0xA3, 0xF0, +0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0x74, 0x0C, 0xF0, 0x22, 0x90, 0x01, 0x01, 0xE0, 0x44, 0x04, 0xF0, +0x90, 0x01, 0x9C, 0x74, 0x7E, 0xF0, 0xA3, 0x74, 0x92, 0xF0, 0xA3, 0x74, 0xA0, 0xF0, 0xA3, 0x74, +0x24, 0xF0, 0x90, 0x01, 0x9B, 0x74, 0x49, 0xF0, 0x90, 0x01, 0x9A, 0x74, 0xE0, 0xF0, 0x90, 0x01, +0x99, 0xE4, 0xF0, 0x90, 0x01, 0x98, 0x04, 0xF0, 0x22, 0xE4, 0x90, 0x81, 0x51, 0xF0, 0xA3, 0xF0, +0x90, 0x01, 0x98, 0xE0, 0x7F, 0x00, 0x30, 0xE4, 0x02, 0x7F, 0x01, 0xEF, 0x64, 0x01, 0x60, 0x3E, +0xC3, 0x90, 0x81, 0x52, 0xE0, 0x94, 0x88, 0x90, 0x81, 0x51, 0xE0, 0x94, 0x13, 0x40, 0x08, 0x90, +0x01, 0xC1, 0xE0, 0x44, 0x10, 0xF0, 0x22, 0x90, 0x81, 0x51, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, +0xA9, 0x7F, 0x14, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0xD3, 0x90, 0x81, 0x52, 0xE0, 0x94, 0x32, 0x90, +0x81, 0x51, 0xE0, 0x94, 0x00, 0x40, 0xB9, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE3, 0xB2, 0x22, 0xE4, +0x90, 0x81, 0x27, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0xF0, 0x54, 0xF0, 0xF0, +0x90, 0x81, 0x24, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x2D, +0x74, 0x01, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xFB, 0xF0, 0xA3, 0xE0, 0x54, 0xFB, +0xF0, 0xE4, 0x90, 0x81, 0x30, 0xF0, 0x90, 0x81, 0x2F, 0x74, 0x07, 0xF0, 0x90, 0x81, 0x32, 0xE4, +0xF0, 0xA3, 0x74, 0x02, 0xF0, 0xE4, 0x90, 0x81, 0x2B, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xFE, +0xF0, 0x90, 0x81, 0x29, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xDF, 0xF0, 0x90, 0x81, +0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0xE0, +0x54, 0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x54, 0xF7, 0xF0, 0x90, 0x81, 0x34, 0x12, 0x20, 0xDA, 0x00, +0x00, 0x00, 0x00, 0x90, 0x80, 0x3C, 0xE0, 0xB4, 0x01, 0x08, 0x90, 0x81, 0x31, 0x74, 0x99, 0xF0, +0x80, 0x12, 0x90, 0x80, 0x3C, 0xE0, 0x90, 0x81, 0x31, 0xB4, 0x03, 0x05, 0x74, 0x90, 0xF0, 0x80, +0x03, 0x74, 0x40, 0xF0, 0x90, 0x81, 0x38, 0x74, 0x01, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xE0, +0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, +0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0x54, 0xBF, 0xF0, +0xE4, 0xA3, 0xF0, 0x22, 0xE4, 0x90, 0x81, 0x59, 0xF0, 0x90, 0x81, 0x59, 0xE0, 0x64, 0x01, 0xF0, +0x24, 0x24, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x5C, 0xA3, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0xFF, 0x90, +0x81, 0x29, 0xE0, 0x6F, 0x60, 0x03, 0x12, 0x47, 0x2A, 0xD1, 0x08, 0xBF, 0x01, 0x02, 0x91, 0x5F, +0xB1, 0xF2, 0x12, 0x32, 0x9E, 0xBF, 0x01, 0x02, 0xB1, 0x67, 0x12, 0x42, 0x4D, 0x80, 0xCA, 0xD3, +0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0x24, 0xE0, 0x30, 0xE0, 0x24, 0x90, 0x81, 0x1F, +0xE0, 0xFF, 0x30, 0xE0, 0x1A, 0xC3, 0x13, 0x30, 0xE0, 0x07, 0xB1, 0xFB, 0xBF, 0x01, 0x12, 0x80, +0x0A, 0x90, 0x81, 0x23, 0xE0, 0xFF, 0x60, 0x03, 0xB4, 0x08, 0x06, 0x91, 0x96, 0x80, 0x02, 0x91, +0xA6, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xB1, 0x22, 0x91, +0xBA, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0x2A, 0xE0, 0x70, 0x0D, 0xD1, 0x2F, 0xBF, 0x01, +0x08, 0x91, 0x96, 0x90, 0x01, 0xE5, 0xE0, 0x04, 0xF0, 0x22, 0xB1, 0xF3, 0x90, 0x00, 0x08, 0xE0, +0x54, 0xEF, 0xFD, 0x7F, 0x08, 0x12, 0x32, 0x1E, 0xE4, 0xFF, 0x8F, 0x50, 0xE4, 0x90, 0x81, 0x5A, +0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x09, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0xEF, 0x65, +0x50, 0x60, 0x3E, 0xC3, 0x90, 0x81, 0x5B, 0xE0, 0x94, 0x88, 0x90, 0x81, 0x5A, 0xE0, 0x94, 0x13, +0x40, 0x08, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x10, 0xF0, 0x22, 0x90, 0x81, 0x5A, 0xE4, 0x75, 0xF0, +0x01, 0x12, 0x44, 0xA9, 0x7F, 0x14, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0xD3, 0x90, 0x81, 0x5B, 0xE0, +0x94, 0x32, 0x90, 0x81, 0x5A, 0xE0, 0x94, 0x00, 0x40, 0xB9, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE0, +0xB2, 0x22, 0x90, 0x81, 0x31, 0xE0, 0xFD, 0x7F, 0x93, 0x12, 0x32, 0x1E, 0x90, 0x81, 0x28, 0xE0, +0x60, 0x12, 0x90, 0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x05, 0x74, 0x10, 0xF0, 0x80, 0x06, 0x90, 0x01, +0x2F, 0x74, 0x90, 0xF0, 0x90, 0x00, 0x08, 0xE0, 0x44, 0x10, 0xFD, 0x7F, 0x08, 0x12, 0x32, 0x1E, +0x7F, 0x01, 0x91, 0xCA, 0x90, 0x00, 0x90, 0xE0, 0x44, 0x01, 0xFD, 0x7F, 0x90, 0x12, 0x32, 0x1E, +0x7F, 0x14, 0x7E, 0x00, 0x02, 0x32, 0xAA, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x2D, +0xA7, 0xE4, 0xF5, 0x52, 0x12, 0x32, 0x9E, 0xEF, 0x60, 0x73, 0x63, 0x52, 0x01, 0xE5, 0x52, 0x24, +0x67, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x5D, 0xA3, 0xF0, 0x90, 0x00, 0x88, 0xE0, 0xF5, 0x50, 0xF5, +0x51, 0x54, 0x0F, 0x60, 0xDF, 0xE5, 0x50, 0x30, 0xE0, 0x0B, 0x20, 0xE4, 0x03, 0x12, 0x29, 0xC5, +0x53, 0x51, 0xEE, 0x80, 0x3F, 0xE5, 0x50, 0x30, 0xE1, 0x16, 0x20, 0xE5, 0x0E, 0x12, 0x11, 0xBD, +0xEF, 0x70, 0x03, 0x43, 0x51, 0x20, 0x90, 0x01, 0x06, 0xE4, 0xF0, 0x53, 0x51, 0xFD, 0x80, 0x24, +0xE5, 0x50, 0x30, 0xE2, 0x0B, 0x20, 0xE6, 0x03, 0x12, 0x67, 0x06, 0x53, 0x51, 0xFB, 0x80, 0x14, +0xE5, 0x50, 0x30, 0xE3, 0x0F, 0x20, 0xE7, 0x09, 0x12, 0x61, 0x6E, 0xEF, 0x70, 0x03, 0x43, 0x51, +0x80, 0x53, 0x51, 0xF7, 0xAD, 0x51, 0x7F, 0x88, 0x12, 0x32, 0x1E, 0x80, 0x87, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x22, 0x90, 0x00, 0x90, 0xE0, 0x20, 0xE0, 0xF9, 0x22, 0x90, 0x81, 0x22, 0xE0, 0x64, +0x02, 0x7F, 0x01, 0x60, 0x02, 0x7F, 0x00, 0x22, 0x7F, 0x02, 0x90, 0x81, 0x41, 0xE0, 0xFE, 0xEF, +0xC3, 0x9E, 0x50, 0x18, 0xEF, 0x25, 0xE0, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE4, 0x0B, 0x90, 0x01, +0xB8, 0x74, 0x08, 0xF0, 0xA3, 0xF0, 0x7F, 0x00, 0x22, 0x0F, 0x80, 0xDE, 0x7F, 0x01, 0x22, 0x90, +0x02, 0x87, 0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x01, 0xF0, 0x80, 0x17, 0x90, 0x02, 0x86, +0xE0, 0x20, 0xE1, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, +0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x08, 0xF0, 0x7F, 0x00, 0x22, 0xE4, 0xFB, 0xFA, +0xFD, 0x7F, 0x01, 0x12, 0x44, 0x4E, 0x90, 0x81, 0xBD, 0xEF, 0xF0, 0x60, 0xF0, 0xD1, 0x71, 0x80, +0xEC, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0x90, 0x81, +0xBE, 0xF0, 0x90, 0x81, 0xBE, 0xE0, 0xFD, 0x70, 0x02, 0xE1, 0x9C, 0x90, 0x82, 0x09, 0xE0, 0xFF, +0x74, 0x01, 0x7E, 0x00, 0xA8, 0x07, 0x08, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, +0xFF, 0xEF, 0x5D, 0x70, 0x02, 0xE1, 0x95, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, +0xD0, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xBF, 0xF0, 0x75, 0x13, 0x01, 0x75, 0x14, 0x81, 0x75, +0x15, 0xBF, 0x75, 0x16, 0x01, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0xC0, 0x12, 0x2B, 0xED, 0x90, 0x82, +0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD1, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC1, 0xF0, +0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD2, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, +0xC2, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD3, 0x12, 0x45, 0x0A, 0xE0, +0x90, 0x81, 0xC3, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF0, 0x12, 0x45, +0x0A, 0xE0, 0x90, 0x81, 0xC4, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF1, +0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC5, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, 0x04, 0x90, +0x01, 0xF2, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC6, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0x75, 0xF0, +0x04, 0x90, 0x01, 0xF3, 0x12, 0x45, 0x0A, 0xE0, 0x90, 0x81, 0xC7, 0xF0, 0x90, 0x81, 0xBE, 0xE0, +0xFF, 0x90, 0x82, 0x09, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x06, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, +0xFC, 0xF4, 0x5F, 0x90, 0x81, 0xBE, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, +0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x90, 0x01, 0xCC, 0xF0, 0x90, 0x81, 0xC0, 0xE0, 0xFF, +0x7B, 0x01, 0x7A, 0x81, 0x79, 0xC1, 0x12, 0x55, 0x3F, 0x90, 0x82, 0x09, 0xE0, 0x04, 0xF0, 0xE0, +0x54, 0x03, 0xF0, 0xC1, 0x82, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x02, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, +0x22, 0xE4, 0xFB, 0xFA, 0xFD, 0x7F, 0x01, 0x12, 0x44, 0x4E, 0x90, 0x81, 0xD0, 0xEF, 0xF0, 0x60, +0xF0, 0x12, 0x6C, 0x19, 0x80, 0xEB, 0x90, 0x81, 0xD4, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0x12, +0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x90, 0x81, 0xE2, 0xF0, 0x7F, 0x24, 0x7E, 0x08, 0x12, +0x2D, 0x5C, 0x90, 0x81, 0xDA, 0x12, 0x20, 0xCE, 0x90, 0x81, 0xD4, 0xE0, 0xFB, 0x70, 0x08, 0x90, +0x81, 0xDA, 0x12, 0x44, 0xD9, 0x80, 0x16, 0xEB, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, +0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2D, 0x5C, 0x90, 0x81, 0xDE, +0x12, 0x20, 0xCE, 0x90, 0x81, 0xD5, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x17, 0x12, 0x20, +0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x81, 0xDE, 0x12, 0x44, 0xD9, 0xED, +0x54, 0x7F, 0xFD, 0xEC, 0x54, 0x80, 0xFC, 0x12, 0x44, 0xCC, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x81, +0xDE, 0x12, 0x20, 0xCE, 0x90, 0x81, 0xDA, 0x12, 0x44, 0xD9, 0xEC, 0x54, 0x7F, 0xFC, 0x90, 0x85, +0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xD4, 0xE0, 0x75, +0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, +0xFF, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x81, 0xDE, 0x12, 0x44, 0xD9, 0x90, 0x85, 0xBB, 0x12, 0x20, +0xCE, 0xD0, 0x07, 0xD0, 0x06, 0x12, 0x2E, 0xA2, 0x90, 0x81, 0xDA, 0x12, 0x44, 0xD9, 0xEC, 0x44, +0x80, 0xFC, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, +0x81, 0xD4, 0xE0, 0x70, 0x04, 0x7F, 0x20, 0x80, 0x09, 0x90, 0x81, 0xD4, 0xE0, 0xB4, 0x01, 0x16, +0x7F, 0x28, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0x78, 0x08, 0x12, 0x20, 0xA8, 0xEF, 0x54, 0x01, 0xFF, +0xE4, 0x90, 0x81, 0xE2, 0xEF, 0xF0, 0x90, 0x81, 0xE2, 0xE0, 0x90, 0x81, 0xD4, 0x60, 0x0E, 0xE0, +0x75, 0xF0, 0x08, 0xA4, 0x24, 0x66, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0x80, 0x0C, 0xE0, 0x75, 0xF0, +0x08, 0xA4, 0x24, 0x64, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, +0x12, 0x2D, 0x5C, 0xED, 0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x90, 0x81, 0xD6, 0x12, 0x20, 0xCE, 0x90, +0x81, 0xD6, 0x02, 0x44, 0xD9, 0x90, 0x81, 0xE3, 0xEF, 0xF0, 0xAB, 0x05, 0x90, 0x81, 0xE9, 0x12, +0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x03, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x14, 0x12, 0x20, +0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x81, 0xE5, 0x12, 0x44, 0xD9, 0xED, +0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x12, 0x44, 0xCC, 0xEC, 0x54, 0x0F, 0xFC, 0x90, 0x81, 0xE9, 0x12, +0x20, 0xCE, 0x90, 0x81, 0xE3, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x60, 0xF5, 0x82, 0xE4, 0x34, +0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x81, 0xE9, 0x12, +0x44, 0xD9, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0xD0, 0x07, 0xD0, 0x06, 0x02, 0x2E, 0xA2, 0xD3, +0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x5F, 0xB6, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x78, 0x10, +0x74, 0x01, 0xF2, 0x90, 0x02, 0x09, 0xE0, 0x78, 0x00, 0xF2, 0x08, 0x74, 0x20, 0xF2, 0x18, 0xE2, +0xFF, 0x30, 0xE0, 0x05, 0x08, 0xE2, 0x24, 0x80, 0xF2, 0xEF, 0xC3, 0x13, 0x90, 0xFD, 0x10, 0xF0, +0x78, 0x01, 0xE2, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x78, 0x03, 0xF2, +0x64, 0x04, 0x60, 0x0D, 0xE2, 0xFF, 0x64, 0x08, 0x60, 0x07, 0xEF, 0x64, 0x0C, 0x60, 0x02, 0x61, +0xDE, 0xE4, 0x78, 0x02, 0xF2, 0x78, 0x03, 0xE2, 0xFF, 0x18, 0xE2, 0xC3, 0x9F, 0x50, 0x2D, 0xE2, +0xFD, 0x18, 0xE2, 0x2D, 0x90, 0x81, 0x5A, 0xF0, 0xE0, 0xFF, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, +0xFC, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x04, 0x2D, 0xF8, 0xEE, 0xF2, 0xEF, 0xB4, 0xFF, 0x06, 0x90, +0xFD, 0x10, 0xE0, 0x04, 0xF0, 0x78, 0x02, 0xE2, 0x04, 0xF2, 0x80, 0xC9, 0x78, 0x04, 0xE2, 0x78, +0x12, 0xF2, 0xFF, 0x78, 0x05, 0xE2, 0x78, 0x11, 0xF2, 0x78, 0x06, 0xE2, 0x78, 0x13, 0xF2, 0x78, +0x07, 0xE2, 0x78, 0x14, 0xF2, 0x78, 0x08, 0xE2, 0x78, 0x33, 0xF2, 0x78, 0x09, 0xE2, 0x78, 0x34, +0xF2, 0x78, 0x0A, 0xE2, 0x78, 0x35, 0xF2, 0x78, 0x0B, 0xE2, 0x78, 0x36, 0xF2, 0x78, 0x0C, 0xE2, +0x78, 0x37, 0xF2, 0x78, 0x0D, 0xE2, 0x78, 0x38, 0xF2, 0x78, 0x0E, 0xE2, 0x78, 0x39, 0xF2, 0x78, +0x0F, 0xE2, 0x78, 0x3A, 0xF2, 0xE4, 0x78, 0x15, 0xF2, 0xEF, 0x24, 0xF8, 0x60, 0x75, 0x24, 0xFC, +0x60, 0x6C, 0x24, 0x08, 0x60, 0x02, 0x61, 0xC0, 0x78, 0x11, 0xE2, 0xB4, 0x01, 0x05, 0x12, 0x29, +0xC5, 0x61, 0xC5, 0x78, 0x11, 0xE2, 0xB4, 0x02, 0x05, 0x12, 0x11, 0xBD, 0x61, 0xC5, 0x78, 0x11, +0xE2, 0xB4, 0x03, 0x04, 0xF1, 0x06, 0x61, 0xC5, 0x78, 0x11, 0xE2, 0xB4, 0x10, 0x17, 0x78, 0x14, +0xE2, 0xFE, 0x18, 0xE2, 0xFD, 0xED, 0xFF, 0x78, 0x16, 0xEE, 0xF2, 0xFE, 0x08, 0xEF, 0xF2, 0xFF, +0x12, 0x32, 0xAA, 0x61, 0xC5, 0x78, 0x11, 0xE2, 0xB4, 0x11, 0x17, 0x78, 0x14, 0xE2, 0xFE, 0x18, +0xE2, 0xFD, 0xED, 0xFF, 0x78, 0x16, 0xEE, 0xF2, 0xFE, 0x08, 0xEF, 0xF2, 0xFF, 0x12, 0x32, 0x06, +0x61, 0xC5, 0x78, 0x11, 0xE2, 0xF4, 0x60, 0x02, 0x61, 0xC5, 0x18, 0xF2, 0x61, 0xC5, 0x78, 0x15, +0x74, 0x01, 0xF2, 0x78, 0x11, 0xE2, 0x64, 0x07, 0x60, 0x02, 0x61, 0xAA, 0x78, 0x34, 0xE2, 0xFF, +0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x20, 0xBB, 0xC0, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, +0x07, 0x78, 0x33, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0xC0, 0x04, +0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x78, 0x35, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x10, +0x12, 0x20, 0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x78, 0x18, +0x12, 0x44, 0xFE, 0x78, 0x15, 0xE2, 0x70, 0x02, 0x61, 0x93, 0x18, 0xE2, 0xFF, 0x18, 0xE2, 0xFD, +0x31, 0x5F, 0x78, 0x1C, 0x12, 0x44, 0xFE, 0x78, 0x38, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, +0x08, 0x12, 0x20, 0xBB, 0xC0, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x78, 0x37, 0xE2, 0xFF, +0xE4, 0xFC, 0xFD, 0xFE, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, +0x07, 0x78, 0x39, 0xE2, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x10, 0x12, 0x20, 0xBB, 0xD0, 0x03, +0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x78, 0x20, 0x12, 0x44, 0xFE, 0x78, 0x20, +0x12, 0x44, 0xE5, 0x12, 0x20, 0x9B, 0x78, 0x1C, 0x12, 0x44, 0xF1, 0x12, 0x44, 0xBF, 0xC0, 0x04, +0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x78, 0x18, 0x12, 0x44, 0xE5, 0x78, 0x20, 0x12, 0x44, 0xF1, +0x12, 0x44, 0xBF, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x78, 0x18, +0x12, 0x44, 0xFE, 0x78, 0x18, 0x12, 0x44, 0xE5, 0x90, 0x81, 0xF9, 0x12, 0x20, 0xCE, 0x78, 0x13, +0xE2, 0xFD, 0x08, 0xE2, 0xFF, 0x12, 0x55, 0x1C, 0x80, 0x1B, 0x78, 0x13, 0xE2, 0xFF, 0x08, 0xE2, +0xFD, 0x78, 0x11, 0xE2, 0xFB, 0x78, 0x15, 0xE2, 0x90, 0x81, 0xBC, 0xF0, 0x71, 0xE1, 0x80, 0x05, +0x78, 0x10, 0x74, 0x02, 0xF2, 0x78, 0x10, 0xE2, 0xFF, 0xC3, 0x94, 0x02, 0x50, 0x10, 0xEF, 0x60, +0x0A, 0x78, 0x02, 0xE2, 0xFF, 0x18, 0xE2, 0x2F, 0xF2, 0x21, 0x90, 0x7F, 0x01, 0x22, 0x7F, 0x00, +0x22, 0xAC, 0x07, 0xED, 0xAD, 0x04, 0x78, 0x24, 0xF2, 0xED, 0x08, 0xF2, 0xEB, 0xB4, 0x04, 0x07, +0x78, 0x27, 0x74, 0x01, 0xF2, 0x80, 0x0E, 0xEB, 0x78, 0x27, 0xB4, 0x05, 0x05, 0x74, 0x02, 0xF2, +0x80, 0x03, 0x74, 0x04, 0xF2, 0xD3, 0x78, 0x25, 0xE2, 0x94, 0xFF, 0x18, 0xE2, 0x94, 0x00, 0x50, +0x63, 0xE4, 0x78, 0x26, 0xF2, 0x78, 0x27, 0xE2, 0xFF, 0x18, 0xE2, 0xFE, 0xC3, 0x9F, 0x40, 0x02, +0xA1, 0x7F, 0x74, 0x33, 0x2E, 0xF8, 0xE2, 0x78, 0x28, 0xF2, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x2D, +0x74, 0x37, 0x2E, 0xF8, 0xE2, 0x78, 0x32, 0xF2, 0xEE, 0xFF, 0x78, 0x25, 0xE2, 0x2F, 0xFF, 0x18, +0xE2, 0x34, 0x00, 0x8F, 0x82, 0xF5, 0x83, 0xE0, 0x78, 0x29, 0xF2, 0x78, 0x32, 0xE2, 0xFF, 0xF4, +0xFE, 0x78, 0x29, 0xE2, 0x5E, 0xFE, 0x18, 0xE2, 0xFD, 0xEF, 0x5D, 0x4E, 0xF2, 0x78, 0x24, 0x08, +0xE2, 0xFF, 0x08, 0xE2, 0x2F, 0xFF, 0x78, 0x28, 0xE2, 0xFD, 0x12, 0x32, 0x1E, 0x78, 0x26, 0xE2, +0x04, 0xF2, 0x80, 0xA1, 0xD3, 0x78, 0x25, 0xE2, 0x94, 0xFF, 0x18, 0xE2, 0x94, 0x07, 0x50, 0x69, +0xE4, 0x78, 0x26, 0xF2, 0x78, 0x27, 0xE2, 0xFF, 0x18, 0xE2, 0xFE, 0xC3, 0x9F, 0x40, 0x02, 0xA1, +0x7F, 0x74, 0x33, 0x2E, 0xF8, 0xE2, 0x78, 0x28, 0xF2, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x2D, 0x78, +0x26, 0xE2, 0xFF, 0xFD, 0x18, 0xE2, 0x2D, 0xFD, 0x18, 0xE2, 0x34, 0x00, 0x8D, 0x82, 0xF5, 0x83, +0xE0, 0x78, 0x29, 0xF2, 0x74, 0x37, 0x2F, 0xF8, 0xE2, 0x78, 0x32, 0xF2, 0xE2, 0xFF, 0xF4, 0xFE, +0x78, 0x29, 0xE2, 0x5E, 0xFE, 0x18, 0xE2, 0xFD, 0xEF, 0x5D, 0x4E, 0xF2, 0x78, 0x28, 0xE2, 0xFF, +0x78, 0x26, 0xE2, 0xFD, 0x18, 0xE2, 0x2D, 0xFD, 0x18, 0xE2, 0x34, 0x00, 0x8D, 0x82, 0xF5, 0x83, +0xEF, 0xF0, 0x78, 0x26, 0xE2, 0x04, 0xF2, 0x80, 0x9B, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x0F, 0x78, +0x24, 0xE2, 0xFE, 0x08, 0xE2, 0xFF, 0x12, 0x2D, 0x5C, 0x78, 0x2E, 0x12, 0x44, 0xFE, 0xE4, 0x78, +0x26, 0xF2, 0x78, 0x27, 0xE2, 0xFF, 0x18, 0xE2, 0xFE, 0xC3, 0x9F, 0x50, 0x5D, 0x74, 0x33, 0x2E, +0xF8, 0xE2, 0x78, 0x28, 0xF2, 0x90, 0x81, 0xBC, 0xE0, 0x60, 0x2B, 0x78, 0x2E, 0x12, 0x44, 0xE5, +0x78, 0x26, 0xE2, 0xFB, 0x75, 0xF0, 0x08, 0xA4, 0xF9, 0xF8, 0x12, 0x20, 0xA8, 0x78, 0x29, 0xEF, +0xF2, 0x74, 0x37, 0x2B, 0xF8, 0xE2, 0x78, 0x32, 0xF2, 0xE2, 0xFE, 0xF4, 0x5F, 0xFF, 0x78, 0x28, +0xE2, 0xFD, 0xEE, 0x5D, 0x4F, 0xF2, 0x78, 0x28, 0xE2, 0xFF, 0x78, 0x26, 0xE2, 0xFD, 0xC3, 0x74, +0x03, 0x9D, 0xFD, 0xE4, 0x94, 0x00, 0xFC, 0x7B, 0xFE, 0x74, 0x2A, 0x2D, 0xF9, 0x74, 0x80, 0x3C, +0xFA, 0xEF, 0x12, 0x1F, 0xEA, 0xE2, 0x04, 0xF2, 0x80, 0x98, 0x78, 0x2A, 0x12, 0x44, 0xE5, 0x90, +0x85, 0xBB, 0x12, 0x20, 0xCE, 0x78, 0x24, 0xE2, 0xFE, 0x08, 0xE2, 0xFF, 0x12, 0x2E, 0xA2, 0x22, +0x22, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x1F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xFE, 0x12, +0x1F, 0xA4, 0xFD, 0xC3, 0x13, 0x30, 0xE0, 0x12, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, 0x90, 0x00, +0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0xCF, 0xF0, 0x80, 0x05, 0x90, 0x81, 0xCF, 0xEF, 0xF0, 0x90, +0x81, 0xCE, 0xEE, 0xF0, 0x90, 0x81, 0xCF, 0xE0, 0xFE, 0x90, 0x81, 0xCE, 0xE0, 0xFF, 0xD3, 0x9E, +0x50, 0x38, 0x90, 0x81, 0xCB, 0x12, 0x45, 0x16, 0x12, 0x1F, 0xA4, 0x54, 0x01, 0xFE, 0x74, 0xDE, +0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xEE, 0xF0, 0x74, 0xDE, 0x2F, 0xF5, 0x82, 0xE4, +0x34, 0x80, 0xF5, 0x83, 0xE0, 0x70, 0x04, 0xD1, 0x25, 0x80, 0x07, 0x90, 0x81, 0xCE, 0xE0, 0xFF, +0xB1, 0x80, 0x90, 0x81, 0xCE, 0xE0, 0x04, 0xF0, 0x80, 0xBA, 0x90, 0x80, 0xDE, 0xE0, 0x70, 0x24, +0x90, 0x81, 0x2A, 0xE0, 0x70, 0x04, 0xFF, 0x12, 0x49, 0x93, 0x90, 0x81, 0x2A, 0xE0, 0x64, 0x0C, +0x60, 0x02, 0xD1, 0x26, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xBF, +0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x22, 0x90, 0x06, 0x04, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x05, 0x22, +0xE4, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x22, 0x90, 0x81, 0xED, 0xEF, 0xF0, 0xA3, 0xED, +0xF0, 0xAD, 0x03, 0xAC, 0x02, 0xE4, 0x90, 0x81, 0xF5, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0xC4, 0x74, +0x39, 0xF0, 0x74, 0x66, 0xA3, 0xF0, 0xEC, 0x54, 0x3F, 0xFC, 0x90, 0x01, 0x40, 0xED, 0xF0, 0xAE, +0x04, 0xEE, 0xA3, 0xF0, 0x90, 0x81, 0xED, 0xE0, 0x24, 0x81, 0x60, 0x34, 0x24, 0xDA, 0x60, 0x1C, +0x24, 0x3C, 0x70, 0x41, 0x90, 0x81, 0xEE, 0xE0, 0xC4, 0x33, 0x33, 0x33, 0x54, 0x80, 0x90, 0x81, +0xF2, 0xF0, 0xA3, 0x74, 0x69, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x80, 0x2C, 0x90, 0x81, 0xEE, 0xE0, +0x54, 0x01, 0x90, 0x81, 0xF2, 0xF0, 0xA3, 0x74, 0xA5, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0x80, 0x18, +0x90, 0x81, 0xEE, 0xE0, 0xC4, 0x54, 0x10, 0x90, 0x81, 0xF2, 0xF0, 0xA3, 0x74, 0x7F, 0xF0, 0xA3, +0x74, 0x10, 0xF0, 0x80, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x81, 0xF3, 0xE0, 0x90, 0x01, 0x06, 0xF0, +0x90, 0x81, 0xF2, 0xE0, 0x60, 0x0E, 0x90, 0x01, 0x42, 0xF0, 0x90, 0x81, 0xF1, 0xE0, 0x90, 0x01, +0x43, 0xF0, 0x80, 0x0D, 0x90, 0x01, 0x43, 0xE4, 0xF0, 0x90, 0x81, 0xF2, 0xE0, 0x90, 0x01, 0x42, +0xF0, 0x90, 0x81, 0xF4, 0xE0, 0xFF, 0x90, 0x01, 0x42, 0xE0, 0x5F, 0xFF, 0x90, 0x81, 0xF2, 0xE0, +0x6F, 0x60, 0xEE, 0x74, 0x39, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x66, 0xA3, 0xF0, 0x90, 0x01, +0x43, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0xE4, 0x90, 0x81, 0x6A, 0xF0, 0x90, 0x87, 0x5F, 0xE0, 0x90, +0x81, 0x69, 0xF0, 0xE4, 0x90, 0x81, 0x76, 0xF0, 0x90, 0x81, 0x66, 0xF0, 0x90, 0x81, 0x66, 0xE0, +0xFF, 0xC3, 0x94, 0x40, 0x50, 0x15, 0x74, 0x79, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, +0x74, 0xFF, 0xF0, 0x90, 0x81, 0x66, 0xE0, 0x04, 0xF0, 0x80, 0xE1, 0xE4, 0x90, 0x81, 0x66, 0xF0, +0x90, 0x81, 0x69, 0xE0, 0xFF, 0x90, 0x81, 0x66, 0xE0, 0xFE, 0xC3, 0x9F, 0x40, 0x03, 0x02, 0x68, +0x12, 0x74, 0xDF, 0x2E, 0xF9, 0xE4, 0x34, 0x86, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, +0x16, 0x0A, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x5B, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x5C, 0xE0, 0xFF, +0x12, 0x2F, 0x27, 0xEF, 0x04, 0x90, 0x81, 0x76, 0xF0, 0x90, 0x81, 0x5B, 0xE0, 0xFF, 0xA3, 0xE0, +0xFD, 0x12, 0x31, 0xEA, 0xEF, 0x24, 0xC8, 0x90, 0x81, 0x78, 0xF0, 0x75, 0xF0, 0x08, 0xA4, 0xF0, +0x90, 0x81, 0x5C, 0xE0, 0x54, 0x0F, 0x90, 0x81, 0x77, 0xF0, 0xE4, 0x90, 0x81, 0x65, 0xF0, 0x90, +0x81, 0x67, 0xF0, 0x90, 0x81, 0x67, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, 0x57, 0x90, 0x81, 0x77, +0xE0, 0xFE, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x13, 0xD8, 0xFC, 0x20, 0xE0, 0x3E, 0x90, 0x81, +0x67, 0xE0, 0x25, 0xE0, 0xFF, 0x90, 0x81, 0x78, 0xE0, 0x2F, 0x24, 0x79, 0xF9, 0xE4, 0x34, 0x81, +0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x01, 0x90, 0x81, 0x65, 0xE0, 0x75, 0xF0, 0x02, 0xA4, 0x24, +0x5D, 0xF9, 0x74, 0x81, 0x35, 0xF0, 0x8B, 0x13, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x02, 0xD0, +0x01, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x65, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x67, 0xE0, +0x04, 0xF0, 0x80, 0x9F, 0x90, 0x81, 0x76, 0xE0, 0xFF, 0x90, 0x81, 0x66, 0xE0, 0x2F, 0xF0, 0x02, +0x67, 0x40, 0xE4, 0x90, 0x81, 0x6A, 0xF0, 0x90, 0x81, 0x6A, 0xE0, 0xC3, 0x94, 0x40, 0x40, 0x02, +0x41, 0xAF, 0xE0, 0xFF, 0x24, 0x79, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x90, 0x81, +0x6C, 0xF0, 0xE0, 0xFE, 0x54, 0xF0, 0xC4, 0x54, 0x0F, 0xFD, 0x90, 0x81, 0x6B, 0xF0, 0xEE, 0x54, +0x0F, 0xFE, 0xA3, 0xF0, 0x74, 0x7A, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x90, +0x81, 0x6D, 0xF0, 0xFC, 0xEE, 0xFE, 0xEC, 0xFB, 0xEB, 0xFF, 0x90, 0x81, 0x72, 0xEE, 0xF0, 0xA3, +0xEF, 0xF0, 0xED, 0x12, 0x45, 0x28, 0x68, 0x8B, 0x00, 0x68, 0xC2, 0x01, 0x69, 0x73, 0x02, 0x6A, +0xA0, 0x03, 0x69, 0x8E, 0x04, 0x69, 0xAF, 0x05, 0x69, 0xAF, 0x06, 0x69, 0xAF, 0x07, 0x69, 0xAF, +0x08, 0x6A, 0x33, 0x09, 0x6A, 0x69, 0x0A, 0x00, 0x00, 0x6A, 0xAF, 0x90, 0x81, 0x6A, 0xE0, 0xFD, +0x24, 0x7C, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x7B, 0x2D, 0xF5, 0x82, +0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFD, 0xED, 0xFF, 0x90, 0x81, 0x74, 0xEE, 0xF0, 0xFC, 0xA3, +0xEF, 0xF0, 0x90, 0x81, 0x6D, 0xE0, 0xFF, 0x12, 0x2F, 0x96, 0x90, 0x81, 0x68, 0x74, 0x02, 0xF0, +0x41, 0xA0, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7C, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, +0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, +0xAB, 0x07, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, +0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, +0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7D, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFF, 0xE4, +0xFC, 0xFD, 0xFE, 0x78, 0x10, 0x12, 0x20, 0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, +0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x81, 0x6A, 0xE0, 0x24, +0x7E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x18, +0x12, 0x20, 0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x90, 0x81, +0x6E, 0x12, 0x20, 0xCE, 0x90, 0x81, 0x6E, 0x12, 0x44, 0xD9, 0x90, 0x85, 0x96, 0x12, 0x20, 0xCE, +0x90, 0x81, 0x72, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2E, 0xE4, 0x90, 0x81, 0x68, 0x74, 0x04, +0xF0, 0x41, 0xA0, 0x90, 0x81, 0x6D, 0xE0, 0xFD, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, +0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFB, 0xE4, 0xFF, 0x12, 0x30, 0xC7, 0x80, 0x19, 0x90, 0x81, +0x6D, 0xE0, 0xFD, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, +0xE0, 0xFB, 0xE4, 0xFF, 0x12, 0x30, 0x6A, 0x90, 0x81, 0x68, 0x74, 0x01, 0xF0, 0x41, 0xA0, 0x90, +0x81, 0x68, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7C, 0xF5, 0x82, 0xE4, 0x34, 0x81, +0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, +0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x81, +0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x12, 0x44, 0xCC, 0xC0, 0x04, 0xC0, 0x05, 0xC0, +0x06, 0xC0, 0x07, 0x90, 0x81, 0x6C, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x10, 0x12, 0x20, +0xBB, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x44, 0xCC, 0x90, 0x81, 0x6E, 0x12, +0x20, 0xCE, 0x90, 0x81, 0x6B, 0xE0, 0x24, 0xFB, 0xFF, 0xC0, 0x07, 0x90, 0x81, 0x6E, 0x12, 0x44, +0xD9, 0x90, 0x81, 0xF9, 0x12, 0x20, 0xCE, 0x90, 0x81, 0x6D, 0xE0, 0xFD, 0xD0, 0x07, 0x12, 0x55, +0x1C, 0x80, 0x6D, 0x90, 0x81, 0x68, 0x74, 0x01, 0xF0, 0x90, 0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF9, +0xE4, 0x34, 0x81, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x01, 0x7B, 0xFE, 0x7A, +0x80, 0x79, 0x33, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x6D, 0xE0, 0xFF, 0x90, 0x81, 0x6C, 0xE0, 0xFD, +0xE4, 0x90, 0x81, 0xBC, 0xF0, 0x7B, 0x04, 0x80, 0x34, 0x90, 0x81, 0x68, 0x74, 0x04, 0xF0, 0x90, +0x81, 0x6A, 0xE0, 0x24, 0x7B, 0xF9, 0xE4, 0x34, 0x81, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, +0x75, 0x16, 0x04, 0x7B, 0xFE, 0x7A, 0x80, 0x79, 0x33, 0x12, 0x2B, 0xED, 0x90, 0x81, 0x6D, 0xE0, +0xFF, 0x90, 0x81, 0x6C, 0xE0, 0xFD, 0xE4, 0x90, 0x81, 0xBC, 0xF0, 0x7B, 0x06, 0x12, 0x63, 0xE1, +0x90, 0x81, 0x68, 0xE0, 0x24, 0x02, 0xFF, 0x90, 0x81, 0x6A, 0xE0, 0x2F, 0xF0, 0x01, 0x17, 0x22, +0x90, 0x02, 0x09, 0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x80, 0x3D, +0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x3E, 0xF0, 0x90, 0x00, +0x02, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x3F, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, +0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x40, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xAE, +0x05, 0xED, 0x2F, 0x90, 0x80, 0x41, 0xF0, 0x22, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0x30, +0xE0, 0x26, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x38, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, +0x81, 0x39, 0xF0, 0xEF, 0x54, 0xFE, 0xFF, 0xA3, 0xE0, 0x54, 0x01, 0x4F, 0xF0, 0x90, 0x00, 0x03, +0x12, 0x1F, 0xBD, 0x90, 0x81, 0x3B, 0xF0, 0x22, 0x90, 0x81, 0x38, 0x74, 0x01, 0xF0, 0xA3, 0x74, +0x05, 0xF0, 0xA3, 0xE0, 0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0x22, 0x12, 0x1F, +0xA4, 0x90, 0x81, 0x3E, 0xF0, 0x90, 0x81, 0x3E, 0xE0, 0x90, 0x01, 0xE7, 0xF0, 0x22, 0x12, 0x1F, +0xA4, 0x90, 0x81, 0x4A, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x4B, 0xF0, 0x22, +0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xFD, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, +0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0xFD, 0xE0, 0xFE, 0xA3, 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0xE0, +0x60, 0x2D, 0xC3, 0x90, 0x82, 0x00, 0xE0, 0x94, 0xE8, 0x90, 0x81, 0xFF, 0xE0, 0x94, 0x03, 0x40, +0x0B, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x80, 0xF0, 0x7F, 0x00, 0x80, 0x15, 0x90, 0x81, 0xFF, 0xE4, +0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, 0x7F, 0x0A, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x80, 0xC5, 0x7F, +0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xD1, +0x12, 0x45, 0x1F, 0x90, 0x82, 0x0A, 0xE0, 0xFF, 0x04, 0xF0, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, +0xFC, 0x7F, 0xAF, 0x7E, 0x01, 0x71, 0x60, 0xEF, 0x60, 0x3A, 0x90, 0x81, 0xD1, 0x12, 0x45, 0x16, +0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x90, 0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xF5, 0x16, +0x7B, 0x01, 0x7A, 0x01, 0x79, 0xA0, 0x12, 0x2B, 0xED, 0x90, 0x81, 0xD1, 0x12, 0x45, 0x16, 0x90, +0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x90, 0x01, 0xAE, 0xF0, 0xA3, 0x74, 0xFF, 0xF0, 0x90, 0x01, 0xCB, +0xE0, 0x64, 0x80, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0xE4, 0xFF, 0x90, 0x80, 0xD9, 0xE0, 0xFE, 0x90, 0x80, 0xD8, 0xE0, 0xFD, 0xB5, 0x06, 0x04, 0x7E, +0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x64, 0x01, 0x60, 0x32, 0x90, 0x01, 0xAF, 0xE0, 0x70, 0x13, +0xED, 0x75, 0xF0, 0x0F, 0xA4, 0x24, 0x42, 0xF9, 0x74, 0x80, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0x71, +0xB6, 0x7F, 0x01, 0xEF, 0x60, 0x16, 0x90, 0x80, 0xD8, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, +0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, 0x90, 0x80, 0xD8, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, +0x22, 0x8F, 0x0D, 0x22, 0x8F, 0x0E, 0x22, 0x22, 0x90, 0x01, 0x34, 0xE0, 0x55, 0x3D, 0xF5, 0x41, +0xA3, 0xE0, 0x55, 0x3E, 0xF5, 0x42, 0xA3, 0xE0, 0x55, 0x3F, 0xF5, 0x43, 0xA3, 0xE0, 0x55, 0x40, +0xF5, 0x44, 0x90, 0x01, 0x34, 0xE5, 0x41, 0xF0, 0xA3, 0xE5, 0x42, 0xF0, 0xA3, 0xE5, 0x43, 0xF0, +0xA3, 0xE5, 0x44, 0xF0, 0x22, 0x90, 0x01, 0x3C, 0xE0, 0x55, 0x45, 0xF5, 0x49, 0xA3, 0xE0, 0x55, +0x46, 0xF5, 0x4A, 0xA3, 0xE0, 0x55, 0x47, 0xF5, 0x4B, 0xA3, 0xE0, 0x55, 0x48, 0xF5, 0x4C, 0x90, +0x01, 0x3C, 0xE5, 0x49, 0xF0, 0xA3, 0xE5, 0x4A, 0xF0, 0xA3, 0xE5, 0x4B, 0xF0, 0xA3, 0xE5, 0x4C, +0xF0, 0x53, 0x91, 0xDF, 0x22, 0x90, 0x81, 0x1F, 0xE0, 0x30, 0xE0, 0x05, 0xE4, 0xA3, 0xF0, 0xA3, +0xF0, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x19, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x13, +0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0x12, 0x4F, 0xF4, 0x90, 0x01, 0x57, +0x74, 0x05, 0xF0, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x26, 0x90, 0x81, 0x27, 0xE0, +0x60, 0x20, 0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, +0xE0, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x70, 0x03, 0x12, +0x47, 0x2A, 0x22, 0x90, 0x80, 0xDE, 0xE0, 0xB4, 0x01, 0x14, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x0E, +0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x02, 0x80, 0x03, 0xD1, 0x7F, 0x22, 0x90, +0x04, 0x1D, 0xE0, 0x70, 0x13, 0x90, 0x80, 0x3E, 0xE0, 0xFF, 0xE4, 0xFD, 0xB1, 0x69, 0x8E, 0x4E, +0x8F, 0x4F, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x82, 0x0E, 0xED, 0xF0, 0x90, 0x82, 0x0D, 0xEF, 0xF0, 0xE4, 0xFD, 0xFC, 0xF1, 0x37, 0x7C, +0x00, 0xAD, 0x07, 0x90, 0x82, 0x0D, 0xE0, 0x90, 0x04, 0x25, 0xF0, 0x90, 0x82, 0x0E, 0xE0, 0x60, +0x0E, 0x74, 0x0F, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0xAF, +0x05, 0x74, 0x08, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x09, 0x2F, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF0, 0xF0, 0x74, 0x21, 0x2D, 0xF5, 0x82, +0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF7, 0xF0, 0xAE, 0x04, 0xAF, 0x05, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x8F, 0x4E, 0xF1, 0x4B, 0xBF, 0x01, 0x18, 0x90, 0x80, 0x40, 0xE0, 0xFF, 0x7D, 0x01, +0xB1, 0x69, 0xAD, 0x07, 0xAC, 0x06, 0xAF, 0x4E, 0x12, 0x4F, 0x82, 0x90, 0x04, 0x1F, 0x74, 0x20, +0xF0, 0x22, 0x90, 0x06, 0xA9, 0xE0, 0x90, 0x81, 0x4C, 0xF0, 0xE0, 0xFD, 0x54, 0xC0, 0x70, 0x09, +0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFE, 0xF0, 0x80, 0x72, 0xED, 0x30, 0xE6, 0x4B, 0x90, 0x81, 0x27, +0xE0, 0x64, 0x02, 0x70, 0x2A, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0xC3, 0x13, 0x20, 0xE0, 0x09, 0x90, +0x81, 0x2B, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x28, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x64, 0x01, +0x70, 0x2D, 0x90, 0x81, 0x2B, 0xE0, 0x44, 0x04, 0xF0, 0x7F, 0x01, 0xB1, 0xD2, 0x80, 0x20, 0x90, +0x81, 0x2B, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x81, 0x26, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x04, +0xB1, 0x4F, 0x80, 0x0B, 0xD1, 0x7F, 0x80, 0x07, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFE, 0xF0, 0x90, +0x81, 0x4C, 0xE0, 0x90, 0x81, 0x2B, 0x30, 0xE7, 0x11, 0x12, 0x4F, 0xF1, 0x90, 0x01, 0x57, 0x74, +0x05, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0x90, +0x01, 0x5F, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x08, 0xF0, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, +0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x5C, 0x7E, 0x01, 0x12, 0x50, +0x05, 0x90, 0x01, 0x5F, 0x74, 0x05, 0xF0, 0x90, 0x06, 0x92, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, +0xE0, 0x44, 0x10, 0xF0, 0x90, 0x81, 0x2A, 0xE0, 0x64, 0x0C, 0x60, 0x0C, 0xE4, 0xFD, 0x7F, 0x0C, +0x12, 0x47, 0x3D, 0xE4, 0xFF, 0x12, 0x4F, 0x0D, 0x22, 0xE4, 0x90, 0x81, 0x4C, 0xF0, 0x90, 0x06, +0xA9, 0xE0, 0x90, 0x81, 0x4C, 0xF0, 0xE0, 0x54, 0xC0, 0x70, 0x0D, 0x90, 0x81, 0x2B, 0xE0, 0x54, +0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x02, 0x47, 0x2A, 0x90, 0x81, 0x4C, 0xE0, 0x30, 0xE6, 0x21, 0x90, +0x81, 0x27, 0xE0, 0x64, 0x01, 0x70, 0x20, 0x90, 0x81, 0x2B, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x81, +0x26, 0xE0, 0x54, 0x0F, 0x64, 0x02, 0x60, 0x04, 0xB1, 0x4F, 0x80, 0x0B, 0xD1, 0x7F, 0x80, 0x07, +0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x81, 0x4C, 0xE0, 0x90, 0x81, 0x2B, 0x30, 0xE7, +0x11, 0x12, 0x4F, 0xF1, 0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x44, 0x04, +0xF0, 0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0xE4, 0xFE, 0xEF, 0xC3, 0x13, 0xFD, 0xEF, 0x30, 0xE0, +0x02, 0x7E, 0x80, 0x90, 0xFD, 0x10, 0xED, 0xF0, 0xAF, 0x06, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, +0xC0, 0xD0, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x1A, 0x90, 0x05, 0x22, 0xE0, 0x54, 0x90, 0x60, 0x07, +0x90, 0x01, 0xC0, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE1, 0xE4, 0x7F, 0x00, +0x80, 0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0x27, 0xE0, 0x60, 0x03, 0x12, +0x73, 0xE1, 0x90, 0x81, 0x3F, 0xE0, 0x30, 0xE0, 0x03, 0x12, 0x49, 0xDD, 0x22, 0x90, 0x81, 0x27, +0xE0, 0x60, 0x35, 0x90, 0x06, 0x92, 0xE0, 0x30, 0xE1, 0x24, 0xE4, 0xF5, 0x1D, 0x90, 0x81, 0x3A, +0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xF5, 0x1E, 0xE4, 0xFB, 0xFD, 0x7F, 0x5C, 0x7E, 0x01, 0x12, 0x50, +0x05, 0x90, 0x01, 0x5F, 0x74, 0x05, 0xF0, 0x90, 0x06, 0x92, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x81, +0x24, 0xE0, 0x54, 0xEF, 0xF0, 0x12, 0x47, 0x2A, 0x22, 0x12, 0x71, 0x48, 0x90, 0x81, 0x4D, 0xEF, +0xF0, 0x90, 0x81, 0x24, 0x30, 0xE0, 0x06, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x04, 0xE0, 0x54, 0xFE, +0xF0, 0x90, 0x81, 0x4D, 0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x04, 0xE4, +0xF0, 0x80, 0x06, 0x90, 0x01, 0x2F, 0x74, 0x80, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0x30, 0xE0, 0x1A, +0x90, 0x81, 0x32, 0xE4, 0xF0, 0xA3, 0x74, 0x07, 0xF0, 0x90, 0x81, 0x32, 0xA3, 0xE0, 0x90, 0x05, +0x58, 0xF0, 0x90, 0x04, 0xEC, 0xE0, 0x54, 0xDD, 0xF0, 0x22, 0x90, 0x04, 0xEC, 0xE0, 0x44, 0x22, +0xF0, 0x22, 0x90, 0x81, 0x4A, 0xE0, 0x60, 0x0F, 0xE4, 0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x01, +0xF0, 0x90, 0x05, 0xFD, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0xC4, 0x13, 0x13, +0x54, 0x03, 0x30, 0xE0, 0x27, 0xEF, 0x54, 0xBF, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x81, 0x25, +0x30, 0xE0, 0x06, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x10, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x01, 0xB9, +0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x12, 0x47, 0x2A, 0xE4, 0xFF, 0x90, 0x81, +0x45, 0xE0, 0x30, 0xE0, 0x48, 0x90, 0x81, 0x49, 0xE0, 0xFD, 0x60, 0x41, 0x74, 0x01, 0x7E, 0x00, +0xA8, 0x07, 0x08, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x04, 0xE0, +0xE0, 0xFB, 0xEF, 0x5B, 0x60, 0x06, 0xE4, 0x90, 0x81, 0x49, 0xF0, 0x22, 0x90, 0x81, 0x47, 0xE0, +0xD3, 0x9D, 0x50, 0x10, 0x90, 0x01, 0xC7, 0x74, 0x10, 0xF0, 0x11, 0xBE, 0x90, 0x81, 0x45, 0xE0, +0x54, 0xFE, 0xF0, 0x22, 0x12, 0x4F, 0x0B, 0x90, 0x81, 0x49, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x80, +0x3C, 0xE0, 0x64, 0x02, 0x60, 0x07, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x81, +0x24, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, 0xE0, 0x2C, 0xEF, 0x54, 0x7F, 0xF0, +0x90, 0x04, 0xE0, 0xE0, 0x90, 0x81, 0x25, 0x30, 0xE1, 0x06, 0xE0, 0x44, 0x02, 0xF0, 0x80, 0x0F, +0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x04, 0xF0, 0x90, +0x81, 0x27, 0xE0, 0x60, 0x03, 0x12, 0x47, 0x2A, 0x7F, 0x01, 0x01, 0x6E, 0xC3, 0xEE, 0x94, 0x01, +0x40, 0x0A, 0x0D, 0xED, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xC3, 0xEE, 0x94, +0x01, 0x40, 0x24, 0x90, 0xFD, 0x11, 0xE0, 0x6D, 0x70, 0x1A, 0x90, 0x01, 0x17, 0xE0, 0xB5, 0x05, +0x0D, 0x90, 0x01, 0xE4, 0x74, 0x77, 0xF0, 0x90, 0xFD, 0x11, 0xE4, 0xF0, 0x80, 0x06, 0xED, 0x04, +0x90, 0xFD, 0x11, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xE4, 0x90, 0x81, 0x4E, 0xF0, 0xA3, 0xF0, 0xA3, +0xF0, 0x90, 0x00, 0x83, 0xE0, 0x90, 0x81, 0x4E, 0xF0, 0x90, 0x00, 0x83, 0xE0, 0xFE, 0x90, 0x81, +0x4E, 0xE0, 0xFF, 0xB5, 0x06, 0x01, 0x22, 0xC3, 0x90, 0x81, 0x50, 0xE0, 0x94, 0x64, 0x90, 0x81, +0x4F, 0xE0, 0x94, 0x00, 0x40, 0x0D, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x4E, +0xE0, 0xFF, 0x22, 0x90, 0x81, 0x4F, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x44, 0xA9, 0x80, 0xC2, 0x74, +0x45, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, +0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, +0x12, 0xED, 0xF0, 0x90, 0x82, 0x11, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x70, 0xE0, 0xFF, 0x74, +0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x47, 0xE0, +0x5F, 0xFD, 0x7F, 0x47, 0x12, 0x32, 0x1E, 0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, +0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x46, 0xE0, 0x4F, 0xFD, 0x7F, 0x46, +0x12, 0x32, 0x1E, 0x90, 0x82, 0x12, 0xE0, 0x60, 0x18, 0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, +0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x4F, 0x80, +0x17, 0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, +0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x5F, 0xFD, 0x7F, 0x45, 0x80, 0x7E, 0x90, 0x82, 0x11, +0xE0, 0x24, 0xF8, 0xF0, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, +0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x5F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, +0x90, 0x82, 0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, +0xFF, 0x90, 0x00, 0x43, 0xE0, 0x4F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, 0x90, 0x82, 0x12, 0xE0, +0x60, 0x1D, 0x90, 0x82, 0x11, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, +0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x4F, 0xFD, 0x7F, 0x42, 0x80, 0x1C, 0x90, +0x82, 0x11, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, +0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x5F, 0xFD, 0x7F, 0x42, 0x12, 0x32, 0x1E, 0xD0, 0xD0, +0x92, 0xAF, 0x22, 0x90, 0x81, 0x24, 0xE0, 0x54, 0xFB, 0xF0, 0xE4, 0x90, 0x81, 0x30, 0xF0, 0x90, +0x81, 0x2B, 0xF0, 0x22, 0xEF, 0x24, 0xFE, 0x60, 0x0C, 0x04, 0x70, 0x28, 0x90, 0x81, 0x2D, 0x74, +0x01, 0xF0, 0xA3, 0xF0, 0x22, 0xED, 0x70, 0x0A, 0x90, 0x81, 0x3B, 0xE0, 0x90, 0x81, 0x2D, 0xF0, +0x80, 0x05, 0x90, 0x81, 0x2D, 0xED, 0xF0, 0x90, 0x81, 0x2D, 0xE0, 0xA3, 0xF0, 0x90, 0x81, 0x25, +0xE0, 0x44, 0x08, 0xF0, 0x22, 0x12, 0x4E, 0xAB, 0xEF, 0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8, +0x74, 0x01, 0xF0, 0x80, 0x67, 0x90, 0x81, 0x2B, 0xE0, 0xFF, 0x54, 0x03, 0x60, 0x08, 0x90, 0x01, +0xB8, 0x74, 0x02, 0xF0, 0x80, 0x56, 0x90, 0x81, 0x29, 0xE0, 0xFE, 0xE4, 0xC3, 0x9E, 0x50, 0x08, +0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x44, 0xEF, 0x30, 0xE2, 0x08, 0x90, 0x01, 0xB8, 0x74, +0x08, 0xF0, 0x80, 0x38, 0x90, 0x81, 0x2B, 0xE0, 0x30, 0xE4, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x10, +0xF0, 0x80, 0x29, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x54, 0x3F, 0x20, 0xE0, 0x08, 0x90, 0x01, +0xB8, 0x74, 0x20, 0xF0, 0x80, 0x16, 0x90, 0x81, 0x3E, 0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74, +0x80, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, +0x04, 0xF0, 0x7F, 0x00, 0x22, 0xEF, 0x60, 0x42, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x3A, +0x90, 0x81, 0x25, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x05, 0x22, 0x74, 0x0F, 0xF0, 0x90, 0x06, 0x04, +0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0xFF, 0x12, 0x4F, 0x0D, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x24, 0xE0, +0x44, 0x40, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x06, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x01, +0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F, +0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x02, 0xF0, 0x90, 0x81, +0x23, 0xF0, 0x22, 0x12, 0x54, 0x65, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x23, 0xF0, +0x22, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x11, 0xEF, 0x54, 0xFB, +0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x70, 0x42, 0x80, 0x3D, 0x90, 0x81, +0x30, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x30, 0xE0, 0xFF, +0xB4, 0x01, 0x02, 0x80, 0x04, 0xEF, 0xB4, 0x02, 0x06, 0x90, 0x05, 0x58, 0xE0, 0x04, 0xF0, 0x90, +0x81, 0x38, 0xE0, 0xFF, 0x90, 0x81, 0x30, 0xE0, 0xD3, 0x9F, 0x40, 0x0F, 0x90, 0x80, 0xDE, 0xE0, +0xB4, 0x01, 0x0B, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x47, 0x2A, 0x22, 0x22, +0x90, 0x05, 0x2B, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0x22, 0x90, 0x05, 0x22, 0x74, +0xFF, 0xF0, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, 0x22, +0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x12, 0x49, 0xDD, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, +0x22, 0x12, 0x49, 0xE3, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F, +0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0xAE, +0x07, 0x12, 0x51, 0x73, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x60, 0x0A, 0xAF, +0x06, 0x7D, 0x01, 0x12, 0x47, 0x3D, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0x90, 0x01, 0x57, 0xE0, +0x60, 0x48, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, +0x13, 0x54, 0x3F, 0x30, 0xE0, 0x0C, 0xEF, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, +0xF0, 0x22, 0x90, 0x81, 0x30, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xEF, 0xF0, 0x90, +0x81, 0x38, 0xE0, 0xFF, 0x90, 0x81, 0x30, 0xE0, 0xD3, 0x9F, 0x40, 0x0E, 0x90, 0x80, 0xDE, 0xE0, +0xB4, 0x01, 0x07, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x90, 0x80, 0x3F, 0xE0, 0xFF, +0x7D, 0x01, 0x12, 0x6D, 0x69, 0x8E, 0x54, 0x8F, 0x55, 0xAD, 0x55, 0xAC, 0x54, 0xAF, 0x53, 0x12, +0x4F, 0x82, 0xAF, 0x55, 0xAE, 0x54, 0x90, 0x04, 0x80, 0xE0, 0x54, 0x0F, 0xFD, 0xAC, 0x07, 0x74, +0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01, 0xF0, 0x74, 0x11, 0x2C, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC, 0x07, 0x74, 0x16, 0x2C, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74, 0x15, 0x2C, 0xF5, 0x82, +0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74, 0x06, 0x2C, 0xF5, 0x82, +0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x0F, 0xF0, 0x90, 0x04, 0x53, 0xE4, 0xF0, 0x90, 0x04, +0x52, 0xF0, 0x90, 0x04, 0x51, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0x50, 0x74, 0xFD, 0xF0, 0x74, 0x14, +0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D, 0xFD, 0x74, 0x14, 0x2F, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0xAB, 0x07, 0xAA, 0x06, 0xED, 0x2B, +0xFB, 0xE4, 0x3A, 0xFA, 0xC3, 0x90, 0x80, 0xDB, 0xE0, 0x9B, 0x90, 0x80, 0xDA, 0xE0, 0x9A, 0x50, +0x13, 0xA3, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0xDA, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0xEB, 0x9F, +0xFB, 0xEA, 0x9E, 0xFA, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x74, 0x00, 0x2F, 0xF5, 0x82, +0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, +0x81, 0x42, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x0A, 0x90, 0x00, 0x01, +0x12, 0x1F, 0xBD, 0x90, 0x81, 0x43, 0xF0, 0x22, 0x90, 0x81, 0x45, 0xE0, 0x30, 0xE0, 0x2D, 0x90, +0x81, 0x48, 0xE0, 0x04, 0xF0, 0xE0, 0xFF, 0x90, 0x81, 0x46, 0xE0, 0xB5, 0x07, 0x1E, 0x90, 0x06, +0x92, 0xE0, 0x54, 0x1C, 0x70, 0x0B, 0x12, 0x4F, 0x0B, 0x90, 0x81, 0x49, 0xE0, 0x04, 0xF0, 0x80, +0x06, 0x90, 0x06, 0x92, 0x74, 0x1C, 0xF0, 0xE4, 0x90, 0x81, 0x48, 0xF0, 0x22, 0x00, 0xBB, 0x8E, +}; diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h new file mode 100755 index 00000000..2328ec3c --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h @@ -0,0 +1,29 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ +#ifndef __INC_HAL8188E_FW_IMG_H +#define __INC_HAL8188E_FW_IMG_H + +//V10(1641) +#define Rtl8188EFWImgArrayLength 13904 + +extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength]; + +#endif //__INC_HAL8188E_FW_IMG_H + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c new file mode 100755 index 00000000..355d0afa --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c @@ -0,0 +1,1105 @@ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + RateAdaptive.c + +Abstract: + Implement Rate Adaptive functions for common operations. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-12 Page Create. + +--*/ +#include "../odm_precomp.h" + +//#if( DM_ODM_SUPPORT_TYPE == ODM_MP) +//#include "Mp_Precomp.h" +//#endif + +#if (RATE_ADAPTIVE_SUPPORT == 1) +// Rate adaptive parameters + + +static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 + {6,5,4,3,0,4},//86 , idx=1 + {6,5,4,2,0,4},//81 , idx=2 + {8,7,6,4,0,6},//75 , idx=3 + {10,9,8,6,0,8},//71 , idx=4 + {10,9,8,4,0,8},//66 , idx=5 + {10,9,8,2,0,8},//62 , idx=6 + {10,9,8,0,0,8},//59 , idx=7 + {18,17,16,8,0,16},//53 , idx=8 + {26,25,24,16,0,24},//50 , idx=9 + {34,33,32,24,0,32},//47 , idx=0x0a + //{34,33,32,16,0,32},//43 , idx=0x0b + //{34,33,32,8,0,32},//40 , idx=0x0c + //{34,33,28,8,0,32},//37 , idx=0x0d + //{34,33,20,8,0,32},//32 , idx=0x0e + //{34,32,24,8,0,32},//26 , idx=0x0f + //{49,48,32,16,0,48},//20 , idx=0x10 + //{49,48,24,0,0,48},//17 , idx=0x11 + //{49,47,16,16,0,48},//15 , idx=0x12 + //{49,44,16,16,0,48},//12 , idx=0x13 + //{49,40,16,0,0,48},//9 , idx=0x14 + {34,31,28,20,0,32},//43 , idx=0x0b + {34,31,27,18,0,32},//40 , idx=0x0c + {34,31,26,16,0,32},//37 , idx=0x0d + {34,30,22,16,0,32},//32 , idx=0x0e + {34,30,24,16,0,32},//26 , idx=0x0f + {49,46,40,16,0,48},//20 , idx=0x10 + {49,45,32,0,0,48},//17 , idx=0x11 + {49,45,22,18,0,48},//15 , idx=0x12 + {49,40,24,16,0,48},//12 , idx=0x13 + {49,32,18,12,0,48},//9 , idx=0x14 + {49,22,18,14,0,48},//6 , idx=0x15 + {49,16,16,0,0,48}};//3 //3, idx=0x16 + +static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up + +static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; + +#if 0 +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SSTH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SSTH + 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; +#else + +// wilson modify +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SSTH + 0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; + +#endif + +/*static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ +static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, + 24,36,48,72,96,144,192,216, + 60,80,100,160,240,400,560,640, + 300,320,480,720,1000,1200,1600,2000}; +static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, + 12,18,24,36,48,72,96,108, + 30,40,50,80,120,200,280,320, + 150,160,240,360,500,600,800,1000}; +static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2, + 2,2,3,3,4,4,5,7, + 4,4,7,10,10,12,12,18, + 5,7,7,8,11,18,36,60}; // 0329 // 1207 +#if 0 +static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, + 30,30,25,25,20,15,15,10, + 30,25,25,20,15,10,10,10, + 30,25,25,20,15,10,10,10}; +#endif + +static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1, + 1,2,3,4,5,6,7,8, + 1,2,3,4,5,6,7,8, + 5,6,7,8,9,10,11,12}; + + +static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode + 0x0f8ff010, // 1: 40M GN mode + 0x0f8ff005, // 2: BN mode/ 40M BGN mode + 0x0f8ff000, // 3: N mode + 0x00000ff5, // 4: BG mode + 0x00000ff0, // 5: G mode + 0x0000000d, // 6: B mode + 0, // 7: + 0, // 8: + 0, // 9: + 0, // 10: + 0, // 11: + 0, // 12: + 0, // 13: + 0, // 14: + 0, // 15: + + }; +static u1Byte PendingForRateUpFail[5]={2,10,24,40,60}; +static u2Byte DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms + +// End Rate adaptive parameters + +static void +odm_SetTxRPTTiming_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo, + IN u1Byte extend + ) +{ + u1Byte idx = 0; + + for(idx=0; idx<5; idx++) + if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime) + break; + + if (extend==0) // back to default timing + idx=0; //200ms + else if (extend==1) {// increase the timing + idx+=1; + if (idx>5) + idx=5; + } + else if (extend==2) {// decrease the timing + if(idx!=0) + idx-=1; + } + pRaInfo->RptTime=DynamicTxRPTTiming[idx]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime=0x%x\n", pRaInfo->RptTime)); +} + +static int +odm_RateDown_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID, LowestRate, HighestRate; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); + if(NULL == pRaInfo) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); + return -1; + } + RateID = pRaInfo->PreRate; + LowestRate = pRaInfo->LowestRate; + HighestRate = pRaInfo->HighestRate; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", + RateID, LowestRate, HighestRate, pRaInfo->RateSGI)); + if (RateID > HighestRate) + { + RateID=HighestRate; + } + else if(pRaInfo->RateSGI) + { + pRaInfo->RateSGI=0; + } + else if (RateID > LowestRate) + { + if (RateID > 0) + { + for (i=RateID-1; i>LowestRate;i--) + { + if (pRaInfo->RAUseRate & BIT(i)) + { + RateID=i; + goto RateDownFinish; + + } + } + } + } + else if (RateID <= LowestRate) + { + RateID = LowestRate; + } +RateDownFinish: + if (pRaInfo->RAWaitingCounter==1){ + pRaInfo->RAWaitingCounter+=1; + pRaInfo->RAPendingCounter+=1; + } + else if(pRaInfo->RAWaitingCounter==0){ + } + else{ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + + if(pRaInfo->RAPendingCounter>=4) + pRaInfo->RAPendingCounter=4; + + pRaInfo->DecisionRate=RateID; + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 2); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down, RPT Timing default\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDown_8188E() \n")); + return 0; +} + +static int +odm_RateUp_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID, HighestRate; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E() \n")); + if(NULL == pRaInfo) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); + return -1; + } + RateID = pRaInfo->PreRate; + HighestRate = pRaInfo->HighestRate; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" RateID=%d HighestRate=%d\n", + RateID, HighestRate)); + if (pRaInfo->RAWaitingCounter==1){ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + else if (pRaInfo->RAWaitingCounter>1){ + pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; + goto RateUpfinish; + } + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E():Decrease RPT Timing\n")); + + if (RateID < HighestRate) + { + for (i=RateID+1; i<=HighestRate; i++) + { + if (pRaInfo->RAUseRate & BIT(i)) + { + RateID=i; + goto RateUpfinish; + } + } + } + else if(RateID == HighestRate) + { + if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) + pRaInfo->RateSGI = 1; + else if((pRaInfo->SGIEnable) !=1 ) + pRaInfo->RateSGI = 0; + } + else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) + { + RateID = HighestRate; + + } +RateUpfinish: + //if(pRaInfo->RAWaitingCounter==10) + if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) + pRaInfo->RAWaitingCounter=0; + else + pRaInfo->RAWaitingCounter++; + + pRaInfo->DecisionRate=RateID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate up to RateID %d\n", RateID)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateUp_8188E() \n")); + return 0; +} + +static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){ + u1Byte RateID; + RateID=pRaInfo->DecisionRate; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; +} + +static void +odm_RateDecision_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; + //u4Byte pool_retry; + static u1Byte DynamicTxRPTTimingCounter=0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n")); + + if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits + { + if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + // Start RA decision + if (pRaInfo->PreRate > pRaInfo->HighestRate) + RateID = pRaInfo->HighestRate; + else + RateID = pRaInfo->PreRate; + if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) + RtyPtID=0; + else + RtyPtID=1; + PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscDown init is %d\n", pRaInfo->NscDown)); + //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; + pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; + pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; + pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; + pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; + pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscDown is %d, total*penalty[5] is %d\n", + pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); + if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) + pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; + else + pRaInfo->NscDown=0; + + // rate up + PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscUp init is %d\n", pRaInfo->NscUp)); + pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; + pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; + pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; + pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; + pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("NscUp is %d, total*up[5] is %d\n", + pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))); + if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) + pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; + else + pRaInfo->NscUp = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE|ODM_COMP_INIT, ODM_DBG_LOUD, + (" RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d SGI=%d\n", + pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI)); + if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) + odm_RateDown_8188E(pDM_Odm,pRaInfo); + //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) + odm_RateUp_8188E(pDM_Odm,pRaInfo); + + if(pRaInfo->DecisionRate > pRaInfo->HighestRate) + pRaInfo->DecisionRate = pRaInfo->HighestRate; + + if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) + DynamicTxRPTTimingCounter+=1; + else + DynamicTxRPTTimingCounter=0; + + if (DynamicTxRPTTimingCounter>=4) { + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<=====Rate don't change 4 times, Extend RPT Timing\n")); + DynamicTxRPTTimingCounter=0; + } + + pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120 + + odm_ResetRaCounter_8188E( pRaInfo); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDecision_8188E() \n")); +} + +static int +odm_ARFBRefresh_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ // Wilson 2011/10/26 + u4Byte MaskFromReg; + s1Byte i; + + switch(pRaInfo->RateID){ + case RATR_INX_WIRELESS_NGB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015; + break; + case RATR_INX_WIRELESS_NG: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; + break; + case RATR_INX_WIRELESS_NB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005; + break; + case RATR_INX_WIRELESS_N: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; + break; + case RATR_INX_WIRELESS_GB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5; + break; + case RATR_INX_WIRELESS_G: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; + break; + case RATR_INX_WIRELESS_B: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; + break; + case 12: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR0); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 13: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR1); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 14: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR2); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 15: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR3); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + + default: + pRaInfo->RAUseRate=(pRaInfo->RateMask); + break; + } + // Highest rate + if (pRaInfo->RAUseRate){ + for (i=RATESIZE;i>=0;i--) + { + if((pRaInfo->RAUseRate)&BIT(i)){ + pRaInfo->HighestRate=i; + break; + } + } + } + else{ + pRaInfo->HighestRate=0; + } + // Lowest rate + if (pRaInfo->RAUseRate){ + for (i=0;iRAUseRate)&BIT(i)) + { + pRaInfo->LowestRate=i; + break; + } + } + } + else{ + pRaInfo->LowestRate=0; + } + +#if POWER_TRAINING_ACTIVE == 1 + if (pRaInfo->HighestRate >0x13) + pRaInfo->PTModeSS=3; + else if(pRaInfo->HighestRate >0x0b) + pRaInfo->PTModeSS=2; + else if(pRaInfo->HighestRate >0x0b) + pRaInfo->PTModeSS=1; + else + pRaInfo->PTModeSS=0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_ARFBRefresh_8188E(): PTModeSS=%d\n", pRaInfo->PTModeSS)); + +#endif + + if(pRaInfo->DecisionRate > pRaInfo->HighestRate) + pRaInfo->DecisionRate = pRaInfo->HighestRate; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_ARFBRefresh_8188E(): RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d,DecisionRate=%d \n", + pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate,pRaInfo->DecisionRate)); + return 0; +} + +#if POWER_TRAINING_ACTIVE == 1 +static void +odm_PTTryState_8188E( + IN PODM_RA_INFO_T pRaInfo + ) +{ + pRaInfo->PTTryState=0; + switch (pRaInfo->PTModeSS) + { + case 3: + if (pRaInfo->DecisionRate>=0x19) + pRaInfo->PTTryState=1; + break; + case 2: + if (pRaInfo->DecisionRate>=0x11) + pRaInfo->PTTryState=1; + break; + case 1: + if (pRaInfo->DecisionRate>=0x0a) + pRaInfo->PTTryState=1; + break; + case 0: + if (pRaInfo->DecisionRate>=0x03) + pRaInfo->PTTryState=1; + break; + default: + pRaInfo->PTTryState=0; + } + + if (pRaInfo->RssiStaRA<48) + { + pRaInfo->PTStage=0; + } + else if (pRaInfo->PTTryState==1) + { + if ((pRaInfo->PTStopCount>=10)||(pRaInfo->PTPreRssi>pRaInfo->RssiStaRA+5) + ||(pRaInfo->PTPreRssiRssiStaRA-5)||(pRaInfo->DecisionRate!=pRaInfo->PTPreRate)) + { + if (pRaInfo->PTStage==0) + pRaInfo->PTStage=1; + else if(pRaInfo->PTStage==1) + pRaInfo->PTStage=3; + else + pRaInfo->PTStage=5; + + pRaInfo->PTPreRssi=pRaInfo->RssiStaRA; + pRaInfo->PTStopCount=0; + + } + else{ + pRaInfo->RAstage=0; + pRaInfo->PTStopCount++; + } + } + else{ + pRaInfo->PTStage=0; + pRaInfo->RAstage=0; + } + pRaInfo->PTPreRate=pRaInfo->DecisionRate; +} + +static void +odm_PTDecision_8188E( + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte stage_BUF; + u1Byte j; + u1Byte temp_stage; + u4Byte numsc; + u4Byte num_total; + u1Byte stage_id; + + stage_BUF=pRaInfo->PTStage; + numsc = 0; + num_total= pRaInfo->TOTAL* PT_PENALTY[5]; + for(j=0;j<=4;j++) + { + numsc += pRaInfo->RTY[j] * PT_PENALTY[j]; + if(numsc>num_total) + break; + } + + j=j>>1; + temp_stage= (pRaInfo->PTStage +1)>>1; + if (temp_stage>j) + stage_id=temp_stage-j; + else + stage_id=0; + + pRaInfo->PTSmoothFactor=(pRaInfo->PTSmoothFactor>>1) + (pRaInfo->PTSmoothFactor>>2) + stage_id*16+2; + if (pRaInfo->PTSmoothFactor>192) + pRaInfo->PTSmoothFactor=192; + stage_id =pRaInfo->PTSmoothFactor>>6; + temp_stage=stage_id*2; + if (temp_stage!=0) + temp_stage-=1; + if (pRaInfo->DROP>3) + temp_stage=0; + pRaInfo->PTStage=temp_stage; + +} +#endif + +static VOID +odm_RATxRPTTimerSetting( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime +) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n")); + + + if(pDM_Odm->CurrminRptTime != minRptTime){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + (" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime)); + #if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_AP)) + ODM_RA_Set_TxRPT_Time(pDM_Odm,minRptTime); + #else + rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime); + #endif + pDM_Odm->CurrminRptTime = minRptTime; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" <=====odm_RATxRPTTimerSetting()\n")); +} + + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n")); + + // 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! + if (pDM_Odm->SupportICType == ODM_RTL8188E) + pDM_Odm->RaSupport88E = TRUE; + +} + + + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID]; + #if 1 + u1Byte WirelessMode=0xFF; //invalid value + u1Byte max_rate_idx = 0x13; //MCS7 + if(pDM_Odm->pWirelessMode!=NULL){ + WirelessMode=*(pDM_Odm->pWirelessMode); + } + + if(WirelessMode != 0xFF ){ + if(WirelessMode & ODM_WM_N24G) + max_rate_idx = 0x13; + else if(WirelessMode & ODM_WM_G) + max_rate_idx = 0x0b; + else if(WirelessMode & ODM_WM_B) + max_rate_idx = 0x03; + } + + //printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n", + WirelessMode,max_rate_idx)); + + pRaInfo->DecisionRate = max_rate_idx; + pRaInfo->PreRate = max_rate_idx; + pRaInfo->HighestRate=max_rate_idx; + #else + pRaInfo->DecisionRate = 0x13; + pRaInfo->PreRate = 0x13; + pRaInfo->HighestRate= 0x13; + #endif + pRaInfo->LowestRate=0; + pRaInfo->RateID=0; + pRaInfo->RateMask=0xffffffff; + pRaInfo->RssiStaRA=0; + pRaInfo->PreRssiStaRA=0; + pRaInfo->SGIEnable=0; + pRaInfo->RAUseRate=0xffffffff; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->RateSGI=0; + pRaInfo->Active=1; //Active is not used at present. by page, 110819 + pRaInfo->RptTime = 0x927c; + pRaInfo->DROP=0; + pRaInfo->RTY[0]=0; + pRaInfo->RTY[1]=0; + pRaInfo->RTY[2]=0; + pRaInfo->RTY[3]=0; + pRaInfo->RTY[4]=0; + pRaInfo->TOTAL=0; + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; +#if POWER_TRAINING_ACTIVE == 1 + pRaInfo->PTActive=1; // Active when this STA is use + pRaInfo->PTTryState=0; + pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS + pRaInfo->PTSmoothFactor=192; + pRaInfo->PTStopCount=0; + pRaInfo->PTPreRate=0; + pRaInfo->PTPreRssi=0; + pRaInfo->PTModeSS=0; + pRaInfo->RAstage=0; +#endif + return 0; +} + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte MacID = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n")); + pDM_Odm->CurrminRptTime = 0; + + for(MacID=0; MacID= ASSOCIATE_ENTRY_NUM)) + return 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("MacID=%d SGI=%d\n", MacID, pDM_Odm->RAInfo[MacID].RateSGI)); + return pDM_Odm->RAInfo[MacID].RateSGI; +} + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + u1Byte DecisionRate = 0; + + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + DecisionRate = (pDM_Odm->RAInfo[MacID].DecisionRate); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" MacID=%d DecisionRate=0x%x\n", MacID, DecisionRate)); + return DecisionRate; +} + +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + u1Byte PTStage = 5; + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + PTStage = (pDM_Odm->RAInfo[MacID].PTStage); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("MacID=%d PTStage=0x%x\n", MacID, PTStage)); + return PTStage; +} + +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ) +{ + PODM_RA_INFO_T pRaInfo = NULL; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n", + MacID, RateID, RateMask, SGIEnable)); + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &(pDM_Odm->RAInfo[MacID]); + pRaInfo->RateID = RateID; + pRaInfo->RateMask = RateMask; + pRaInfo->SGIEnable = SGIEnable; + odm_ARFBRefresh_8188E(pDM_Odm, pRaInfo); +} + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ) +{ + PODM_RA_INFO_T pRaInfo = NULL; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" MacID=%d Rssi=%d\n", MacID, Rssi)); + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &(pDM_Odm->RAInfo[MacID]); + pRaInfo->RssiStaRA = Rssi; +} + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (minRptTime != 0xffff) +#endif + ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); +} + + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ) +{ + PODM_RA_INFO_T pRAInfo = NULL; + u1Byte MacId = 0; + pu1Byte pBuffer = NULL; + u4Byte valid = 0, ItemNum = 0; + u2Byte minRptTime = 0x927c; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n", + MacIDValidEntry0, MacIDValidEntry1, TxRPT_Len)); + + ItemNum = TxRPT_Len >> 3; + pBuffer = TxRPT_Buf; + + do + { + if(MacId >= ASSOCIATE_ENTRY_NUM) + valid = 0; + else if(MacId >= 32) + valid = (1<<(MacId-32)) & MacIDValidEntry1; + else + valid = (1<RAInfo[MacId]); + if(valid) + { + +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + pRAInfo->RTY[0] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_0(pBuffer); + pRAInfo->RTY[1] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_1(pBuffer); + pRAInfo->RTY[2] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_2(pBuffer); + pRAInfo->RTY[3] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_3(pBuffer); + pRAInfo->RTY[4] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_4(pBuffer); + pRAInfo->DROP = (u2Byte)GET_TX_REPORT_TYPE1_DROP_0(pBuffer); +#else + pRAInfo->RTY[0] = (unsigned short)(pBuffer[1] << 8 | pBuffer[0]); + pRAInfo->RTY[1] = pBuffer[2]; + pRAInfo->RTY[2] = pBuffer[3]; + pRAInfo->RTY[3] = pBuffer[4]; + pRAInfo->RTY[4] = pBuffer[5]; + pRAInfo->DROP = pBuffer[6]; +#endif + pRAInfo->TOTAL = pRAInfo->RTY[0] + \ + pRAInfo->RTY[1] + \ + pRAInfo->RTY[2] + \ + pRAInfo->RTY[3] + \ + pRAInfo->RTY[4] + \ + pRAInfo->DROP; + if(pRAInfo->TOTAL != 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n", + MacId, + pRAInfo->TOTAL, + pRAInfo->RTY[0], + pRAInfo->RTY[1], + pRAInfo->RTY[2], + pRAInfo->RTY[3], + pRAInfo->RTY[4], + pRAInfo->DROP, + MacIDValidEntry0 , + MacIDValidEntry1)); +#if POWER_TRAINING_ACTIVE == 1 + if (pRAInfo->PTActive){ + if(pRAInfo->RAstage<5){ + odm_RateDecision_8188E(pDM_Odm,pRAInfo); + } + else if(pRAInfo->RAstage==5){ // Power training try state + odm_PTTryState_8188E(pRAInfo); + } + else {// RAstage==6 + odm_PTDecision_8188E(pRAInfo); + } + + // Stage_RA counter + if (pRAInfo->RAstage<=5) + pRAInfo->RAstage++; + else + pRAInfo->RAstage=0; + } + else{ + odm_RateDecision_8188E(pDM_Odm,pRAInfo); + } +#else + odm_RateDecision_8188E(pDM_Odm, pRAInfo); +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + extern void RTL8188E_SetStationTxRateInfo(PDM_ODM_T, PODM_RA_INFO_T, int); + RTL8188E_SetStationTxRateInfo(pDM_Odm, pRAInfo, MacId); +#ifdef DETECT_STA_EXISTANCE + void RTL8188E_DetectSTAExistance(PDM_ODM_T pDM_Odm, PODM_RA_INFO_T pRAInfo, int MacID); + RTL8188E_DetectSTAExistance(pDM_Odm, pRAInfo, MacId); +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("macid=%d R0=%d R1=%d R2=%d R3=%d R4=%d drop=%d valid0=%x RateID=%d SGI=%d\n", + MacId, + pRAInfo->RTY[0], + pRAInfo->RTY[1], + pRAInfo->RTY[2], + pRAInfo->RTY[3], + pRAInfo->RTY[4], + pRAInfo->DROP, + MacIDValidEntry0, + pRAInfo->DecisionRate, + pRAInfo->RateSGI)); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" TOTAL=0!!!!\n")); + } + + if(minRptTime > pRAInfo->RptTime) + minRptTime = pRAInfo->RptTime; + + pBuffer += TX_RPT2_ITEM_SIZE; + MacId++; + }while(MacId < ItemNum); + + odm_RATxRPTTimerSetting(pDM_Odm,minRptTime); + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<===== ODM_RA_TxRPT2Handle_8188E()\n")); +} + +#else + +static VOID +odm_RATxRPTTimerSetting( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime +) +{ + return; +} + + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ) +{ + return; +} + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ) +{ + return 0; +} + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ) +{ + return; +} + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ) +{ + return; +} + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ) +{ + return; +} + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ) +{ + return; +} + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h new file mode 100755 index 00000000..e7c1e125 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h @@ -0,0 +1,108 @@ +#ifndef __INC_RA_H +#define __INC_RA_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + RateAdaptive.h + +Abstract: + Prototype of RA and related data structure. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-12 Page Create. +--*/ + +// Rate adaptive define +#define PERENTRY 23 +#define RETRYSIZE 5 +#define RATESIZE 28 +#define TX_RPT2_ITEM_SIZE 8 + +#if (DM_ODM_SUPPORT_TYPE != ODM_MP) +// +// TX report 2 format in Rx desc +// +#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) +#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) +#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) +#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) +#endif + +// End rate adaptive define + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ); + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ); + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); + +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ); + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ); + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ); + + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ); +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h new file mode 100755 index 00000000..a5086c9b --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h @@ -0,0 +1,47 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: Hal8188EReg.h +// +// Description: +// +// This file is for RTL8188E register definition. +// +// +//============================================================ +#ifndef __HAL_8188E_REG_H__ +#define __HAL_8188E_REG_H__ + +// +// Register Definition +// +#define TRX_ANTDIV_PATH 0x860 +#define RX_ANTDIV_PATH 0xb2c +#define ODM_R_A_AGC_CORE1_8188E 0xc50 + + +// +// Bitmap Definition +// +#define BIT_FA_RESET_8188E BIT0 + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c new file mode 100755 index 00000000..91f9af2e --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c @@ -0,0 +1,891 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "../odm_precomp.h" + +#ifdef CONFIG_IOL_IOREG_CFG +#include +#endif + +#if (RTL8188E_SUPPORT == 1) +static BOOLEAN +CheckCondition( + const u4Byte Condition, + const u4Byte Hex + ) +{ + u4Byte _board = (Hex & 0x000000FF); + u4Byte _interface = (Hex & 0x0000FF00) >> 8; + u4Byte _platform = (Hex & 0x00FF0000) >> 16; + u4Byte cond = Condition; + + if ( Condition == 0xCDCDCDCD ) + return TRUE; + + cond = Condition & 0x000000FF; + if ( (_board == cond) && cond != 0x00) + return FALSE; + + cond = Condition & 0x0000FF00; + cond = cond >> 8; + if ( (_interface & cond) == 0 && cond != 0x07) + return FALSE; + + cond = Condition & 0x00FF0000; + cond = cond >> 16; + if ( (_platform & cond) == 0 && cond != 0x0F) + return FALSE; + return TRUE; +} + + +/****************************************************************************** +* AGC_TAB_1T.TXT +******************************************************************************/ + +u4Byte Array_AGC_TAB_1T_8188E[] = { + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xE7190001, + 0xC78, 0xE61A0001, + 0xC78, 0xE51B0001, + 0xC78, 0xE41C0001, + 0xC78, 0xE31D0001, + 0xC78, 0xE21E0001, + 0xC78, 0xE11F0001, + 0xC78, 0x8A200001, + 0xC78, 0x89210001, + 0xC78, 0x88220001, + 0xC78, 0x87230001, + 0xC78, 0x86240001, + 0xC78, 0x85250001, + 0xC78, 0x84260001, + 0xC78, 0x83270001, + 0xC78, 0x82280001, + 0xC78, 0x6B290001, + 0xC78, 0x6A2A0001, + 0xC78, 0x692B0001, + 0xC78, 0x682C0001, + 0xC78, 0x672D0001, + 0xC78, 0x662E0001, + 0xC78, 0x652F0001, + 0xC78, 0x64300001, + 0xC78, 0x63310001, + 0xC78, 0x62320001, + 0xC78, 0x61330001, + 0xC78, 0x46340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFB470001, + 0xC78, 0xFB480001, + 0xC78, 0xFA490001, + 0xC78, 0xF94A0001, + 0xC78, 0xF84B0001, + 0xC78, 0xF74C0001, + 0xC78, 0xF64D0001, + 0xC78, 0xF54E0001, + 0xC78, 0xF44F0001, + 0xC78, 0xF3500001, + 0xC78, 0xF2510001, + 0xC78, 0xF1520001, + 0xC78, 0xF0530001, + 0xC78, 0xEF540001, + 0xC78, 0xEE550001, + 0xC78, 0xED560001, + 0xC78, 0xEC570001, + 0xC78, 0xEB580001, + 0xC78, 0xEA590001, + 0xC78, 0xE95A0001, + 0xC78, 0xE85B0001, + 0xC78, 0xE75C0001, + 0xC78, 0xE65D0001, + 0xC78, 0xE55E0001, + 0xC78, 0xE45F0001, + 0xC78, 0xE3600001, + 0xC78, 0xE2610001, + 0xC78, 0xC3620001, + 0xC78, 0xC2630001, + 0xC78, 0xC1640001, + 0xC78, 0x8B650001, + 0xC78, 0x8A660001, + 0xC78, 0x89670001, + 0xC78, 0x88680001, + 0xC78, 0x87690001, + 0xC78, 0x866A0001, + 0xC78, 0x856B0001, + 0xC78, 0x846C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x60740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, +}; + +HAL_STATUS +ODM_ReadAndConfig_AGC_TAB_1T_8188E( + IN PDM_ODM_T pDM_Odm + ) +{ + #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) + + u4Byte hex = 0; + u4Byte i = 0; + u2Byte count = 0; + pu4Byte ptr_array = NULL; + u1Byte platform = pDM_Odm->SupportPlatform; + u1Byte interfaceValue = pDM_Odm->SupportInterface; + u1Byte board = pDM_Odm->BoardType; + u4Byte ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u4Byte); + pu4Byte Array = Array_AGC_TAB_1T_8188E; + BOOLEAN biol = FALSE; +#ifdef CONFIG_IOL_IOREG_CFG + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pxmit_frame; + u8 bndy_cnt=1; +#endif//#ifdef CONFIG_IOL_IOREG_CFG + HAL_STATUS rst =HAL_STATUS_SUCCESS; + + hex += board; + hex += interfaceValue << 8; + hex += platform << 16; + hex += 0xFF000000; +#ifdef CONFIG_IOL_IOREG_CFG + biol = rtw_IOL_applied(Adapter); + + if(biol){ + if((pxmit_frame= rtw_IOL_accquire_xmit_frame(Adapter)) == NULL){ + printk("rtw_IOL_accquire_xmit_frame failed\n"); + return HAL_STATUS_FAILURE; + } + } +#endif//#ifdef CONFIG_IOL_IOREG_CFG + + for (i = 0; i < ArrayLen; i += 2 ) + { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + + // This (offset, data) pair meets the condition. + if ( v1 < 0xCDCDCDCD ) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); + } + continue; + } + else + { // This line is the start line of branch. + if ( !CheckCondition(Array[i], hex) ) + { // Discard the following (offset, data) pairs. + READ_NEXT_PAIR(v1, v2, i); + while ( v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + i -= 2; // prevent from for-loop += 2 + } + else // Configure matched pairs and skip to end of if-else. + { + READ_NEXT_PAIR(v1, v2, i); + while ( v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); + } + READ_NEXT_PAIR(v1, v2, i); + } + + while (v2 != 0xDEAD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + + } + } + } +#ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) + { + #ifdef CONFIG_IOL_IOREG_CFG_DBG + printk("~~~ %s Success !!! \n",__FUNCTION__); + { + //dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + + } + else{ + printk("~~~ %s IOL_exec_cmds Failed !!! \n",__FUNCTION__); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + { + //dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + + rst = HAL_STATUS_FAILURE; + } + } +#endif //#ifdef CONFIG_IOL_IOREG_CFG + return rst; +} + +/****************************************************************************** +* PHY_REG_1T.TXT +******************************************************************************/ + +u4Byte Array_PHY_REG_1T_8188E[] = { + 0x800, 0x80040000, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x061F0649, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x07000760, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x00000000, + 0x880, 0xB0000C1C, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF000C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E7F120F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0xA80, 0x218075B1, + 0xB2C, 0x80000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x08800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC47, + 0xC34, 0x469652AF, + 0xC38, 0x49795994, + 0xC3C, 0x0A97971C, + 0xC40, 0x1F7C403F, + 0xC44, 0x000100B7, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00013169, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C00BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020610DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0xC84, 0x20F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x00000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00000740, + 0xD04, 0x00020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC43, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCC979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x00000000, + 0xD3C, 0x00127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000008, + 0xE68, 0x001B25A4, + 0xE6C, 0x00C00014, + 0xE70, 0x00C00014, + 0xE74, 0x01000014, + 0xE78, 0x01000014, + 0xE7C, 0x01000014, + 0xE80, 0x01000014, + 0xE84, 0x00C00014, + 0xE88, 0x01000014, + 0xE8C, 0x00C00014, + 0xED0, 0x00C00014, + 0xED4, 0x00C00014, + 0xED8, 0x00C00014, + 0xEDC, 0x00000014, + 0xEE0, 0x00000014, + 0xEEC, 0x01C00014, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, +}; + + +HAL_STATUS +ODM_ReadAndConfig_PHY_REG_1T_8188E( + IN PDM_ODM_T pDM_Odm + ) +{ + #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) + + u4Byte hex = 0; + u4Byte i = 0; + u2Byte count = 0; + pu4Byte ptr_array = NULL; + u1Byte platform = pDM_Odm->SupportPlatform; + u1Byte interfaceValue = pDM_Odm->SupportInterface; + u1Byte board = pDM_Odm->BoardType; + u4Byte ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u4Byte); + pu4Byte Array = Array_PHY_REG_1T_8188E; + BOOLEAN biol = FALSE; +#ifdef CONFIG_IOL_IOREG_CFG + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pxmit_frame; + u8 bndy_cnt=1; + #ifdef CONFIG_IOL_IOREG_CFG_DBG + struct cmd_cmp cmpdata[ArrayLen]; + u4Byte cmpdata_idx=0; + #endif +#endif//#ifdef CONFIG_IOL_IOREG_CFG + HAL_STATUS rst =HAL_STATUS_SUCCESS; + hex += board; + hex += interfaceValue << 8; + hex += platform << 16; + hex += 0xFF000000; +#ifdef CONFIG_IOL_IOREG_CFG + biol = rtw_IOL_applied(Adapter); + + if(biol){ + if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) + { + printk("rtw_IOL_accquire_xmit_frame failed\n"); + return HAL_STATUS_FAILURE; + } + } +#endif//#ifdef CONFIG_IOL_IOREG_CFG + + for (i = 0; i < ArrayLen; i += 2 ) + { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + + + // This (offset, data) pair meets the condition. + if ( v1 < 0xCDCDCDCD ) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + + + if (v1 == 0xfe){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); + } + else if (v1 == 0xfd){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); + } + else if (v1 == 0xfc){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); + } + else if (v1 == 0xfb){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); + } + else if (v1 == 0xfa){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); + } + else if (v1 == 0xf9){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); + } + else{ + if (v1 == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = v2; + + rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + cmpdata[cmpdata_idx].addr = v1; + cmpdata[cmpdata_idx].value= v2; + cmpdata_idx++; + #endif + } + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); + } + continue; + } + else + { // This line is the start line of branch. + if ( !CheckCondition(Array[i], hex) ) + { // Discard the following (offset, data) pairs. + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + i -= 2; // prevent from for-loop += 2 + } + else // Configure matched pairs and skip to end of if-else. + { + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + if (v1 == 0xfe){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); + } + else if (v1 == 0xfd){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); + } + else if (v1 == 0xfc){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); + } + else if (v1 == 0xfb){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); + } + else if (v1 == 0xfa){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); + } + else if (v1 == 0xf9){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); + } + else{ + if (v1 == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = v2; + + rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + cmpdata[cmpdata_idx].addr = v1; + cmpdata[cmpdata_idx].value= v2; + cmpdata_idx++; + #endif + } + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); + } + READ_NEXT_PAIR(v1, v2, i); + } + + while (v2 != 0xDEAD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + + } + } + } +#ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) + { + #ifdef CONFIG_IOL_IOREG_CFG_DBG + printk("~~~ %s IOL_exec_cmds Success !!! \n",__FUNCTION__); + { + u4Byte idx; + u4Byte cdata; + printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx); + printk("### %s data compared !!###\n",__FUNCTION__); + for(idx=0;idx< cmpdata_idx;idx++) + { + cdata = ODM_Read4Byte(pDM_Odm, cmpdata[idx].addr); + if(cdata != cmpdata[idx].value){ + printk(" addr:0x%04x, data:(0x%02x : 0x%02x) \n", + cmpdata[idx].addr,cmpdata[idx].value,cdata); + rst = HAL_STATUS_FAILURE; + } + } + printk("### %s data compared !!###\n",__FUNCTION__); + //if(rst == HAL_STATUS_FAILURE) + {//dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + + } + else{ + rst = HAL_STATUS_FAILURE; + printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + { + //dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + } + } +#endif //#ifdef CONFIG_IOL_IOREG_CFG + return rst; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_PHY_REG_PG_8188E[] = { + 0xE00, 0xFFFFFFFF, 0x06070809, + 0xE04, 0xFFFFFFFF, 0x02020405, + 0xE08, 0x0000FF00, 0x00000006, + 0x86C, 0xFFFFFF00, 0x00020400, + 0xE10, 0xFFFFFFFF, 0x08090A0B, + 0xE14, 0xFFFFFFFF, 0x01030607, + 0xE18, 0xFFFFFFFF, 0x08090A0B, + 0xE1C, 0xFFFFFFFF, 0x01030607, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x02020202, + 0xE04, 0xFFFFFFFF, 0x00020202, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x04040404, + 0xE14, 0xFFFFFFFF, 0x00020404, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x02020202, + 0xE04, 0xFFFFFFFF, 0x00020202, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x04040404, + 0xE14, 0xFFFFFFFF, 0x00020404, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x02020202, + 0xE04, 0xFFFFFFFF, 0x00020202, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x04040404, + 0xE14, 0xFFFFFFFF, 0x00020404, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + +}; + +void +ODM_ReadAndConfig_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte hex = 0; + u4Byte i = 0; + u2Byte count = 0; + pu4Byte ptr_array = NULL; + u1Byte platform = pDM_Odm->SupportPlatform; + u1Byte interfaceValue = pDM_Odm->SupportInterface; + u1Byte board = pDM_Odm->BoardType; + u4Byte ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u4Byte); + pu4Byte Array = Array_PHY_REG_PG_8188E; + BOOLEAN biol = FALSE; + + hex += board; + hex += interfaceValue << 8; + hex += platform << 16; + hex += 0xFF000000; + + for (i = 0; i < ArrayLen; i += 3 ) + { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + + // this line is a line of pure_body + if ( v1 < 0xCDCDCDCD ) + { + + odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3); + + continue; + } + else + { // this line is the start of branch + if ( !CheckCondition(Array[i], hex) ) + { // don't need the hw_body + i += 2; // skip the pair of expression + v1 = Array[i]; + v2 = Array[i+1]; + v3 = Array[i+2]; + while (v2 != 0xDEAD) + { + i += 3; + v1 = Array[i]; + v2 = Array[i+1]; + v3 = Array[i+1]; + } + } + } + } + +} + + + +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h new file mode 100755 index 00000000..1b92f29f --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_BB_8188E_HW_IMG_H +#define __INC_BB_8188E_HW_IMG_H + +//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex); + +/****************************************************************************** +* AGC_TAB_1T.TXT +******************************************************************************/ + +HAL_STATUS +ODM_ReadAndConfig_AGC_TAB_1T_8188E( + IN PDM_ODM_T pDM_Odm +); + +/****************************************************************************** +* PHY_REG_1T.TXT +******************************************************************************/ + +HAL_STATUS +ODM_ReadAndConfig_PHY_REG_1T_8188E( + IN PDM_ODM_T pDM_Odm +); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm +); + +#endif +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c new file mode 100755 index 00000000..a515df2d --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c @@ -0,0 +1,1077 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ +#if 0 +#include "Mp_Precomp.h" +#endif +#include "../odm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + +u1Byte Array_8188E_FW_AP[] = { + +}; +u4Byte ArrayLength_8188E_FW_AP = 0; + + +void +ODM_ReadFirmware_8188E_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ + ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_AP, ArrayLength_8188E_FW_AP); + *pFirmwareSize = ArrayLength_8188E_FW_AP; +} + + +#else + +#if 0 +u1Byte Array_8188E_FW_NIC[] = { + +}; +u4Byte ArrayLength_8188E_FW_NIC = 0; + + +void +ODM_ReadFirmware_8188E_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ + ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_NIC, ArrayLength_8188E_FW_NIC); + *pFirmwareSize = ArrayLength_8188E_FW_NIC; +} +#endif + +const u8 Array_8188E_FW_WoWLAN[] = { +0xE1, 0x88, 0x30, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01, 0x21, 0x11, 0x27, 0x74, 0x3D, 0x00, 0x00, +0x2D, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x4A, 0x3A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x49, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4F, 0xDE, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xE7, 0x09, 0xF6, 0x08, 0xDF, 0xFA, 0x80, 0x46, 0xE7, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x3E, +0x88, 0x82, 0x8C, 0x83, 0xE7, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x32, 0xE3, 0x09, 0xF6, 0x08, +0xDF, 0xFA, 0x80, 0x78, 0xE3, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x70, 0x88, 0x82, 0x8C, 0x83, +0xE3, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x64, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF6, 0x08, +0xDF, 0xFA, 0x80, 0x58, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x4C, +0x80, 0xD2, 0x80, 0xFA, 0x80, 0xC6, 0x80, 0xD4, 0x80, 0x69, 0x80, 0xF2, 0x80, 0x33, 0x80, 0x10, +0x80, 0xA6, 0x80, 0xEA, 0x80, 0x9A, 0x80, 0xA8, 0x80, 0xDA, 0x80, 0xE2, 0x80, 0xCA, 0x80, 0x33, +0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, +0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, +0x0D, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF6, 0x08, 0xDF, 0xF9, 0xEC, 0xFA, 0xA9, 0xF0, +0xED, 0xFB, 0x22, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, +0xC5, 0x83, 0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xEA, 0xDE, +0xE8, 0x80, 0xDB, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF2, 0x08, 0xDF, 0xF9, 0x80, 0xCC, +0x88, 0xF0, 0xEF, 0x60, 0x01, 0x0E, 0x4E, 0x60, 0xC3, 0x88, 0xF0, 0xED, 0x24, 0x02, 0xB4, 0x04, +0x00, 0x50, 0xB9, 0xF5, 0x82, 0xEB, 0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0xAF, 0x23, 0x23, 0x45, +0x82, 0x23, 0x90, 0x42, 0x50, 0x73, 0xBB, 0x01, 0x09, 0x89, 0x82, 0x8A, 0x83, 0xF8, 0xE0, 0x28, +0xF0, 0x22, 0x50, 0x03, 0x27, 0xF7, 0x22, 0xBB, 0xFE, 0x05, 0xF8, 0xE3, 0x28, 0xF3, 0x22, 0x8A, +0x83, 0x89, 0x82, 0xF8, 0xE4, 0x93, 0x28, 0x22, 0xBB, 0x01, 0x0F, 0xF8, 0xE5, 0x82, 0x29, 0xF5, +0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE0, 0x28, 0xF0, 0x22, 0x50, 0x09, 0xC5, 0x82, 0x29, 0xF8, +0xE5, 0x82, 0x26, 0xF6, 0x22, 0xBB, 0xFE, 0x09, 0xC5, 0x82, 0x29, 0xF8, 0xE2, 0x25, 0x82, 0xF2, +0x22, 0xF8, 0xEA, 0x25, 0x83, 0xF5, 0x83, 0xE9, 0x93, 0x28, 0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, +0x28, 0xF0, 0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, +0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, +0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xA4, 0x25, 0x82, 0xF5, 0x82, 0xE5, +0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB, +0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xBB, 0x01, 0x1A, 0x89, 0x82, 0x8A, 0x83, 0xD0, +0xF0, 0xD0, 0xE0, 0xF8, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xE8, 0xC0, 0xE0, +0xC0, 0xF0, 0x02, 0x43, 0x8F, 0x50, 0x16, 0xE9, 0xF8, 0xD0, 0x83, 0xD0, 0x82, 0xD0, 0xE0, 0xF9, +0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xC0, 0x82, 0xC0, 0x83, 0x02, 0x46, 0x3C, 0xBB, 0xFE, 0x16, +0xE9, 0xF8, 0xD0, 0x83, 0xD0, 0x82, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xC0, +0x82, 0xC0, 0x83, 0x02, 0x46, 0x45, 0x22, 0xBB, 0x01, 0x20, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5, +0x83, 0x3A, 0xF5, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0xF8, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, +0xE0, 0xFB, 0xE8, 0xC0, 0xE0, 0xC0, 0xF0, 0x02, 0x43, 0x8F, 0x50, 0x18, 0xE9, 0x25, 0x82, 0xF8, +0xD0, 0x83, 0xD0, 0x82, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xC0, 0x82, 0xC0, +0x83, 0x02, 0x46, 0x3C, 0xBB, 0xFE, 0x18, 0xE9, 0x25, 0x82, 0xF8, 0xD0, 0x83, 0xD0, 0x82, 0xD0, +0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xC0, 0x82, 0xC0, 0x83, 0x02, 0x46, 0x45, 0x22, +0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, +0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, 0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, +0xEF, 0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0xE3, 0xF5, 0xF0, 0x09, 0xE2, 0x08, 0xB5, 0xF0, 0x6B, 0xDF, +0xF5, 0x80, 0x67, 0xE3, 0xF5, 0xF0, 0x09, 0xE6, 0x08, 0xB5, 0xF0, 0x5E, 0xDF, 0xF5, 0x80, 0x5A, +0x87, 0xF0, 0x09, 0xE6, 0x08, 0xB5, 0xF0, 0x52, 0xDF, 0xF6, 0x80, 0x4E, 0x87, 0xF0, 0x09, 0xE2, +0x08, 0xB5, 0xF0, 0x46, 0xDF, 0xF6, 0x80, 0x42, 0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE0, +0xA3, 0xB5, 0xF0, 0x36, 0xDF, 0xF6, 0x80, 0x32, 0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE4, +0x93, 0xA3, 0xB5, 0xF0, 0x25, 0xDF, 0xF5, 0x80, 0x21, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, +0x09, 0xE0, 0xA3, 0xB5, 0xF0, 0x14, 0xDF, 0xF5, 0x80, 0x10, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, +0xF0, 0x09, 0xE4, 0x93, 0xA3, 0xB5, 0xF0, 0x02, 0xDF, 0xF4, 0x02, 0x45, 0x95, 0x80, 0x87, 0x80, +0xE9, 0x80, 0x90, 0x80, 0xD4, 0x80, 0x3E, 0x80, 0x15, 0x80, 0x6E, 0x80, 0x7E, 0x80, 0x9D, 0x80, +0xB7, 0x80, 0x8D, 0x80, 0xA3, 0x80, 0x51, 0x80, 0x74, 0x80, 0x3C, 0x02, 0x45, 0xA1, 0x89, 0x82, +0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, +0xCC, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x76, 0xDF, +0xE3, 0xDE, 0xE1, 0x80, 0x70, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xE2, 0x08, +0xB5, 0xF0, 0x62, 0xDF, 0xF4, 0x80, 0x5E, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE6, +0x08, 0xB5, 0xF0, 0x51, 0xDF, 0xF5, 0x80, 0x4D, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, +0xE2, 0x08, 0xB5, 0xF0, 0x40, 0xDF, 0xF5, 0x80, 0x3C, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, +0xF0, 0xA3, 0xE6, 0x08, 0xB5, 0xF0, 0x2E, 0xDF, 0xF4, 0x80, 0x2A, 0x80, 0x02, 0x80, 0x57, 0x89, +0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, +0x83, 0xCC, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x06, 0xDF, +0xE4, 0xDE, 0xE2, 0x80, 0x00, 0x7F, 0xFF, 0xB5, 0xF0, 0x02, 0x0F, 0x22, 0x40, 0x02, 0x7F, 0x01, +0x22, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, +0xC5, 0x83, 0xCC, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0xD5, +0xDF, 0xE5, 0xDE, 0xE3, 0x80, 0xCF, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xF5, 0xF0, 0xA3, +0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, +0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0xAF, 0xDF, 0xE4, 0xDE, 0xE2, 0x80, 0xA9, 0x88, 0xF0, 0xEF, 0x60, +0x01, 0x0E, 0x4E, 0x60, 0xAB, 0xED, 0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0x98, 0xF5, 0x82, 0xEB, +0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0x8E, 0x23, 0x23, 0x45, 0x82, 0x23, 0x90, 0x44, 0xDD, 0x73, +0xEF, 0x4E, 0x60, 0x12, 0xEF, 0x60, 0x01, 0x0E, 0xED, 0xBB, 0x01, 0x0B, 0x89, 0x82, 0x8A, 0x83, +0xF0, 0xA3, 0xDF, 0xFC, 0xDE, 0xFA, 0x22, 0x89, 0xF0, 0x50, 0x07, 0xF7, 0x09, 0xDF, 0xFC, 0xA9, +0xF0, 0x22, 0xBB, 0xFE, 0xFC, 0xF3, 0x09, 0xDF, 0xFC, 0xA9, 0xF0, 0x22, 0xEB, 0xF6, 0x08, 0xEA, +0xF6, 0x08, 0xE9, 0xF6, 0x22, 0xEB, 0xF2, 0x08, 0xEA, 0xF2, 0x08, 0xE9, 0xF2, 0x22, 0xC2, 0xAF, +0x80, 0xFE, 0x32, 0x12, 0x46, 0x52, 0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0, 0xC2, 0x8C, +0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A, 0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C, 0xEC, 0x24, +0x8B, 0xF8, 0xE6, 0xBC, 0x04, 0x02, 0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00, 0x40, 0xCE, +0x79, 0x05, 0x78, 0x80, 0x16, 0xE6, 0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1, 0x03, 0x44, +0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9, 0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF, 0x23, 0x24, +0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF, 0x05, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30, 0xE4, 0xF2, +0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50, 0x20, 0x05, 0x0C, 0x74, 0x8A, 0x25, 0x0C, 0xF8, 0xE6, 0xFD, +0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C, 0xBE, 0x04, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8, 0x6D, 0x60, +0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80, 0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5, 0x0C, 0x24, +0x8B, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE, 0x04, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD, 0xF8, 0xE5, +0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0, 0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x8A, 0xC8, 0xF6, +0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C, 0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF, 0xE6, 0x30, +0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F, 0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F, 0x08, 0x54, +0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x8A, 0xA6, 0x81, 0x74, +0x04, 0x60, 0x06, 0xFF, 0x08, 0x76, 0xFF, 0xDF, 0xFB, 0x7F, 0x05, 0xE4, 0x78, 0x80, 0xF6, 0x08, +0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81, 0x76, 0x30, 0x90, 0x49, 0xA7, 0x74, 0x01, 0x93, 0xC0, 0xE0, +0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89, 0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2, 0x8C, 0xD2, +0xAF, 0x22, 0x04, 0xEF, 0xD3, 0x94, 0x04, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81, 0x2F, 0x2F, +0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE, 0x0C, 0xEE, +0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74, 0x8A, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18, 0xBE, 0x04, +0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09, 0x09, 0x80, +0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE, 0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81, 0xEE, 0xD3, +0x9F, 0x40, 0x22, 0x74, 0x8A, 0x2E, 0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02, 0xA9, 0x81, +0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09, 0xF7, 0x19, +0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF, 0x24, 0x8A, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F, 0x04, 0x90, +0x49, 0xA7, 0x93, 0xF6, 0x08, 0xEF, 0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x04, +0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4, 0xC2, 0xAF, +0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF, 0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x8A, 0x2F, 0xF8, 0xE6, +0xF5, 0x81, 0x02, 0x46, 0x9B, 0x50, 0x2E, 0x74, 0x8B, 0x2F, 0xF8, 0xE6, 0xBF, 0x04, 0x02, 0x74, +0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74, 0x8A, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C, 0x60, 0x08, +0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19, 0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5, 0x0C, 0xB5, +0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74, 0x8B, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01, 0x0F, 0x74, +0x8A, 0x2F, 0xF8, 0xA6, 0x01, 0x08, 0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC, 0x81, 0xED, +0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8, 0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5, 0x07, 0xDE, +0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x04, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, +0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6, 0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4, 0xD2, 0xE2, +0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30, 0xE2, 0x01, 0x0F, 0x02, 0x46, 0x9A, 0x8F, 0xF0, 0xE4, 0xFF, +0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80, 0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08, 0xE6, 0x60, +0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50, 0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6, 0x60, 0x25, +0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30, 0xE2, 0x0C, +0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC, 0x4E, 0xF6, +0xD2, 0xAF, 0x02, 0x46, 0x9B, 0x7F, 0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF, 0x56, 0xC6, +0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF, 0x22, 0x02, 0x49, 0x35, 0x02, 0x47, 0x2B, 0xE4, 0x93, 0xA3, +0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03, 0xF6, 0x80, 0x01, 0xF2, 0x08, 0xDF, 0xF4, 0x80, 0x29, 0xE4, +0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, 0x33, 0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, +0x83, 0x40, 0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, 0xDF, 0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, +0x08, 0x10, 0x20, 0x40, 0x80, 0x90, 0x49, 0x7A, 0xE4, 0x7E, 0x01, 0x93, 0x60, 0xBC, 0xA3, 0xFF, +0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, 0x93, 0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, +0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40, 0xB8, 0xE4, 0x93, 0xA3, 0xFA, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, +0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, +0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, 0xBE, 0x00, 0x41, 0x83, 0xA5, 0x00, 0x41, +0x83, 0xA6, 0x00, 0x41, 0x83, 0xB1, 0x00, 0x41, 0x83, 0x5C, 0x00, 0x44, 0x83, 0x4C, 0x00, 0x50, +0xF2, 0x01, 0x44, 0x83, 0x50, 0x00, 0x0F, 0xAC, 0x01, 0x44, 0x83, 0x54, 0x00, 0x0F, 0xAC, 0x03, +0x44, 0x83, 0x58, 0x00, 0x0F, 0xAC, 0x04, 0x51, 0x7D, 0x58, 0xE8, 0x59, 0x06, 0x5A, 0x4A, 0x5B, +0x6F, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, +0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, +0xC4, 0x74, 0xB1, 0xF0, 0x74, 0x49, 0xA3, 0xF0, 0x51, 0x00, 0x74, 0xB1, 0x04, 0x90, 0x01, 0xC4, +0xF0, 0x74, 0x49, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, +0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, +0x90, 0x00, 0x54, 0xE0, 0x55, 0x35, 0xF5, 0x39, 0xA3, 0xE0, 0x55, 0x36, 0xF5, 0x3A, 0xA3, 0xE0, +0x55, 0x37, 0xF5, 0x3B, 0xA3, 0xE0, 0x55, 0x38, 0xF5, 0x3C, 0xAD, 0x39, 0x7F, 0x54, 0x12, 0x32, +0x1E, 0xAD, 0x3A, 0x7F, 0x55, 0x12, 0x32, 0x1E, 0xAD, 0x3B, 0x7F, 0x56, 0x12, 0x32, 0x1E, 0xAD, +0x3C, 0x7F, 0x57, 0x12, 0x32, 0x1E, 0x53, 0x91, 0xEF, 0x22, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, +0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, +0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0x3A, 0xF0, 0x74, 0x4A, 0xA3, +0xF0, 0x12, 0x63, 0x7E, 0xE5, 0x41, 0x30, 0xE3, 0x02, 0xF1, 0xB8, 0xE5, 0x41, 0x30, 0xE4, 0x04, +0x7F, 0x02, 0x11, 0x75, 0xE5, 0x43, 0x30, 0xE1, 0x02, 0x51, 0xA1, 0x74, 0x3A, 0x04, 0x90, 0x01, +0xC4, 0xF0, 0x74, 0x4A, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, +0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, +0x32, 0x91, 0x5B, 0x90, 0x81, 0xFC, 0xE0, 0x30, 0xE0, 0x2D, 0x90, 0x80, 0xA3, 0xE0, 0xB4, 0x01, +0x26, 0x90, 0x83, 0xB1, 0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x0A, 0x0B, 0x90, 0x81, 0xFE, 0xE0, 0x04, +0xF0, 0xE4, 0x90, 0x83, 0xB1, 0xF0, 0x90, 0x81, 0xFE, 0xE0, 0xFF, 0x90, 0x81, 0xFD, 0xE0, 0xB5, +0x07, 0x05, 0xE4, 0xA3, 0xF0, 0x51, 0xD8, 0x22, 0xE4, 0xFF, 0x8F, 0x4E, 0x90, 0x04, 0x1D, 0xE0, +0x60, 0x19, 0x90, 0x05, 0x22, 0xE0, 0xF5, 0x51, 0x74, 0xFF, 0xF0, 0x12, 0x67, 0xB9, 0xBF, 0x01, +0x02, 0x71, 0x51, 0x90, 0x05, 0x22, 0xE5, 0x51, 0xF0, 0x80, 0x02, 0x71, 0x51, 0x90, 0x04, 0x1F, +0x74, 0x20, 0xF0, 0x7F, 0x01, 0x22, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, +0xE0, 0x54, 0x3F, 0xF0, 0xEF, 0x60, 0x1D, 0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, +0x83, 0xE0, 0x44, 0x10, 0xF0, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, +0x44, 0x80, 0xF0, 0x22, 0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, +0xEF, 0xF0, 0x74, 0x1F, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x40, 0xF0, +0x22, 0x90, 0x80, 0x04, 0xE0, 0xFF, 0x7D, 0x01, 0x71, 0xF2, 0x8E, 0x4F, 0x8F, 0x50, 0xAD, 0x50, +0xAC, 0x4F, 0xAF, 0x4E, 0x71, 0x06, 0xAF, 0x50, 0xAE, 0x4F, 0x90, 0x04, 0x80, 0xE0, 0x54, 0x0F, +0xFD, 0xAC, 0x07, 0x74, 0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01, +0xF0, 0x74, 0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC, +0x07, 0x74, 0x16, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74, +0x15, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74, +0x06, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x0F, 0xF0, 0x90, 0x04, 0x53, +0xE4, 0xF0, 0x90, 0x04, 0x52, 0xF0, 0x90, 0x04, 0x51, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0x50, 0x74, +0xFD, 0xF0, 0x74, 0x14, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D, +0xFD, 0x74, 0x14, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0xE0, 0xFF, +0x7D, 0x01, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x83, 0xA8, 0xED, 0xF0, 0x90, 0x83, +0xA7, 0xEF, 0xF0, 0xE4, 0xFD, 0xFC, 0xF1, 0x8F, 0x7C, 0x00, 0xAD, 0x07, 0x90, 0x83, 0xA7, 0xE0, +0x90, 0x04, 0x25, 0xF0, 0x90, 0x83, 0xA8, 0xE0, 0x60, 0x0E, 0x74, 0x0F, 0x2F, 0xF5, 0x82, 0xE4, +0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0xAF, 0x05, 0x74, 0x08, 0x2F, 0xF5, 0x82, 0xE4, +0x34, 0xFC, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x09, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, +0xE0, 0x54, 0xF0, 0xF0, 0x74, 0x21, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, +0xF7, 0xF0, 0xAE, 0x04, 0xAF, 0x05, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0xFF, 0xE0, 0x30, +0xE0, 0x2C, 0x90, 0x82, 0x02, 0xE0, 0x04, 0xF0, 0xE0, 0xFF, 0x90, 0x82, 0x00, 0xE0, 0xB5, 0x07, +0x1D, 0x90, 0x06, 0x92, 0xE0, 0x54, 0x1C, 0x70, 0x0A, 0x51, 0xD8, 0x90, 0x82, 0x03, 0xE0, 0x04, +0xF0, 0x80, 0x06, 0x90, 0x06, 0x92, 0x74, 0x1C, 0xF0, 0xE4, 0x90, 0x82, 0x02, 0xF0, 0x22, 0x90, +0x81, 0xFF, 0xE0, 0x30, 0xE0, 0x47, 0x90, 0x82, 0x03, 0xE0, 0xFD, 0x60, 0x40, 0x74, 0x01, 0x7E, +0x00, 0xA8, 0x07, 0x08, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x04, +0xE0, 0xE0, 0xFB, 0xEF, 0x5B, 0x60, 0x06, 0xE4, 0x90, 0x82, 0x03, 0xF0, 0x22, 0x90, 0x82, 0x01, +0xE0, 0xD3, 0x9D, 0x50, 0x10, 0x90, 0x01, 0xC7, 0x74, 0x10, 0xF0, 0x91, 0xDE, 0x90, 0x81, 0xFF, +0xE0, 0x54, 0xFE, 0xF0, 0x22, 0x51, 0xD8, 0x90, 0x82, 0x03, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x80, +0x01, 0xE0, 0x64, 0x02, 0x70, 0x4B, 0x90, 0x80, 0xE6, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, +0x01, 0x30, 0xE0, 0x08, 0x90, 0x01, 0x4D, 0xE0, 0x64, 0x80, 0xF0, 0x22, 0x90, 0x80, 0xE5, 0xE0, +0xFE, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x13, 0xEF, 0x54, 0x7F, 0xFF, 0xE4, 0xFD, 0xB1, 0x39, +0x90, 0x80, 0xE6, 0xE0, 0x54, 0x7F, 0xFF, 0x7D, 0x01, 0x80, 0x14, 0x90, 0x80, 0xE6, 0xE0, 0x54, +0x7F, 0xFF, 0x7D, 0x01, 0xB1, 0x39, 0x90, 0x80, 0xE6, 0xE0, 0x54, 0x7F, 0xFF, 0xE4, 0xFD, 0x80, +0x08, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x83, 0xAC, 0xED, 0xF0, 0x90, 0x83, 0xAB, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x70, 0xE0, +0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, +0x47, 0xE0, 0x5F, 0xFD, 0x7F, 0x47, 0x12, 0x32, 0x1E, 0x90, 0x83, 0xAB, 0xE0, 0xFF, 0x74, 0x01, +0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x46, 0xE0, 0x4F, 0xFD, +0x7F, 0x46, 0x12, 0x32, 0x1E, 0x90, 0x83, 0xAC, 0xE0, 0x60, 0x18, 0x90, 0x83, 0xAB, 0xE0, 0xFF, +0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x45, 0xE0, +0x4F, 0x80, 0x17, 0x90, 0x83, 0xAB, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, +0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x45, 0xE0, 0x5F, 0xFD, 0x7F, 0x45, 0x80, 0x7E, 0x90, +0x83, 0xAB, 0xE0, 0x24, 0xF8, 0xF0, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, +0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x5F, 0xFD, 0x7F, 0x43, 0x12, +0x32, 0x1E, 0x90, 0x83, 0xAB, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, +0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x4F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, 0x90, 0x83, +0xAC, 0xE0, 0x60, 0x1D, 0x90, 0x83, 0xAB, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, +0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x4F, 0xFD, 0x7F, 0x42, 0x80, +0x1C, 0x90, 0x83, 0xAB, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, +0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x5F, 0xFD, 0x7F, 0x42, 0x12, 0x32, 0x1E, +0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x82, 0x46, 0x12, 0x43, 0x8F, 0x12, 0x63, 0xAB, 0xEF, 0x64, +0x01, 0x60, 0x02, 0xE1, 0x13, 0x90, 0x81, 0xF2, 0x71, 0xEE, 0x90, 0x82, 0x4D, 0xF1, 0x14, 0x90, +0x82, 0x4F, 0xEF, 0xF0, 0x90, 0x82, 0x4D, 0xA3, 0xE0, 0x24, 0x20, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, +0x7B, 0x01, 0x90, 0x82, 0x4C, 0xE0, 0xFD, 0x12, 0x66, 0xAF, 0x90, 0x82, 0x4D, 0xA3, 0xE0, 0x24, +0x30, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x82, +0x49, 0x12, 0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x06, 0xD0, 0x01, 0xD0, +0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x4D, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0x2F, 0x24, +0x3A, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x82, +0x49, 0x12, 0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x06, 0xD0, 0x01, 0xD0, +0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x4D, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0x2F, 0x24, +0x40, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x82, +0x46, 0x12, 0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x04, 0xD0, 0x01, 0xD0, +0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x90, 0x06, 0x30, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x04, 0x1F, +0x74, 0x20, 0xF0, 0x22, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, 0x20, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, +0x7B, 0x01, 0xE4, 0x90, 0x83, 0xB2, 0xF0, 0xFF, 0x12, 0x1F, 0xA4, 0x30, 0xE7, 0x08, 0x90, 0x83, +0xB2, 0x74, 0x02, 0xF0, 0x80, 0x05, 0xE4, 0x90, 0x83, 0xB2, 0xF0, 0x12, 0x68, 0x8C, 0x90, 0x83, +0xB2, 0xE0, 0x24, 0x18, 0x2F, 0xFF, 0x22, 0xF1, 0x8F, 0x7E, 0x00, 0x90, 0x83, 0xAF, 0xF1, 0x14, +0x90, 0x83, 0xAF, 0xA3, 0xE0, 0x2F, 0x24, 0x36, 0xF9, 0xE4, 0x34, 0xFC, 0x75, 0x13, 0x01, 0xF5, +0x14, 0x89, 0x15, 0x75, 0x16, 0x04, 0x7B, 0x01, 0x7A, 0x80, 0x79, 0xF6, 0x12, 0x2B, 0xED, 0xE4, +0xFF, 0x74, 0x18, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x06, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0xEA, 0x2F, +0xF5, 0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xEE, 0xF0, 0x0F, 0xEF, 0xB4, 0x06, 0xE3, 0x22, 0xE4, +0xFE, 0xEF, 0xC3, 0x13, 0xFD, 0xEF, 0x30, 0xE0, 0x02, 0x7E, 0x80, 0x90, 0xFD, 0x10, 0xED, 0xF0, +0xAF, 0x06, 0x22, 0x41, 0xA3, 0xE4, 0xFF, 0x81, 0x8F, 0x7F, 0x01, 0x81, 0x8F, 0xEF, 0x60, 0x07, +0x90, 0x81, 0xF2, 0xE0, 0xFF, 0xF1, 0x47, 0x22, 0x90, 0x80, 0xE4, 0xE0, 0x30, 0xE0, 0x04, 0x7F, +0x04, 0x11, 0x75, 0x22, 0x90, 0x04, 0x1D, 0xE0, 0x70, 0x13, 0x90, 0x80, 0x03, 0xE0, 0xFF, 0xE4, +0xFD, 0x71, 0xF2, 0x8E, 0x0D, 0x8F, 0x0E, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x22, 0xC0, 0xE0, +0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, +0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xDE, +0xF0, 0x74, 0x4F, 0xA3, 0xF0, 0x11, 0x4F, 0xE5, 0x4C, 0x30, 0xE1, 0x05, 0x7F, 0x03, 0x12, 0x48, +0x75, 0xE5, 0x4C, 0x30, 0xE4, 0x03, 0x12, 0x4F, 0xA3, 0xE5, 0x4C, 0x30, 0xE5, 0x03, 0x12, 0x4F, +0xA5, 0xE5, 0x4C, 0x30, 0xE6, 0x03, 0x12, 0x4F, 0xA9, 0x74, 0xDE, 0x04, 0x90, 0x01, 0xC4, 0xF0, +0x74, 0x4F, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, +0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, +0x01, 0x3C, 0xE0, 0x55, 0x45, 0xF5, 0x49, 0xA3, 0xE0, 0x55, 0x46, 0xF5, 0x4A, 0xA3, 0xE0, 0x55, +0x47, 0xF5, 0x4B, 0xA3, 0xE0, 0x55, 0x48, 0xF5, 0x4C, 0x90, 0x01, 0x3C, 0xE5, 0x49, 0xF0, 0xA3, +0xE5, 0x4A, 0xF0, 0xA3, 0xE5, 0x4B, 0xF0, 0xA3, 0xE5, 0x4C, 0xF0, 0x53, 0x91, 0xDF, 0x22, 0x90, +0x01, 0xC8, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x04, 0x7F, 0xFF, +0xFE, 0x12, 0x2B, 0x27, 0xBF, 0x01, 0x09, 0x90, 0x82, 0x04, 0xE0, 0x64, 0x03, 0x60, 0x03, 0x22, +0x21, 0x41, 0xE4, 0x90, 0x82, 0x09, 0xF0, 0x90, 0x82, 0x09, 0xE0, 0xFF, 0xC3, 0x94, 0x02, 0x40, +0x02, 0x21, 0x7C, 0xC3, 0x74, 0xFE, 0x9F, 0xFF, 0xE4, 0x94, 0x00, 0xFE, 0x7B, 0x01, 0x7A, 0x82, +0x79, 0x05, 0x12, 0x2B, 0x27, 0xEF, 0x64, 0x01, 0x70, 0x77, 0x90, 0x82, 0x05, 0xE0, 0xFF, 0x54, +0xC0, 0xFE, 0x60, 0x05, 0xEF, 0x54, 0x0C, 0x70, 0x16, 0x90, 0x82, 0x05, 0xE0, 0xFF, 0x54, 0x30, +0x60, 0x67, 0xEF, 0x54, 0x03, 0x60, 0x62, 0x90, 0x82, 0x06, 0x74, 0x01, 0xF0, 0x80, 0x05, 0xE4, +0x90, 0x82, 0x06, 0xF0, 0x90, 0x82, 0x06, 0xE0, 0x90, 0x82, 0x05, 0x70, 0x16, 0xE0, 0xFF, 0xEE, +0x13, 0x13, 0x54, 0x3F, 0x90, 0x82, 0x07, 0xF0, 0xEF, 0x54, 0x0C, 0x13, 0x13, 0x54, 0x3F, 0xA3, +0xF0, 0x80, 0x0D, 0xE0, 0xFE, 0x54, 0x30, 0x90, 0x82, 0x07, 0xF0, 0xEE, 0x54, 0x03, 0xA3, 0xF0, +0x90, 0x82, 0x07, 0xE0, 0x64, 0x30, 0x70, 0x54, 0xA3, 0xE0, 0x64, 0x02, 0x70, 0x4E, 0x90, 0x00, +0xF5, 0xE0, 0x54, 0x40, 0x90, 0x82, 0x0A, 0xF0, 0xE0, 0x70, 0x41, 0xA3, 0x74, 0x02, 0xF0, 0x80, +0x10, 0x90, 0x82, 0x0B, 0x74, 0x01, 0xF0, 0x80, 0x08, 0x90, 0x82, 0x09, 0xE0, 0x04, 0xF0, 0x01, +0xA7, 0x90, 0x01, 0xC4, 0x74, 0x7F, 0xF0, 0x74, 0x50, 0xA3, 0xF0, 0x90, 0x82, 0x0B, 0xE0, 0x90, +0x01, 0xC8, 0xF0, 0x90, 0x82, 0x05, 0xE0, 0x90, 0x01, 0xC9, 0xF0, 0x90, 0x82, 0x06, 0xE0, 0x90, +0x01, 0xCA, 0xF0, 0xE4, 0xFD, 0x7F, 0x1F, 0x12, 0x32, 0x1E, 0x80, 0xD5, 0x22, 0x90, 0x00, 0x80, +0xE0, 0x44, 0x80, 0xFD, 0x7F, 0x80, 0x12, 0x32, 0x1E, 0x90, 0xFD, 0x00, 0xE0, 0x54, 0xBF, 0xF0, +0x11, 0x7F, 0xF1, 0x24, 0x12, 0x32, 0x77, 0x12, 0x62, 0xD1, 0xD1, 0xFF, 0x7F, 0x01, 0x12, 0x47, +0x63, 0x90, 0x81, 0xFB, 0x74, 0x02, 0xF0, 0xFF, 0x12, 0x47, 0x63, 0x90, 0x81, 0xFB, 0xE0, 0x04, +0xF0, 0x7F, 0x03, 0x12, 0x47, 0x63, 0x90, 0x81, 0xFB, 0xE0, 0x04, 0xF0, 0x7F, 0x04, 0x12, 0x47, +0x63, 0x90, 0x81, 0xFB, 0xE0, 0x04, 0xF0, 0x51, 0x01, 0x31, 0xE6, 0x90, 0x00, 0x80, 0xE0, 0x44, +0x40, 0xFD, 0x7F, 0x80, 0x12, 0x32, 0x1E, 0x75, 0x20, 0xFF, 0xF1, 0x15, 0x12, 0x63, 0x01, 0xF1, +0x2C, 0xE4, 0xFF, 0x02, 0x47, 0xEC, 0xF1, 0x03, 0xF1, 0x1C, 0x51, 0x43, 0xF1, 0x37, 0x90, 0x81, +0xFF, 0xE0, 0x54, 0xFE, 0xF0, 0xA3, 0x74, 0x03, 0xF0, 0xA3, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, +0x22, 0xF1, 0x89, 0x90, 0x80, 0x01, 0xEF, 0xF0, 0x51, 0x13, 0x90, 0x01, 0x64, 0x74, 0x01, 0xF0, +0x02, 0x2D, 0xA7, 0x12, 0x62, 0x51, 0x12, 0x62, 0x81, 0xF1, 0xBD, 0x12, 0x62, 0xB2, 0xE4, 0xF5, +0x35, 0xF5, 0x36, 0xF5, 0x37, 0xF5, 0x38, 0xAD, 0x35, 0x7F, 0x50, 0x12, 0x32, 0x1E, 0xAD, 0x36, +0x7F, 0x51, 0x12, 0x32, 0x1E, 0xAD, 0x37, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xAD, 0x38, 0x7F, 0x53, +0x02, 0x32, 0x1E, 0x90, 0x80, 0xE4, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x80, 0xE9, 0xE0, 0x54, 0xFE, +0xF0, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x20, 0xF0, 0x90, 0x80, 0xE5, 0xE0, 0x54, 0xFE, 0xF0, 0x54, +0xFD, 0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0x54, 0xBF, +0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0xE0, 0x54, 0x80, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xE0, 0x54, 0xFE, +0xF0, 0x90, 0x80, 0xE6, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x80, 0xE8, 0xE0, 0x54, 0xFD, 0xF0, 0x22, +0xEF, 0x60, 0x59, 0x90, 0x04, 0xEC, 0xE0, 0x54, 0xDD, 0xF0, 0x90, 0x81, 0xF1, 0xE0, 0xFF, 0x60, +0x03, 0x12, 0x69, 0x07, 0x90, 0x01, 0xC7, 0xE4, 0xF0, 0x90, 0x01, 0x17, 0xE0, 0xFE, 0x90, 0x01, +0x16, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x80, 0x9F, 0xF0, 0xA3, 0xEF, 0xF0, +0x90, 0x06, 0x09, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x05, 0x22, 0x74, 0xFF, 0xF0, 0x71, 0x3E, 0x90, +0x02, 0x86, 0xE0, 0x44, 0x04, 0xF0, 0x71, 0x0B, 0xD1, 0xFD, 0x71, 0xCC, 0x90, 0x05, 0x22, 0xE4, +0xF0, 0x90, 0x01, 0x34, 0x74, 0x08, 0xF0, 0xFD, 0xE4, 0xFF, 0xE1, 0x5C, 0x90, 0x04, 0xEC, 0xE0, +0x44, 0x22, 0xF0, 0x7D, 0x08, 0xE4, 0xFF, 0xF1, 0x71, 0x90, 0x06, 0x90, 0xE4, 0xF0, 0x90, 0x02, +0x86, 0xE0, 0x54, 0xFB, 0xF0, 0x71, 0x1B, 0xD1, 0xFE, 0x41, 0x43, 0xD1, 0x36, 0x90, 0x02, 0x87, +0xE0, 0x70, 0xF8, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x02, 0xF0, 0x22, 0x51, 0x58, 0x90, 0x01, 0x3F, +0x74, 0x04, 0xF0, 0x90, 0x80, 0x01, 0xE0, 0xFF, 0xB4, 0x01, 0x07, 0x90, 0xFD, 0x00, 0xE0, 0x54, +0xEF, 0xF0, 0xEF, 0xB4, 0x01, 0x07, 0x90, 0xFE, 0x10, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x67, +0xB9, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0xCC, 0xF0, 0x00, 0xC0, 0x7F, 0x8C, 0x7E, 0x08, 0x12, +0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x14, 0x7F, 0x70, 0x7E, 0x0E, +0x12, 0x2E, 0xA2, 0x90, 0x83, 0x95, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xE4, 0xFD, 0xFF, +0x71, 0xA9, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x83, 0xA1, +0x12, 0x20, 0xCE, 0x90, 0x83, 0xA1, 0x12, 0x43, 0x6E, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, +0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, 0x01, 0x00, 0x74, 0x3F, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, +0xF0, 0x90, 0x05, 0x53, 0xE0, 0x44, 0x20, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0xC0, 0x07, 0xC0, 0x05, 0x90, 0x83, 0x95, 0x12, 0x43, 0x6E, 0x90, 0x83, 0x6E, 0x12, 0x20, 0xCE, +0xD0, 0x05, 0xD0, 0x07, 0x12, 0x60, 0x29, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0x90, 0x01, 0x01, 0xE0, 0x44, 0x02, 0xF0, 0x90, 0x01, 0x00, 0x74, 0xFF, 0xF0, +0x90, 0x06, 0xB7, 0x74, 0x09, 0xF0, 0x90, 0x06, 0xB4, 0x74, 0x86, 0xF0, 0x7F, 0x7C, 0x7E, 0x08, +0x12, 0x2D, 0x5C, 0xEC, 0x54, 0x7F, 0xFC, 0x90, 0x83, 0x9D, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x9D, +0x12, 0x43, 0x6E, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x7C, 0x7E, 0x08, 0x12, 0x2E, 0xA2, +0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0xCC, 0xC0, 0x00, 0xC0, 0x7F, 0x8C, 0x7E, 0x08, 0x12, 0x2E, +0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0x00, 0xC0, 0x00, 0x14, 0x7F, 0x70, 0x7E, 0x0E, 0x12, +0x2E, 0xA2, 0x90, 0x83, 0x95, 0x12, 0x20, 0xDA, 0x00, 0x03, 0x3E, 0x60, 0xE4, 0xFD, 0xFF, 0x71, +0xA9, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x1F, 0xA4, +0xFF, 0x54, 0x01, 0xFE, 0x90, 0x80, 0xE4, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, +0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x04, 0xFD, 0xEF, 0x54, +0xFB, 0x4D, 0xFF, 0x90, 0x80, 0xE4, 0xF0, 0xEE, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0xFF, +0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0xFF, 0x90, 0x80, 0xE4, +0xF0, 0xEE, 0x54, 0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0xF0, 0x90, 0x01, 0x17, 0xE0, 0xFE, 0x90, +0x01, 0x16, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x80, 0x9F, 0xF0, 0xA3, 0xEF, +0xF0, 0x90, 0x01, 0xC2, 0x74, 0x01, 0xF0, 0x90, 0x80, 0xE4, 0xE0, 0xC3, 0x13, 0x54, 0x01, 0xFF, +0x12, 0x4F, 0xAD, 0x90, 0x80, 0xE4, 0xE0, 0x13, 0x13, 0x54, 0x01, 0xFF, 0xF1, 0x09, 0x90, 0x01, +0xC2, 0x74, 0x02, 0xF0, 0x90, 0x80, 0xE4, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x01, 0xFF, 0x12, 0x6B, +0x3D, 0x90, 0x80, 0xE4, 0xE0, 0xC4, 0x54, 0x01, 0xFF, 0xF1, 0x0F, 0x90, 0x01, 0xC2, 0x74, 0x03, +0xF0, 0x04, 0xF0, 0x90, 0x80, 0xE4, 0xE0, 0x54, 0x01, 0xFF, 0x51, 0x90, 0x90, 0x01, 0xC2, 0x74, +0x05, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x82, 0x18, 0x12, 0x43, 0x8F, 0xEF, 0x12, 0x44, +0x40, 0x55, 0x33, 0x00, 0x55, 0x3C, 0x01, 0x55, 0x44, 0x02, 0x55, 0x4D, 0x03, 0x55, 0x56, 0x04, +0x55, 0x66, 0x80, 0x55, 0x5E, 0x81, 0x55, 0x6E, 0x82, 0x55, 0x76, 0x83, 0x55, 0x7F, 0x84, 0x00, +0x00, 0x55, 0x88, 0x90, 0x82, 0x18, 0x12, 0x43, 0x86, 0x02, 0x61, 0xCA, 0x90, 0x82, 0x18, 0x12, +0x43, 0x86, 0x80, 0x78, 0x90, 0x82, 0x18, 0x12, 0x43, 0x86, 0x02, 0x62, 0x12, 0x90, 0x82, 0x18, +0x12, 0x43, 0x86, 0x02, 0x68, 0x6C, 0x90, 0x82, 0x18, 0x12, 0x43, 0x86, 0x80, 0x32, 0x90, 0x82, +0x18, 0x12, 0x43, 0x86, 0x81, 0x46, 0x90, 0x82, 0x18, 0x12, 0x43, 0x86, 0xE1, 0xDC, 0x90, 0x82, +0x18, 0x12, 0x43, 0x86, 0xE1, 0xA3, 0x90, 0x82, 0x18, 0x12, 0x43, 0x86, 0x02, 0x6A, 0xAD, 0x90, +0x82, 0x18, 0x12, 0x43, 0x86, 0x02, 0x6B, 0x0F, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x01, 0xF0, 0x22, +0x31, 0xEE, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0xFF, 0xE0, 0x54, 0xFE, 0x4E, +0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x14, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0x00, +0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0x01, 0xF0, 0x22, 0x90, 0x82, 0x1B, 0x12, +0x43, 0x8F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xFE, 0x12, 0x1F, 0xA4, 0xFD, 0xC3, 0x13, +0x30, 0xE0, 0x12, 0x90, 0x82, 0x1B, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, +0x82, 0x1F, 0xF0, 0x80, 0x05, 0x90, 0x82, 0x1F, 0xEF, 0xF0, 0x90, 0x82, 0x1E, 0xEE, 0xF0, 0x90, +0x82, 0x1F, 0xE0, 0xFE, 0x90, 0x82, 0x1E, 0xE0, 0xFF, 0xD3, 0x9E, 0x50, 0x38, 0x90, 0x82, 0x1B, +0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, 0x54, 0x01, 0xFE, 0x74, 0xA3, 0x2F, 0xF5, 0x82, 0xE4, 0x34, +0x80, 0xF5, 0x83, 0xEE, 0xF0, 0x74, 0xA3, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xE0, +0x70, 0x04, 0xD1, 0xFC, 0x80, 0x07, 0x90, 0x82, 0x1E, 0xE0, 0xFF, 0xD1, 0xFB, 0x90, 0x82, 0x1E, +0xE0, 0x04, 0xF0, 0x80, 0xBA, 0x22, 0x90, 0x01, 0x1F, 0xE0, 0xFE, 0x90, 0x01, 0x1E, 0xE0, 0x7C, +0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x82, 0x1B, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x02, 0x87, +0xE0, 0xF9, 0x90, 0x80, 0xE4, 0xE0, 0x20, 0xE0, 0x02, 0xC1, 0xFA, 0xEC, 0xC3, 0x99, 0x40, 0x02, +0xC1, 0xFA, 0x90, 0x82, 0x1B, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, +0x03, 0xAD, 0x07, 0x74, 0x02, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x0F, +0x33, 0x33, 0x33, 0x54, 0xF8, 0xFB, 0x74, 0x01, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, +0xE0, 0xFE, 0x74, 0x00, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x75, 0x83, 0x00, +0x24, 0x00, 0xFF, 0xE5, 0x83, 0x3E, 0x54, 0x3F, 0xFE, 0xEB, 0x24, 0x18, 0xFB, 0xE4, 0x33, 0xFA, +0xEB, 0x2F, 0xFF, 0xEA, 0x3E, 0xFE, 0x12, 0x5E, 0x31, 0x90, 0x82, 0x1B, 0xEE, 0x8F, 0xF0, 0x12, +0x43, 0x4B, 0x90, 0x80, 0x9F, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xD3, 0x90, 0x82, 0x1C, 0xE0, 0x9F, +0x90, 0x82, 0x1B, 0xE0, 0x9E, 0x40, 0x1B, 0x90, 0x80, 0xA0, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, +0x9F, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x90, 0x82, 0x1C, 0xE0, 0x9F, 0xF0, 0x90, 0x82, 0x1B, 0xE0, +0x9E, 0xF0, 0x90, 0x82, 0x1B, 0xF1, 0x49, 0x0C, 0xC1, 0x5B, 0x22, 0x22, 0x22, 0x22, 0x22, 0xE4, +0xF5, 0x4D, 0x22, 0xE4, 0x90, 0x80, 0xA3, 0xF0, 0x22, 0x90, 0x82, 0x1B, 0xEF, 0xF0, 0x22, 0x90, +0x82, 0x1B, 0xEF, 0xF0, 0x22, 0x75, 0xE8, 0x03, 0x75, 0xA8, 0x84, 0x22, 0xE4, 0x90, 0x80, 0x9D, +0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x01, 0x94, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x01, 0xE4, 0x74, +0x0B, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x81, 0xFC, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0x7F, +0xF0, 0xA3, 0x74, 0x0A, 0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x02, +0x84, 0xEF, 0xF0, 0xEE, 0xA3, 0xF0, 0xA3, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x74, 0x3D, 0x2F, 0xF8, +0xE6, 0x4D, 0xFE, 0xF6, 0x74, 0x30, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, +0x22, 0x74, 0x3D, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, 0xF6, 0x74, 0x30, 0x2F, 0xF5, +0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0x90, 0x00, 0xF7, 0xE0, 0x20, 0xE7, 0x09, +0xE0, 0x7F, 0x01, 0x20, 0xE6, 0x0C, 0x7F, 0x02, 0x22, 0x90, 0x00, 0xF7, 0xE0, 0x30, 0xE6, 0x02, +0x7F, 0x03, 0x22, 0x90, 0x02, 0x09, 0xE0, 0x90, 0x82, 0x1B, 0xF0, 0x12, 0x1F, 0xA4, 0x90, 0x81, +0xEF, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0xF0, 0xF0, 0x22, 0x75, 0x3D, 0x10, +0xE4, 0xF5, 0x3E, 0x75, 0x3F, 0x07, 0x75, 0x40, 0x02, 0x90, 0x01, 0x30, 0xE5, 0x3D, 0xF0, 0xA3, +0xE5, 0x3E, 0xF0, 0xA3, 0xE5, 0x3F, 0xF0, 0xA3, 0xE5, 0x40, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0x12, 0x1F, 0xA4, 0xFC, 0x20, 0xE0, 0x05, 0x71, 0x1B, 0x02, 0x58, 0xE3, 0x12, +0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x80, 0xE5, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, +0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x04, 0xFD, +0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90, 0x80, 0xE5, 0xF0, 0xEE, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, +0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, 0xFE, 0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0xFF, 0x90, +0x80, 0xE5, 0xF0, 0xEE, 0x54, 0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0xFF, 0xF0, 0x12, 0x1F, 0xA4, +0xFE, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D, 0xFF, 0x90, 0x80, 0xE5, 0xF0, 0xEE, 0x54, 0x80, +0xFE, 0xEF, 0x54, 0x7F, 0x4E, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFD, 0x54, 0x80, 0xFF, +0x90, 0x80, 0xE6, 0xE0, 0x54, 0x7F, 0x4F, 0xF0, 0xEC, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x07, +0x90, 0x06, 0x90, 0xE0, 0x44, 0x04, 0xF0, 0x12, 0x1F, 0xA4, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, +0xE0, 0x07, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x80, 0x01, 0xE0, 0x64, 0x02, 0x70, +0x44, 0x90, 0x80, 0xE6, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x20, 0xE0, 0x36, 0xED, +0x54, 0x7F, 0xFE, 0xEF, 0x54, 0x80, 0x4E, 0x90, 0x80, 0xE6, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, +0xBD, 0x90, 0x80, 0xE7, 0xF0, 0x90, 0x80, 0xE5, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x09, +0xA3, 0xE0, 0x54, 0x7F, 0xFF, 0xE4, 0xFD, 0x80, 0x09, 0x90, 0x80, 0xE6, 0xE0, 0x54, 0x7F, 0xFF, +0x7D, 0x01, 0x12, 0x4D, 0x39, 0x90, 0x80, 0x01, 0xE0, 0xB4, 0x01, 0x07, 0x90, 0xFE, 0x10, 0xE0, +0x44, 0x04, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0x90, 0x82, 0x0C, 0xF0, 0x90, 0x82, 0x0C, +0xE0, 0x64, 0x01, 0xF0, 0x24, 0xE8, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x58, 0xA3, 0xF0, 0x31, 0x05, +0x12, 0x46, 0x9B, 0x80, 0xE8, 0x22, 0xE4, 0xFB, 0xFA, 0xFD, 0x7F, 0x01, 0x12, 0x48, 0x9C, 0x90, +0x82, 0x0D, 0xEF, 0xF0, 0x60, 0xF0, 0x31, 0x1A, 0x80, 0xEC, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, +0xD0, 0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0x90, 0x82, 0x0E, 0xF0, 0x90, 0x82, 0x0E, 0xE0, 0xFD, +0x70, 0x02, 0x41, 0x45, 0x90, 0x83, 0xA5, 0xE0, 0xFF, 0x74, 0x01, 0x7E, 0x00, 0xA8, 0x07, 0x08, +0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0xEF, 0x5D, 0x70, 0x02, 0x41, 0x3E, +0x90, 0x83, 0xA5, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xD0, 0x12, 0x43, 0x7A, 0xE0, 0x90, 0x82, +0x0F, 0xF0, 0x75, 0x13, 0x01, 0x75, 0x14, 0x82, 0x75, 0x15, 0x0F, 0x75, 0x16, 0x01, 0x7B, 0x01, +0x7A, 0x82, 0x79, 0x10, 0x12, 0x2B, 0xED, 0x90, 0x83, 0xA5, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, +0xD1, 0x12, 0x43, 0x7A, 0xE0, 0x90, 0x82, 0x11, 0xF0, 0x90, 0x83, 0xA5, 0xE0, 0x75, 0xF0, 0x04, +0x90, 0x01, 0xD2, 0x12, 0x43, 0x7A, 0xE0, 0x90, 0x82, 0x12, 0xF0, 0x90, 0x83, 0xA5, 0xE0, 0x75, +0xF0, 0x04, 0x90, 0x01, 0xD3, 0x12, 0x43, 0x7A, 0xE0, 0x90, 0x82, 0x13, 0xF0, 0x90, 0x83, 0xA5, +0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF0, 0x12, 0x43, 0x7A, 0xE0, 0x90, 0x82, 0x14, 0xF0, 0x90, +0x83, 0xA5, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF1, 0x12, 0x43, 0x7A, 0xE0, 0x90, 0x82, 0x15, +0xF0, 0x90, 0x83, 0xA5, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF2, 0x12, 0x43, 0x7A, 0xE0, 0x90, +0x82, 0x16, 0xF0, 0x90, 0x83, 0xA5, 0xE0, 0x75, 0xF0, 0x04, 0x90, 0x01, 0xF3, 0x12, 0x43, 0x7A, +0xE0, 0x90, 0x82, 0x17, 0xF0, 0x90, 0x82, 0x0E, 0xE0, 0xFF, 0x90, 0x83, 0xA5, 0xE0, 0xFE, 0x74, +0x01, 0xA8, 0x06, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0x5F, 0x90, 0x82, 0x0E, 0xF0, +0x90, 0x83, 0xA5, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, +0x90, 0x01, 0xCC, 0xF0, 0x90, 0x82, 0x10, 0xE0, 0xFF, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x11, 0x12, +0x55, 0x07, 0x90, 0x83, 0xA5, 0xE0, 0x04, 0xF0, 0xE0, 0x54, 0x03, 0xF0, 0x21, 0x2B, 0x90, 0x01, +0xC0, 0xE0, 0x44, 0x02, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0xFB, 0xFA, 0xFD, 0x7F, 0x01, +0x12, 0x48, 0x9C, 0x90, 0x82, 0x20, 0xEF, 0xF0, 0x60, 0xF0, 0x51, 0x5E, 0x80, 0xEC, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xE4, 0xFF, 0x90, 0x80, 0x9E, 0xE0, 0xFE, 0x90, 0x80, 0x9D, 0xE0, +0xFD, 0xB5, 0x06, 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x64, 0x01, 0x60, 0x32, 0x90, +0x01, 0xAF, 0xE0, 0x70, 0x13, 0xED, 0x75, 0xF0, 0x0F, 0xA4, 0x24, 0x07, 0xF9, 0x74, 0x80, 0x35, +0xF0, 0xFA, 0x7B, 0x01, 0x51, 0xB6, 0x7F, 0x01, 0xEF, 0x60, 0x16, 0x90, 0x80, 0x9D, 0xE0, 0x04, +0xF0, 0xE0, 0x7F, 0x00, 0xB4, 0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, 0x90, 0x80, 0x9D, +0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, 0x21, +0x12, 0x43, 0x8F, 0x90, 0x83, 0xA6, 0xE0, 0xFF, 0x04, 0xF0, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, +0xFC, 0x7F, 0xAF, 0x7E, 0x01, 0x71, 0x19, 0xEF, 0x60, 0x3A, 0x90, 0x82, 0x21, 0x12, 0x43, 0x86, +0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x90, 0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xF5, 0x16, +0x7B, 0x01, 0x7A, 0x01, 0x79, 0xA0, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x21, 0x12, 0x43, 0x86, 0x90, +0x00, 0x0E, 0x12, 0x1F, 0xBD, 0x90, 0x01, 0xAE, 0xF0, 0xA3, 0x74, 0xFF, 0xF0, 0x90, 0x01, 0xCB, +0xE0, 0x64, 0x80, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x83, 0x99, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x83, 0x99, +0xE0, 0xFE, 0xA3, 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0xE0, 0x60, 0x2D, 0xC3, 0x90, 0x83, 0x9C, 0xE0, +0x94, 0xE8, 0x90, 0x83, 0x9B, 0xE0, 0x94, 0x03, 0x40, 0x0B, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x80, +0xF0, 0x7F, 0x00, 0x80, 0x15, 0x90, 0x83, 0x9B, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x7F, +0x0A, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x80, 0xC5, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, +0xFB, 0xFA, 0xFD, 0x7F, 0x01, 0x12, 0x48, 0x9C, 0x90, 0x82, 0x24, 0xEF, 0xF0, 0x60, 0xF0, 0xD1, +0x5A, 0xBF, 0x01, 0xEB, 0x71, 0x88, 0x80, 0xE7, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, +0x82, 0x2D, 0x74, 0x08, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x1F, 0xE0, 0xFE, 0x90, +0x01, 0x1E, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x82, 0x25, 0xF0, 0xA3, 0xEF, +0xF0, 0x90, 0x02, 0x82, 0xE0, 0x90, 0x82, 0x2C, 0xF0, 0x90, 0x80, 0xE4, 0xE0, 0x20, 0xE0, 0x02, +0xA1, 0x79, 0x90, 0x80, 0xE9, 0xE0, 0x20, 0xE0, 0x07, 0x90, 0x01, 0x3F, 0xE0, 0x30, 0xE2, 0x18, +0x90, 0x80, 0x01, 0xE0, 0xB4, 0x01, 0x0E, 0x90, 0xFD, 0x01, 0xE0, 0x20, 0xE6, 0x07, 0x90, 0xFD, +0x00, 0xE0, 0x44, 0x10, 0xF0, 0x12, 0x4C, 0xDE, 0xE4, 0x90, 0x82, 0x2B, 0xF0, 0x90, 0x82, 0x2C, +0xE0, 0xFF, 0x90, 0x82, 0x2B, 0xE0, 0xC3, 0x9F, 0x40, 0x02, 0xA1, 0x79, 0x90, 0x82, 0x25, 0xE0, +0xFC, 0xA3, 0xE0, 0xFD, 0xEC, 0xFF, 0x90, 0xFD, 0x11, 0xF0, 0x90, 0x82, 0x27, 0xED, 0xF0, 0x90, +0x82, 0x2F, 0xEF, 0xF0, 0x90, 0x82, 0x27, 0xE0, 0xFF, 0x24, 0x02, 0xF5, 0x82, 0xE4, 0x34, 0xFB, +0xF5, 0x83, 0xE0, 0x54, 0x0F, 0x33, 0x33, 0x33, 0x54, 0xF8, 0xFE, 0x90, 0x82, 0x29, 0xF0, 0xEF, +0x24, 0x18, 0x2E, 0x90, 0x82, 0x28, 0xF0, 0xE0, 0xFD, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, +0xF5, 0x83, 0xE0, 0x54, 0xFC, 0x90, 0x82, 0x2A, 0xF0, 0x74, 0x00, 0x2D, 0xF9, 0xE4, 0x34, 0xFB, +0xFA, 0x7B, 0x01, 0x12, 0x4F, 0x22, 0x90, 0x82, 0x2E, 0xEF, 0xF0, 0x90, 0x82, 0x27, 0xE0, 0xFD, +0x24, 0x01, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x00, 0x2D, 0xF5, 0x82, +0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x54, 0x3F, 0xFE, +0x90, 0x82, 0x29, 0xE0, 0x24, 0x18, 0xFD, 0xEC, 0x33, 0xFC, 0xED, 0x2F, 0xFF, 0xEC, 0x3E, 0xFE, +0xD1, 0x31, 0x90, 0x82, 0x27, 0xE0, 0x24, 0x0F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, +0xFD, 0x90, 0x82, 0x25, 0xEE, 0x8F, 0xF0, 0x12, 0x43, 0x4B, 0x90, 0x80, 0x9F, 0xE0, 0xFE, 0xA3, +0xE0, 0xFF, 0xD3, 0x90, 0x82, 0x26, 0xE0, 0x9F, 0x90, 0x82, 0x25, 0xE0, 0x9E, 0x40, 0x1B, 0x90, +0x80, 0xA0, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0x9F, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x90, 0x82, +0x26, 0xE0, 0x9F, 0xF0, 0x90, 0x82, 0x25, 0xE0, 0x9E, 0xF0, 0xED, 0x30, 0xE7, 0x06, 0x90, 0x01, +0xC7, 0x74, 0x21, 0xF0, 0xED, 0x30, 0xE6, 0x06, 0x90, 0x01, 0xC7, 0x74, 0x22, 0xF0, 0xED, 0x30, +0xE5, 0x06, 0x90, 0x01, 0xC7, 0x74, 0x23, 0xF0, 0x90, 0x82, 0x2A, 0xE0, 0x24, 0x40, 0x60, 0x04, +0x24, 0x20, 0x70, 0x21, 0x90, 0x80, 0xE5, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x30, +0xE0, 0x43, 0x90, 0x82, 0x28, 0xE0, 0xFF, 0xD1, 0x97, 0xEF, 0x60, 0x39, 0x90, 0x82, 0x2A, 0xE0, +0xFF, 0xB1, 0xF4, 0x80, 0x30, 0x90, 0x82, 0x28, 0xE0, 0xFF, 0x90, 0x82, 0x2E, 0xE0, 0xFD, 0x90, +0x82, 0x2D, 0xE0, 0xFB, 0x90, 0x82, 0x2F, 0xE0, 0x90, 0x82, 0x33, 0xF0, 0xB1, 0x7E, 0x90, 0x80, +0xE4, 0xE0, 0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x0D, 0x90, 0x82, 0x28, 0xE0, 0xFF, 0x90, 0x82, 0x2E, +0xE0, 0xFD, 0x12, 0x69, 0x67, 0x90, 0x80, 0xE9, 0xE0, 0x20, 0xE0, 0x07, 0x90, 0x01, 0x3F, 0xE0, +0x30, 0xE2, 0x03, 0x12, 0x4C, 0xDE, 0xD1, 0x0B, 0xBF, 0x01, 0x0E, 0x90, 0x82, 0x25, 0x12, 0x57, +0x49, 0x90, 0x82, 0x2B, 0xE0, 0x04, 0xF0, 0x61, 0xED, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x74, 0x00, +0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x0C, 0x64, 0x08, 0x70, 0x64, 0xEF, +0x2D, 0xFE, 0x24, 0x06, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x64, 0x88, 0x70, 0x53, +0x74, 0x07, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x64, 0x8E, 0x70, 0x44, 0xEF, +0x2D, 0x2B, 0xFE, 0x24, 0x01, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x64, 0x03, 0x70, +0x32, 0x74, 0x06, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x30, 0xE3, 0x1A, 0x90, +0x80, 0xE5, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, 0x18, 0x90, 0x01, 0xC7, 0x74, 0x01, +0xF0, 0x90, 0x80, 0xE9, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x7E, 0x00, 0x90, 0x82, 0x33, 0xE0, 0xFD, +0x12, 0x71, 0x15, 0x22, 0xEF, 0x90, 0x01, 0xC7, 0xB4, 0xA0, 0x05, 0x74, 0x04, 0xF0, 0x80, 0x03, +0x74, 0x08, 0xF0, 0x90, 0x80, 0xE9, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x80, 0xE9, 0xE0, 0xFF, +0x20, 0xE0, 0x07, 0x90, 0x01, 0x3F, 0xE0, 0x30, 0xE2, 0x14, 0xEF, 0x44, 0x01, 0x90, 0x80, 0xE9, +0xF0, 0x90, 0x80, 0xE5, 0xE0, 0xC4, 0x54, 0x0F, 0x20, 0xE0, 0x03, 0x7F, 0x00, 0x22, 0x7F, 0x01, +0x22, 0x7D, 0x7F, 0xEF, 0x5D, 0xC3, 0x60, 0x14, 0x74, 0xFF, 0x9D, 0xFD, 0x74, 0xFF, 0x94, 0x00, +0x5E, 0xFE, 0xED, 0x5F, 0x24, 0x80, 0xFF, 0xE4, 0x3E, 0xFE, 0x80, 0x0D, 0x74, 0xFF, 0x9D, 0xFD, +0x74, 0xFF, 0x94, 0x00, 0x5E, 0xFE, 0xED, 0x5F, 0xFF, 0x22, 0xE4, 0x90, 0x83, 0xAD, 0xF0, 0xA3, +0xF0, 0x90, 0x02, 0x86, 0xE0, 0x20, 0xE1, 0x2C, 0xC3, 0x90, 0x83, 0xAE, 0xE0, 0x94, 0xD0, 0x90, +0x83, 0xAD, 0xE0, 0x94, 0x07, 0x40, 0x0A, 0x90, 0x01, 0xC1, 0xE0, 0x44, 0x04, 0xF0, 0x7F, 0x00, +0x22, 0x90, 0x83, 0xAD, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x7F, 0x0A, 0x7E, 0x00, 0x12, +0x32, 0xAA, 0x80, 0xCD, 0x7F, 0x01, 0x22, 0xE4, 0xFE, 0x74, 0x10, 0x2E, 0xF5, 0x82, 0xE4, 0x34, +0x06, 0xF5, 0x83, 0xE0, 0xFD, 0x74, 0x36, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xED, +0xF0, 0xEF, 0x2E, 0x24, 0x04, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFD, 0x74, 0x30, +0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xED, 0xF0, 0x0E, 0xEE, 0xB4, 0x06, 0xCA, 0x78, +0x36, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x30, 0x7E, 0x00, 0x7F, 0x06, 0x12, +0x45, 0xEC, 0xEF, 0x7F, 0x00, 0x70, 0x02, 0x7F, 0x01, 0x22, 0x90, 0x83, 0x5D, 0xEF, 0xF0, 0xA3, +0xED, 0xF0, 0xA3, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x90, 0x83, 0x6B, 0xF0, 0x7F, +0x24, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0x90, 0x83, 0x63, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x5D, 0xE0, +0xFB, 0x70, 0x08, 0x90, 0x83, 0x63, 0x12, 0x43, 0x6E, 0x80, 0x16, 0xEB, 0x75, 0xF0, 0x08, 0xA4, +0x24, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2D, +0x5C, 0x90, 0x83, 0x67, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x5E, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, +0x78, 0x17, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x83, 0x67, +0x12, 0x43, 0x6E, 0xED, 0x54, 0x7F, 0xFD, 0xEC, 0x54, 0x80, 0xFC, 0x12, 0x43, 0x61, 0xEC, 0x44, +0x80, 0xFC, 0x90, 0x83, 0x67, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x63, 0x12, 0x43, 0x6E, 0xEC, 0x54, +0x7F, 0xFC, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, 0x12, 0x2E, 0xA2, 0x90, +0x83, 0x5D, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, +0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x83, 0x67, 0x12, 0x43, 0x6E, 0x90, +0x85, 0xBB, 0x12, 0x20, 0xCE, 0xD0, 0x07, 0xD0, 0x06, 0x12, 0x2E, 0xA2, 0x90, 0x83, 0x63, 0x12, +0x43, 0x6E, 0xEC, 0x44, 0x80, 0xFC, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0x7F, 0x24, 0x7E, 0x08, +0x12, 0x2E, 0xA2, 0x90, 0x83, 0x5D, 0xE0, 0x70, 0x04, 0x7F, 0x20, 0x80, 0x09, 0x90, 0x83, 0x5D, +0xE0, 0xB4, 0x01, 0x16, 0x7F, 0x28, 0x7E, 0x08, 0x12, 0x2D, 0x5C, 0x78, 0x08, 0x12, 0x20, 0xA8, +0xEF, 0x54, 0x01, 0xFF, 0xE4, 0x90, 0x83, 0x6B, 0xEF, 0xF0, 0x90, 0x83, 0x6B, 0xE0, 0x90, 0x83, +0x5D, 0x60, 0x0E, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x66, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0x80, +0x0C, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x64, 0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, +0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x2D, 0x5C, 0xED, 0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x90, 0x83, 0x5F, +0x12, 0x20, 0xCE, 0x90, 0x83, 0x5F, 0x02, 0x43, 0x6E, 0x90, 0x83, 0x6C, 0xEF, 0xF0, 0xAB, 0x05, +0x90, 0x83, 0x72, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x03, 0xE4, 0xFC, 0xFD, 0xFE, +0x78, 0x14, 0x12, 0x20, 0xBB, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, 0xAB, 0x07, 0x90, 0x83, 0x6E, +0x12, 0x43, 0x6E, 0xED, 0x54, 0x0F, 0xFD, 0xE4, 0xFC, 0x12, 0x43, 0x61, 0xEC, 0x54, 0x0F, 0xFC, +0x90, 0x83, 0x72, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x6C, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x60, +0xF5, 0x82, 0xE4, 0x34, 0x87, 0xF5, 0x83, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC0, 0x06, 0xC0, 0x07, +0x90, 0x83, 0x72, 0x12, 0x43, 0x6E, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xCE, 0xD0, 0x07, 0xD0, 0x06, +0x02, 0x2E, 0xA2, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x5E, 0xEA, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x8E, 0x19, 0x8F, 0x1A, 0xE5, 0x1E, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, 0x85, 0x19, +0x83, 0x85, 0x1A, 0x82, 0xF0, 0xE5, 0x1D, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, 0xFF, 0xE5, 0x1E, +0x13, 0x13, 0x13, 0x54, 0x1F, 0x4F, 0xA3, 0xF0, 0xEB, 0x54, 0x07, 0xC4, 0x33, 0x54, 0xE0, 0xFF, +0xE5, 0x1D, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x4F, 0x85, 0x1A, 0x82, 0x85, 0x19, 0x83, 0xA3, 0xA3, +0xF0, 0xBD, 0x01, 0x0C, 0x85, 0x1A, 0x82, 0x8E, 0x83, 0xA3, 0xA3, 0xA3, 0x74, 0x03, 0xF0, 0x22, +0x85, 0x1A, 0x82, 0x85, 0x19, 0x83, 0xA3, 0xA3, 0xA3, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x83, 0x76, +0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xAD, 0x03, 0xAC, 0x02, 0xE4, 0x90, 0x83, 0x7E, 0xF0, 0xA3, 0xF0, +0x90, 0x01, 0xC4, 0x74, 0xFD, 0xF0, 0x74, 0x60, 0xA3, 0xF0, 0xEC, 0x54, 0x3F, 0xFC, 0x90, 0x01, +0x40, 0xED, 0xF0, 0xAE, 0x04, 0xEE, 0xA3, 0xF0, 0x90, 0x83, 0x76, 0xE0, 0x24, 0x81, 0x60, 0x34, +0x24, 0xDA, 0x60, 0x1C, 0x24, 0x3C, 0x70, 0x41, 0x90, 0x83, 0x77, 0xE0, 0xC4, 0x33, 0x33, 0x33, +0x54, 0x80, 0x90, 0x83, 0x7B, 0xF0, 0xA3, 0x74, 0x69, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x80, 0x2C, +0x90, 0x83, 0x77, 0xE0, 0x54, 0x01, 0x90, 0x83, 0x7B, 0xF0, 0xA3, 0x74, 0xA5, 0xF0, 0xA3, 0x74, +0x01, 0xF0, 0x80, 0x18, 0x90, 0x83, 0x77, 0xE0, 0xC4, 0x54, 0x10, 0x90, 0x83, 0x7B, 0xF0, 0xA3, +0x74, 0x7F, 0xF0, 0xA3, 0x74, 0x10, 0xF0, 0x80, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x83, 0x7C, 0xE0, +0x90, 0x01, 0x06, 0xF0, 0x90, 0x83, 0x7B, 0xE0, 0x60, 0x0E, 0x90, 0x01, 0x42, 0xF0, 0x90, 0x83, +0x7A, 0xE0, 0x90, 0x01, 0x43, 0xF0, 0x80, 0x0D, 0x90, 0x01, 0x43, 0xE4, 0xF0, 0x90, 0x83, 0x7B, +0xE0, 0x90, 0x01, 0x42, 0xF0, 0x90, 0x83, 0x7D, 0xE0, 0xFF, 0x90, 0x01, 0x42, 0xE0, 0x5F, 0xFF, +0x90, 0x83, 0x7B, 0xE0, 0x6F, 0x60, 0xEE, 0x74, 0xFD, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x60, +0xA3, 0xF0, 0x90, 0x01, 0x43, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0x90, 0x02, 0x09, 0xE0, 0xFD, 0x12, +0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x80, 0x02, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, +0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x03, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0xED, +0x2F, 0x90, 0x80, 0x04, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, +0x05, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x80, 0x06, +0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x1F, 0xA4, 0xFF, 0x90, 0x80, 0xE3, +0xF0, 0xBF, 0x01, 0x12, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x17, 0x90, 0x05, +0x22, 0x74, 0x6F, 0xF0, 0x80, 0x0F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x05, +0x90, 0x05, 0x22, 0xE4, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x8F, 0x0F, 0x22, 0x8F, 0x1F, 0x22, +0x22, 0x90, 0x01, 0x30, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x38, 0xF0, +0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x50, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x51, +0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x52, 0x12, 0x32, 0x1E, 0xE4, 0xFD, 0x7F, 0x53, 0x02, 0x32, +0x1E, 0x90, 0x01, 0x34, 0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x3C, +0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xFD, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, +0x55, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x56, 0x12, 0x32, 0x1E, 0x7D, 0xFF, 0x7F, 0x57, 0x02, +0x32, 0x1E, 0x75, 0x45, 0x0E, 0x75, 0x46, 0x01, 0x75, 0x47, 0x03, 0x75, 0x48, 0x62, 0x90, 0x01, +0x38, 0xE5, 0x45, 0xF0, 0xA3, 0xE5, 0x46, 0xF0, 0xA3, 0xE5, 0x47, 0xF0, 0xA3, 0xE5, 0x48, 0xF0, +0x22, 0x90, 0x01, 0x01, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x01, 0x9C, 0x74, 0x7E, 0xF0, 0xA3, 0x74, +0x92, 0xF0, 0xA3, 0x74, 0xA0, 0xF0, 0xA3, 0x74, 0x24, 0xF0, 0x90, 0x01, 0x9B, 0x74, 0x49, 0xF0, +0x90, 0x01, 0x9A, 0x74, 0xE0, 0xF0, 0x90, 0x01, 0x99, 0xE4, 0xF0, 0x90, 0x01, 0x98, 0x04, 0xF0, +0x22, 0xE4, 0x90, 0x82, 0x04, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x98, 0xE0, 0x7F, 0x00, 0x30, 0xE4, +0x02, 0x7F, 0x01, 0xEF, 0x64, 0x01, 0x60, 0x3E, 0xC3, 0x90, 0x82, 0x05, 0xE0, 0x94, 0x88, 0x90, +0x82, 0x04, 0xE0, 0x94, 0x13, 0x40, 0x08, 0x90, 0x01, 0xC1, 0xE0, 0x44, 0x10, 0xF0, 0x22, 0x90, +0x82, 0x04, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x7F, 0x14, 0x7E, 0x00, 0x12, 0x32, 0xAA, +0xD3, 0x90, 0x82, 0x05, 0xE0, 0x94, 0x32, 0x90, 0x82, 0x04, 0xE0, 0x94, 0x00, 0x40, 0xB9, 0x90, +0x01, 0xC6, 0xE0, 0x30, 0xE3, 0xB2, 0x22, 0x7F, 0x02, 0x90, 0x81, 0xFB, 0xE0, 0xFE, 0xEF, 0xC3, +0x9E, 0x50, 0x18, 0xEF, 0x25, 0xE0, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE4, 0x0B, 0x90, 0x01, 0xB8, +0x74, 0x08, 0xF0, 0xA3, 0xF0, 0x7F, 0x00, 0x22, 0x0F, 0x80, 0xDE, 0x7F, 0x01, 0x22, 0x90, 0x01, +0x34, 0xE0, 0x55, 0x3D, 0xF5, 0x41, 0xA3, 0xE0, 0x55, 0x3E, 0xF5, 0x42, 0xA3, 0xE0, 0x55, 0x3F, +0xF5, 0x43, 0xA3, 0xE0, 0x55, 0x40, 0xF5, 0x44, 0x90, 0x01, 0x34, 0xE5, 0x41, 0xF0, 0xA3, 0xE5, +0x42, 0xF0, 0xA3, 0xE5, 0x43, 0xF0, 0xA3, 0xE5, 0x44, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, +0xC0, 0xD0, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x1A, 0x90, 0x05, 0x22, 0xE0, 0x54, 0x90, 0x60, 0x07, +0x90, 0x01, 0xC0, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE1, 0xE4, 0x7F, 0x00, +0x80, 0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x82, 0x47, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x90, 0x82, 0x5F, 0x74, 0x18, +0xF0, 0x7E, 0x00, 0x7F, 0x80, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x67, 0x12, 0x46, 0x10, +0x90, 0x81, 0xF4, 0xE0, 0xFF, 0x12, 0x4F, 0x8F, 0x90, 0x82, 0x5E, 0xEF, 0xF0, 0xF9, 0xE0, 0xFE, +0x24, 0x21, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x74, 0x41, 0xF0, 0xEE, 0x24, 0x20, 0xFD, +0xE4, 0x33, 0xFC, 0x90, 0x82, 0x5F, 0xE0, 0x7A, 0x00, 0x2D, 0xFE, 0xEA, 0x3C, 0x90, 0x82, 0x63, +0xF0, 0xA3, 0xCE, 0xF0, 0x74, 0x20, 0x29, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x90, 0x82, +0x49, 0xE0, 0xFD, 0xD1, 0xAF, 0x90, 0x82, 0x63, 0xE4, 0x75, 0xF0, 0x08, 0x12, 0x43, 0x4B, 0x90, +0x82, 0x63, 0xE4, 0x75, 0xF0, 0x08, 0x12, 0x43, 0x4B, 0x90, 0x82, 0x63, 0xE0, 0xFF, 0xA3, 0xE0, +0x90, 0x82, 0x61, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x82, 0x67, 0x74, 0x01, 0xF0, 0xA3, 0x74, +0x03, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0x74, 0x5F, 0xF0, 0x90, 0x82, 0x63, 0xE4, 0x75, 0xF0, 0x04, +0x12, 0x43, 0x4B, 0x90, 0x81, 0x59, 0xE0, 0xFF, 0x7E, 0x02, 0xB4, 0xFE, 0x02, 0x7E, 0xFE, 0x90, +0x82, 0x63, 0xA3, 0xE0, 0xFD, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xEE, 0xF0, +0x74, 0x00, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x90, 0x82, 0x6B, 0xF0, 0x90, +0x82, 0x63, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x90, 0x81, 0xEE, 0xE0, 0x90, 0x82, 0x47, +0xB4, 0x01, 0x0B, 0xE0, 0x44, 0x03, 0xFC, 0xA3, 0xE0, 0x44, 0x10, 0xFD, 0x80, 0x09, 0xE0, 0x44, +0x03, 0xFC, 0xA3, 0xE0, 0x44, 0x20, 0xFD, 0x90, 0x82, 0x65, 0xEC, 0xF0, 0xA3, 0xED, 0xF0, 0x90, +0x82, 0x6C, 0x74, 0x03, 0xF0, 0xA3, 0x74, 0x12, 0xF0, 0x90, 0x82, 0x63, 0xE4, 0x75, 0xF0, 0x02, +0x12, 0x43, 0x4B, 0xEF, 0x64, 0xFE, 0x70, 0x37, 0x90, 0x82, 0x63, 0xA3, 0xE0, 0x24, 0x00, 0xF9, +0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0x8B, 0x13, 0x75, 0x14, 0x81, 0x75, 0x15, 0x5C, +0x75, 0x16, 0x02, 0xD0, 0x03, 0x12, 0x2B, 0xED, 0x75, 0x13, 0x01, 0x75, 0x14, 0x81, 0x75, 0x15, +0x5C, 0x75, 0x16, 0x02, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x6E, 0x12, 0x2B, 0xED, 0x80, 0x60, 0x90, +0x81, 0x0B, 0xE0, 0xFF, 0xB4, 0x02, 0x2B, 0x90, 0x82, 0x63, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x24, +0x00, 0xF5, 0x82, 0x74, 0xFC, 0x3C, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x01, 0x2D, 0xF5, 0x82, 0x74, +0xFC, 0x3C, 0xF5, 0x83, 0x74, 0x20, 0xF0, 0xE4, 0x90, 0x82, 0x6E, 0xF0, 0xA3, 0x74, 0x20, 0xF0, +0x80, 0x2D, 0xEF, 0xB4, 0x04, 0x29, 0x90, 0x82, 0x63, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x24, 0x00, +0xF5, 0x82, 0x74, 0xFC, 0x3E, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x01, 0x2F, 0xF5, 0x82, 0x74, 0xFC, +0x3E, 0xF5, 0x83, 0x74, 0x10, 0xF0, 0xE4, 0x90, 0x82, 0x6E, 0xF0, 0xA3, 0x74, 0x10, 0xF0, 0x90, +0x82, 0x63, 0xE4, 0x75, 0xF0, 0x02, 0x12, 0x43, 0x4B, 0xE4, 0x90, 0x82, 0x60, 0xF0, 0x90, 0x82, +0x60, 0xE0, 0xFF, 0x24, 0x5E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFE, 0x90, 0x82, +0x63, 0xA3, 0xE0, 0xFD, 0xEF, 0x2D, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xEE, +0xF0, 0x90, 0x82, 0x60, 0xE0, 0xFF, 0x24, 0x5E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, +0xFE, 0x74, 0x70, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xEE, 0xF0, 0x90, 0x82, 0x60, +0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x08, 0xB7, 0x90, 0x82, 0x63, 0xE4, 0x75, 0xF0, 0x08, 0x12, 0x43, +0x4B, 0x90, 0x82, 0x63, 0xE4, 0x75, 0xF0, 0x20, 0x12, 0x43, 0x4B, 0x90, 0x82, 0x63, 0xE4, 0x75, +0xF0, 0x10, 0x12, 0x43, 0x4B, 0x90, 0x82, 0x63, 0xE4, 0x75, 0xF0, 0x08, 0x12, 0x43, 0x4B, 0x90, +0x82, 0x63, 0xE4, 0x75, 0xF0, 0x08, 0x12, 0x43, 0x4B, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x67, 0x90, +0x82, 0xEC, 0x12, 0x43, 0x8F, 0x90, 0x82, 0xEF, 0x74, 0x63, 0xF0, 0x7A, 0x82, 0x79, 0x4A, 0xA3, +0x12, 0x43, 0x8F, 0x7A, 0x81, 0x79, 0x0D, 0x7D, 0x10, 0x12, 0x6B, 0x78, 0xE4, 0x90, 0x82, 0x60, +0xF0, 0x90, 0x82, 0x60, 0xE0, 0xFF, 0xC3, 0x94, 0x10, 0x50, 0x41, 0x90, 0x82, 0x63, 0xA3, 0xE0, +0xFE, 0xEF, 0x2E, 0xFF, 0x90, 0x82, 0xE7, 0xF0, 0x7E, 0x00, 0x90, 0x81, 0xF4, 0xE0, 0xFD, 0xF1, +0x4F, 0x90, 0x82, 0x5E, 0xEF, 0xF0, 0x90, 0x82, 0x60, 0xE0, 0x24, 0x4A, 0xF5, 0x82, 0xE4, 0x34, +0x82, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, 0x5E, 0xE0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC, +0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x60, 0xE0, 0x04, 0xF0, 0x80, 0xB5, 0x71, 0xAB, 0xBF, 0x01, +0x19, 0x90, 0x81, 0xF4, 0x12, 0x4B, 0xEE, 0x90, 0x82, 0x5E, 0xEF, 0xF0, 0x90, 0x81, 0xF4, 0xE0, +0x90, 0x04, 0x25, 0xF0, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, +0x82, 0xEB, 0xED, 0xF0, 0x90, 0x82, 0xE8, 0x12, 0x43, 0x8F, 0xE4, 0x90, 0x82, 0xEC, 0xF0, 0xA3, +0xF0, 0x12, 0x4F, 0x22, 0x90, 0x82, 0xEC, 0xEF, 0xF0, 0x90, 0x82, 0xE8, 0x12, 0x43, 0x86, 0x12, +0x68, 0x8C, 0x90, 0x82, 0xED, 0xEF, 0xF0, 0x90, 0x80, 0xFA, 0xE0, 0x24, 0xFE, 0x60, 0x1E, 0x24, +0xFE, 0x60, 0x1A, 0x14, 0x60, 0x07, 0x14, 0x60, 0x04, 0x24, 0x05, 0x70, 0x61, 0x7B, 0x01, 0x7A, +0x80, 0x79, 0xFB, 0x90, 0x82, 0xEB, 0xE0, 0xFD, 0x12, 0x7C, 0xF7, 0x80, 0x23, 0x7B, 0x01, 0x7A, +0x81, 0x79, 0x03, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x8F, 0x90, 0x82, 0xEB, 0xE0, 0x90, 0x82, 0xF4, +0xF0, 0x90, 0x80, 0xFA, 0xE0, 0x90, 0x82, 0xF5, 0xF0, 0x7A, 0x80, 0x79, 0xFB, 0x12, 0x7A, 0xB0, +0x90, 0x82, 0xED, 0xE0, 0xFF, 0x90, 0x82, 0xE8, 0x12, 0x43, 0x86, 0x90, 0x82, 0xEC, 0xE0, 0x7C, +0x00, 0x29, 0xF9, 0xEC, 0x3A, 0xFA, 0xC3, 0xE9, 0x9F, 0xF9, 0xEA, 0x94, 0x00, 0xFA, 0x75, 0x13, +0x01, 0x75, 0x14, 0x80, 0x75, 0x15, 0xFB, 0xA3, 0xE0, 0xF5, 0x16, 0x12, 0x2B, 0xED, 0x22, 0xC3, +0xEE, 0x94, 0x01, 0x40, 0x0A, 0x0D, 0xED, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, +0x90, 0x82, 0x46, 0xED, 0xF0, 0x90, 0x82, 0x44, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0x74, 0xAF, +0x90, 0x82, 0x44, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD, 0x61, 0xD9, 0xFD, 0xE4, 0x33, +0xFC, 0x7E, 0x00, 0xED, 0x2F, 0xFF, 0xEE, 0x3C, 0xFE, 0x90, 0x82, 0x36, 0xE0, 0xFD, 0xC3, 0xEE, +0x94, 0x01, 0x40, 0x24, 0x90, 0xFD, 0x11, 0xE0, 0x6D, 0x70, 0x1A, 0x90, 0x01, 0x17, 0xE0, 0xB5, +0x05, 0x0D, 0x90, 0x01, 0xE4, 0x74, 0x77, 0xF0, 0x90, 0xFD, 0x11, 0xE4, 0xF0, 0x80, 0x06, 0xED, +0x04, 0x90, 0xFD, 0x11, 0xF0, 0xE4, 0x2F, 0xFF, 0x22, 0xE4, 0x90, 0x83, 0xA9, 0xF0, 0xA3, 0xF0, +0x90, 0x05, 0xF8, 0xE0, 0x70, 0x0F, 0xA3, 0xE0, 0x70, 0x0B, 0xA3, 0xE0, 0x70, 0x07, 0xA3, 0xE0, +0x70, 0x03, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x83, 0xAA, 0xE0, 0x94, 0xE8, 0x90, 0x83, 0xA9, 0xE0, +0x94, 0x03, 0x40, 0x0A, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x20, 0xF0, 0x7F, 0x00, 0x22, 0x7F, 0x32, +0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x83, 0xA9, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x80, +0xBF, 0x74, 0x45, 0x2F, 0xF8, 0xE6, 0x4D, 0xFE, 0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, +0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0x74, 0x45, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0xFE, +0xF6, 0x74, 0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0xEE, 0xF0, 0x22, 0xAB, 0x07, +0xAA, 0x06, 0xED, 0x2B, 0xFB, 0xE4, 0x3A, 0xFA, 0xC3, 0x90, 0x80, 0xA0, 0xE0, 0x9B, 0x90, 0x80, +0x9F, 0xE0, 0x9A, 0x50, 0x13, 0xA3, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0x9F, 0xE0, 0x34, 0x00, +0xFE, 0xC3, 0xEB, 0x9F, 0xFB, 0xEA, 0x9E, 0xFA, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x74, +0x00, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x22, 0x12, 0x1F, 0xA4, 0xFF, +0x54, 0x01, 0xFE, 0x90, 0x81, 0xFC, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, +0x0A, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0xFD, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0x90, 0x83, 0x80, 0x12, 0x43, 0x8F, 0xE4, 0x90, 0x83, 0x83, 0xF0, 0x90, 0x83, +0x80, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x04, 0xF9, 0xE4, 0x3A, 0x8B, 0x13, 0xF5, 0x14, 0x89, 0x15, +0x75, 0x16, 0x06, 0x7B, 0x01, 0x7A, 0x83, 0x79, 0x84, 0x12, 0x2B, 0xED, 0x90, 0x83, 0x84, 0xE0, +0x20, 0xE0, 0x05, 0x90, 0x81, 0xEF, 0x80, 0x03, 0x90, 0x81, 0xF0, 0xE0, 0x90, 0x80, 0xFA, 0xF0, +0x90, 0x80, 0xFA, 0xE0, 0x14, 0x60, 0x11, 0x14, 0x60, 0x16, 0x24, 0xFE, 0x60, 0x12, 0x14, 0x60, +0x07, 0x14, 0x60, 0x04, 0x24, 0x06, 0x80, 0x10, 0x90, 0x83, 0x83, 0x74, 0x04, 0xF0, 0x80, 0x0D, +0x90, 0x83, 0x83, 0x74, 0x08, 0xF0, 0x80, 0x05, 0xE4, 0x90, 0x83, 0x83, 0xF0, 0x90, 0x83, 0x83, +0xE0, 0xFF, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x12, 0x4F, 0x8F, 0x7E, 0x00, 0x74, 0x00, 0x2F, 0xF9, +0xE4, 0x34, 0xFC, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x08, 0x7B, 0x01, 0x7A, +0x80, 0x79, 0xFB, 0x12, 0x2B, 0xED, 0x90, 0x80, 0xFB, 0xE0, 0x90, 0x81, 0x03, 0xF0, 0x90, 0x80, +0xFC, 0xE0, 0x90, 0x81, 0x04, 0xF0, 0x90, 0x80, 0xFD, 0xE0, 0x90, 0x81, 0x05, 0xF0, 0x90, 0x80, +0xFE, 0xE0, 0x90, 0x81, 0x06, 0xF0, 0x90, 0x80, 0xFF, 0xE0, 0x90, 0x81, 0x07, 0xF0, 0x90, 0x81, +0x00, 0xE0, 0x90, 0x81, 0x08, 0xF0, 0x90, 0x81, 0x01, 0xE0, 0x90, 0x81, 0x09, 0xF0, 0x90, 0x81, +0x02, 0xE0, 0x90, 0x81, 0x0A, 0xF0, 0x22, 0x90, 0x82, 0x30, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x78, +0x38, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, 0xC0, 0x7E, 0x00, 0x7F, 0x06, 0x12, +0x42, 0xD0, 0x78, 0x3E, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, 0xC6, 0x7E, 0x00, +0x7F, 0x04, 0x12, 0x42, 0xD0, 0x78, 0x42, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x40, 0x79, +0xCA, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x42, 0xD0, 0x90, 0x82, 0x31, 0xE0, 0xFF, 0x90, 0x82, 0x30, +0xE0, 0x2F, 0xFF, 0x24, 0x06, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x64, 0x08, 0x60, +0x02, 0x41, 0xAC, 0x74, 0x07, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x64, 0x06, +0x60, 0x02, 0x41, 0xAC, 0x90, 0x06, 0x30, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x82, 0x30, 0xE0, 0x24, +0x0A, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x06, 0x7B, +0x01, 0x7A, 0x82, 0x79, 0x32, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x31, 0xE0, 0xFF, 0x90, 0x82, 0x30, +0xE0, 0x2F, 0x24, 0x10, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, +0x16, 0x06, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x38, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x31, 0xE0, 0xFF, +0x90, 0x82, 0x30, 0xE0, 0x2F, 0x24, 0x16, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, +0x89, 0x15, 0x75, 0x16, 0x04, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x3E, 0x12, 0x2B, 0xED, 0x78, 0x32, +0x7C, 0x82, 0x7D, 0x01, 0x7B, 0x01, 0x7A, 0x80, 0x79, 0xEA, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x45, +0xEC, 0xEF, 0x70, 0x58, 0x90, 0x82, 0x31, 0xE0, 0xFF, 0x90, 0x82, 0x30, 0xE0, 0x2F, 0x24, 0x20, +0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x04, 0x7B, 0x01, +0x7A, 0x82, 0x79, 0x42, 0x12, 0x2B, 0xED, 0x78, 0x42, 0x7C, 0x82, 0x7D, 0x01, 0x7B, 0x01, 0x7A, +0x80, 0x79, 0xF6, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x18, 0x7B, 0x01, 0x7A, +0x82, 0x79, 0x38, 0x90, 0x82, 0x49, 0x12, 0x43, 0x8F, 0xE4, 0x90, 0x82, 0x4C, 0xF0, 0x7A, 0x82, +0x79, 0x3E, 0x02, 0x4E, 0x45, 0x90, 0x06, 0x30, 0xE0, 0x44, 0x20, 0xF0, 0x22, 0x90, 0x02, 0x09, +0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x81, 0xF1, 0xF0, 0x90, 0x00, +0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x81, 0xF2, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, +0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x81, 0xF3, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0xFF, 0xED, +0x2F, 0x90, 0x81, 0xF4, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x81, +0xF5, 0xF0, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x81, 0xF6, 0xF0, 0x90, +0x00, 0x06, 0x12, 0x1F, 0xBD, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x81, 0xF7, 0xF0, 0x22, 0x90, +0x02, 0x09, 0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x81, 0xF8, 0xF0, +0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x81, 0xF9, 0xF0, 0x90, 0x00, 0x02, +0x12, 0x1F, 0xBD, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x81, 0xFA, 0xF0, 0x22, 0xE4, 0xFD, 0xFC, +0xEF, 0x60, 0x34, 0x90, 0x81, 0xF5, 0xE0, 0xFF, 0x12, 0x4F, 0x8F, 0x7C, 0x00, 0xAD, 0x07, 0x74, +0x00, 0x2F, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x90, 0x82, 0x1B, 0x12, 0x43, 0x8F, 0x90, +0x82, 0x1B, 0x12, 0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x4A, 0x7B, 0x01, +0x7A, 0x81, 0x79, 0x0B, 0x12, 0x2B, 0xED, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, +0x82, 0xE8, 0x12, 0x43, 0x8F, 0x90, 0x82, 0xEB, 0xED, 0xF0, 0xE4, 0x90, 0x83, 0x37, 0xF0, 0x90, +0x83, 0x37, 0xE0, 0xFF, 0xC3, 0x94, 0x40, 0x50, 0x14, 0x74, 0xF4, 0x2F, 0xF5, 0x82, 0xE4, 0x34, +0x82, 0xF5, 0x83, 0xE4, 0xF0, 0x90, 0x83, 0x37, 0xE0, 0x04, 0xF0, 0x80, 0xE2, 0x90, 0x82, 0xE8, +0x12, 0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x90, 0x82, 0xEB, 0xE0, 0xF5, 0x16, 0x7B, +0x01, 0x7A, 0x82, 0x79, 0xF4, 0x12, 0x2B, 0xED, 0xE4, 0x90, 0x82, 0xF3, 0xF0, 0x90, 0x82, 0xF3, +0xE0, 0xFF, 0xC3, 0x94, 0x40, 0x50, 0x16, 0x74, 0xF4, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, +0x83, 0xE0, 0x64, 0x36, 0xF0, 0x90, 0x82, 0xF3, 0xE0, 0x04, 0xF0, 0x80, 0xE0, 0x90, 0x82, 0xEC, +0x12, 0x43, 0x86, 0x90, 0x82, 0xEF, 0xE0, 0xFF, 0xF5, 0x82, 0x75, 0x83, 0x00, 0x74, 0x80, 0x12, +0x1F, 0xFC, 0xEF, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x00, 0xFF, 0xE5, 0xF0, 0x34, 0x02, 0xFC, 0x90, +0x00, 0x7E, 0x12, 0x1F, 0xFC, 0xEF, 0x90, 0x00, 0x7F, 0x12, 0x1F, 0xFC, 0xE4, 0x90, 0x83, 0x34, +0xF0, 0xA3, 0xF0, 0x90, 0x83, 0x34, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0x94, 0xC0, 0xEE, 0x94, +0x00, 0x40, 0x02, 0xA1, 0xD2, 0xC3, 0xEF, 0x94, 0x40, 0xEE, 0x94, 0x00, 0x50, 0x52, 0xA3, 0x74, +0x40, 0xF0, 0x74, 0xF4, 0x2F, 0xF9, 0xE4, 0x34, 0x82, 0xFA, 0x7B, 0x01, 0x74, 0x40, 0x44, 0x88, +0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, 0x34, 0xA3, 0xE0, 0x24, 0xF8, 0xF9, 0xE4, 0x34, 0x82, 0xFA, +0x7B, 0x01, 0xA3, 0xE0, 0x44, 0x89, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, 0x34, 0xA3, 0xE0, 0x24, +0xFC, 0xF9, 0xE4, 0x34, 0x82, 0xFA, 0x7B, 0x01, 0xA3, 0xE0, 0x44, 0x8A, 0xFD, 0x12, 0x28, 0x08, +0x90, 0x83, 0x34, 0xA3, 0xE0, 0x24, 0x00, 0xF9, 0xE4, 0x34, 0x83, 0xFA, 0x7B, 0x01, 0xA1, 0x13, +0xE4, 0x90, 0x83, 0x36, 0xF0, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, 0xE0, 0xFE, +0xA3, 0xE0, 0x29, 0xF9, 0xEA, 0x3E, 0xFA, 0xE9, 0x24, 0xC0, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, 0x74, +0x88, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, 0xE0, 0xFE, +0xA3, 0xE0, 0x29, 0xF9, 0xEA, 0x3E, 0xFA, 0xE9, 0x24, 0xC4, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, 0xA3, +0xE0, 0x44, 0x89, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, +0xE0, 0xFE, 0xA3, 0xE0, 0x29, 0xF9, 0xEA, 0x3E, 0xFA, 0xE9, 0x24, 0xC8, 0xF9, 0xEA, 0x34, 0xFF, +0xFA, 0xA3, 0xE0, 0x44, 0x8A, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, +0x83, 0x34, 0xE0, 0xFE, 0xA3, 0xE0, 0x29, 0xF9, 0xEA, 0x3E, 0xFA, 0xE9, 0x24, 0xCC, 0xF9, 0xEA, +0x34, 0xFF, 0xFA, 0xA3, 0xE0, 0x44, 0x8B, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, 0x36, 0xE0, 0x44, +0x90, 0x90, 0x01, 0x8C, 0xF0, 0xE4, 0x90, 0x83, 0x38, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x8C, 0xE0, +0x30, 0xE4, 0x22, 0xC3, 0x90, 0x83, 0x39, 0xE0, 0x94, 0xE8, 0x90, 0x83, 0x38, 0xE0, 0x94, 0x03, +0x50, 0x13, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x83, 0x38, 0xE4, 0x75, 0xF0, 0x01, +0x12, 0x43, 0x4B, 0x80, 0xD7, 0x90, 0x83, 0x38, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0x94, 0xE8, +0xEE, 0x94, 0x03, 0x40, 0x0C, 0x90, 0x06, 0x31, 0xE0, 0x44, 0x01, 0xF0, 0xEE, 0x90, 0x06, 0x36, +0xF0, 0x90, 0x83, 0x35, 0xE0, 0x54, 0x3F, 0x64, 0x30, 0x70, 0x4B, 0x90, 0x83, 0x38, 0xF0, 0xA3, +0xF0, 0x90, 0x01, 0x8C, 0xE0, 0x20, 0xE5, 0x22, 0xC3, 0x90, 0x83, 0x39, 0xE0, 0x94, 0xE8, 0x90, +0x83, 0x38, 0xE0, 0x94, 0x03, 0x50, 0x13, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x83, +0x38, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x80, 0xD7, 0x90, 0x83, 0x38, 0xE0, 0xFE, 0xA3, +0xE0, 0xFF, 0xC3, 0x94, 0xE8, 0xEE, 0x94, 0x03, 0x40, 0x0C, 0x90, 0x06, 0x31, 0xE0, 0x44, 0x02, +0xF0, 0xEE, 0x90, 0x06, 0x36, 0xF0, 0x90, 0x83, 0x34, 0xE4, 0x75, 0xF0, 0x10, 0x12, 0x43, 0x4B, +0x81, 0x23, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x10, 0xF9, 0xE4, 0x3A, 0xFA, 0x7D, +0x80, 0x12, 0x2A, 0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x0C, 0xF9, 0xE4, 0x3A, +0xFA, 0x7D, 0x81, 0x12, 0x2A, 0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x08, 0xF9, +0xE4, 0x3A, 0xFA, 0x7D, 0x82, 0x12, 0x2A, 0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, +0x04, 0xF9, 0xE4, 0x3A, 0xFA, 0x7D, 0x83, 0x12, 0x2A, 0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, +0x7D, 0x84, 0x12, 0x2A, 0x8F, 0xE4, 0x90, 0x83, 0x37, 0xF0, 0x90, 0x83, 0x37, 0xE0, 0xFF, 0xC3, +0x94, 0x40, 0x50, 0x14, 0x74, 0xF4, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE4, 0xF0, +0x90, 0x83, 0x37, 0xE0, 0x04, 0xF0, 0x80, 0xE2, 0x90, 0x82, 0xE8, 0x12, 0x43, 0x86, 0x8B, 0x13, +0x8A, 0x14, 0x89, 0x15, 0x90, 0x82, 0xEB, 0xE0, 0xF5, 0x16, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0xF4, +0x12, 0x2B, 0xED, 0xE4, 0x90, 0x82, 0xF3, 0xF0, 0x90, 0x82, 0xF3, 0xE0, 0xFF, 0xC3, 0x94, 0x40, +0x50, 0x16, 0x74, 0xF4, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0x64, 0x5C, 0xF0, +0x90, 0x82, 0xF3, 0xE0, 0x04, 0xF0, 0x80, 0xE0, 0xE4, 0x90, 0x82, 0xF3, 0xF0, 0x90, 0x82, 0xF0, +0x12, 0x43, 0x86, 0x90, 0x82, 0xF3, 0xE0, 0xFF, 0xF5, 0x82, 0x75, 0x83, 0x00, 0x12, 0x1F, 0xBD, +0xFE, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x8F, 0x82, 0x75, 0x83, 0x00, 0xEE, 0x12, 0x1F, 0xFC, +0x90, 0x82, 0xF3, 0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x14, 0xD3, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, +0x90, 0x00, 0x14, 0x74, 0x80, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF3, 0x74, 0x15, 0xF0, 0x90, 0x82, +0xF3, 0xE0, 0xFF, 0xC3, 0x94, 0x3E, 0x50, 0x17, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x8F, 0x82, +0x75, 0x83, 0x00, 0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF3, 0xE0, 0x04, 0xF0, 0x80, 0xDF, 0x90, +0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x00, 0x3E, 0x74, 0x02, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x3F, +0x74, 0xA0, 0x12, 0x1F, 0xFC, 0xE4, 0x90, 0x83, 0x34, 0xF0, 0xA3, 0xF0, 0x90, 0x83, 0x34, 0xE0, +0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0x94, 0x80, 0xEE, 0x94, 0x00, 0x40, 0x03, 0x02, 0x70, 0xBD, 0xC3, +0xEF, 0x94, 0x40, 0xEE, 0x94, 0x00, 0x50, 0x52, 0xA3, 0x74, 0x40, 0xF0, 0x74, 0xF4, 0x2F, 0xF9, +0xE4, 0x34, 0x82, 0xFA, 0x7B, 0x01, 0x74, 0x40, 0x44, 0x88, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, +0x34, 0xA3, 0xE0, 0x24, 0xF8, 0xF9, 0xE4, 0x34, 0x82, 0xFA, 0x7B, 0x01, 0xA3, 0xE0, 0x44, 0x89, +0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, 0x34, 0xA3, 0xE0, 0x24, 0xFC, 0xF9, 0xE4, 0x34, 0x82, 0xFA, +0x7B, 0x01, 0xA3, 0xE0, 0x44, 0x8A, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, 0x34, 0xA3, 0xE0, 0x24, +0x00, 0xF9, 0xE4, 0x34, 0x83, 0xFA, 0x7B, 0x01, 0xE1, 0xFD, 0xE4, 0x90, 0x83, 0x36, 0xF0, 0x90, +0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, 0xE0, 0xFE, 0xA3, 0xE0, 0x29, 0xF9, 0xEA, 0x3E, +0xFA, 0xE9, 0x24, 0xC0, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, 0x74, 0x88, 0xFD, 0x12, 0x28, 0x08, 0x90, +0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, 0xE0, 0xFE, 0xA3, 0xE0, 0x29, 0xF9, 0xEA, 0x3E, +0xFA, 0xE9, 0x24, 0xC4, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, 0xA3, 0xE0, 0x44, 0x89, 0xFD, 0x12, 0x28, +0x08, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, 0xE0, 0xFE, 0xA3, 0xE0, 0x29, 0xF9, +0xEA, 0x3E, 0xFA, 0xE9, 0x24, 0xC8, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, 0xA3, 0xE0, 0x44, 0x8A, 0xFD, +0x12, 0x28, 0x08, 0x90, 0x82, 0xEC, 0x12, 0x43, 0x86, 0x90, 0x83, 0x34, 0xE0, 0xFE, 0xA3, 0xE0, +0x29, 0xF9, 0xEA, 0x3E, 0xFA, 0xE9, 0x24, 0xCC, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, 0xA3, 0xE0, 0x44, +0x8B, 0xFD, 0x12, 0x28, 0x08, 0x90, 0x83, 0x36, 0xE0, 0x44, 0x90, 0x90, 0x01, 0x8C, 0xF0, 0xE4, +0x90, 0x83, 0x38, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x8C, 0xE0, 0x30, 0xE4, 0x22, 0xC3, 0x90, 0x83, +0x39, 0xE0, 0x94, 0xE8, 0x90, 0x83, 0x38, 0xE0, 0x94, 0x03, 0x50, 0x13, 0x7F, 0x01, 0x7E, 0x00, +0x12, 0x32, 0xAA, 0x90, 0x83, 0x38, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x43, 0x4B, 0x80, 0xD7, 0x90, +0x83, 0x38, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0x94, 0xE8, 0xEE, 0x94, 0x03, 0x40, 0x0C, 0x90, +0x06, 0x31, 0xE0, 0x44, 0x01, 0xF0, 0xEE, 0x90, 0x06, 0x36, 0xF0, 0x90, 0x83, 0x35, 0xE0, 0x54, +0x3F, 0x64, 0x30, 0x70, 0x4B, 0x90, 0x83, 0x38, 0xF0, 0xA3, 0xF0, 0x90, 0x01, 0x8C, 0xE0, 0x20, +0xE5, 0x22, 0xC3, 0x90, 0x83, 0x39, 0xE0, 0x94, 0xE8, 0x90, 0x83, 0x38, 0xE0, 0x94, 0x03, 0x50, +0x13, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x83, 0x38, 0xE4, 0x75, 0xF0, 0x01, 0x12, +0x43, 0x4B, 0x80, 0xD7, 0x90, 0x83, 0x38, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0x94, 0xE8, 0xEE, +0x94, 0x03, 0x40, 0x0C, 0x90, 0x06, 0x31, 0xE0, 0x44, 0x02, 0xF0, 0xEE, 0x90, 0x06, 0x36, 0xF0, +0x90, 0x83, 0x34, 0xE4, 0x75, 0xF0, 0x10, 0x12, 0x43, 0x4B, 0x02, 0x6F, 0x0C, 0x90, 0x82, 0xF0, +0x12, 0x43, 0x86, 0xE9, 0x24, 0x10, 0xF9, 0xE4, 0x3A, 0xFA, 0x7D, 0x80, 0x12, 0x2A, 0x8F, 0x90, +0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x0C, 0xF9, 0xE4, 0x3A, 0xFA, 0x7D, 0x81, 0x12, 0x2A, +0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x08, 0xF9, 0xE4, 0x3A, 0xFA, 0x7D, 0x82, +0x12, 0x2A, 0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x04, 0xF9, 0xE4, 0x3A, 0xFA, +0x7D, 0x83, 0x12, 0x2A, 0x8F, 0x90, 0x82, 0xF0, 0x12, 0x43, 0x86, 0x7D, 0x84, 0x12, 0x2A, 0x8F, +0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x82, 0x34, 0xEE, +0xF0, 0xA3, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xE4, 0x90, 0x82, 0x3F, 0xF0, 0xA3, 0x74, 0x08, 0xF0, +0xA3, 0xF0, 0x90, 0x06, 0x31, 0xE0, 0x54, 0xEF, 0x44, 0x08, 0xF0, 0x90, 0x82, 0x34, 0xA3, 0xE0, +0x24, 0x00, 0xF9, 0xE4, 0x34, 0xFB, 0xFA, 0x7B, 0x01, 0x12, 0x4F, 0x22, 0x90, 0x82, 0x34, 0xA3, +0xE0, 0x2F, 0xFF, 0x90, 0x82, 0x41, 0xE0, 0x2F, 0x90, 0x82, 0x43, 0xF0, 0x7E, 0x00, 0x7F, 0x83, +0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x55, 0x12, 0x46, 0x10, 0x90, 0x82, 0x43, 0xE0, 0x24, +0x00, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x01, 0x7B, +0x01, 0x7A, 0x81, 0x79, 0x55, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x43, 0xE0, 0x24, 0x01, 0xF9, 0xE4, +0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x01, 0x7B, 0x01, 0x7A, 0x81, +0x79, 0x56, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x43, 0xE0, 0x24, 0x02, 0xF9, 0xE4, 0x34, 0xFB, 0x75, +0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x02, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x57, 0x12, +0x2B, 0xED, 0x90, 0x82, 0x43, 0xE0, 0x24, 0x04, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, +0x14, 0x89, 0x15, 0x75, 0x16, 0x01, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x59, 0x12, 0x2B, 0xED, 0x90, +0x82, 0x43, 0xE0, 0x24, 0x05, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, +0x75, 0x16, 0x02, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0x5A, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x43, 0xE0, +0x24, 0x07, 0xF9, 0xE4, 0x34, 0xFB, 0x75, 0x13, 0x01, 0xF5, 0x14, 0x89, 0x15, 0x75, 0x16, 0x02, +0x7B, 0x01, 0x7A, 0x81, 0x79, 0x5C, 0x12, 0x2B, 0xED, 0xE4, 0x90, 0x82, 0x42, 0xF0, 0x90, 0x82, +0x42, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x50, 0x33, 0xA3, 0xE0, 0x24, 0x09, 0x12, 0x67, 0x7D, 0x7E, +0x00, 0x90, 0x82, 0x3D, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, +0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, 0x42, 0xE0, 0x24, 0x5E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, +0x83, 0xEF, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0x04, 0xF0, 0x80, 0xC3, 0xE4, 0x90, 0x82, 0x42, 0xF0, +0x90, 0x82, 0x42, 0xE0, 0xFF, 0xC3, 0x94, 0x20, 0x50, 0x33, 0xA3, 0xE0, 0x24, 0x11, 0x12, 0x67, +0x7D, 0x7E, 0x00, 0x90, 0x82, 0x3D, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4, +0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, 0x42, 0xE0, 0x24, 0x66, 0xF5, 0x82, 0xE4, 0x34, +0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0x04, 0xF0, 0x80, 0xC3, 0xE4, 0x90, 0x82, +0x42, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0xFF, 0xC3, 0x94, 0x10, 0x50, 0x33, 0xA3, 0xE0, 0x24, 0x31, +0x12, 0x67, 0x7D, 0x7E, 0x00, 0x90, 0x82, 0x3D, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, 0x00, 0xF5, +0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, 0x42, 0xE0, 0x24, 0x86, 0xF5, 0x82, +0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0x04, 0xF0, 0x80, 0xC3, 0xE4, +0x90, 0x82, 0x42, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x50, 0x33, 0xA3, 0xE0, +0x24, 0x41, 0x12, 0x67, 0x7D, 0x7E, 0x00, 0x90, 0x82, 0x3D, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, +0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, 0x42, 0xE0, 0x24, 0x96, +0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0x04, 0xF0, 0x80, +0xC3, 0xE4, 0x90, 0x82, 0x42, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x50, 0x33, +0xA3, 0xE0, 0x24, 0x49, 0x12, 0x67, 0x7D, 0x7E, 0x00, 0x90, 0x82, 0x3D, 0xEE, 0xF0, 0xA3, 0xEF, +0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, 0x42, 0xE0, +0x24, 0x9E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0x04, +0xF0, 0x80, 0xC3, 0xE4, 0x90, 0x82, 0x42, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0xFF, 0xC3, 0x94, 0x10, +0x50, 0x33, 0xA3, 0xE0, 0x24, 0x51, 0x12, 0x67, 0x7D, 0x7E, 0x00, 0x90, 0x82, 0x3D, 0xEE, 0xF0, +0xA3, 0xEF, 0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x82, +0x42, 0xE0, 0x24, 0xA6, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x82, 0x42, +0xE0, 0x04, 0xF0, 0x80, 0xC3, 0xE4, 0x90, 0x82, 0x42, 0xF0, 0x90, 0x82, 0x42, 0xE0, 0xFF, 0xC3, +0x94, 0x02, 0x50, 0x33, 0xA3, 0xE0, 0x24, 0x61, 0x12, 0x67, 0x7D, 0x7E, 0x00, 0x90, 0x82, 0x3D, +0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, +0x90, 0x82, 0x42, 0xE0, 0x24, 0xB6, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x90, +0x82, 0x42, 0xE0, 0x04, 0xF0, 0x80, 0xC3, 0xE4, 0x90, 0x82, 0x42, 0xF0, 0x90, 0x82, 0x42, 0xE0, +0xFF, 0xC3, 0x94, 0x20, 0x50, 0x33, 0xA3, 0xE0, 0x24, 0x63, 0x12, 0x67, 0x7D, 0x7E, 0x00, 0x90, +0x82, 0x3D, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, +0xE0, 0xFF, 0x90, 0x82, 0x42, 0xE0, 0x24, 0xB8, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, +0xF0, 0x90, 0x82, 0x42, 0xE0, 0x04, 0xF0, 0x80, 0xC3, 0x90, 0x81, 0x57, 0xE0, 0xFC, 0xA3, 0xE0, +0xFA, 0xEC, 0xFF, 0xEA, 0xFE, 0x90, 0x82, 0x39, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x81, 0xB6, +0xE0, 0xFE, 0xA3, 0xE0, 0xFD, 0xED, 0xFF, 0x90, 0x82, 0x3B, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, +0x81, 0x5A, 0xE0, 0xFE, 0xA3, 0xE0, 0xFD, 0xED, 0xFF, 0x90, 0x82, 0x37, 0xEE, 0xF0, 0xA3, 0xEF, +0xF0, 0x30, 0xE3, 0x05, 0x12, 0x4C, 0xDE, 0x80, 0x3F, 0x90, 0x82, 0x37, 0xA3, 0xE0, 0xFF, 0x7C, +0x00, 0x54, 0x07, 0xFD, 0x64, 0x01, 0x60, 0x05, 0xED, 0x64, 0x02, 0x70, 0x2B, 0xED, 0x64, 0x02, +0x4C, 0x70, 0x25, 0xEF, 0x54, 0x30, 0xFF, 0xE4, 0xC4, 0xF8, 0x54, 0xF0, 0xC8, 0xEF, 0xC4, 0x54, +0x0F, 0x48, 0x90, 0x81, 0xEE, 0xF0, 0xAE, 0x04, 0xAF, 0x05, 0xE4, 0xFD, 0x12, 0x67, 0x60, 0x90, +0x06, 0x31, 0xE0, 0x54, 0xF7, 0x44, 0x10, 0xF0, 0x7F, 0x00, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, +0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x81, 0xF0, 0xE0, 0xFD, 0xB4, 0x02, 0x0C, 0x90, 0x82, +0x7E, 0x74, 0x80, 0xF0, 0xA3, 0x74, 0x08, 0xF0, 0x80, 0x0E, 0xED, 0xB4, 0x04, 0x0A, 0x90, 0x82, +0x7E, 0x74, 0x80, 0xF0, 0xA3, 0x74, 0x10, 0xF0, 0xEF, 0x64, 0x02, 0x4E, 0x60, 0x02, 0xA1, 0xAC, +0x90, 0x81, 0x56, 0xE0, 0xFF, 0x64, 0xFE, 0x70, 0x02, 0xA1, 0xAC, 0xEF, 0x64, 0x02, 0x60, 0x07, +0xEF, 0x64, 0x03, 0x60, 0x02, 0xA1, 0xAC, 0x90, 0x81, 0xB6, 0xE0, 0xFE, 0xA3, 0xE0, 0xFD, 0xED, +0xFF, 0x90, 0x82, 0x82, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x7E, 0x00, 0x7F, 0x20, 0x7D, 0x00, 0x7B, +0x01, 0x7A, 0x82, 0x79, 0x5E, 0x12, 0x46, 0x10, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0xB8, 0x90, 0x86, +0x67, 0x12, 0x43, 0x8F, 0x7A, 0x82, 0x79, 0x5E, 0x90, 0x86, 0x6A, 0x12, 0x43, 0x8F, 0x7A, 0x81, +0x79, 0x1D, 0x7D, 0x03, 0x12, 0x02, 0x00, 0x75, 0x13, 0x01, 0x75, 0x14, 0x82, 0x75, 0x15, 0x66, +0x75, 0x16, 0x10, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x47, 0x12, 0x2B, 0xED, 0x90, 0x82, 0x64, 0xE0, +0xFF, 0x54, 0x03, 0x90, 0x82, 0x84, 0xF0, 0x70, 0x02, 0x04, 0xF0, 0xEF, 0x54, 0x04, 0x90, 0x82, +0x85, 0xF0, 0x90, 0x82, 0x84, 0xE0, 0xFF, 0x90, 0x82, 0x57, 0xF0, 0x90, 0x82, 0x7F, 0xE0, 0x2F, +0xFE, 0x90, 0x82, 0x7E, 0xE0, 0x34, 0x00, 0x90, 0x82, 0x80, 0xF0, 0xA3, 0xCE, 0xF0, 0x7E, 0x00, +0x7F, 0x06, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x58, 0x12, 0x46, 0x10, 0x90, 0x82, 0x57, +0xE0, 0xFF, 0x90, 0x82, 0x80, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x7B, 0x01, 0x7A, 0x82, 0x79, 0x47, +0x90, 0x82, 0x8C, 0x12, 0x43, 0x8F, 0x7A, 0x82, 0x79, 0x58, 0xB1, 0xB1, 0xD0, 0xD0, 0x92, 0xAF, +0x22, 0x90, 0x82, 0x86, 0xEF, 0xF0, 0xA3, 0xEC, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0x12, 0x43, 0x8F, +0x90, 0x82, 0x8C, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, 0x90, 0x06, 0x74, 0xF0, 0x90, 0x00, 0x01, +0x12, 0x1F, 0xBD, 0x90, 0x06, 0x75, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x76, +0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x77, 0xF0, 0x90, 0x82, 0x86, 0xE0, 0x75, +0xF0, 0x08, 0xA4, 0x24, 0x02, 0x90, 0x06, 0x70, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x04, 0xF0, 0xA3, +0x74, 0x80, 0xF0, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x82, 0x8C, 0x12, 0x43, 0x86, +0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x74, 0xF0, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, +0x90, 0x06, 0x75, 0xF0, 0x90, 0x00, 0x06, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x76, 0xF0, 0x90, 0x00, +0x07, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x77, 0xF0, 0x90, 0x82, 0x86, 0xE0, 0x75, 0xF0, 0x08, 0xA4, +0x24, 0x03, 0x90, 0x06, 0x70, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x04, 0xF0, 0xA3, 0x74, 0x80, 0xF0, +0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x82, 0x8C, 0x12, 0x43, 0x86, 0x90, 0x00, 0x08, +0x12, 0x1F, 0xBD, 0x90, 0x06, 0x74, 0xF0, 0x90, 0x00, 0x09, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x75, +0xF0, 0x90, 0x00, 0x0A, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x76, 0xF0, 0x90, 0x00, 0x0B, 0x12, 0x1F, +0xBD, 0x90, 0x06, 0x77, 0xF0, 0x90, 0x82, 0x86, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x04, 0x90, +0x06, 0x70, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x04, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x7F, 0x01, 0x7E, +0x00, 0x12, 0x32, 0xAA, 0x90, 0x82, 0x8C, 0x12, 0x43, 0x86, 0x90, 0x00, 0x0C, 0x12, 0x1F, 0xBD, +0x90, 0x06, 0x74, 0xF0, 0x90, 0x00, 0x0D, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x75, 0xF0, 0x90, 0x00, +0x0E, 0x12, 0x1F, 0xBD, 0x90, 0x06, 0x76, 0xF0, 0x90, 0x00, 0x0F, 0x12, 0x1F, 0xBD, 0x90, 0x06, +0x77, 0xF0, 0x90, 0x82, 0x86, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x05, 0x90, 0x06, 0x70, 0xF0, +0xA3, 0xE4, 0xF0, 0xA3, 0x04, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, +0xAA, 0x90, 0x82, 0x86, 0xE0, 0xFF, 0x44, 0x10, 0x90, 0x06, 0x74, 0xF0, 0xA3, 0x74, 0x80, 0xF0, +0xA3, 0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xEF, 0x75, 0xF0, 0x08, 0xA4, 0x90, 0x06, 0x70, 0xF0, 0xA3, +0xE4, 0xF0, 0xA3, 0x04, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, +0x90, 0x06, 0x74, 0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x82, 0x86, 0xE0, +0x75, 0xF0, 0x08, 0xA4, 0x04, 0x90, 0x06, 0x70, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x04, 0xF0, 0xA3, +0x74, 0x80, 0xF0, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x32, 0xAA, 0x90, 0x06, 0x72, 0xE4, 0xF0, 0x22, +0x90, 0x83, 0x8A, 0x12, 0x43, 0x8F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFD, 0x70, 0x04, 0xFE, +0x7F, 0x01, 0x22, 0xED, 0xC3, 0x94, 0x06, 0x40, 0x69, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, 0xE9, +0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, 0x01, 0x7A, 0x83, 0x79, 0x4C, +0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x48, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, +0x90, 0x00, 0x06, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x70, 0x38, 0x90, 0x00, 0x07, 0x12, 0x1F, 0xBD, +0x70, 0x30, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, +0x90, 0x12, 0x43, 0x86, 0x12, 0x43, 0x98, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, +0x12, 0x1F, 0xBD, 0x24, 0x02, 0xFF, 0x90, 0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0x02, +0x78, 0xB6, 0x90, 0x83, 0x8D, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, +0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x05, 0xF9, 0xE4, 0x3A, 0xFA, 0xC3, 0xD0, 0x82, 0xD0, 0x83, +0xD0, 0xE0, 0xE9, 0x95, 0x82, 0xEA, 0x95, 0x83, 0x50, 0x53, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, +0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xC3, 0x94, 0x14, 0x40, 0x42, 0x90, 0x83, 0x8A, 0x12, 0x43, +0x86, 0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, 0x01, 0x7A, 0x83, +0x79, 0x58, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x21, 0x90, 0x83, 0x8A, 0x12, +0x43, 0x86, 0xE9, 0x24, 0x06, 0xF9, 0xE4, 0x3A, 0xFA, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, +0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x08, 0x12, 0x43, 0xE7, 0x21, 0x2B, 0x90, 0x83, 0x8A, +0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xD3, 0x94, 0x06, 0x40, 0x5E, 0x90, 0x83, +0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, +0x01, 0x7A, 0x83, 0x79, 0x50, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x3D, 0x90, +0x83, 0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x06, 0xF9, 0xE4, 0x3A, 0xFA, 0xC0, 0x03, 0xC0, 0x02, +0xC0, 0x01, 0x90, 0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x0B, 0x12, 0x43, 0xE7, 0x90, 0x83, +0x8A, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0xFC, 0xFF, 0x90, 0x83, 0x90, +0x12, 0x43, 0x86, 0x90, 0x00, 0x0E, 0xEF, 0x12, 0x1F, 0xFC, 0x80, 0x6F, 0x90, 0x83, 0x8A, 0x12, +0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xD3, 0x94, 0x06, 0x40, 0x5E, 0x90, 0x83, 0x8A, +0x12, 0x43, 0x86, 0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, 0x01, +0x7A, 0x83, 0x79, 0x54, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x3D, 0x90, 0x83, +0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x06, 0xF9, 0xE4, 0x3A, 0xFA, 0xC0, 0x03, 0xC0, 0x02, 0xC0, +0x01, 0x90, 0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x0F, 0x12, 0x43, 0xE7, 0x90, 0x83, 0x8A, +0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0xFC, 0xFF, 0x90, 0x83, 0x90, 0x12, +0x43, 0x86, 0x90, 0x00, 0x12, 0xEF, 0x12, 0x1F, 0xFC, 0x80, 0x00, 0xE4, 0xFE, 0xFF, 0x22, 0x90, +0x83, 0x3D, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x3A, 0x12, 0x43, 0x8F, 0xE4, 0x90, 0x83, 0x4A, 0xF0, +0xA3, 0xF0, 0x90, 0x83, 0x44, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x3D, 0x12, 0x43, 0x6E, 0xE9, 0x2F, +0xF9, 0xEA, 0x3E, 0xFA, 0xEB, 0x3D, 0xFB, 0x90, 0x83, 0x47, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x47, +0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0xE9, +0x24, 0x01, 0xF9, 0xE4, 0x3A, 0xFA, 0xC3, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xE0, 0xE9, 0x95, 0x82, +0xEA, 0x95, 0x83, 0x40, 0x02, 0x41, 0xA7, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, +0xB4, 0xDD, 0x4E, 0x90, 0x83, 0x3D, 0x12, 0x43, 0x6E, 0x90, 0x83, 0x3A, 0x12, 0x43, 0x86, 0xE9, +0x2F, 0xF9, 0xEA, 0x3E, 0xFA, 0xEB, 0x3D, 0xFB, 0xE9, 0x24, 0xFF, 0xF9, 0xEA, 0x34, 0xFF, 0xFA, +0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0xD0, 0x82, 0xD0, 0x83, +0xD0, 0xE0, 0x6B, 0x70, 0x08, 0xE9, 0x65, 0x82, 0x70, 0x03, 0xEA, 0x65, 0x83, 0x70, 0x02, 0x41, +0xA7, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x70, 0x02, 0x41, +0xA7, 0x90, 0x83, 0x47, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, 0x44, +0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x7E, 0x00, 0xE9, 0x24, 0x02, 0xF9, +0xE4, 0x3A, 0xFA, 0xE9, 0x2F, 0xF9, 0xEE, 0x3A, 0xFA, 0xD3, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xE0, +0xE9, 0x95, 0x82, 0xEA, 0x95, 0x83, 0x40, 0x02, 0x41, 0xA7, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, +0x12, 0x1F, 0xA4, 0xFF, 0xB4, 0x30, 0x36, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, +0x02, 0xC0, 0x01, 0x90, 0x83, 0x41, 0x12, 0x43, 0x86, 0x90, 0x00, 0x04, 0x12, 0x43, 0xE7, 0x90, +0x83, 0x44, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xFE, 0x90, 0x83, +0x41, 0x12, 0x43, 0x86, 0x90, 0x00, 0x07, 0xEE, 0x12, 0x1F, 0xFC, 0x80, 0x2F, 0xEF, 0xB4, 0xDD, +0x2B, 0x90, 0x83, 0x47, 0x12, 0x43, 0x86, 0x90, 0x83, 0x8D, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x41, +0x12, 0x43, 0x86, 0x90, 0x83, 0x90, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0x12, +0x77, 0x50, 0x90, 0x83, 0x4A, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x80, 0x1B, 0x90, 0x83, 0x44, 0x12, +0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xFF, 0xE4, 0x33, 0x90, 0x83, 0x45, +0x8F, 0xF0, 0x12, 0x43, 0x4B, 0x21, 0x5D, 0x90, 0x83, 0x4A, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, +0x90, 0x82, 0xEE, 0x12, 0x43, 0x8F, 0x90, 0x82, 0xF4, 0xE0, 0x60, 0x02, 0x61, 0x84, 0x90, 0x82, +0xF1, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, 0xF4, 0x60, 0x02, 0x61, 0x79, 0x12, 0x1F, 0xEA, 0x90, +0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xF4, 0x60, 0x02, 0x61, 0x69, +0x90, 0x00, 0x01, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xF4, 0x70, 0x6F, 0x90, +0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x03, 0x12, +0x1F, 0xBD, 0xF4, 0x70, 0x4E, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0xE4, 0x12, +0x1F, 0xFC, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xF4, 0x70, 0x2D, 0x90, 0x82, 0xF1, 0x12, 0x43, +0x86, 0x90, 0x00, 0x04, 0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0x90, 0x82, +0xF1, 0xB4, 0xFF, 0x0C, 0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0xE4, 0x12, 0x1F, 0xFC, 0x80, 0x44, +0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0x80, 0x2A, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, +0x04, 0x80, 0x1F, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0x80, 0x14, 0x90, 0x82, +0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0x80, 0x09, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, +0x00, 0x01, 0x74, 0x01, 0x12, 0x43, 0x18, 0x80, 0x0B, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x74, +0x01, 0x12, 0x42, 0xF6, 0x90, 0x82, 0xF5, 0xE0, 0xFF, 0x64, 0x04, 0x60, 0x02, 0x81, 0x33, 0x90, +0x82, 0xF1, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0xEE, +0x12, 0x1F, 0xEA, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFE, +0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x02, +0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x03, 0x74, 0x20, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, +0x43, 0x86, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, +0x00, 0x04, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0x12, +0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0xEE, 0x12, 0x1F, 0xFC, +0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, +0x12, 0x43, 0x86, 0x90, 0x00, 0x06, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, +0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x07, +0xEE, 0x81, 0xF3, 0xEF, 0x64, 0x02, 0x60, 0x02, 0x81, 0xF6, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, +0x12, 0x1F, 0xA4, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0xEF, 0x12, 0x1F, 0xEA, 0x90, 0x82, +0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x44, 0x20, 0x54, 0x7F, 0xFF, 0x90, +0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, +0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, +0x00, 0x02, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x03, 0x74, 0x20, 0x12, 0x1F, 0xFC, 0x90, 0x82, +0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, +0x86, 0x90, 0x00, 0x04, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, +0x03, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0xEF, 0x12, +0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0x90, +0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x06, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, +0x43, 0x86, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, +0x00, 0x07, 0xEF, 0x12, 0x1F, 0xFC, 0x22, 0x90, 0x82, 0xF1, 0xED, 0xF0, 0x90, 0x82, 0xEE, 0x12, +0x43, 0x8F, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0xF5, 0xF0, 0x90, 0x82, 0xEE, 0x12, +0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x03, 0x7B, 0x01, 0x7A, 0x82, 0x79, +0xF2, 0x12, 0x2B, 0xED, 0x90, 0x82, 0xF1, 0xE0, 0x70, 0x46, 0xFF, 0x74, 0xF2, 0x2F, 0xF5, 0x82, +0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0xB4, 0xFF, 0x0E, 0x74, 0xF2, 0x2F, 0xF5, 0x82, 0xE4, 0x34, +0x82, 0xF5, 0x83, 0xE4, 0xF0, 0x80, 0x0F, 0x74, 0xF2, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5, +0x83, 0xE0, 0x04, 0xF0, 0x80, 0x05, 0x0F, 0xEF, 0xB4, 0x03, 0xD0, 0x75, 0x13, 0x01, 0x75, 0x14, +0x82, 0x75, 0x15, 0xF2, 0x75, 0x16, 0x03, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x12, 0x2B, 0xED, +0x22, 0x00, 0x39, 0xD4, +}; +#if 0 +u4Byte ArrayLength_8188E_FW_WoWLAN = 15764; + + +void +ODM_ReadFirmware_8188E_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ + ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_WoWLAN, ArrayLength_8188E_FW_WoWLAN); + *pFirmwareSize = ArrayLength_8188E_FW_WoWLAN; +} + +#endif + +#endif // end of DM_ODM_SUPPORT_TYPE & (ODM_AP) + + +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h new file mode 100755 index 00000000..43f6ac07 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_FW_8188E_HW_IMG_H +#define __INC_FW_8188E_HW_IMG_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) +void +ODM_ReadFirmware_8188E_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#else +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ +#if 0 +void +ODM_ReadFirmware_8188E_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); +#endif +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ +#if 0 +void +ODM_ReadFirmware_8188E_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); +#endif +#define ArrayLength_8188E_FW_WoWLAN 15764 +extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN]; +#endif + +#endif +#endif // end of HWIMG_SUPPORT diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c new file mode 100755 index 00000000..ff800f98 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c @@ -0,0 +1,329 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "../odm_precomp.h" +#ifdef CONFIG_IOL_IOREG_CFG +#include +#endif +#if (RTL8188E_SUPPORT == 1) +static BOOLEAN +CheckCondition( + const u4Byte Condition, + const u4Byte Hex + ) +{ + u4Byte _board = (Hex & 0x000000FF); + u4Byte _interface = (Hex & 0x0000FF00) >> 8; + u4Byte _platform = (Hex & 0x00FF0000) >> 16; + u4Byte cond = Condition; + + if ( Condition == 0xCDCDCDCD ) + return TRUE; + + cond = Condition & 0x000000FF; + if ( (_board == cond) && cond != 0x00) + return FALSE; + + cond = Condition & 0x0000FF00; + cond = cond >> 8; + if ( (_interface & cond) == 0 && cond != 0x07) + return FALSE; + + cond = Condition & 0x00FF0000; + cond = cond >> 16; + if ( (_platform & cond) == 0 && cond != 0x0F) + return FALSE; + return TRUE; +} + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MAC_REG_8188E[] = { + 0x026, 0x00000041, + 0x027, 0x00000035, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000001, + 0x432, 0x00000002, + 0x433, 0x00000004, + 0x434, 0x00000005, + 0x435, 0x00000006, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x438, 0x00000000, + 0x439, 0x00000000, + 0x43A, 0x00000001, + 0x43B, 0x00000002, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000006, + 0x43F, 0x00000007, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000015, + 0x445, 0x000000F0, + 0x446, 0x0000000F, + 0x447, 0x00000000, + 0x458, 0x00000041, + 0x459, 0x000000A8, + 0x45A, 0x00000072, + 0x45B, 0x000000B9, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x480, 0x00000008, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4D3, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x652, 0x00000020, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, +}; + +HAL_STATUS +ODM_ReadAndConfig_MAC_REG_8188E( + IN PDM_ODM_T pDM_Odm + ) +{ + #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) + + u4Byte hex = 0; + u4Byte i = 0; + u2Byte count = 0; + pu4Byte ptr_array = NULL; + u1Byte platform = pDM_Odm->SupportPlatform; + u1Byte interfaceValue = pDM_Odm->SupportInterface; + u1Byte board = pDM_Odm->BoardType; + u4Byte ArrayLen = sizeof(Array_MAC_REG_8188E)/sizeof(u4Byte); + pu4Byte Array = Array_MAC_REG_8188E; + BOOLEAN biol = FALSE; + +#ifdef CONFIG_IOL_IOREG_CFG + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pxmit_frame; + u8 bndy_cnt = 1; + #ifdef CONFIG_IOL_IOREG_CFG_DBG + struct cmd_cmp cmpdata[ArrayLen]; + u4Byte cmpdata_idx=0; + #endif +#endif //CONFIG_IOL_IOREG_CFG + HAL_STATUS rst =HAL_STATUS_SUCCESS; + hex += board; + hex += interfaceValue << 8; + hex += platform << 16; + hex += 0xFF000000; + +#ifdef CONFIG_IOL_IOREG_CFG + biol = rtw_IOL_applied(Adapter); + + if(biol){ + if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) + { + printk("rtw_IOL_accquire_xmit_frame failed\n"); + return HAL_STATUS_FAILURE; + } + } + +#endif //CONFIG_IOL_IOREG_CFG + + for (i = 0; i < ArrayLen; i += 2 ) + { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + + // This (offset, data) pair meets the condition. + if ( v1 < 0xCDCDCDCD ) + { + #ifdef CONFIG_IOL_IOREG_CFG + + if(biol){ + + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + cmpdata[cmpdata_idx].addr = v1; + cmpdata[cmpdata_idx].value= v2; + cmpdata_idx++; + #endif + } + else + #endif //endif CONFIG_IOL_IOREG_CFG + { + odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); + } + continue; + } + else + { // This line is the start line of branch. + if ( !CheckCondition(Array[i], hex) ) + { // Discard the following (offset, data) pairs. + READ_NEXT_PAIR(v1, v2, i); + while ( v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + i -= 2; // prevent from for-loop += 2 + } + else // Configure matched pairs and skip to end of if-else. + { + READ_NEXT_PAIR(v1, v2, i); + while ( v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + cmpdata[cmpdata_idx].addr = v1; + cmpdata[cmpdata_idx].value= v2; + cmpdata_idx++; + #endif + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); + } + + READ_NEXT_PAIR(v1, v2, i); + } + + while (v2 != 0xDEAD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + + } + } + } + +#ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + + if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) + { + #ifdef CONFIG_IOL_IOREG_CFG_DBG + printk("~~~ IOL Config MAC Success !!! \n"); + //compare writed data + { + u4Byte idx; + u1Byte cdata; + // HAL_STATUS_FAILURE; + printk(" MAC data compare => array_len:%d \n",cmpdata_idx); + for(idx=0;idx< cmpdata_idx;idx++) + { + cdata = ODM_Read1Byte(pDM_Odm, cmpdata[idx].addr); + if(cdata != cmpdata[idx].value){ + printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n", + cmpdata[idx].addr,cmpdata[idx].value,cdata); + //rst = HAL_STATUS_FAILURE; + } + } + + + //dump data from TX packet buffer + //if(rst == HAL_STATUS_FAILURE) + { + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + + } + else{ + printk("~~~ MAC IOL_exec_cmds Failed !!! \n"); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + { + //dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + rst = HAL_STATUS_FAILURE; + } + + } +#endif //#ifdef CONFIG_IOL_IOREG_CFG + return rst; +} + +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h new file mode 100755 index 00000000..e6f9cf7c --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h @@ -0,0 +1,38 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MAC_8188E_HW_IMG_H +#define __INC_MAC_8188E_HW_IMG_H + +//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex); + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +HAL_STATUS +ODM_ReadAndConfig_MAC_REG_8188E( + IN PDM_ODM_T pDM_Odm +); + +#endif +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c new file mode 100755 index 00000000..fbe04d9f --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c @@ -0,0 +1,377 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "../odm_precomp.h" + +#ifdef CONFIG_IOL_IOREG_CFG +#include +#endif + +#if (RTL8188E_SUPPORT == 1) +static BOOLEAN +CheckCondition( + const u4Byte Condition, + const u4Byte Hex + ) +{ + u4Byte _board = (Hex & 0x000000FF); + u4Byte _interface = (Hex & 0x0000FF00) >> 8; + u4Byte _platform = (Hex & 0x00FF0000) >> 16; + u4Byte cond = Condition; + + if ( Condition == 0xCDCDCDCD ) + return TRUE; + + cond = Condition & 0x000000FF; + if ( (_board == cond) && cond != 0x00) + return FALSE; + + cond = Condition & 0x0000FF00; + cond = cond >> 8; + if ( (_interface & cond) == 0 && cond != 0x07) + return FALSE; + + cond = Condition & 0x00FF0000; + cond = cond >> 16; + if ( (_platform & cond) == 0 && cond != 0x0F) + return FALSE; + return TRUE; +} + + +/****************************************************************************** +* RadioA_1T.TXT +******************************************************************************/ + +u4Byte Array_RadioA_1T_8188E[] = { + 0x000, 0x00030000, + 0x008, 0x00084000, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF8FC, + 0x0B1, 0x00054400, + 0x0B2, 0x000CCC19, + 0x0B4, 0x00043003, + 0x0B6, 0x0004953E, + 0x0B7, 0x0001C718, + 0x0B8, 0x000060FF, + 0x0B9, 0x00080001, + 0x0BA, 0x00040000, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x00088820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x0006B27D, + 0xFF0F041F, 0xABCD, + 0x052, 0x0007E4DD, + 0xCDCDCDCD, 0xCDCD, + 0x052, 0x0007E49D, + 0xFF0F041F, 0xDEAD, + 0x053, 0x00000073, + 0x056, 0x00051FF3, + 0x035, 0x00000086, + 0x035, 0x00000186, + 0x035, 0x00000286, + 0x036, 0x00001C25, + 0x036, 0x00009C25, + 0x036, 0x00011C25, + 0x036, 0x00019C25, + 0x0B6, 0x00048538, + 0x018, 0x00000C07, + 0x05A, 0x0004BD00, + 0x019, 0x000739D0, + 0x034, 0x0000ADF3, + 0x034, 0x00009DF0, + 0x034, 0x00008DED, + 0x034, 0x00007DEA, + 0x034, 0x00006DE7, + 0x034, 0x000054EE, + 0x034, 0x000044EB, + 0x034, 0x000034E8, + 0x034, 0x0000246B, + 0x034, 0x00001468, + 0x034, 0x0000006D, + 0x000, 0x00030159, + 0x084, 0x00068200, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x000, 0x00010159, + 0x018, 0x0000F407, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E60, +}; + +HAL_STATUS +ODM_ReadAndConfig_RadioA_1T_8188E( + IN PDM_ODM_T pDM_Odm + ) +{ + #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) + + u4Byte hex = 0; + u4Byte i = 0; + u2Byte count = 0; + pu4Byte ptr_array = NULL; + u1Byte platform = pDM_Odm->SupportPlatform; + u1Byte interfaceValue = pDM_Odm->SupportInterface; + u1Byte board = pDM_Odm->BoardType; + u4Byte ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u4Byte); + pu4Byte Array = Array_RadioA_1T_8188E; + BOOLEAN biol = FALSE; +#ifdef CONFIG_IOL_IOREG_CFG + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pxmit_frame; + u8 bndy_cnt = 1; + #ifdef CONFIG_IOL_IOREG_CFG_DBG + struct cmd_cmp cmpdata[ArrayLen]; + u4Byte cmpdata_idx=0; + #endif +#endif//#ifdef CONFIG_IOL_IOREG_CFG + HAL_STATUS rst =HAL_STATUS_SUCCESS; + + hex += board; + hex += interfaceValue << 8; + hex += platform << 16; + hex += 0xFF000000; +#ifdef CONFIG_IOL_IOREG_CFG + biol = rtw_IOL_applied(Adapter); + + if(biol){ + if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) + { + printk("rtw_IOL_accquire_xmit_frame failed\n"); + return HAL_STATUS_FAILURE; + } + } +#endif//#ifdef CONFIG_IOL_IOREG_CFG + + for (i = 0; i < ArrayLen; i += 2 ) + { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + + // This (offset, data) pair meets the condition. + if ( v1 < 0xCDCDCDCD ) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + + if(v1 == 0xffe) + { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); + } + else if (v1 == 0xfd){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); + } + else if (v1 == 0xfc){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); + } + else if (v1 == 0xfb){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); + } + else if (v1 == 0xfa){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); + } + else if (v1 == 0xf9){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); + } + else{ + rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ; + #ifdef CONFIG_IOL_IOREG_CFG_DBG + cmpdata[cmpdata_idx].addr = v1; + cmpdata[cmpdata_idx].value= v2; + cmpdata_idx++; + #endif + } + + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); + } + continue; + } + else + { // This line is the start line of branch. + if ( !CheckCondition(Array[i], hex) ) + { // Discard the following (offset, data) pairs. + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + i -= 2; // prevent from for-loop += 2 + } + else // Configure matched pairs and skip to end of if-else. + { + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen -2) + { + #ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + + if(v1 == 0xffe) + { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); + } + else if (v1 == 0xfd){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); + } + else if (v1 == 0xfc){ + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); + } + else if (v1 == 0xfb){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); + } + else if (v1 == 0xfa){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); + } + else if (v1 == 0xf9){ + rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); + } + else{ + rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ; + #ifdef CONFIG_IOL_IOREG_CFG_DBG + cmpdata[cmpdata_idx].addr = v1; + cmpdata[cmpdata_idx].value= v2; + cmpdata_idx++; + #endif + + } + + } + else + #endif //#ifdef CONFIG_IOL_IOREG_CFG + { + odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); + } + READ_NEXT_PAIR(v1, v2, i); + } + + while (v2 != 0xDEAD && i < ArrayLen -2) + { + READ_NEXT_PAIR(v1, v2, i); + } + + } + } + } +#ifdef CONFIG_IOL_IOREG_CFG + if(biol){ + //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) + { + #ifdef CONFIG_IOL_IOREG_CFG_DBG + printk("~~~ %s Success !!! \n",__FUNCTION__); + { + u4Byte idx; + u4Byte cdata; + printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx); + printk("### %s data compared !!###\n",__FUNCTION__); + for(idx=0;idx< cmpdata_idx;idx++) + { + cdata = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A,cmpdata[idx].addr,bRFRegOffsetMask); + if(cdata != cmpdata[idx].value){ + printk("addr:0x%04x, data:(0x%02x : 0x%02x) \n", + cmpdata[idx].addr,cmpdata[idx].value,cdata); + rst = HAL_STATUS_FAILURE; + } + } + printk("### %s data compared !!###\n",__FUNCTION__); + //if(rst == HAL_STATUS_FAILURE) + {//dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + + } + else{ + rst = HAL_STATUS_FAILURE; + printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); + #ifdef CONFIG_IOL_IOREG_CFG_DBG + { + //dump data from TX packet buffer + rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); + } + #endif //CONFIG_IOL_IOREG_CFG_DBG + } + } + + +#endif //#ifdef CONFIG_IOL_IOREG_CFG + return rst; +} + +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h new file mode 100755 index 00000000..93ea0610 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h @@ -0,0 +1,38 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_RF_8188E_HW_IMG_H +#define __INC_RF_8188E_HW_IMG_H + +//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex); + +/****************************************************************************** +* RadioA_1T.TXT +******************************************************************************/ + +HAL_STATUS +ODM_ReadAndConfig_RadioA_1T_8188E( + IN PDM_ODM_T pDM_Odm +); + +#endif +#endif // end of HWIMG_SUPPORT + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c new file mode 100755 index 00000000..d3e858ab --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c @@ -0,0 +1,3500 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "../odm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_88E 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ +/*----------------------------------------------------------------------------- + * Function: ODM_TxPwrTrackAdjust88E() + * + * Overview: 88E we can not write 0xc80/c94/c4c/ 0xa2x. Instead of write TX agc. + * No matter OFDM & CCK use the same method. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * 04/23/2012 MHC Adjust TX agc directly not throughput BB digital. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackAdjust88E( + PDM_ODM_T pDM_Odm, + u1Byte Type, // 0 = OFDM, 1 = CCK + pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease) + pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust + ) +{ + u1Byte pwr_value = 0; + // + // Tx power tracking BB swing table. + // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB + // + if (Type == 0) // For OFDM afjust + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm)); + + if (pDM_Odm->BbSwingIdxOfdm <= pDM_Odm->BbSwingIdxOfdmBase) + { + *pDirection = 1; + pwr_value = (pDM_Odm->BbSwingIdxOfdmBase - pDM_Odm->BbSwingIdxOfdm); + } + else + { + *pDirection = 2; + pwr_value = (pDM_Odm->BbSwingIdxOfdm - pDM_Odm->BbSwingIdxOfdmBase); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm)); + + } + else if (Type == 1) // For CCK adjust. + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase)); + + if (pDM_Odm->BbSwingIdxCck <= pDM_Odm->BbSwingIdxCckBase) + { + *pDirection = 1; + pwr_value = (pDM_Odm->BbSwingIdxCckBase - pDM_Odm->BbSwingIdxCck); + } + else + { + *pDirection = 2; + pwr_value = (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); + } + } + + // + // 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking + // need to be less than 6 power index for 88E. + // + if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1) + pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E; + + *pOutWriteVal = pwr_value | (pwr_value<<8) | (pwr_value<<16) | (pwr_value<<24); + +} // ODM_TxPwrTrackAdjust88E + + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +odm_TxPwrTrackSetPwr88E( + PDM_ODM_T pDM_Odm + ) +{ + if (pDM_Odm->BbSwingFlagOfdm == TRUE || pDM_Odm->BbSwingFlagCck == TRUE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE )) + PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *(pDM_Odm->pChannel)); +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); +#endif + pDM_Odm->BbSwingFlagOfdm = FALSE; + pDM_Odm->BbSwingFlagCck = FALSE; + } +} // odm_TxPwrTrackSetPwr88E + + +//091212 chiyokolin +VOID +odm_TXPowerTrackingCallback_ThermalMeter_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ) +{ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; +#endif + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0; + s4Byte ele_A=0, ele_D, TempCCk, X, value32; + s4Byte Y, ele_C=0; + s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; + u4Byte i = 0, j = 0; + BOOLEAN is2T = FALSE; + BOOLEAN bInteralPA = FALSE; + + u1Byte OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/; + s1Byte OFDM_index_mapping[2][index_mapping_NUM_88E] = { + {0, 0, 2, 3, 4, 4, //2.4G, decrease power + 5, 6, 7, 7, 8, 9, + 10, 10, 11}, // For lower temperature, 20120220 updated on 20120220. + {0, 0, -1, -2, -3, -4, //2.4G, increase power + -4, -4, -4, -5, -7, -8, + -9, -9, -10}, + }; + u1Byte Thermal_mapping[2][index_mapping_NUM_88E] = { + {0, 2, 4, 6, 8, 10, //2.4G, decrease power + 12, 14, 16, 18, 20, 22, + 24, 26, 27}, + {0, 2, 4, 6, 8, 10, //2.4G,, increase power + 12, 14, 16, 18, 20, 22, + 25, 25, 25}, + }; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + odm_TxPwrTrackSetPwr88E(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. +#endif + + // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. + pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)); + + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); //0x42: RF Reg[15:10] 88E + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, pHalData->EEPROMThermalMeter)); + + if(is2T) + rf = 2; + else + rf = 1; + + if(ThermalValue) + { +// if(!pHalData->ThermalValue) + { + //Query OFDM path A default setting + ele_D = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for(i=0; iBbSwingIdxOfdmBase = (u1Byte)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial pathA ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n", + rOFDM0_XATxIQImbalance, ele_D, OFDM_index_old[0])); + break; + } + } + + //Query OFDM path B default setting + if(is2T) + { + ele_D = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for(i=0; ipriv); +#else + { + //Query CCK default setting From 0xa24 + TempCCk = pDM_Odm->RFCalibrateInfo.RegA24; + + for(i=0 ; iRFCalibrateInfo.bCCKinCH14) + { + if(ODM_CompareMemory(pDM_Odm,(void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==0) + { + CCK_index_old =(u1Byte) i; + pDM_Odm->BbSwingIdxCckBase = (u1Byte)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", + rCCK0_TxFilter2, TempCCk, CCK_index_old, pDM_Odm->RFCalibrateInfo.bCCKinCH14)); + break; + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("RegA24: 0x%X, CCKSwingTable_Ch1_Ch13[%d][2]: CCKSwingTable_Ch1_Ch13[i][2]: 0x%X\n", TempCCk, i, CCKSwingTable_Ch1_Ch13[i][2])); + if(ODM_CompareMemory(pDM_Odm,(void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==0) + { + CCK_index_old =(u1Byte) i; + pDM_Odm->BbSwingIdxCckBase = (u1Byte)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", + rCCK0_TxFilter2, TempCCk, CCK_index_old, pDM_Odm->RFCalibrateInfo.bCCKinCH14)); + break; + } + } + } + } +#endif + + if(!pDM_Odm->RFCalibrateInfo.ThermalValue) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter; +#else + pDM_Odm->RFCalibrateInfo.ThermalValue = pDM_Odm->priv->pmib->dot11RFEntry.ther; +#endif + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + + for(i = 0; i < rf; i++) + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_index_old[i]; + pDM_Odm->RFCalibrateInfo.CCK_index = CCK_index_old; + } + + if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + } + + //calculate average thermal meter + { + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for(i = 0; i < AVG_THERMAL_NUM_88E; i++) + { + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) + { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); + } + } + } + + if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex = FALSE; + pDM_Odm->RFCalibrateInfo.bDoneTxpower = FALSE; + } + else if(pDM_Odm->RFCalibrateInfo.bDoneTxpower) + { + delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); + } + else + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - (pDM_Odm->priv->pmib->dot11RFEntry.ther)):((pDM_Odm->priv->pmib->dot11RFEntry.ther) - ThermalValue); +#endif + } + delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x delta_LCK 0x%x delta_IQK 0x%x \n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, pHalData->EEPROMThermalMeter, delta, delta_LCK, delta_IQK)); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x delta_LCK 0x%x delta_IQK 0x%x \n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, pDM_Odm->priv->pmib->dot11RFEntry.ther, delta, delta_LCK, delta_IQK)); +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("pre thermal meter LCK 0x%x pre thermal meter IQK 0x%x delta_LCK_bound 0x%x delta_IQK_bound 0x%x\n", pDM_Odm->RFCalibrateInfo.ThermalValue_LCK, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK, pDM_Odm->RFCalibrateInfo.Delta_LCK, pDM_Odm->RFCalibrateInfo.Delta_IQK)); + + + + //if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) + if ((delta_LCK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. + { + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_LCCalibrate_8188E(Adapter); +#else + PHY_LCCalibrate_8188E(pDM_Odm); +#endif + } + + if(delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + //calculate new OFDM / CCK offset + { + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + j = 1; + else + j = 0; + + for(offset = 0; offset < index_mapping_NUM_88E; offset++) + { + if(delta < Thermal_mapping[j][offset]) + { + if(offset != 0) + offset--; + break; + } + } + if(offset >= index_mapping_NUM_88E) + offset = index_mapping_NUM_88E-1; + + index = OFDM_index_mapping[j][offset]; + + for(i = 0; i < rf; i++) + OFDM_index[i] = pDM_Odm->RFCalibrateInfo.OFDM_index[i] + OFDM_index_mapping[j][offset]; + CCK_index = pDM_Odm->RFCalibrateInfo.CCK_index + OFDM_index_mapping[j][offset]; + } + + if(is2T) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", + pDM_Odm->RFCalibrateInfo.OFDM_index[0], pDM_Odm->RFCalibrateInfo.OFDM_index[1], pDM_Odm->RFCalibrateInfo.CCK_index)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("temp OFDM_A_index=0x%x, CCK_index=0x%x\n", + pDM_Odm->RFCalibrateInfo.OFDM_index[0], pDM_Odm->RFCalibrateInfo.CCK_index)); + } + + for(i = 0; i < rf; i++) + { + if(OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) + { + OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; + } + else if (OFDM_index[i] < OFDM_min_index) + { + OFDM_index[i] = OFDM_min_index; + } + } + + { + if(CCK_index > CCK_TABLE_SIZE-1) + CCK_index = CCK_TABLE_SIZE-1; + else if (CCK_index < 0) + CCK_index = 0; + } + + if(is2T) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", + OFDM_index[0], OFDM_index[1], CCK_index)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("new OFDM_A_index=0x%x, CCK_index=0x%x\n", + OFDM_index[0], CCK_index)); + } + } + + //2 temporarily remove bNOPG + //Config by SwingTable + if(pDM_Odm->RFCalibrateInfo.TxPowerTrackControl /*&& !pHalData->bNOPG*/) + { + pDM_Odm->RFCalibrateInfo.bDoneTxpower = TRUE; + + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable[(u1Byte)OFDM_index[0]] & 0xFFC00000)>>22; + X = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][0]; + Y = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][1]; + + // + // Revse TX power table. + // + pDM_Odm->BbSwingIdxOfdm = (u1Byte)OFDM_index[0]; + pDM_Odm->BbSwingIdxCck = (u1Byte)CCK_index; + + //DbgPrint("pDM_Odm->BbSwingIdxOfdm = %d\n", pDM_Odm->BbSwingIdxOfdm); + + if (pDM_Odm->BbSwingIdxOfdmCurrent != pDM_Odm->BbSwingIdxOfdm) + { + pDM_Odm->BbSwingIdxOfdmCurrent = pDM_Odm->BbSwingIdxOfdm; + pDM_Odm->BbSwingFlagOfdm = TRUE; + } + + if (pDM_Odm->BbSwingIdxCckCurrent != pDM_Odm->BbSwingIdxCck) + { + pDM_Odm->BbSwingIdxCckCurrent = pDM_Odm->BbSwingIdxCck; + pDM_Odm->BbSwingFlagCck = TRUE; + } + + if(X != 0) + { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x000003FF; + + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // +#if 0 + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); +#endif + } + else + { +#if 0 + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[0]]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); +#endif + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking for path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xe94 = 0x%x 0xe9c = 0x%x\n", + (u4Byte)X, (u4Byte)Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)X, (u4Byte)Y)); + + { + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // +#if 0 + //Adjust CCK according to IQK result + if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){ + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][7]); + } + else{ + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14[(u1Byte)CCK_index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14[(u1Byte)CCK_index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14[(u1Byte)CCK_index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14[(u1Byte)CCK_index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14[(u1Byte)CCK_index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14[(u1Byte)CCK_index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14[(u1Byte)CCK_index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14[(u1Byte)CCK_index][7]); + } +#endif + } + + if(is2T) + { + ele_D = (OFDMSwingTable[(u1Byte)OFDM_index[1]] & 0xFFC00000)>>22; + + //new element A = element D x X + X = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][4]; + Y = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][5]; + + //if(X != 0 && pHalData->CurrentBandType92D == ODM_BAND_ON_2_4G) + if((X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + + { + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + } + else + { + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[1]]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)X, (u4Byte)Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)X, (u4Byte)Y)); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xc94, bMaskDWord), ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x24, bRFRegOffsetMask))); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) + if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. + { + ODM_ResetIQKResult(pDM_Odm); + +#if(DM_ODM_SUPPORT_TYPE & ODM_MP) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8188E(Adapter, FALSE); + +#if(DM_ODM_SUPPORT_TYPE & ODM_MP) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif + } +#endif + //update thermal meter value + if(pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { + //Adapter->HalFunc.SetHalDefVarHandler(Adapter, HAL_DEF_THERMAL_VALUE, &ThermalValue); + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; + } + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); + + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + +} + + + + + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + //1 Tx IQK + //path-A IQK setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + + return result; + + + } + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); + + //PA,PAD off + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + { + result |= 0x01; + } + else + { + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );//if Tx not OK, ignore Rx + return result; + } + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); + +#if 0 + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; + + + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); + regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); + regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +_PHY_PathAFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if !(DM_ODM_SUPPORT_TYPE & ODM_MP) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; + if(FALSE == is2T){ + pathOn = 0x0bdb25a0; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x0); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); +} + +VOID +_PHY_PIModeSwitch( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; + BOOLEAN is2T; + s4Byte tmp1 = 0,tmp2 = 0; + + if( (pDM_Odm->RFType ==ODM_2T2R )||(pDM_Odm->RFType ==ODM_2T3R )||(pDM_Odm->RFType ==ODM_2T4R )) + is2T = TRUE; + else + is2T = FALSE; + + if(is2T) + bound = 8; + else + bound = 4; + + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { +// diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if((i==1) || (i==3) || (i==5) || (i==7)) + { + if((result[c1][i]& 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if((result[c2][i]& 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } + else + { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte i; + u1Byte PathAOK, PathBOK; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD + }; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + u4Byte retryCount = 9; +#else + u4Byte retryCount = 2; +#endif +#endif +if ( *(pDM_Odm->mp_mode) == 1) + retryCount = 9; +else + retryCount = 2; + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#ifdef MP_TEST + if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if(t==0) + { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, TRUE); +#else + _PHY_PIModeSwitch(pDM_Odm, TRUE); +#endif + } + + //BB setting + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + + //Page B init + //AP or IQK + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } + + // IQ calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T); +#else + PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T); +#endif +// if(PathAOK == 0x03){ + if(PathAOK == 0x01){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } +#if 0 + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK(pAdapter, is2T); +#else + PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); +#endif + if(PathAOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + } + + if(0x00 == PathAOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + } + + if(is2T){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathAStandBy(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8188E(pAdapter); +#else + PathBOK = phy_PathB_IQK_8188E(pDM_Odm); +#endif + if(PathBOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); + + if(t!=0) + { + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, FALSE); +#else + _PHY_PIModeSwitch(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if(is2T){ + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); + +} + + +VOID +phy_LCCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_sleep_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +if ( *(pDM_Odm->mp_mode) == 1) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; +} +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +//#if MP_DRIVER != 1 +if (*(pDM_Odm->mp_mode) != 1) + return; +//#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + if(path == RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); + if(path == RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(!IS_HARDWARE_TYPE_8723A(pAdapter)) + ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + u1Byte channelToIQK = 7; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + BOOLEAN is2T; + + is2T = (pDM_Odm->RFType == ODM_2T2R)?TRUE:FALSE; +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if MP_DRIVER == 1 +if (*(pDM_Odm->mp_mode) == 1) +{ + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +} +#endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(bReCovery) +#else//for ODM_MP + if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + return; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + +#if 0//Suggested by Edlu,120413 + + // IQK on channel 7, should switch back when completed. + //originChannel = pHalData->CurrentChannel; + originChannel = *(pDM_Odm->pChannel); + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK); +#endif + +#endif + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + if((i==0) ||(i==2) || (i==4) || (i==6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter))); +// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n")); + for (i=0; i<3; i++) + { + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8188E(pAdapter, result, i, is2T); +#else + phy_IQCalibrate_8188E(pDM_Odm, result, i, is2T); +#endif + + + if(i == 1) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); +#endif + if(is12simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if(i == 2) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); +#endif + if(is13simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); +#endif + if(is23simular) + { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); + } + else + { + /* + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + */ + final_candidate = 3; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (is2T) + { + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + { + _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if(final_candidate < 4) + { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); +#if 0 //Suggested by Edlu,120413 + + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel); + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel); + #endif + +#endif + +} + + +VOID +PHY_LCCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + + + +#if MP_DRIVER == 1 +if (*(pDM_Odm->mp_mode) == 1) +{ + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +} +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(pDM_Odm->RFType == ODM_2T2R) + { + phy_LCCalibrate_8188E(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8188E(pAdapter, FALSE); +#else + phy_LCCalibrate_8188E(pDM_Odm, FALSE); +#endif + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(pDM_Odm->RFType == ODM_2T2R){ + phy_APCalibrate_8188E(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8188E(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); +#endif + } +} +VOID phy_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + if(!pAdapter->bHWInitReady) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pAdapter->hw_init_completed == _FALSE) + #endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + +#endif + + if(is2T) //92C + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + } + else //88C + { + + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux + } +} +VOID PHY_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(pDM_Odm->RFType == ODM_2T2R) + { + phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); +#else + phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); +#endif + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +//digital predistortion +VOID +phy_DigitalPredistortion( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if ( RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8188E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; + + if(pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(pDM_Odm->RFType == ODM_2T2R){ + phy_DigitalPredistortion(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + if(!pAdapter->bHWInitReady) + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if(is2T) // + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) + return TRUE; + else + return FALSE; + } + else + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9) == 0x02) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + +#if DISABLE_BB_RF + return TRUE; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + //if(IS_92C_SERIAL( pHalData->VersionID)){ + if(pDM_Odm->RFType == ODM_2T2R){ + return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); +#endif + } +} +#endif diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h new file mode 100755 index 00000000..6035ca50 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h @@ -0,0 +1,135 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8188E_H__ +#define __HAL_PHY_RF_8188E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_88E 10 //ms +#define index_mapping_NUM_88E 15 +#define AVG_THERMAL_NUM_88E 4 + + +VOID +ODM_TxPwrTrackAdjust88E( + PDM_ODM_T pDM_Odm, + u1Byte Type, // 0 = OFDM, 1 = CCK + pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease) + pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust + ); + + +VOID +odm_TXPowerTrackingCallback_ThermalMeter_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ); + + +//1 7. IQK + +void +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c new file mode 100755 index 00000000..fb99d0ee --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c @@ -0,0 +1,1290 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "../odm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +VOID +ODM_DIG_LowerBound_88E( + IN PDM_ODM_T pDM_Odm +) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); + } + //If only one Entry connected + + + +} + +#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +VOID +odm_RX_HWAntDivInit( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32; + PADAPTER Adapter = pDM_Odm->Adapter; + #if (MP_DRIVER == 1) + if (*(pDM_Odm->mp_mode) == 1) + { + pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS + return; + } + #endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n")); + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + //Pin Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + //OFDM Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); + //CCK Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table + + //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv + //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv +} + +VOID +odm_TRX_HWAntDivInit( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32; + PADAPTER Adapter = pDM_Odm->Adapter; + + #if (MP_DRIVER == 1) + if (*(pDM_Odm->mp_mode) == 1) + { + pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) + return; + } + + #endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n")); + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + //Pin Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + //OFDM Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); + //CCK Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + //Tx Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg + ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); + + //antenna mapping table + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + } + else //MPchip + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001 + + //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv + //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv +} + +VOID +odm_FastAntTrainingInit( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32, i; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte AntCombination = 2; + PADAPTER Adapter = pDM_Odm->Adapter; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n")); + +#if (MP_DRIVER == 1) + if (*(pDM_Odm->mp_mode) == 1) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); + return; + } +#endif + + for(i=0; i<6; i++) + { + pDM_FatTable->Bssid[i] = 0; + pDM_FatTable->antSumRSSI[i] = 0; + pDM_FatTable->antRSSIcnt[i] = 0; + pDM_FatTable->antAveRSSI[i] = 0; + } + pDM_FatTable->TrainIdx = 0; + pDM_FatTable->FAT_State = FAT_NORMAL_STATE; + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match + //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); + //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet + + //Match MAC ADDR + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); + + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); + + //antenna mapping table + if(AntCombination == 2) + { + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + } + else //MPchip + { + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); + } + } + else if(AntCombination == 7) + { + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); + ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 + } + else //MPchip + { + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3); + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4); + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7); + } + } + + //Default Ant Setting when no fast training + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX + //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX + + //Enter Traing state + ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 + //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv + //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training + //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv + + + //SW Control + //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); + //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); + //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); + //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); + //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); + //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); +} + +VOID +ODM_AntennaDiversityInit_88E( + IN PDM_ODM_T pDM_Odm +) +{ +/* + //2012.03.27 LukeLee: For temp use, should be removed later + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + //{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); + //pHalData->AntDivCfg = 1; + //} +*/ + if(pDM_Odm->SupportICType != ODM_RTL8188E) + return; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", + // pDM_Odm->AntDivType, pHalData->AntDivCfg)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE"))); + + if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDivInit(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDivInit(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_FastAntTrainingInit(pDM_Odm); +} + + +VOID +ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant) +{ + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte DefaultAnt, OptionalAnt; + + if(pDM_FatTable->RxIdleAnt != Ant) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n")); + if(Ant == MAIN_ANT) + { + DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX; + OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX; + } + else + { + DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX; + OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX; + } + + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX + ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx + + } + else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + { + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX + } + } + pDM_FatTable->RxIdleAnt = Ant; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + printk("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); +} + + +VOID +odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId) +{ + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte TargetAnt; + + if(Ant == MAIN_ANT) + TargetAnt = MAIN_ANT_CG_TRX; + else + TargetAnt = AUX_ANT_CG_TRX; + + pDM_FatTable->antsel_a[MacId] = TargetAnt&BIT0; + pDM_FatTable->antsel_b[MacId] = (TargetAnt&BIT1)>>1; + pDM_FatTable->antsel_c[MacId] = (TargetAnt&BIT2)>>2; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Tx from TxInfo, TargetAnt=%s\n", + (Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", + pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId + ) +{ + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) + { + SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); + SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); + SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + // macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId])); + } +} +#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm + ) +{ +} +#endif + +VOID +ODM_AntselStatistics_88E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u1Byte RxPWDBAll +) +{ + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + if(antsel_tr_mux == MAIN_ANT_CG_TRX) + { + + pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll; + pDM_FatTable->MainAnt_Cnt[MacId]++; + } + else + { + pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll; + pDM_FatTable->AuxAnt_Cnt[MacId]++; + + } + } + else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + { + if(antsel_tr_mux == MAIN_ANT_CGCS_RX) + { + + pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll; + pDM_FatTable->MainAnt_Cnt[MacId]++; + } + else + { + pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll; + pDM_FatTable->AuxAnt_Cnt[MacId]++; + + } + } +} + +#define TX_BY_REG 0 +VOID +odm_HWAntDiv( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI; + u4Byte Main_RSSI, Aux_RSSI; + u1Byte RxIdleAnt=0, TargetAnt=7; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + BOOLEAN bMatchBSSID; + BOOLEAN bPktFilterMacth = FALSE; + PSTA_INFO_T pEntry; + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + //2 Caculate RSSI per Antenna + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI)); + + //2 Select MaxRSSI for DIG + LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; + if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) + AntDivMaxRSSI = LocalMaxRSSI; + if(LocalMaxRSSI > MaxRSSI) + MaxRSSI = LocalMaxRSSI; + + //2 Select RX Idle Antenna + if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) + Main_RSSI = Aux_RSSI; + else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) + Aux_RSSI = Main_RSSI; + + LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI; + if(LocalMinRSSI < MinRSSI) + { + MinRSSI = LocalMinRSSI; + RxIdleAnt = TargetAnt; + } +#if TX_BY_REG + +#else + //2 Select TRX Antenna + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i); +#endif + } + pDM_FatTable->MainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + + //2 Set RX Idle Antenna + ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt); + + pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; + pDM_DigTable->RSSI_max = MaxRSSI; +} + + +#if (!(DM_ODM_SUPPORT_TYPE == ODM_CE)) +VOID +odm_SetNextMACAddrTarget( + IN PDM_ODM_T pDM_Odm +) +{ + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PSTA_INFO_T pEntry; + //u1Byte Bssid[6]; + u4Byte value32, i; + + // + //2012.03.26 LukeLee: The MAC address is changed according to MACID in turn + // + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n")); + if(pDM_Odm->bLinked) + { + for (i=0; iTrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM) + pDM_FatTable->TrainIdx = 0; + else + pDM_FatTable->TrainIdx++; + + pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; + if(IS_STA_VALID(pEntry)) + { + //Match MAC ADDR +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4]; +#else + value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4]; +#endif + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0]; +#else + value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0]; +#endif + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n",pDM_FatTable->TrainIdx)); +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", + pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0])); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", + pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0])); +#endif + + break; + } + } + + } + +#if 0 + // + //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn + // + #if( DM_ODM_SUPPORT_TYPE & ODM_MP) + { + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + for (i=0; i<6; i++) + { + Bssid[i] = pMgntInfo->Bssid[i]; + //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]); + } + } + #endif + + //odm_SetNextMACAddrTarget(pDM_Odm); + + //1 Select MAC Address Filter + for (i=0; i<6; i++) + { + if(Bssid[i] != pDM_FatTable->Bssid[i]) + { + bMatchBSSID = FALSE; + break; + } + } + if(bMatchBSSID == FALSE) + { + //Match MAC ADDR + value32 = (Bssid[5]<<8)|Bssid[4]; + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); + value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0]; + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); + } + + return bMatchBSSID; +#endif + +} + +VOID +odm_FastAntTraining( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i, MaxRSSI=0; + u1Byte TargetAnt=2; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + BOOLEAN bPktFilterMacth = FALSE; + PSTA_INFO_T pEntry; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n")); + + //1 TRAINING STATE + if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n")); + //2 Caculate RSSI per Antenna + for (i=0; i<7; i++) + { + if(pDM_FatTable->antRSSIcnt[i] == 0) + pDM_FatTable->antAveRSSI[i] = 0; + else + { + pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i]; + bPktFilterMacth = TRUE; + } + if(pDM_FatTable->antAveRSSI[i] > MaxRSSI) + { + MaxRSSI = pDM_FatTable->antAveRSSI[i]; + TargetAnt = (u1Byte) i; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%d] = %d, pDM_FatTable->antRSSIcnt[%d] = %d\n", + i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i])); + } + + //2 Select TRX Antenna + if(bPktFilterMacth == FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n")); + + ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%d\n",TargetAnt,MaxRSSI)); + + ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training + //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT + //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info + +#if 0 + pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; + + if(IS_STA_VALID(pEntry)) + { + pEntry->antsel_a = TargetAnt&BIT0; + pEntry->antsel_b = (TargetAnt&BIT1)>>1; + pEntry->antsel_c = (TargetAnt&BIT2)>>2; + } +#else + pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0; + pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1; + pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2; +#endif + + + if(TargetAnt == 0) + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv + + } + + //2 Reset Counter + for(i=0; i<7; i++) + { + pDM_FatTable->antSumRSSI[i] = 0; + pDM_FatTable->antRSSIcnt[i] = 0; + } + + pDM_FatTable->FAT_State = FAT_NORMAL_STATE; + return; + } + + //1 NORMAL STATE + if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n")); + + odm_SetNextMACAddrTarget(pDM_Odm); + +#if 0 + pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; + if(IS_STA_VALID(pEntry)) + { + pEntry->antsel_a = TargetAnt&BIT0; + pEntry->antsel_b = (TargetAnt&BIT1)>>1; + pEntry->antsel_c = (TargetAnt&BIT2)>>2; + } +#endif + + //2 Prepare Training + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n")); + ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms + + } + +} + +VOID +odm_FastAntTrainingCallback( + IN PDM_ODM_T pDM_Odm +) +{ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + //if(*pDM_Odm->pbNet_closed == TRUE) + // return; +#endif + +#if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem); +#else + odm_FastAntTraining(pDM_Odm); +#endif +} + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PDM_ODM_T pDM_Odm +) +{ + odm_FastAntTraining(pDM_Odm); +} +#endif + +VOID +ODM_AntennaDiversity_88E( + IN PDM_ODM_T pDM_Odm +) +{ + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); + return; + } +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + if(pDM_Odm->bLinked){ + if(pDM_Odm->Adapter->registrypriv.force_ant != 0) + { + u4Byte Main_RSSI, Aux_RSSI; + u8 i=0; + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI)); + pDM_FatTable->MainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + if(pDM_Odm->Adapter->registrypriv.force_ant==1){ + ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); + printk("%s fixed antenna in Main ant\n",__FUNCTION__); + return; + } + else if(pDM_Odm->Adapter->registrypriv.force_ant==2){ + ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT); + printk("%s fixed antenna in AUX ant\n",__FUNCTION__); + return; + } + } +#endif + + + + if(!pDM_Odm->bLinked) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); + if(pDM_FatTable->bBecomeLinked == TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); + //Because HW AntDiv is disabled before Link, we enable HW AntDiv after link + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv + //ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { +#if TX_BY_REG + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg +#else + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info +#endif + } + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + + + if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) + odm_HWAntDiv(pDM_Odm); + #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE)) + else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_FastAntTraining(pDM_Odm); + #endif +} + + +/* +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) +VOID +odm_FastAntTrainingCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + //#if DEV_BUS_TYPE==RT_PCI_INTERFACE + //#if USE_WORKITEM + //PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem); + //#else + odm_FastAntTraining(&pHalData->DM_OutSrc); + //#endif + //#else + //PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem); + //#endif + +} +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +VOID odm_FastAntTrainingCallback(void *FunctionContext) +{ + PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + odm_FastAntTraining(pDM_Odm); +} +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID odm_FastAntTrainingCallback(void *FunctionContext) +{ + PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; + odm_FastAntTraining(pDM_Odm); +} + +#endif +*/ + +#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId + ) +{ +} +#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm + ) +{ +} +#endif +#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +//3============================================================ +//3 Dynamic Primary CCA +//3============================================================ + +VOID +odm_PrimaryCCA_Init( + IN PDM_ODM_T pDM_Odm) +{ + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->Monitor_flag = 0; + PrimaryCCA->PriCCA_flag = 0; +} + +BOOLEAN +ODM_DynamicPrimaryCCA_DupRTS( + IN PDM_ODM_T pDM_Odm + ) +{ + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + return PrimaryCCA->DupRTS_flag; +} + +VOID +odm_DynamicPrimaryCCA( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER Adapter = pDM_Odm->Adapter; // for NIC + prtl8192cd_priv priv = pDM_Odm->priv; // for AP + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP)) + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_WLAN_STA pEntry; +#endif + + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + BOOLEAN Is40MHz; + BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW + BOOLEAN bConnected = FALSE; // connected or not + static u1Byte Client_40MHz_pre = 0; + static u8Byte lastTxOkCnt = 0; + static u8Byte lastRxOkCnt = 0; + static u4Byte Counter = 0; + static u1Byte Delay = 1; + u8Byte curTxOkCnt; + u8Byte curRxOkCnt; + u1Byte SecCHOffset; + u1Byte i; + +#if((DM_ODM_SUPPORT_TYPE==ODM_ADSL) ||( DM_ODM_SUPPORT_TYPE==ODM_CE)) + return; +#endif + + if(pDM_Odm->SupportICType != ODM_RTL8188E) + return; + + Is40MHz = *(pDM_Odm->pBandWidth); + SecCHOffset = *(pDM_Odm->pSecChOffset); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + if(Is40MHz==1) + SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); + //3 Check Current WLAN Traffic + curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; + curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; + lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + //3 Check Current WLAN Traffic + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); +#endif + + //==================Debug Message==================== + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", FalseAlmCnt->Cnt_BW_USC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", FalseAlmCnt->Cnt_OFDM_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail)); + //================================================ + +#if (DM_ODM_SUPPORT_TYPE == ODM_MP) + if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode +#endif + { + + #if (DM_ODM_SUPPORT_TYPE == ODM_MP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter))); + //3 To get entry's connection and BW infomation status. + for(i=0;iHTInfo.bBw40MHz; // client BW + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp)); + if(Client_tmp>Client_40MHz) + Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High + + if(pEntry->bAssociated) + { + bConnected=TRUE; // client is connected or not + break; + } + } + else + { + break; + } + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + //3 To get entry's connection and BW infomation status. + + PSTA_INFO_T pstat; + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) + { + Client_tmp = pstat->tx_bw; + if(Client_tmp>Client_40MHz) + Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High + + bConnected = TRUE; + } + } +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz)); + //1 Monitor whether the interference exists or not + if(PrimaryCCA->Monitor_flag == 1) + { + if(SecCHOffset == 1) // secondary channel is below the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500)) + { + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + { + PrimaryCCA->intf_type = 1; + PrimaryCCA->PriCCA_flag = 1; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF + if(PrimaryCCA->DupRTS_flag == 1) + PrimaryCCA->DupRTS_flag = 0; + } + else + { + PrimaryCCA->intf_type = 2; + if(PrimaryCCA->DupRTS_flag == 0) + PrimaryCCA->DupRTS_flag = 1; + } + + } + else // interferecne disappear + { + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + } + else if(SecCHOffset == 2) // secondary channel is above the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500)) + { + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + { + PrimaryCCA->intf_type = 1; + PrimaryCCA->PriCCA_flag = 1; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF + if(PrimaryCCA->DupRTS_flag == 1) + PrimaryCCA->DupRTS_flag = 0; + } + else + { + PrimaryCCA->intf_type = 2; + if(PrimaryCCA->DupRTS_flag == 0) + PrimaryCCA->DupRTS_flag = 1; + } + + } + else // interferecne disappear + { + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + + + } + PrimaryCCA->Monitor_flag = 0; + } + + //1 Dynamic Primary CCA Main Function + if(PrimaryCCA->Monitor_flag == 0) + { + if(Is40MHz) // if RFBW==40M mode which require to process primary cca + { + //2 STA is NOT Connected + if(!bConnected) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n")); + + if(PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected + { + PrimaryCCA->PriCCA_flag = 0; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); + } + if(PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected + PrimaryCCA->DupRTS_flag = 0; + + if(SecCHOffset == 1) // secondary channel is below the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) + { + PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + else + { + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + } + else if(SecCHOffset == 2) // secondary channel is above the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) + { + PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + else + { + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type)); + } + //2 STA is Connected + else + { + if(Client_40MHz == 0) //3 // client BW = 20MHz + { + if(PrimaryCCA->PriCCA_flag == 0) + { + PrimaryCCA->PriCCA_flag = 1; + if(SecCHOffset==1) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); + else if(SecCHOffset==2) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag)); + } + else //3 // client BW = 40MHz + { + if(PrimaryCCA->intf_flag == 1) // interference is detected!! + { + if(PrimaryCCA->intf_type == 1) + { + if(PrimaryCCA->PriCCA_flag!=1) + { + PrimaryCCA->PriCCA_flag = 1; + if(SecCHOffset==1) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); + else if(SecCHOffset==2) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); + } + } + else if(PrimaryCCA->intf_type == 2) + { + if(PrimaryCCA->DupRTS_flag!=1) + PrimaryCCA->DupRTS_flag = 1; + } + } + else // if intf_flag==0 + { + if((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low + { + if(SecCHOffset == 1) + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + } + else if(SecCHOffset == 2) + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + + } + } + else // TP Traffic is High + { + if(SecCHOffset == 1) + { + if(FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500)) + { + if(Delay == 0) // add delay to avoid interference occurring abruptly, jump one time + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + Delay = 1; + } + else + Delay = 0; + } + } + else if(SecCHOffset == 2) + { + if(FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500)) + { + if(Delay == 0) // add delay to avoid interference occurring abruptly + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + Delay = 1; + } + else + Delay = 0; + } + } + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", PrimaryCCA->PriCCA_flag)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag)); + } + + }// end of connected + } + } + //1 Dynamic Primary CCA Monitor Counter + if((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1)) + { + if(Client_40MHz == 0) // client=20M no need to monitor primary cca flag + { + Client_40MHz_pre = Client_40MHz; + return; + } + Counter++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter)); + if((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time + { + PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!! + if(PrimaryCCA->PriCCA_flag == 1) + { + PrimaryCCA->PriCCA_flag = 0; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); + } + Counter = 0; + } + } + } + + Client_40MHz_pre = Client_40MHz; +} +#else //#if (RTL8188E_SUPPORT == 1) +VOID +ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant) +{ +} +VOID +odm_PrimaryCCA_Init( + IN PDM_ODM_T pDM_Odm) +{ +} +VOID +odm_DynamicPrimaryCCA( + IN PDM_ODM_T pDM_Odm + ) +{ +} +BOOLEAN +ODM_DynamicPrimaryCCA_DupRTS( + IN PDM_ODM_T pDM_Odm + ) +{ + return FALSE; +} +#endif //#if (RTL8188E_SUPPORT == 1) + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h new file mode 100755 index 00000000..ac0e0067 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h @@ -0,0 +1,109 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8188E_H__ +#define __ODM_RTL8188E_H__ + +#define MAIN_ANT 0 +#define AUX_ANT 1 +#define MAIN_ANT_CG_TRX 1 +#define AUX_ANT_CG_TRX 0 +#define MAIN_ANT_CGCS_RX 0 +#define AUX_ANT_CGCS_RX 1 + +VOID +ODM_DIG_LowerBound_88E( + IN PDM_ODM_T pDM_Odm +); +#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE)) +VOID +odm_FastAntTrainingInit( + IN PDM_ODM_T pDM_Odm +); +#endif + +VOID +ODM_AntennaDiversityInit_88E( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_AntennaDiversity_88E +( + IN PDM_ODM_T pDM_Odm +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +); +#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm +); +#endif + +VOID +ODM_UpdateRxIdleAnt_88E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Ant +); + +VOID +ODM_AntselStatistics_88E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u1Byte RxPWDBAll +); + +#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE)) +VOID +odm_FastAntTraining( + IN PDM_ODM_T pDM_Odm +); + +VOID +odm_FastAntTrainingCallback( + IN PDM_ODM_T pDM_Odm +); + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PDM_ODM_T pDM_Odm +); +#endif +VOID +odm_PrimaryCCA_Init( + IN PDM_ODM_T pDM_Odm); + +BOOLEAN +ODM_DynamicPrimaryCCA_DupRTS( + IN PDM_ODM_T pDM_Odm); + +VOID +odm_DynamicPrimaryCCA( + IN PDM_ODM_T pDM_Odm); + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c new file mode 100755 index 00000000..e0e7c8b8 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c @@ -0,0 +1,209 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "../odm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +void +odm_ConfigRFReg_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd) + { + ODM_delay_ms(5); + } + else if (Addr == 0xfc) + { + ODM_delay_ms(1); + } + else if (Addr == 0xfb) + { + ODM_delay_us(50); + } + else if (Addr == 0xfa) + { + ODM_delay_us(5); + } + else if (Addr == 0xf9) + { + ODM_delay_us(1); + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe){ + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd){ + ODM_delay_ms(5); + } + else if (Addr == 0xfc){ + ODM_delay_ms(1); + } + else if (Addr == 0xfb){ + ODM_delay_us(50); + } + else if (Addr == 0xfa){ + ODM_delay_us(5); + } + else if (Addr == 0xf9){ + ODM_delay_us(1); + } + else{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); + + #if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); + #endif + } + +} + +void +odm_ConfigBB_PHY_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe){ + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd){ + ODM_delay_ms(5); + } + else if (Addr == 0xfc){ + ODM_delay_ms(1); + } + else if (Addr == 0xfb){ + ODM_delay_us(50); + } + else if (Addr == 0xfa){ + ODM_delay_us(5); + } + else if (Addr == 0xf9){ + ODM_delay_us(1); + } + else{ + if (Addr == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = Data; + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); + } +} +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h new file mode 100755 index 00000000..211b96de --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8188E +#define __INC_ODM_REGCONFIG_H_8188E + +#if (RTL8188E_SUPPORT == 1) + +void +odm_ConfigRFReg_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); +#endif +#endif // end of SUPPORT + -- cgit