From 871480933a1c28f8a9fed4c4d34d06c439a7a422 Mon Sep 17 00:00:00 2001 From: Srikant Patnaik Date: Sun, 11 Jan 2015 12:28:04 +0530 Subject: Moved, renamed, and deleted files The original directory structure was scattered and unorganized. Changes are basically to make it look like kernel structure. --- arch/arm/plat-mxc/include/mach/irqs.h | 65 +++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/irqs.h (limited to 'arch/arm/plat-mxc/include/mach/irqs.h') diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h new file mode 100644 index 00000000..fd9efb04 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -0,0 +1,65 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_IRQS_H__ +#define __ASM_ARCH_MXC_IRQS_H__ + +#include + +/* + * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC + * have 128 IRQs, and those with AVIC have 64. + * + * To support single image, the biggest number should be defined on + * top of the list. + */ +#if defined CONFIG_ARM_GIC +#define MXC_INTERNAL_IRQS 160 +#elif defined CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#else +#define MXC_INTERNAL_IRQS 64 +#endif + +#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase MXC_BOARD_IRQS, but keep it + * within sensible limits. + */ +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) + +#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 +#define MXC_BOARD_IRQS 80 +#else +#define MXC_BOARD_IRQS 16 +#endif + +#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) + +#ifdef CONFIG_MX3_IPU_IRQS +#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS +#else +#define MX3_IPU_IRQS 0 +#endif +/* REVISIT: Add IPU irqs on IMX51 */ + +#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) + +extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); + +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch between IRQ and FIQ */ +extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); + +#endif /* __ASM_ARCH_MXC_IRQS_H__ */ -- cgit