From 871480933a1c28f8a9fed4c4d34d06c439a7a422 Mon Sep 17 00:00:00 2001 From: Srikant Patnaik Date: Sun, 11 Jan 2015 12:28:04 +0530 Subject: Moved, renamed, and deleted files The original directory structure was scattered and unorganized. Changes are basically to make it look like kernel structure. --- ANDROID_3.4.5/arch/powerpc/kernel/cpu_setup_44x.S | 74 ----------------------- 1 file changed, 74 deletions(-) delete mode 100644 ANDROID_3.4.5/arch/powerpc/kernel/cpu_setup_44x.S (limited to 'ANDROID_3.4.5/arch/powerpc/kernel/cpu_setup_44x.S') diff --git a/ANDROID_3.4.5/arch/powerpc/kernel/cpu_setup_44x.S b/ANDROID_3.4.5/arch/powerpc/kernel/cpu_setup_44x.S deleted file mode 100644 index e32b4a9a..00000000 --- a/ANDROID_3.4.5/arch/powerpc/kernel/cpu_setup_44x.S +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file contains low level CPU setup functions. - * Valentine Barshak - * MontaVista Software, Inc (c) 2007 - * - * Based on cpu_setup_6xx code by - * Benjamin Herrenschmidt - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include - -_GLOBAL(__setup_cpu_440ep) - b __init_fpu_44x -_GLOBAL(__setup_cpu_440epx) - mflr r4 - bl __init_fpu_44x - bl __plb_disable_wrp - bl __fixup_440A_mcheck - mtlr r4 - blr -_GLOBAL(__setup_cpu_440grx) - mflr r4 - bl __plb_disable_wrp - bl __fixup_440A_mcheck - mtlr r4 - blr -_GLOBAL(__setup_cpu_460ex) -_GLOBAL(__setup_cpu_460gt) -_GLOBAL(__setup_cpu_460sx) -_GLOBAL(__setup_cpu_apm821xx) - mflr r4 - bl __init_fpu_44x - bl __fixup_440A_mcheck - mtlr r4 - blr - -_GLOBAL(__setup_cpu_440x5) -_GLOBAL(__setup_cpu_440gx) -_GLOBAL(__setup_cpu_440spe) - b __fixup_440A_mcheck - -/* enable APU between CPU and FPU */ -_GLOBAL(__init_fpu_44x) - mfspr r3,SPRN_CCR0 - /* Clear DAPUIB flag in CCR0 */ - rlwinm r3,r3,0,12,10 - mtspr SPRN_CCR0,r3 - isync - blr - -/* - * Workaround for the incorrect write to DDR SDRAM errata. - * The write address can be corrupted during writes to - * DDR SDRAM when write pipelining is enabled on PLB0. - * Disable write pipelining here. - */ -#define DCRN_PLB4A0_ACR 0x81 - -_GLOBAL(__plb_disable_wrp) - mfdcr r3,DCRN_PLB4A0_ACR - /* clear WRP bit in PLB4A0_ACR */ - rlwinm r3,r3,0,8,6 - mtdcr DCRN_PLB4A0_ACR,r3 - isync - blr - -- cgit