diff options
Diffstat (limited to 'drivers/video/wmt/hw')
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-cec-reg.h | 325 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-govrh-reg.h | 194 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-hdmi-reg.h | 587 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-lvds-reg.h | 149 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-scl-reg.h | 835 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-vpp-hw.h | 40 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/wmt/hw/wmt-vpp-reg.h | 168 |
7 files changed, 944 insertions, 1354 deletions
diff --git a/drivers/video/wmt/hw/wmt-cec-reg.h b/drivers/video/wmt/hw/wmt-cec-reg.h index 17e7275c..e93939fd 100755..100644 --- a/drivers/video/wmt/hw/wmt-cec-reg.h +++ b/drivers/video/wmt/hw/wmt-cec-reg.h @@ -28,193 +28,142 @@ #define CEC_BASE_ADDR (LVDS_BASE_ADDR + 0x100) #define CEC_BASE2_ADDR (LVDS_BASE_ADDR + 0x200) -struct cec_base_regs { - union { - unsigned int val; - struct { - unsigned int wr_start:1; - } b; - } enable; /* 0x0 */ - - union { - unsigned int val; - struct { - unsigned int wr_num:8; - } b; - } encode_number; /* 0x04 */ - - union { - unsigned int val; - struct { - unsigned int wr_data_ack:1; - unsigned int wr_data_eom:1; - unsigned int _02_03:2; - unsigned int wr_data:8; - } b; - } encode_data[16]; /* 0x08 header,0x0c - 0x44 */ - - union { - unsigned int val; - struct { - unsigned int finish_reset:1; - } b; - } decode_reset; /* 0x48 */ - - union { - unsigned int val; - struct { - unsigned int rd_start:1; - unsigned int rd_all_ack:1; - unsigned int rd_finish:1; - } b; - } decode_start; /* 0x4c */ - - union { - unsigned int val; - struct { - unsigned int rd_data_ack:1; - unsigned int rd_data_eom:1; - unsigned int _02_03:2; - unsigned int rd_data:8; - } b; - } decode_data[16]; /* 0x50 header, 0x54 - 0x8c */ - - unsigned int wr_start_set0; /* 0x90 */ - unsigned int wr_start_set1; /* 0x94 */ - unsigned int wr_logic0_set0; /* 0x98 */ - unsigned int wr_logic0_set1; /* 0x9c */ - unsigned int wr_logic1_set0; /* 0xa0 */ - unsigned int wr_logic1_set1; /* 0xa4 */ - unsigned int rd_start_l_set0; /* 0xa8 */ - unsigned int rd_start_r_set0; /* 0xac */ - unsigned int rd_start_l_set1; /* 0xb0 */ - unsigned int rd_start_r_set1; /* 0xb4 */ - unsigned int rd_logic0_l_set0; /* 0xb8 */ - unsigned int rd_logic0_r_set0; /* 0xbc */ - unsigned int rd_logic0_l_set1; /* 0xc0 */ - unsigned int rd_logic0_r_set1; /* 0xc4 */ - unsigned int rd_logic1_l_set0; /* 0xc8 */ - unsigned int rd_logic1_r_set0; /* 0xcc */ - unsigned int rd_logic1_l_set1; /* 0xd0 */ - unsigned int rd_logic1_r_set1; /* 0xd4 */ - unsigned int physical_addr; /* 0xd8 */ - - union { - unsigned int val; - struct { - unsigned int addr1:4; - unsigned int addr2:4; - unsigned int addr3:4; - unsigned int addr4:4; - unsigned int addr5:4; - unsigned int _20_23:4; - unsigned int valid1:1; - unsigned int valid2:1; - unsigned int valid3:1; - unsigned int valid4:1; - unsigned int valid5:1; - } b; - } logical_addr; /* 0xdc */ - - union { - unsigned int val; - struct { - unsigned int retry:4; - } b; - } wr_retry; /* 0xe0 */ - - union { - unsigned int val; - struct { - unsigned int free_3x:4; - unsigned int _04_07:4; - unsigned int free_5x:4; - unsigned int _12_15:4; - unsigned int free_7x:4; - } b; - } free_3x; /* 0xe4 */ - - unsigned int wr_set0_error; /* 0xe8 */ - unsigned int wr_set1_error; /* 0xec */ - - union { - unsigned int val; - struct { - unsigned int next_decode:1; /*read enable*/ - } b; - } reject; /* 0xf0 */ - - unsigned int rd_l_set0_error; /* 0xf4 */ - unsigned int rd_r_set1_error; /* 0xf8 */ - unsigned int rd_l_error; /* 0xfc */ - - unsigned int rx_trig_range; /* 0x100 */ - unsigned int rx_sample_l_range; /* 0x104 */ - unsigned int rx_sample_r_range; /* 0x108 */ - - union { - unsigned int val; - struct { - unsigned int disable:1; - } b; - } comp; /* 0x10c */ - - union { - unsigned int val; - struct { - unsigned int err:1; - unsigned int no_ack:1; - } b; - } handle_disable; /* 0x110 */ - - union { - unsigned int val; - struct { - unsigned int r1_encode_ok:1; /* write finish */ - unsigned int r1_decode_ok:1; /* read finish */ - unsigned int r1_error:1; /* read error */ - unsigned int r1_arb_fail:1; /* wr arb fail */ - unsigned int r1_no_ack:1; /* wr no ack */ - } b; - } status; /* 0x114 */ - - unsigned int int_enable; /* 0x118 */ - - union { - unsigned int val; - struct { - unsigned int disable:1; - } b; - } decode_full; /* 0x11c */ - - union { - unsigned int val; - struct { - unsigned int start:1; - unsigned int logic0:1; - unsigned int logic1:1; - } b; - } status4_disable; /* 0x120 */ - - union { - unsigned int val; - struct { - unsigned int enable:1; /*1:rd self wr & all dest data */ - } b; - } rd_encode; /* 0x124 */ - - union { - unsigned int val; - struct { - unsigned int disable:1; /* 1 : disable arb check */ - } b; - } arb_check; /* 0x128 */ -}; - -#define REG_CEC_BEGIN (CEC_BASE_ADDR + 0x0) -#define REG_CEC_END (CEC_BASE2_ADDR + 0x28) -#ifndef CEC_C -extern struct cec_base_regs *cec_regs; -#endif + +#define REG_CEC_BEGIN (CEC_BASE_ADDR + 0x0) +#define REG_CEC_ENABLE (CEC_BASE_ADDR + 0x0) +#define REG_CEC_ENCODE_NUMBER (CEC_BASE_ADDR + 0x4) +#define REG_CEC_ENCODE_HEADER (CEC_BASE_ADDR + 0x8) +#define REG_CEC_ENCODE_DATA (CEC_BASE_ADDR + 0xC) /* Data1(0x0C) - Data15(0x44) */ +#define REG_CEC_DECODE_RESET (CEC_BASE_ADDR + 0x48) +#define REG_CEC_DECODE_START (CEC_BASE_ADDR + 0x4C) +#define REG_CEC_DECODE_HEADER (CEC_BASE_ADDR + 0x50) +#define REG_CEC_DECODE_DATA (CEC_BASE_ADDR + 0x54) /* Data1(0x54) - Data15(0x8C) */ +#define REG_CEC_WR_START_SET0 (CEC_BASE_ADDR + 0x90) /* val * CEC_CLK = 3.7 ms */ +#define REG_CEC_WR_START_SET1 (CEC_BASE_ADDR + 0x94) /* val * CEC_CLK = 4.5 ms */ +#define REG_CEC_WR_LOGIC0_SET0 (CEC_BASE_ADDR + 0x98) /* val * CEC_CLK = 0.6 ms */ +#define REG_CEC_WR_LOGIC0_SET1 (CEC_BASE_ADDR + 0x9C) /* val * CEC_CLK = 2.4 ms */ +#define REG_CEC_WR_LOGIC1_SET0 (CEC_BASE_ADDR + 0xA0) /* val * CEC_CLK = 1.5 ms */ +#define REG_CEC_WR_LOGIC1_SET1 (CEC_BASE_ADDR + 0xA4) /* val * CEC_CLK = 2.4 ms */ +#define REG_CEC_RD_START_L_SET0 (CEC_BASE_ADDR + 0xA8) /* val * CEC_CLK = 3.5 ms */ +#define REG_CEC_RD_START_R_SET0 (CEC_BASE_ADDR + 0xAC) /* val * CEC_CLK = 3.9 ms */ +#define REG_CEC_RD_START_L_SET1 (CEC_BASE_ADDR + 0xB0) /* val * CEC_CLK = 4.3 ms */ +#define REG_CEC_RD_START_R_SET1 (CEC_BASE_ADDR + 0xB4) /* val * CEC_CLK = 4.7 ms */ +#define REG_CEC_RD_LOGIC0_L_SET0 (CEC_BASE_ADDR + 0xB8) /* val * CEC_CLK = 1.3 ms */ +#define REG_CEC_RD_LOGIC0_R_SET0 (CEC_BASE_ADDR + 0xBC) /* val * CEC_CLK = 1.7 ms */ +#define REG_CEC_RD_LOGIC0_L_SET1 (CEC_BASE_ADDR + 0xC0) /* val * CEC_CLK = 2.05 ms */ +#define REG_CEC_RD_LOGIC0_R_SET1 (CEC_BASE_ADDR + 0xC4) /* val * CEC_CLK = 2.75 ms */ +#define REG_CEC_RD_LOGIC1_L_SET0 (CEC_BASE_ADDR + 0xC8) /* val * CEC_CLK = 0.4 ms */ +#define REG_CEC_RD_LOGIC1_R_SET0 (CEC_BASE_ADDR + 0xCC) /* val * CEC_CLK = 0.8 ms */ +#define REG_CEC_RD_LOGIC1_L_SET1 (CEC_BASE_ADDR + 0xD0) /* val * CEC_CLK = 2.05 ms */ +#define REG_CEC_RD_LOGIC1_R_SET1 (CEC_BASE_ADDR + 0xD4) /* val * CEC_CLK = 2.75 ms */ +#define REG_CEC_PHYSICAL_ADDR (CEC_BASE_ADDR + 0xD8) +#define REG_CEC_LOGICAL_ADDR (CEC_BASE_ADDR + 0xDC) +#define REG_CEC_WR_RETRY (CEC_BASE_ADDR + 0xE0) +#define REG_CEC_FREE_3X (CEC_BASE_ADDR + 0xE4) +#define REG_CEC_WR_SET0_ERROR (CEC_BASE_ADDR + 0xE8) /* val * CEC_CLK = 2.25 ms */ +#define REG_CEC_WR_SET1_ERROR (CEC_BASE_ADDR + 0xEC) +#define REG_CEC_REJECT (CEC_BASE_ADDR + 0xF0) +#define REG_CEC_RD_L_SET0_ERROR (CEC_BASE_ADDR + 0xF4) /* val * CEC_CLK = 1.82 ms */ +#define REG_CEC_RD_R_SET1_ERROR (CEC_BASE_ADDR + 0xF8) /* val * CEC_CLK = 2.38 ms */ +#define REG_CEC_RD_L_ERROR (CEC_BASE_ADDR + 0xFC) /* val * CEC_CLK = 2.87 ms */ + +#define REG_CEC_RX_TRIG_RANGE (CEC_BASE2_ADDR + 0x00) +#define REG_CEC_RX_SAMPLE_L_RANGE (CEC_BASE2_ADDR + 0x04) /* val * CEC_CLK = 0.85 ms */ +#define REG_CEC_RX_SAMPLE_R_RANGE (CEC_BASE2_ADDR + 0x08) /* val * CEC_CLK = 1.25 ms */ +#define REG_CEC_COMP_DISABLE (CEC_BASE2_ADDR + 0x0C) +#define REG_CEC_ERR_HANDLE_DISABLE (CEC_BASE2_ADDR + 0x10) +#define REG_CEC_STATUS (CEC_BASE2_ADDR + 0x14) +#define REG_CEC_INT_ENABLE (CEC_BASE2_ADDR + 0x18) +#define REG_CEC_DECODE_FULL_DISABLE (CEC_BASE2_ADDR + 0x1C) +#define REG_CEC_STATUS4_DISABLE (CEC_BASE2_ADDR + 0x20) +#define REG_CEC_RD_ENCODE_ENABLE (CEC_BASE2_ADDR + 0x24) +#define REG_CEC_DIS_ARB_CHECK (CEC_BASE2_ADDR + 0x28) +#define REG_CEC_END (CEC_BASE2_ADDR + 0x28) + +/* REG_CEC_ENABLE,0x0 */ +#define CEC_WR_START REG_CEC_ENABLE, BIT0, 0 + +/* REG_CEC_ENCODE_NUMBER,0x4 */ +#define CEC_WR_NUM REG_CEC_ENCODE_NUMBER, 0xFF, 0x0 + +/* REG_CEC_ENCODE_HEADER,0x8 */ +#define CEC_WR_HEADER_ACK REG_CEC_ENCODE_HEADER, BIT0, 0 +#define CEC_WR_HEADER_EOM REG_CEC_ENCODE_HEADER, BIT1, 1 +#define CEC_WR_HEADER_DATA REG_CEC_ENCODE_HEADER, 0xFF0, 4 + +/* REG_CEC_ENCODE_DATA,Data1(0x0C) - Data15(0x44) */ +#define CEC_WR_DATA_ACK REG_CEC_ENCODE_DATA, BIT0, 0 +#define CEC_WR_DATA_EOM REG_CEC_ENCODE_DATA, BIT1, 1 +#define CEC_WR_DATA REG_CEC_ENCODE_DATA, 0xFF0, 4 + +/* REG_CEC_DECODE_RESET,0x48 */ +#define CEC_FINISH_RESET REG_CEC_DECODE_RESET, BIT0, 0 + +/* REG_CEC_DECODE_START,0x4C */ +#define CEC_RD_START REG_CEC_DECODE_START, BIT0, 0 +#define CEC_RD_ALL_ACK REG_CEC_DECODE_START, BIT1, 1 +#define CEC_RD_FINISH REG_CEC_DECODE_START, BIT2, 2 + +/* REG_CEC_DECODE_HEADER,0x50 */ +#define CEC_RD_HEADER_ACK REG_CEC_DECODE_HEADER, BIT0, 0 +#define CEC_RD_HEADER_EOM REG_CEC_DECODE_HEADER, BIT1, 1 +#define CEC_RD_HEADER_DATA REG_CEC_DECODE_HEADER, 0xFF0, 4 + +/* REG_CEC_DECODE_DATA,Data1(0x54) - Data15(0x8C) */ +#define CEC_RD_DATA_ACK REG_CEC_DECODE_DATA, BIT0, 0 +#define CEC_RD_DATA_EOM REG_CEC_DECODE_DATA, BIT1, 1 +#define CEC_RD_DATA REG_CEC_DECODE_DATA, 0xFF0, 4 + +/* REG_CEC_LOGICAL_ADDR,0xDC */ +#define CEC_LOGICAL_ADDR1 REG_CEC_LOGICAL_ADDR, 0xF, 0 +#define CEC_LOGICAL_ADDR2 REG_CEC_LOGICAL_ADDR, 0xF0, 4 +#define CEC_LOGICAL_ADDR3 REG_CEC_LOGICAL_ADDR, 0xF00, 8 +#define CEC_LOGICAL_ADDR4 REG_CEC_LOGICAL_ADDR, 0xF000, 12 +#define CEC_LOGICAL_ADDR5 REG_CEC_LOGICAL_ADDR, 0xF0000, 16 +#define CEC_ADDR_VALID1 REG_CEC_LOGICAL_ADDR, BIT24, 24 +#define CEC_ADDR_VALID2 REG_CEC_LOGICAL_ADDR, BIT25, 25 +#define CEC_ADDR_VALID3 REG_CEC_LOGICAL_ADDR, BIT26, 26 +#define CEC_ADDR_VALID4 REG_CEC_LOGICAL_ADDR, BIT27, 27 +#define CEC_ADDR_VALID5 REG_CEC_LOGICAL_ADDR, BIT28, 28 + +/* REG_CEC_WR_RETRY,0xE0 */ +#define CEC_WR_RETRY REG_CEC_WR_RETRY, 0xF, 0 + +/* REG_CEC_FREE_3X,0xE4 */ +#define CEC_FREE_3X REG_CEC_FREE_3X, 0xF, 0 +#define CEC_FREE_5X REG_CEC_FREE_3X, 0xF00, 8 +#define CEC_FREE_7X REG_CEC_FREE_3X, 0xF0000, 16 + +/* REG_CEC_REJECT,0xF0 */ +#define CEC_REJECT_NEXT_DECODE REG_CEC_REJECT, BIT0, 0 /*read enable*/ + +/* REG_CEC_COMP_DISABLE,0x0C */ +#define CEC_COMP_DISABLE REG_CEC_COMP_DISABLE, BIT0, 0 + +/* REG_CEC_ERR_HANDLE_DISABLE,0x10 */ +#define CEC_ERR_HANDLE_DISABLE REG_CEC_ERR_HANDLE_DISABLE, BIT0, 0 +#define CEC_NO_ACK_DISABLE REG_CEC_ERR_HANDLE_DISABLE, BIT1, 1 + +/* REG_CEC_STATUS,0x14 */ +#define CEC_R1_ENCODE_OK REG_CEC_STATUS, BIT0, 0 /* write finish */ +#define CEC_R1_DECODE_OK REG_CEC_STATUS, BIT1, 1 /* read finish */ +#define CEC_R1_ERROR REG_CEC_STATUS, BIT2, 2 /* read error */ +#define CEC_R1_ARB_FAIL REG_CEC_STATUS, BIT3, 3 /* wr arb fail */ +#define CEC_R1_NO_ACK REG_CEC_STATUS, BIT4, 4 /* wr no ack */ + +/* REG_CEC_DECODE_FULL_DISABLE,0x1C */ +#define CEC_DECODE_FULL_DISABLE REG_CEC_DECODE_FULL_DISABLE, BIT0, 0 + +/* REG_CEC_STATUS4_DISABLE,0x20 */ +#define CEC_STATUS4_START_DISABLE REG_CEC_STATUS4_DISABLE, BIT0, 0 +#define CEC_STATUS4_LOGIC0_DISABLE REG_CEC_STATUS4_DISABLE, BIT1, 1 +#define CEC_STATUS4_LOGIC1_DISABLE REG_CEC_STATUS4_DISABLE, BIT2, 2 + +/* REG_CEC_RD_ENCODE_ENABLE,0x24 */ +#define CEC_RD_ENCODE_ENABLE REG_CEC_RD_ENCODE_ENABLE, BIT0, 0 /* 1 : read self write and all dest data */ + +/* REG_CEC_DIS_ARB_CHECK,0x28 */ +#define CEC_ARB_CHECK_DISABLE REG_CEC_DIS_ARB_CHECK, BIT0, 0 /* 1 : disable arbitration check */ + #endif /* WMT_CEC_REG_H */ diff --git a/drivers/video/wmt/hw/wmt-govrh-reg.h b/drivers/video/wmt/hw/wmt-govrh-reg.h index ecdeb4f2..4e2e2341 100755..100644 --- a/drivers/video/wmt/hw/wmt-govrh-reg.h +++ b/drivers/video/wmt/hw/wmt-govrh-reg.h @@ -2,7 +2,7 @@ * linux/drivers/video/wmt/hw/wmt-govrh-reg.h * WonderMedia video post processor (VPP) driver * - * Copyright c 2014 WonderMedia Technologies, Inc. + * Copyright c 2013 WonderMedia Technologies, Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -43,38 +43,38 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int start:11; - unsigned int reserved:5; - unsigned int end:11; + unsigned int start : 11; + unsigned int reserved : 5; + unsigned int end : 11; } b; } cur_hcoord; /* 0x14 */ union { unsigned int val; struct { - unsigned int start:11; - unsigned int reserved:5; - unsigned int end:11; + unsigned int start : 11; + unsigned int reserved : 5; + unsigned int end : 11; } b; } cur_vcoord; /* 0x18 */ union { unsigned int val; struct { - unsigned int enable:1; - unsigned int reserved:7; - unsigned int out_field:1; /* 0:frame,1-field */ + unsigned int enable : 1; + unsigned int reserved : 7; + unsigned int out_field : 1; /* 0:frame,1-field */ } b; } cur_status; /* 0x1C */ union { unsigned int val; struct { - unsigned int colkey:24; - unsigned int enable:1; - unsigned int invert:1; - unsigned int reserved:2; - unsigned int alpha:1; + unsigned int colkey : 24; + unsigned int enable : 1; + unsigned int invert : 1; + unsigned int reserved : 2; + unsigned int alpha : 1; } b; } cur_color_key; /* 0x20 */ @@ -83,29 +83,29 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int rgb:1; - unsigned int yuv422:1; + unsigned int rgb : 1; + unsigned int yuv422 : 1; } b; } dvo_pix; /* 0x30 */ union { unsigned int val; struct { - unsigned int delay:14; - unsigned int inv:1; + unsigned int delay : 14; + unsigned int inv : 1; } b; } dvo_dly_sel; /* 0x34 */ union { unsigned int val; struct { - unsigned int cur_enable:1; - unsigned int mem_enable:1; - unsigned int reserved:7; - unsigned int err_sts:1; - unsigned int reserved2:6; - unsigned int cur_sts:1; - unsigned int mem_sts:1; + unsigned int cur_enable : 1; + unsigned int mem_enable : 1; + unsigned int reserved : 7; + unsigned int err_sts : 1; + unsigned int reserved2 : 6; + unsigned int cur_sts : 1; + unsigned int mem_sts : 1; } b; } interrupt; /* 0x38 */ @@ -114,17 +114,17 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int v:8; - unsigned int u:8; - unsigned int y:8; + unsigned int v : 8; + unsigned int u : 8; + unsigned int y : 8; } b; } saturation; /* 0x44 */ union { unsigned int val; struct { - unsigned int enable:1; - unsigned int format:1; /* 0:YCbCr, 1:RGB */ + unsigned int enable : 1; + unsigned int format : 1; /* 0:YCbCr, 1:RGB */ } b; } saturation_enable; /* 0x48 */ @@ -132,31 +132,31 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int enable:1; - unsigned int reserved:7; - unsigned int h264:1; + unsigned int enable : 1; + unsigned int reserved : 7; + unsigned int h264 : 1; } b; } mif; /* 0x80 */ unsigned int colfmt; /* 0x84, 0:422,1:420 */ unsigned int srcfmt; /* 0x88, 0:frame,1:field */ unsigned int dstfmt; /* 0x8C, 0:frame,1:field */ - unsigned int ysa; /* 0x90 */ + unsigned int ysa; /* 0x90 */ unsigned int csa; unsigned int pixwid; unsigned int bufwid; - unsigned int vcrop; /* 0xA0 */ + unsigned int vcrop; /* 0xA0 */ unsigned int hcrop; unsigned int fhi; - unsigned int colfmt2; /* 0xAC, 1-444,other refer 0x84 */ + unsigned int colfmt2; /* 0xAC, 1-444,other refer 0x84 */ unsigned int ysa2; /* 0xB0 */ unsigned int csa2; union { unsigned int val; struct { - unsigned int req_num:8; /* Y & RGB */ - unsigned int req_num_c:8; /* C */ - unsigned int frame_enable:1; + unsigned int req_num : 8; /* Y & RGB */ + unsigned int req_num_c : 8; /* C */ + unsigned int frame_enable : 1; } b; } mif_frame_mode; /* 0xB8 */ @@ -164,17 +164,17 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int update:1; - unsigned int reserved:7; - unsigned int level:1; /* 0:level 1, 1:level2 */ + unsigned int update : 1; + unsigned int reserved : 7; + unsigned int level : 1; /* 0:level 1, 1:level2 */ } b; } sts; /* 0xE4 */ union { unsigned int val; struct { - unsigned int fixed:1; /* 0-top, 1-bottom */ - unsigned int enable:1; + unsigned int fixed : 1; /* 0-top, 1-bottom */ + unsigned int enable : 1; } b; } swfld; /* 0xE8 */ @@ -183,9 +183,9 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int enable:1; - unsigned int reserved:7; - unsigned int mode:1; /* 0-frame,1-field */ + unsigned int enable : 1; + unsigned int reserved : 7; + unsigned int mode : 1; /* 0-frame,1-field */ } b; } tg_enable; /* 0x100 */ @@ -203,9 +203,9 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int offset:12; - unsigned int reserved:4; - unsigned int field_invert:1; + unsigned int offset : 12; + unsigned int reserved : 4; + unsigned int field_invert : 1; } b; } vsync_offset; /* 0x130 */ @@ -214,13 +214,11 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int mode:3; /* 011-frame packing progressive - format,111-frame packing interlace format */ - unsigned int inv_filed_polar:1; - unsigned int blank_value:16; - unsigned int reserved:11; - unsigned int addr_sel:1; /* in frame packing - interlace mode */ + unsigned int mode : 3; /* 011-frame packing progressive format,111-frame packing interlace format */ + unsigned int inv_filed_polar : 1; + unsigned int blank_value : 16; + unsigned int reserved : 11; + unsigned int addr_sel : 1; /* in frame packing interlace mode */ } b; } hdmi_3d; /* 0x13C */ @@ -228,16 +226,14 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int outwidth:1; /* 0-24bit,1-12bit */ - unsigned int hsync_polar:1; /* 0-act high,1-act low */ - unsigned int enable:1; - unsigned int vsync_polar:1; /* 0-act high,1-act low */ - unsigned int reserved:4; - unsigned int rgb_swap:2; /* 0-RGB[7:0],1-RGB[0:7], - 2-BGR[7:0],3-BGR[0:7] */ - unsigned int reserved2:6; - unsigned int blk_dis:1; /* 0-Blank Data, - 1-Embeded sync CCIR656 */ + unsigned int outwidth : 1; /* 0-24bit,1-12bit */ + unsigned int hsync_polar : 1; /* 0-active high,1-active low */ + unsigned int enable : 1; + unsigned int vsync_polar : 1; /* 0-active high,1-active low */ + unsigned int reserved : 4; + unsigned int rgb_swap : 2; /* 0-RGB[7:0],1-RGB[0:7],2-BGR[7:0],3-BGR[0:7] */ + unsigned int reserved2 : 6; + unsigned int blk_dis : 1; /* 0-Blank Data,1-Embeded sync CCIR656 */ } b; } dvo_set; /* 0x148 */ @@ -245,11 +241,11 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int enable:1; - unsigned int reserved1:7; - unsigned int mode:1; - unsigned int reserved2:7; - unsigned int inversion:1; + unsigned int enable : 1; + unsigned int reserved1 : 7; + unsigned int mode : 1; + unsigned int reserved2 : 7; + unsigned int inversion : 1; } b; } cb_enable; /* 0x150 */ @@ -267,17 +263,17 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int outwidth:1; /* 0-24bit,1-12bit */ - unsigned int hsync_polar:1; /* 0-act high,1-act low */ - unsigned int enable:1; - unsigned int vsync_polar:1; /* 0-act high,1-act low */ + unsigned int outwidth : 1; /* 0-24bit,1-12bit */ + unsigned int hsync_polar : 1; /* 0-active high,1-active low */ + unsigned int enable : 1; + unsigned int vsync_polar : 1; /* 0-active high,1-active low */ } b; } lvds_ctrl; /* 0x180 */ union { unsigned int val; struct { - unsigned int pix:2; /* 0-YUV444,1-RGB,2-YUV422,3-RGB */ + unsigned int pix : 2; /* 0-YUV444,1-RGB,2-YUV422,3-RGB */ } b; } lvds_ctrl2; /* 0x184 */ @@ -286,9 +282,9 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int praf:8; - unsigned int pbaf:8; - unsigned int yaf:8; + unsigned int praf : 8; + unsigned int pbaf : 8; + unsigned int yaf : 8; } b; } contrast; /* 0x1B8 */ @@ -304,45 +300,45 @@ struct govrh_regs { union { unsigned int val; struct { - unsigned int mode:1; /* 1: YUV2RGB, 0: RGB2YUV */ - unsigned int clamp:1; /* 0:Y,1:Y-16 */ + unsigned int mode : 1; /* 1: YUV2RGB, 0: RGB2YUV */ + unsigned int clamp : 1; /* 0:Y,1:Y-16 */ } b; } csc_mode; /* 0x1E0 */ union { unsigned int val; struct { - unsigned int dvo:1; - unsigned int vga:1; - unsigned int reserved1:1; - unsigned int dac_clkinv:1; - unsigned int blank_zero:1; - unsigned int disp:1; - unsigned int lvds:1; - unsigned int hdmi:1; - unsigned int rgb_mode:2; /*0-YUV,1-RGB24,2-1555,3-565*/ + unsigned int dvo : 1; + unsigned int vga : 1; + unsigned int reserved1 : 1; + unsigned int dac_clkinv : 1; + unsigned int blank_zero : 1; + unsigned int disp : 1; + unsigned int lvds : 1; + unsigned int hdmi : 1; + unsigned int rgb_mode : 2; /* 0-YUV, 1-RGB24, 2-1555, 3-565 */ } b; } yuv2rgb; /* 0x1E4 */ unsigned int h264_input_en; /* 0x1E8 */ unsigned int reserved9; - unsigned int lvds_clkinv; /* 0x1F0 */ + unsigned int lvds_clkinv; /* 0x1F0 */ unsigned int hscale_up; /* 0x1F4 */ union { unsigned int val; struct { - unsigned int mode:3; /* 0:888,1:555,2:666,3:565,4:ori */ - unsigned int reserved:5; - unsigned int ldi:1; /* 0:shift right,1:shift left */ + unsigned int mode : 3; /* 0:888,1:555,2:666,3:565,4:original */ + unsigned int reserved : 5; + unsigned int ldi : 1; /* 0:shift right,1:shift left */ } b; } igs_mode; /* 0x1F8 */ union { unsigned int val; struct { - unsigned int mode:3; /* 0:888,1:555,2:666,3:565,4:ori */ - unsigned int reserved:5; - unsigned int ldi:1; /* 0:shift right,1:shift left */ + unsigned int mode : 3; /* 0:888,1:555,2:666,3:565,4:original */ + unsigned int reserved : 5; + unsigned int ldi : 1; /* 0:shift right,1:shift left */ } b; } igs_mode2; /* 0x1FC */ }; diff --git a/drivers/video/wmt/hw/wmt-hdmi-reg.h b/drivers/video/wmt/hw/wmt-hdmi-reg.h index c0650555..919d6ab3 100755..100644 --- a/drivers/video/wmt/hw/wmt-hdmi-reg.h +++ b/drivers/video/wmt/hw/wmt-hdmi-reg.h @@ -2,7 +2,7 @@ * linux/drivers/video/wmt/hw/wmt-hdmi-reg.h * WonderMedia video post processor (VPP) driver * - * Copyright c 2014 WonderMedia Technologies, Inc. + * Copyright c 2013 WonderMedia Technologies, Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,354 +26,241 @@ #define WMT_FTBLK_HDMI -#define HDMI_BASE_ADDR (HDMI_TRANSMITTE_BASE_ADDR + 0xC000) - -struct hdmi_base1_regs { - unsigned int _100_11c[8]; - - union { - unsigned int val; - struct { - unsigned int eeprom_reset:1; - unsigned int encode_enable:1; - unsigned int hden:1; - unsigned int eess_enable:1; - unsigned int verify_pj_enable:1; - unsigned int i2c_enable:1; - unsigned int auth_test_key:1; - unsigned int _7:1; - unsigned int cipher_1_1:1; - unsigned int _9_11:3; - unsigned int preamble:4; - unsigned int _16_19:4; - unsigned int encode_window:3; - } b; - } ctrl; /* 0x120 */ - - union { - unsigned int val; - struct { - unsigned int _0_6:7; - unsigned int force_exit_fsm:1; - unsigned int key_read_word:7; - unsigned int i2c_sw_reset:1; - unsigned int i2c_clk_divider:16; - } b; - } i2c_ctrl; /* 0x124 */ - - union { - unsigned int val; - struct { - unsigned int wr_data:8; - unsigned int rd_data:8; - unsigned int sw_start_req:1; - unsigned int sw_stop_req:1; - unsigned int wr_data_avail:1; - unsigned int i2c_status:1; /* 0-not using,1-in using */ - unsigned int cp_key_req:1; - unsigned int cp_key_read:1; - unsigned int cp_key_last:1; - unsigned int _23:1; - unsigned int cp_src_sel:1; - unsigned int sw_read:1; - unsigned int sw_i2c_req:1; - unsigned int ksv_list_avail:1; - unsigned int ksv_verify_done:1; - } b; - } i2c_ctrl2; /* 0x128 */ - - unsigned int _12c_27c[85]; - - union { - unsigned int val; - struct { - unsigned int reset:1; - unsigned int enable:1; - unsigned int _2_5:4; - unsigned int dvi_mode_enable:1; - unsigned int output_format:2; /* 0-RGB, - 1-YUV444,2-YUV422 */ - unsigned int convert_yuv422:1; - unsigned int hsync_low_active:1; /* 0-active hi,1-lo */ - unsigned int dbg_bus_select:1; /* 0-before,1-after */ - unsigned int _12:1; - unsigned int vsync_low_active:1; /* 0-active hi,1-lo */ - unsigned int _14_15:2; - unsigned int cp_delay:7; - unsigned int _23:1; - unsigned int vsync_enable:3; /* write only */ - unsigned int state_machine_status:5; - } b; - } general_ctrl; /* 0x280 */ - - union { - unsigned int val; - struct { - unsigned int select:1; /* 0-fifo1,1-fifo2 */ - unsigned int fifo1_rdy:1; /* Info frame FIFO 1 ready */ - unsigned int fifo2_rdy:1; /* Info frame FIFO 2 ready */ - unsigned int _3:1; - unsigned int fifo1_addr:4; /* FIFO 1 start address */ - unsigned int fifo1_len:5; /* FIFO 1 length */ - unsigned int _13_15:3; - unsigned int fifo2_addr:4; /* FIFO 2 start address */ - unsigned int fifo2_len:5; /* FIFO 2 length */ - unsigned int _25_27:3; - unsigned int horiz_blank_max_pck:3; /* Max packets - that insert during HSYNC */ - } b; - } infoframe_ctrl; /* 0x284 */ - unsigned int _288_290[3]; - - union { - unsigned int val; - struct { - unsigned int pck_insert_reset:1; - unsigned int pck_insert_enable:1; - unsigned int avmute_set_enable:1; - unsigned int avmute_clr_enable:1; - unsigned int insert_delay:12; - unsigned int _16_29:14; - unsigned int pixel_repetition:2; /* 0-none,1-2x,2-4x */ - } b; - } aud_insert_ctrl; /* 0x294 */ - - unsigned int _298; - - union { - unsigned int val; - struct { - unsigned int _0_7:8; - unsigned int acr_ratio:20; - unsigned int acr_enable:1; - unsigned int mute:1; - } b; - } aud_ratio; /* 0x29c */ - - unsigned int aud_enable; /* 0x2a0 */ - unsigned int _2a4_2a8[2]; - - union { - unsigned int val; - struct { - unsigned int sub_packet:4; - unsigned int spflat:4; - unsigned int _2ch_eco:1; - unsigned int _9:1; - unsigned int layout:1; /* 0-2 channel,1-8 channel */ - unsigned int pwr_saving:1; /* 0-normal,1-power saving */ - } b; - } aud_mode; /* 0x2ac */ - - unsigned int _2b0_38c[56]; - unsigned int aud_chan_status0; /* 0x390 */ - unsigned int aud_chan_status1; /* 0x394 */ - unsigned int aud_chan_status2; /* 0x398 */ - unsigned int aud_chan_status3; /* 0x39c */ - unsigned int aud_chan_status4; /* 0x3a0 */ - unsigned int aud_chan_status5; /* 0x3a4 */ - - union { - unsigned int val; - struct { - unsigned int n_20bits:20; - unsigned int cts_low_12bits:12; - } b; - } aud_sample_rate1; /* 0x3a8 */ - - union { - unsigned int val; - struct { - unsigned int cts_hi_8bits:8; - unsigned int _8_27:20; - unsigned int aipclk_rate:2; /* 0-N/2,1-N,2-N/4,3-N*2 */ - unsigned int cts_select:1; /* 0-auto,1-fixed from reg */ - } b; - } aud_sample_rate2; /* 0x3ac */ - - unsigned int _3b0_3bc[4]; - unsigned int wr_fifo_addr[9]; /* 0x3c0 - 0x3e0 */ - - union { - unsigned int val; - struct { - unsigned int wr_strobe:1; - unsigned int rd_strobe:1; - unsigned int _2_7:6; - unsigned int addr:8; - } b; - } fifo_ctrl; /* 0x3e4 */ - - union { - unsigned int val; - struct { - unsigned int ch0_data:10; - unsigned int ch0_enable:1; - unsigned int _11_15:5; - unsigned int ch1_data:10; - unsigned int ch1_enable:1; - } b; - } channel_test; /* 0x3e8 */ - - union { - unsigned int val; - struct { - unsigned int ch2_data:10; - unsigned int ch2_enable:1; - unsigned int _11_15:5; - unsigned int in_enable:1; - unsigned int out_enable:1; - unsigned int _18_23:6; - unsigned int in_sts:1; - unsigned int out_sts:1; - unsigned int _26_30:5; - unsigned int sts:1; /* 0-plug out,1-plug in */ - } b; - } hotplug_detect; /* 0x3ec */ - - union { - unsigned int val; - struct { - unsigned int sample:8; - unsigned int _8_15:8; - unsigned int detect:9; - } b; - } hotplug_debounce; /* 0x3f0 */ - - unsigned int _3f4; - - union { - unsigned int val; - struct { - unsigned int test_enable:1; - unsigned int test_format:1; - unsigned int _2_9:8; - unsigned int infoframe_sram_enable:1; - unsigned int _11_15:5; - unsigned int clock_select:1; /* 0-clk 1x, 1-clk 2x */ - } b; - } tmds_ctrl; /* 0x3f8 */ - - unsigned int _3fc; - unsigned int rd_fifo_addr[9]; /* 0x400 - 0x420 */ -}; - -struct hdmi_base2_regs { - union { - unsigned int val; - struct { - unsigned int inv_clk:1; - unsigned int _1_3:3; - unsigned int dual_channel:1; - unsigned int _5_7:3; - unsigned int test:4; - unsigned int _12_18:7; - unsigned int internal_ldo:1; - } b; - } status; /* 0x00 */ - - union { - unsigned int val; - struct { - unsigned int drv_pdmode:1; - unsigned int _1:1; - unsigned int vbg_sel:2; - unsigned int _4_7:4; - unsigned int pd:1; - unsigned int tre_en:2; - unsigned int _11:1; - unsigned int pllck_dly:3; - unsigned int _15:1; - unsigned int pll_cpset:2; - unsigned int pll_r_f:1; - } b; - } test; /* 0x04 */ - - union { - unsigned int val; - struct { - unsigned int update:1; - unsigned int _1_7:7; - unsigned int level:1; - } b; - } level; /* 0x08 */ - - union { - unsigned int val; - struct { - unsigned int bpp_type:3; /* 0-888,1-555,2-666,3-565 */ - unsigned int _3_7:5; - unsigned int ldi_shift_left:1; /* 0-right,1-left */ - } b; - } igs; /* 0x0c */ - - union { - unsigned int val; - struct { - unsigned int out_data_12:1; /* 0-24bit,1-12bit */ - unsigned int hsync_polar_lo:1; /* 0-act hi,1-act low */ - unsigned int dvo_enable:1; - unsigned int vsync_polar_lo:1; /* 0-act hi,1-act low */ - } b; - } set; /* 0x10 */ - - union { - unsigned int val; - struct { - unsigned int colfmt_rgb:1;/* 0-RGB or YUV444,1-YUV422 */ - unsigned int colfmt_yuv422:1; - } b; - } set2; /* 0x14 */ - - union { - unsigned int val; - struct { - unsigned int pll_ready:1; - unsigned int _1_7:7; - unsigned int rsen:1; - } b; - } detect; /* 0x18 */ - - union { - unsigned int val; - struct { - unsigned int pll_tsync:1; - unsigned int tp2s_type:1; - unsigned int div_sel:2; - unsigned int pd_v2i:1; - unsigned int vco_sx:1; - unsigned int vco_mode:1; - unsigned int _7:1; - unsigned int vsref_sel:2; - unsigned int mode:1; - unsigned int pd_l2ha:1; - unsigned int pd_l2hb:1; - unsigned int l2ha_hsen:1; - unsigned int resa_en:1; - unsigned int resa_s:1; - unsigned int pll_lpfs:2; - } b; - } test2; /* 0x1c */ - - unsigned int test3; /* 0x20 */ - - union { - unsigned int val; - struct { - unsigned int _0_15:16; - unsigned int reset_pll:1; - } b; - } dftset2; /* 0x24 */ -}; - -#define REG_HDMI_BEGIN (HDMI_BASE_ADDR + 0x100) -#define REG_HDMI_END (HDMI_BASE_ADDR + 0x420) -#define REG_HDMI2_BEGIN (HDMI_BASE2_ADDR + 0x00) -#define REG_HDMI2_END (HDMI_BASE2_ADDR + 0x28) - -#ifndef HDMI_C -extern HW_REG struct hdmi_base1_regs *hdmi_regs1; -extern HW_REG struct hdmi_base2_regs *hdmi_regs2; -#endif +#define HDMI_BASE_ADDR (HDMI_TRANSMITTE_BASE_ADDR + 0xC000) + +/* HDMI registers */ +#define REG_HDMI_BEGIN (HDMI_BASE_ADDR + 0x100) +#define REG_HDMI_CTRL (HDMI_BASE_ADDR + 0x120) +#define REG_HDMI_I2C_CTRL (HDMI_BASE_ADDR + 0x124) +#define REG_HDMI_I2C_CTRL2 (HDMI_BASE_ADDR + 0x128) +#define REG_HDMI_GENERAL_CTRL (HDMI_BASE_ADDR + 0x280) +#define REG_HDMI_INFOFRAME_CTRL (HDMI_BASE_ADDR + 0x284) +#define REG_HDMI_AUD_INSERT_CTRL (HDMI_BASE_ADDR + 0x294) +#define REG_HDMI_AUD_RATIO (HDMI_BASE_ADDR + 0x29c) +#define REG_HDMI_AUD_ENABLE (HDMI_BASE_ADDR + 0x2a0) +#define REG_HDMI_AUD_MODE (HDMI_BASE_ADDR + 0x2ac) +#define REG_HDMI_AUD_CHAN_STATUS0 (HDMI_BASE_ADDR + 0x390) +#define REG_HDMI_AUD_CHAN_STATUS1 (HDMI_BASE_ADDR + 0x394) +#define REG_HDMI_AUD_CHAN_STATUS2 (HDMI_BASE_ADDR + 0x398) +#define REG_HDMI_AUD_CHAN_STATUS3 (HDMI_BASE_ADDR + 0x39c) +#define REG_HDMI_AUD_CHAN_STATUS4 (HDMI_BASE_ADDR + 0x3a0) +#define REG_HDMI_AUD_CHAN_STATUS5 (HDMI_BASE_ADDR + 0x3a4) +#define REG_HDMI_AUD_SAMPLE_RATE1 (HDMI_BASE_ADDR + 0x3a8) +#define REG_HDMI_AUD_SAMPLE_RATE2 (HDMI_BASE_ADDR + 0x3ac) + +/* HDMI info WR FIFO 0x3c0 - 0x3e0 */ +#define REG_HDMI_WR_FIFO_ADDR (HDMI_BASE_ADDR + 0x3c0) +#define REG_HDMI_FIFO_CTRL (HDMI_BASE_ADDR + 0x3e4) +#define REG_HDMI_CHANNEL_TEST (HDMI_BASE_ADDR + 0x3e8) +#define REG_HDMI_HOTPLUG_DETECT (HDMI_BASE_ADDR + 0x3ec) +#define REG_HDMI_HOTPLUG_DEBOUNCE (HDMI_BASE_ADDR + 0x3f0) +#define REG_HDMI_TMDS_CTRL (HDMI_BASE_ADDR + 0x3f8) + +/* HDMI info RD FIFO 0x400 - 0x420 */ +#define REG_HDMI_RD_FIFO_ADDR (HDMI_BASE_ADDR + 0x400) + +#define REG_HDMI_END (HDMI_BASE_ADDR + 0x420) + +/* REG_HDMI_CTRL,0x120 */ +#define HDMI_EEPROM_RESET REG_HDMI_CTRL, BIT0, 0 +#define HDMI_ENCODE_ENABLE REG_HDMI_CTRL, BIT1, 1 +#define HDMI_HDEN REG_HDMI_CTRL, BIT2, 2 +#define HDMI_EESS_ENABLE REG_HDMI_CTRL, BIT3, 3 +#define HDMI_VERIFY_PJ_ENABLE REG_HDMI_CTRL, BIT4, 4 +#define HDMI_I2C_ENABLE REG_HDMI_CTRL, BIT5, 5 +#define HDMI_AUTH_TEST_KEY REG_HDMI_CTRL, BIT6, 6 +#define HDMI_CIPHER_1_1 REG_HDMI_CTRL, BIT8, 8 +#define HDMI_PREAMBLE REG_HDMI_CTRL, 0xF000, 12 +#define HDMI_ENCODE_WINDOW REG_HDMI_CTRL, 0x700000, 20 + +/* REG_HDMI_I2C_CTRL,0x124 */ +#define HDMI_FORCE_EXIT_FSM REG_HDMI_I2C_CTRL, BIT7, 7 +#define HDMI_KEY_READ_WORD REG_HDMI_I2C_CTRL, 0xFF00, 8 +#define HDMI_I2C_SW_RESET REG_HDMI_I2C_CTRL, 0x8000, 15 +#define HDMI_I2C_CLK_DIVIDER REG_HDMI_I2C_CTRL, 0xFFFF0000, 16 + +/* REG_HDMI_I2C_CTRL2,0x128 */ +#define HDMI_WR_DATA REG_HDMI_I2C_CTRL2, 0xFF, 0 +#define HDMI_RD_DATA REG_HDMI_I2C_CTRL2, 0xFF00, 8 +#define HDMI_SW_START_REQ REG_HDMI_I2C_CTRL2, BIT16, 16 +#define HDMI_SW_STOP_REQ REG_HDMI_I2C_CTRL2, BIT17, 17 +#define HDMI_WR_DATA_AVAIL REG_HDMI_I2C_CTRL2, BIT18, 18 +#define HDMI_I2C_STATUS REG_HDMI_I2C_CTRL2, BIT19, 19 /* 0-not using, 1-in using */ +#define HDMI_CP_KEY_REQ REG_HDMI_I2C_CTRL2, BIT20, 20 +#define HDMI_CP_KEY_READ REG_HDMI_I2C_CTRL2, BIT21, 21 +#define HDMI_CP_KEY_LAST REG_HDMI_I2C_CTRL2, BIT22, 22 +#define HDMI_CP_SRC_SEL REG_HDMI_I2C_CTRL2, BIT24, 24 +#define HDMI_SW_READ REG_HDMI_I2C_CTRL2, BIT25, 25 +#define HDMI_SW_I2C_REQ REG_HDMI_I2C_CTRL2, BIT26, 26 +#define HDMI_KSV_LIST_AVAIL REG_HDMI_I2C_CTRL2, BIT27, 27 +#define HDMI_KSV_VERIFY_DONE REG_HDMI_I2C_CTRL2, BIT28, 28 + +/* REG_HDMI_GENERAL_CTRL,0x280 */ +#define HDMI_RESET REG_HDMI_GENERAL_CTRL, BIT0, 0 +#define HDMI_ENABLE REG_HDMI_GENERAL_CTRL, BIT1, 1 +#define HDMI_DVI_MODE_ENABLE REG_HDMI_GENERAL_CTRL, BIT6, 6 +#define HDMI_OUTPUT_FORMAT REG_HDMI_GENERAL_CTRL, 0x180, 7 /* 0-RGB,1-YUV444,2-YUV422 */ +#define HDMI_CONVERT_YUV422 REG_HDMI_GENERAL_CTRL, BIT9, 9 +#define HDMI_HSYNC_LOW_ACTIVE REG_HDMI_GENERAL_CTRL, BIT10, 10 /* 0-active high,1-active low */ +#define HDMI_DBG_BUS_SELECT REG_HDMI_GENERAL_CTRL, BIT11, 11 /* 0-before,1-after */ +#define HDMI_VSYNC_LOW_ACTIVE REG_HDMI_GENERAL_CTRL, BIT13, 13 /* 0-active high,1-active low */ +#define HDMI_CP_DELAY REG_HDMI_GENERAL_CTRL, 0x7F0000, 16 /* delay for CP after HSYNC raising edge */ +#define HDMI_VSYNC_384_ENABLE REG_HDMI_GENERAL_CTRL, BIT24, 24 +#define HDMI_VSYNC_385_507_ENABLE REG_HDMI_GENERAL_CTRL, BIT25, 25 +#define HDMI_VSYNC_650_ENABLE REG_HDMI_GENERAL_CTRL, BIT26, 26 +#define HDMI_STATE_MACHINE_STATUS REG_HDMI_GENERAL_CTRL, 0xF8000000, 27 + +/* REG_HDMI_INFOFRAME_CTRL,0x284 */ +#define HDMI_INFOFRAME_SELECT REG_HDMI_INFOFRAME_CTRL, BIT0, 0 /* 0-fifo1,1-fifo2 */ +#define HDMI_INFOFRAME_FIFO1_RDY REG_HDMI_INFOFRAME_CTRL, BIT1, 1 /* Info frame FIFO 1 ready */ +#define HDMI_INFOFRAME_FIFO2_RDY REG_HDMI_INFOFRAME_CTRL, BIT2, 2 /* Info frame FIFO 2 ready */ +#define HDMI_INFOFRAME_FIFO1_ADDR REG_HDMI_INFOFRAME_CTRL, 0xF0, 4 /* Info frame FIFO 1 start address */ +#define HDMI_INFOFRAME_FIFO1_LEN REG_HDMI_INFOFRAME_CTRL, 0x1F00, 8 /* Info frame FIFO 1 length */ +#define HDMI_INFOFRAME_FIFO2_ADDR REG_HDMI_INFOFRAME_CTRL, 0xF0000, 16 /* Info frame FIFO 2 start address */ +#define HDMI_INFOFRAME_FIFO2_LEN REG_HDMI_INFOFRAME_CTRL, 0x1F00000, 20 /* Info frame FIFO 2 length */ +#define HDMI_HORIZ_BLANK_MAX_PCK REG_HDMI_INFOFRAME_CTRL, 0x70000000, 28 /* Max packets that insert during HSYNC */ + +/* REG_HDMI_AUD_INSERT_CTRL,0x294 */ +#define HDMI_AUD_PCK_INSERT_RESET REG_HDMI_AUD_INSERT_CTRL, BIT0, 0 +#define HDMI_AUD_PCK_INSERT_ENABLE REG_HDMI_AUD_INSERT_CTRL, BIT1, 1 +#define HDMI_AVMUTE_SET_ENABLE REG_HDMI_AUD_INSERT_CTRL, BIT2, 2 +#define HDMI_AVMUTE_CLR_ENABLE REG_HDMI_AUD_INSERT_CTRL, BIT3, 3 +#define HDMI_AUD_INSERT_DELAY REG_HDMI_AUD_INSERT_CTRL, 0xFFF0, 4 +#define HDMI_AUD_PIXEL_REPETITION REG_HDMI_AUD_INSERT_CTRL, 0xC0000000, 30 /* 0-none,1-2 times,2-4 times */ + +/* REG_HDMI_AUD_RATIO,0x29c */ +#define HDMI_AUD_ACR_RATIO REG_HDMI_AUD_RATIO, 0x0FFFFF00, 8 +#define HDMI_AUD_ACR_ENABLE REG_HDMI_AUD_RATIO, BIT28, 28 +#define HDMI_AUD_MUTE REG_HDMI_AUD_RATIO, BIT29, 29 + +/* REG_HDMI_AUD_ENABLE,0x2a0 */ +#define HDMI_AUD_ENABLE REG_HDMI_AUD_ENABLE, BIT0, 0 + +/* REG_HDMI_AUD_MODE,0x2ac */ +#define HDMI_AUD_SUB_PACKET REG_HDMI_AUD_MODE, 0xF, 0 +#define HDMI_AUD_SPFLAT REG_HDMI_AUD_MODE, 0xF0, 4 +#define HDMI_AUD_2CH_ECO REG_HDMI_AUD_MODE, BIT8, 8 +#define HDMI_AUD_LAYOUT REG_HDMI_AUD_MODE, BIT10, 10 /* 0-2 channel,1-8 channel */ +#define HDMI_AUD_PWR_SAVING REG_HDMI_AUD_MODE, BIT11, 11 /* 0-normal, 1-power saving */ + +/* REG_HDMI_AUD_CHAN_STATUS0,0x390 */ +/* REG_HDMI_AUD_CHAN_STATUS1,0x394 */ +/* REG_HDMI_AUD_CHAN_STATUS2,0x398 */ +/* REG_HDMI_AUD_CHAN_STATUS3,0x39c */ +/* REG_HDMI_AUD_CHAN_STATUS4,0x3a0 */ +/* REG_HDMI_AUD_CHAN_STATUS5,0x3a4 */ + +/* REG_HDMI_AUD_SAMPLE_RATE1,0x3a8 */ +#define HDMI_AUD_N_20BITS REG_HDMI_AUD_SAMPLE_RATE1, 0xFFFFF, 0 +#define HDMI_AUD_CTS_LOW_12BITS REG_HDMI_AUD_SAMPLE_RATE1, 0xFFF00000, 20 + +/* REG_HDMI_AUD_SAMPLE_RATE2,0x3ac */ +#define HDMI_AUD_CTS_HI_8BITS REG_HDMI_AUD_SAMPLE_RATE2, 0xFF, 0 +#define HDMI_AUD_AIPCLK_RATE REG_HDMI_AUD_SAMPLE_RATE2, 0x30000000, 28 /* 0-N/2,1-N,2-N/4,3-N*2 */ +#define HDMI_AUD_CTS_SELECT REG_HDMI_AUD_SAMPLE_RATE2, BIT30, 30 /* 0-auto, 1-fixed from register */ + +/* 0x3c0 - 0x3e0 : Info frame FIFO data */ + +/* REG_HDMI_FIFO_CTRL,0x3e4 */ +#define HDMI_INFOFRAME_WR_STROBE REG_HDMI_FIFO_CTRL, BIT0, 0 +#define HDMI_INFOFRAME_RD_STROBE REG_HDMI_FIFO_CTRL, BIT1, 1 +#define HDMI_INFOFRAME_FIFO_ADDR REG_HDMI_FIFO_CTRL, 0xFF00, 8 + +/* REG_HDMI_CHANNEL_TEST,0x3e8 */ +#define HDMI_CH1_TEST_MODE_ENABLE REG_HDMI_CHANNEL_TEST, BIT26, 26 +#define HDMI_CH1_TEST_DATA REG_HDMI_CHANNEL_TEST, 0x3FF0000, 16 +#define HDMI_CH0_TEST_MODE_ENABLE REG_HDMI_CHANNEL_TEST, BIT10, 10 +#define HDMI_CH0_TEST_DATA REG_HDMI_CHANNEL_TEST, 0x3FF, 0 + +/* REG_HDMI_HOTPLUG_DETECT,0x3ec */ +#define HDMI_HOTPLUG_IN REG_HDMI_HOTPLUG_DETECT, BIT31, 31 /* 0-plug out,1-plug in */ +#define HDMI_HOTPLUG_OUT_STS REG_HDMI_HOTPLUG_DETECT, BIT25, 25 +#define HDMI_HOTPLUG_IN_STS REG_HDMI_HOTPLUG_DETECT, BIT24, 24 +#define HDMI_HOTPLUG_OUT_INT REG_HDMI_HOTPLUG_DETECT, BIT17, 17 +#define HDMI_HOTPLUG_IN_INT REG_HDMI_HOTPLUG_DETECT, BIT16, 16 +#define HDMI_CH2_TEST_MODE_ENABLE REG_HDMI_HOTPLUG_DETECT, BIT10, 10 +#define HDMI_CH2_TEST_DATA REG_HDMI_HOTPLUG_DETECT, 0x3FF, 0 + +/* REG_HDMI_HOTPLUG_DEBOUNCE,0x3f0 */ +#define HDMI_DEBOUNCE_DETECT REG_HDMI_HOTPLUG_DEBOUNCE, 0x1FF0000, 16 +#define HDMI_DEBOUNCE_SAMPLE REG_HDMI_HOTPLUG_DEBOUNCE, 0xFF, 0 + +/* REG_HDMI_TMDS_CTRL,0x3f8 */ +#define HDMI_CLOCK_SELECT REG_HDMI_TMDS_CTRL, BIT16, 16 /* 0-clk 1x, 1-clk 2x */ +#define HDMI_INFOFRAME_SRAM_ENABLE REG_HDMI_TMDS_CTRL, BIT10, 10 +#define HDMI_TMDS_TST_FORMAT REG_HDMI_TMDS_CTRL, BIT1, 1 +#define HDMI_TMDS_TST_ENABLE REG_HDMI_TMDS_CTRL, BIT0, 0 + +/* 0x400 - 0x420 : HDMI info frame FIFO data (RO) */ + +#define REG_HDMI2_BEGIN (HDMI_BASE2_ADDR + 0x00) +#define REG_HDMI_STATUS (HDMI_BASE2_ADDR + 0x00) +#define REG_HDMI_TEST (HDMI_BASE2_ADDR + 0x04) +#define REG_HDMI_LEVEL (HDMI_BASE2_ADDR + 0x08) +#define REG_HDMI_IGS (HDMI_BASE2_ADDR + 0x0C) +#define REG_HDMI_SET (HDMI_BASE2_ADDR + 0x10) +#define REG_HDMI_SET2 (HDMI_BASE2_ADDR + 0x14) +#define REG_HDMI_DETECT (HDMI_BASE2_ADDR + 0x18) +#define REG_HDMI_TEST2 (HDMI_BASE2_ADDR + 0x1C) +#define REG_HDMI_TEST3 (HDMI_BASE2_ADDR + 0x20) +#define REG_HDMI_DFTSET2 (HDMI_BASE2_ADDR + 0x24) +#define REG_HDMI2_END (HDMI_BASE2_ADDR + 0x28) + +/* REG_HDMI_STATUS,0x00 */ +#define HDMI_INTERNAL_LDO REG_HDMI_STATUS, 0x80000, 19 +#define HDMI_TEST REG_HDMI_STATUS, 0xF00, 8 +#define HDMI_DUAL_CHANNEL REG_HDMI_STATUS, BIT4, 4 +#define HDMI_INV_CLK REG_HDMI_STATUS, BIT0, 0 + +/* REG_HDMI_TEST,0x04 */ +#define HDMI_PLL_R_F REG_HDMI_TEST, BIT18, 18 +#define HDMI_PLL_CPSET REG_HDMI_TEST, 0x30000, 16 +#define HDMI_PLLCK_DLY REG_HDMI_TEST, 0x7000, 12 +#define HDMI_TRE_EN REG_HDMI_TEST, 0x600, 9 +#define HDMI_PD REG_HDMI_TEST, BIT8, 8 +#define HDMI_VBG_SEL REG_HDMI_TEST, 0xC, 2 +#define HDMI_DRV_PDMODE REG_HDMI_TEST, BIT0, 0 + +/* REG_HDMI_LEVEL,0x08 */ +#define HDMI_REG_LEVEL REG_HDMI_LEVEL, BIT8, 8 +#define HDMI_REG_UPDATE REG_HDMI_LEVEL, BIT0, 0 + +/* REG_HDMI_IGS,0x0C */ +#define HDMI_LDI_SHIFT_LEFT REG_HDMI_IGS, BIT8, 8 /* 0-shift right,1-shift left */ +#define HDMI_IGS_BPP_TYPE REG_HDMI_IGS, 0x7, 0 /* 0-888,1-555,2-666,3-565 */ + +/* REG_HDMI_SET,0x10 */ +#define HDMI_VSYNC_POLAR_LO REG_HDMI_SET, BIT3, 3 /* 0-active high,1-active low */ +#define HDMI_DVO_ENABLE REG_HDMI_SET, BIT2, 2 +#define HDMI_HSYNC_POLAR_LO REG_HDMI_SET, BIT1, 1 /* 0-active high,1-active low */ +#define HDMI_OUT_DATA_12 REG_HDMI_SET, BIT0, 0 /* 0-24bit,1-12bit */ + +/* REG_HDMI_SET2,0x14 */ +#define HDMI_COLFMT_YUV422 REG_HDMI_SET2, BIT1, 1 /* 0-RGB or YUV444,1-YUV422 */ +#define HDMI_COLFMT_RGB REG_HDMI_SET2, BIT0, 0 + +/* REG_HDMI_DETECT,0x18 */ +#define HDMI_RSEN REG_HDMI_DETECT, BIT8, 8 +#define HDMI_PLL_READY REG_HDMI_DETECT, BIT0, 0 + +/* REG_HDMI_TEST2,0x1C */ +#define HDMI_PLL_TSYNC REG_HDMI_TEST2, BIT0, 0 +#define HDMI_TP2S_TYPE REG_HDMI_TEST2, BIT1, 1 +#define HDMI_DIV_SEL REG_HDMI_TEST2, 0xC, 2 +#define HDMI_PD_V2I REG_HDMI_TEST2, BIT4, 4 +#define HDMI_VCO_SX REG_HDMI_TEST2, BIT5, 5 +#define HDMI_VCO_MODE REG_HDMI_TEST2, BIT6, 6 +#define HDMI_VSREF_SEL REG_HDMI_TEST2, 0x300, 8 +#define HDMI_MODE REG_HDMI_TEST2, BIT10, 10 +#define HDMI_PD_L2HA REG_HDMI_TEST2, BIT11, 11 +#define HDMI_PD_L2HB REG_HDMI_TEST2, BIT12, 12 +#define HDMI_L2HA_HSEN REG_HDMI_TEST2, BIT13, 13 +#define HDMI_RESA_EN REG_HDMI_TEST2, BIT14, 14 +#define HDMI_RESA_S REG_HDMI_TEST2, BIT15, 15 +#define HDMI_PLL_LPFS REG_HDMI_TEST2, 0x30000, 16 + +/* REG_HDMI_DFTSET2,0x24 */ +#define HDMI_RESET_PLL REG_HDMI_DFTSET2, BIT16, 16 + #endif /* WMT_HDMI_REG_H */ diff --git a/drivers/video/wmt/hw/wmt-lvds-reg.h b/drivers/video/wmt/hw/wmt-lvds-reg.h index 0a6e616c..d258d6e8 100755..100644 --- a/drivers/video/wmt/hw/wmt-lvds-reg.h +++ b/drivers/video/wmt/hw/wmt-lvds-reg.h @@ -2,7 +2,7 @@ * linux/drivers/video/wmt/hw/wmt-lvds-reg.h * WonderMedia video post processor (VPP) driver * - * Copyright c 2014 WonderMedia Technologies, Inc. + * Copyright c 2013 WonderMedia Technologies, Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,104 +26,67 @@ #define WMT_FTBLK_LVDS -struct lvds_base_regs { - union { - unsigned int val; - struct { - unsigned int inv_clk:1; - unsigned int _01_03:3; - unsigned int dual_channel:1; - unsigned int _05_07:3; - unsigned int test:4; - } b; - } status; /* 0x00 */ +#define REG_LVDS_BEGIN (LVDS_BASE_ADDR + 0x00) +#define REG_LVDS_STATUS (LVDS_BASE_ADDR + 0x00) +#define REG_LVDS_TEST (LVDS_BASE_ADDR + 0x04) +#define REG_LVDS_LEVEL (LVDS_BASE_ADDR + 0x08) +#define REG_LVDS_IGS (LVDS_BASE_ADDR + 0x0C) +#define REG_LVDS_SET (LVDS_BASE_ADDR + 0x10) +#define REG_LVDS_SET2 (LVDS_BASE_ADDR + 0x14) +#define REG_LVDS_DETECT (LVDS_BASE_ADDR + 0x18) +#define REG_LVDS_TEST2 (LVDS_BASE_ADDR + 0x1C) +#define REG_LVDS_END (LVDS_BASE_ADDR + 0x1C) - union { - unsigned int val; - struct { - unsigned int drv_pdmode:1; - unsigned int _01:1; - unsigned int vbg_sel:2; - unsigned int _04_07:4; - unsigned int pd:1; - unsigned int tre_en:2; - unsigned int _11:1; - unsigned int pllck_dly:3; - unsigned int _15:1; - unsigned int pll_cpset:2; - unsigned int pll_r_f:1; - } b; - } test; /* 0x04 */ +/* REG_LVDS_STATUS,0x00 */ +#define LVDS_TEST REG_LVDS_STATUS, 0xF00, 8 +#define LVDS_DUAL_CHANNEL REG_LVDS_STATUS, BIT4, 4 +#define LVDS_INV_CLK REG_LVDS_STATUS, BIT0, 0 - union { - unsigned int val; - struct { - unsigned int update:1; - unsigned int _01_07:7; - unsigned int level:1; - } b; - } level; /* 0x08 */ +/* REG_LVDS_TEST,0x04 */ +#define LVDS_PLL_R_F REG_LVDS_TEST, BIT18, 18 +#define LVDS_PLL_CPSET REG_LVDS_TEST, 0x30000, 16 +#define LVDS_PLLCK_DLY REG_LVDS_TEST, 0x7000, 12 +#define LVDS_TRE_EN REG_LVDS_TEST, 0x600, 9 +#define LVDS_PD REG_LVDS_TEST, BIT8, 8 +#define LVDS_VBG_SEL REG_LVDS_TEST, 0xC, 2 +#define LVDS_DRV_PDMODE REG_LVDS_TEST, BIT0, 0 - union { - unsigned int val; - struct { - unsigned int bpp_type:3; /* 0-888,1-555,2-666,3-565 */ - unsigned int _03_07:5; - unsigned int ldi_shift_left:1; /* 0-shift right,1-left*/ - } b; - } igs; /* 0x0c */ +/* REG_LVDS_LEVEL,0x08 */ +#define LVDS_REG_LEVEL REG_LVDS_LEVEL, BIT8, 8 +#define LVDS_REG_UPDATE REG_LVDS_LEVEL, BIT0, 0 - union { - unsigned int val; - struct { - unsigned int out_data_12:1; /* 0-24bit,1-12bit */ - unsigned int hsync_polar_lo:1; /* 0-active hi,1-low */ - unsigned int dvo_enable:1; - unsigned int vsync_polar_lo:1; /* 0-active hi,1-low */ - } b; - } set; /* 0x10 */ +/* REG_LVDS_IGS,0x0C */ +#define LVDS_LDI_SHIFT_LEFT REG_LVDS_IGS, BIT8, 8 /* 0-shift right,1-shift left */ +#define LVDS_IGS_BPP_TYPE REG_LVDS_IGS, 0x7, 0 /* 0-888,1-555,2-666,3-565 */ - union { - unsigned int val; - struct { - unsigned int colfmt:2; /* 0-YUV444,1/3-RGB,2-YUV422 */ - } b; - } set2; /* 0x14 */ +/* REG_LVDS_SET,0x10 */ +#define LVDS_VSYNC_POLAR_LO REG_LVDS_SET, BIT3, 3 /* 0-active high,1-active low */ +#define LVDS_DVO_ENABLE REG_LVDS_SET, BIT2, 2 +#define LVDS_HSYNC_POLAR_LO REG_LVDS_SET, BIT1, 1 /* 0-active high,1-active low */ +#define LVDS_OUT_DATA_12 REG_LVDS_SET, BIT0, 0 /* 0-24bit,1-12bit */ - union { - unsigned int val; - struct { - unsigned int pll_ready:1; - unsigned int _01_07:7; - unsigned int rsen:1; - } b; - } detect; /* 0x18 */ +/* REG_LVDS_SET2,0x14 */ +#define LVDS_COLFMT_YUV422 REG_LVDS_SET2, BIT1, 1 /* 0-RGB or YUV444,1-YUV422 */ +#define LVDS_COLFMT_RGB REG_LVDS_SET2, BIT0, 0 - union { - unsigned int val; - struct { - unsigned int pll_tsync:1; - unsigned int tp2s_type:1; - unsigned int div_sel:2; - unsigned int pd_v2i:1; - unsigned int vco_sx:1; - unsigned int vco_mode:1; - unsigned int _07:1; - unsigned int vsref_sel:2; - unsigned int mode:1; - unsigned int pd_l2ha:1; - unsigned int pd_l2hb:1; - unsigned int l2ha_hsen:1; - unsigned int resa_en:1; - unsigned int resa_s:1; - unsigned int pll_lpfs:2; - } b; - } test2; /* 0x1c */ -}; +/* REG_LVDS_DETECT,0x18 */ +#define LVDS_RSEN REG_LVDS_DETECT, BIT8, 8 +#define LVDS_PLL_READY REG_LVDS_DETECT, BIT0, 0 + +/* REG_LVDS_TEST2,0x1C */ +#define LVDS_PLL_TSYNC REG_LVDS_TEST2, BIT0, 0 +#define LVDS_TP2S_TYPE REG_LVDS_TEST2, BIT1, 1 +#define LVDS_DIV_SEL REG_LVDS_TEST2, 0xC, 2 +#define LVDS_PD_V2I REG_LVDS_TEST2, BIT4, 4 +#define LVDS_VCO_SX REG_LVDS_TEST2, BIT5, 5 +#define LVDS_VCO_MODE REG_LVDS_TEST2, BIT6, 6 +#define LVDS_VSREF_SEL REG_LVDS_TEST2, 0x300, 8 +#define LVDS_MODE REG_LVDS_TEST2, BIT10, 10 +#define LVDS_PD_L2HA REG_LVDS_TEST2, BIT11, 11 +#define LVDS_PD_L2HB REG_LVDS_TEST2, BIT12, 12 +#define LVDS_L2HA_HSEN REG_LVDS_TEST2, BIT13, 13 +#define LVDS_RESA_EN REG_LVDS_TEST2, BIT14, 14 +#define LVDS_RESA_S REG_LVDS_TEST2, BIT15, 15 +#define LVDS_PLL_LPFS REG_LVDS_TEST2, 0x30000, 16 -#define REG_LVDS_BEGIN (LVDS_BASE_ADDR + 0x00) -#define REG_LVDS_END (LVDS_BASE_ADDR + 0x1C) -#ifndef LVDS_C -extern struct lvds_base_regs *lvds_regs; -#endif #endif /* WMT_LVDS_REG_H */ diff --git a/drivers/video/wmt/hw/wmt-scl-reg.h b/drivers/video/wmt/hw/wmt-scl-reg.h index 773fad96..cabb75a7 100755..100644 --- a/drivers/video/wmt/hw/wmt-scl-reg.h +++ b/drivers/video/wmt/hw/wmt-scl-reg.h @@ -2,7 +2,7 @@ * linux/drivers/video/wmt/hw/wmt-scl-reg.h * WonderMedia video post processor (VPP) driver * - * Copyright c 2014 WonderMedia Technologies, Inc. + * Copyright c 2013 WonderMedia Technologies, Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,511 +33,342 @@ #define WMT_SCL_V_DIV_MAX 8192 #define WMT_SCL_FB_WIDTH_MAX 8192 -#define WMT_SCL_SCALE_DST_H_MAX 1920 /* bypass no limit */ - -struct scl_base1_regs { - union { - unsigned int val; - struct { - unsigned int alu_enable:1; - } b; - } en; /* 0x0 */ - - union { - unsigned int val; - struct { - unsigned int reg_update:1; - } b; - } upd; /* 0x04 */ - - union { - unsigned int val; - struct { - unsigned int reg_level:1; - } b; - } sel; /* 0x08 */ - - unsigned int _0c_38[12]; - - union { - unsigned int val; - struct { - unsigned int hxwidth:13; - } b; - } hxwidth; /* 0x3c */ - - union { - unsigned int val; - struct { - unsigned int mif_en:1; - unsigned int _01_03:3; - unsigned int rgb_mode:2; /* 0-YUV,1-RGB565,3-RGB32 */ - unsigned int _06_07:2; - unsigned int _420c_fmt:1; /* 0-frame,1-field */ - unsigned int vfmt:3; /* 0-YUV422,1-YUV420, - 2-YUV444,4-RGB32 */ - unsigned int h264_fmt:1; /* 0-MPEG,1-H264 */ - unsigned int _13_15:3; - unsigned int iofmt:1; /* 0-frame,1-field */ - unsigned int _17_23:7; - unsigned int color_en:1; /* 0-disable,1-enable */ - unsigned int color_wide:1; /* 0-Normal,1-Wider */ - unsigned int color_inv:1; /* 0-Normal,1-Opposite color*/ - } b; - } r2_ctl; /* 0x40 */ - - unsigned int r2_ysa; /* 0x44 */ - unsigned int r2_csa; /* 0x48 */ - - union { - unsigned int val; - struct { - unsigned int fbw:13; /* frame buffer width pixel */ - unsigned int _13_15:3; - unsigned int lnsize:13; /* line width pixel */ - } b; - } r2_h_size; /* 0x4c */ - - union { - unsigned int val; - struct { - unsigned int hcrop:13; - unsigned int _13_15:3; - unsigned int vcrop:13; - } b; - } r2_crop; /* 0x50 */ - - union { - unsigned int val; - struct { - unsigned int src:2; /* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */ - unsigned int _02_07:6; - unsigned int dst:2; /* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */ - unsigned int _09_15:6; - unsigned int swap:1; /* 0-(alpha,1-a),1:(1-a,alpha) */ - } b; - } alpha_md; /* 0x54 */ - - union { - unsigned int val; - struct { - unsigned int src_fixed:8; - unsigned int dst_fixed:8; - } b; - } alpha_fxd; /* 0x58 */ - - union { - unsigned int val; - struct { - unsigned int enable:1; - unsigned int _01_07:7; - unsigned int from:1; /* 0-RMIF1,1-RMIF2 */ - unsigned int _09_15:7; - unsigned int comp:2; /* 0-888,1-777,2-666,3-555 */ - unsigned int _17_23:7; - unsigned int mode:3; /* (Non-Hit,Hit):0/1-(alpha,alpha), - 2-(alpha,pix1),3-(pix1,alpha),4-(alpha,pix2), - 5-(pix2,alpha),6-(pix1,pix2),7-(pix2,pix1) */ - } b; - } alpha_colorkey; /* 0x5c */ - - union { - unsigned int val; - struct { - unsigned int r:8; - unsigned int g:8; - unsigned int b:8; - } b; - } alpha_colorkey_rgb; /* 0x60 */ - - unsigned int _64_6c[3]; - - union { - unsigned int val; - struct { - unsigned int vxwidth:13; - unsigned int _13_15:3; - unsigned int dst_vxwidth:13; - } b; - } vxwidth; /* 0x70 */ - - union { - unsigned int val; - struct { - unsigned int h:1; - unsigned int _01_15:15; - unsigned int v:1; - } b; - } sclup_en; /* 0x74 */ - - union { - unsigned int val; - struct { - unsigned int thr:13; - unsigned int _13_15:3; - unsigned int substep:13; - } b; - } vscale1; /* 0x78 */ - - union { - unsigned int val; - struct { - unsigned int substepcnt:13; - unsigned int _13_15:3; - unsigned int step:13; - } b; - } vscale2; /* 0x7c */ - - union { - unsigned int val; - struct { - unsigned int stepcnt:17; - } b; - } vscale3; /* 0x80 */ - - union { - unsigned int val; - struct { - unsigned int thr:13; - unsigned int _13_15:3; - unsigned int substep:13; - } b; - } hscale1; /* 0x84 */ - - union { - unsigned int val; - struct { - unsigned int substepcnt:13; - unsigned int _13_15:3; - unsigned int step:13; - } b; - } hscale2; /* 0x88 */ - - union { - unsigned int val; - struct { - unsigned int stepcnt:17; - } b; - } hscale3; /* 0x8c */ - - union { - unsigned int val; - struct { - unsigned int y_req_num:8; - unsigned int c_req_num:8; - } b; - } r_req_num; /* 0x90 */ - - unsigned int scldw; /* 0x94 */ /* (VPU path, scale dn) - 0 - bilinear mode, quality better */ - unsigned int sw_426; /* 0x98 */ /* 1-follow 426, 0-437 */ - unsigned int vbypass; /* 0x9c */ - - union { - unsigned int val; - struct { - unsigned int enable:1; - unsigned int _1_3:3; - unsigned int err_off:1; /*disable TG_EN in tg timeout*/ - unsigned int _5_7:3; - unsigned int watchdog_enable:1; - unsigned int _9_15:7; - unsigned int rdcyc:8; - unsigned int oneshot:1; /* sacling complete will set - SCL tg enable to 0 */ - } b; - } tg_ctl; /* 0xa0 */ - - union { - unsigned int val; - struct { - unsigned int h_allpixel:13; - unsigned int _13_15:3; - unsigned int v_allline:13; - } b; - } tg_total; /* 0xa4 */ - - union { - unsigned int val; - struct { - unsigned int v_actbg:8; - unsigned int _8_15:8; - unsigned int v_actend:13; - } b; - } tg_v_active; /* 0xa8 */ - - union { - unsigned int val; - struct { - unsigned int h_actbg:10; - unsigned int _10_15:6; - unsigned int h_actend:13; - } b; - } tg_h_active; /* 0xac */ - - union { - unsigned int val; - struct { - unsigned int vbie:7; - unsigned int _7:1; - unsigned int pvbi:5; - } b; - } tg_vbi; /* 0xb0 */ - - unsigned int tg_watchdog; /* 0xb4 */ - - union { - unsigned int val; - struct { - unsigned int tgerr:1; - } b; - } tg_sts; /* 0xb8 */ - - union { - unsigned int val; - struct { - unsigned int enable:1; - } b; - } tg_govw; /* 0xbc */ - - union { - unsigned int val; - struct { - unsigned int mif_enable:1; /*0:Disable, 1:Enable */ - unsigned int _1_3:3; - unsigned int rgb_mode:2; /*0:YC,1:RGB565,3:RGB32 */ - unsigned int _6_7:2; - unsigned int src_disp_fmt:1; /*420C 0:Frame, 1:Field */ - unsigned int yuv:2; /*0:422,1:420,2:444*/ - unsigned int rgb:1; /*0:YCbCr, 1:RGB32 */ - unsigned int h264:1; /*0:MPEG, 1:H264 */ - unsigned int _13_15:3; - unsigned int field:1; /*0:Frame, 1:Field */ - unsigned int _17_23:7; - unsigned int colorbar_enable:1; - unsigned int colorbar_mode:1; - unsigned int colorbar_inv:1; - } b; - } r_ctl; /* 0xc0 */ - - unsigned int r_ysa; /* 0xc4 */ - unsigned int r_csa; /* 0xc8 */ - - union { - unsigned int val; - struct { - unsigned int fb_w:13; - unsigned int _13_15:3; - unsigned int pix_w:13; - } b; - } r_h_size; /* 0xcc */ - - union { - unsigned int val; - struct { - unsigned int hcrop:13; - unsigned int _13_15:3; - unsigned int vcrop:13; - } b; - } r_crop; /* 0xd0 */ - - union { - unsigned int val; - struct { - unsigned int thr:4; - unsigned int _4_7:4; - unsigned int r1_mif_err:1; - unsigned int r2_mif_err:1; - } b; - } r_fifo_ctl; /* 0xd4 */ - - unsigned int _d8_dc[2]; - - union { - unsigned int val; - struct { - unsigned int mif_enable:1; - unsigned int _1_7:7; - unsigned int yuv:1; /* 0-444,1-422 */ - unsigned int rgb:1; /* 0-YC,1-RGB32 */ - } b; - } w_ctl; /* 0xe0 */ - - unsigned int w_ysa; /* 0xe4 */ - unsigned int w_csa; /* 0xe8 */ - - union { - unsigned int val; - struct { - unsigned int fb_w:13; - unsigned int _13_15:3; - unsigned int pxl_w:13; - } b; - } w_y_time; /* 0xec */ - - union { - unsigned int val; - struct { - unsigned int fb_w:13; - unsigned int _13_15:3; - unsigned int pxl_w:12; - } b; - } w_c_time; /* 0xf0 */ - - union { - unsigned int val; - struct { - unsigned int mif_c_err:1; - unsigned int _1_7:7; - unsigned int mif_y_err:1; - unsigned int _9_15:7; - unsigned int mif_rgb_err:1; - } b; - } w_ff_ctl; /* 0xf4 */ - - union { - unsigned int val; - struct { - unsigned int mif_c_err:1; - unsigned int mif_y_err:1; - unsigned int mif_rgb_err:1; - unsigned int _3_7:5; - unsigned int r2_mif_enable:1; - unsigned int r1_mif_enable:1; - unsigned int _10_15:6; - unsigned int tg_err:1; - } b; - } w_int_en; /* 0xf8 */ - - union { - unsigned int val; - struct { - unsigned int h:1; - unsigned int _1_7:7; - unsigned int v:1; - } b; - } true_bilinear; /* 0xfc */ -}; - -struct scl_base2_regs { - union { - unsigned int val; - struct { - unsigned int mode:1; /* 0-RGB2YC,1-YC2RGB */ - unsigned int _01_07:7; - unsigned int clamp_enable:1; /* clamp to 16-235 */ - unsigned int _09_15:7; - unsigned int enable:1; - } b; - } csc_ctl; /* 0x0 */ - - unsigned int csc1; /* 0x4 */ - unsigned int csc2; /* 0x8 */ - unsigned int csc3; /* 0xc */ - unsigned int csc4; /* 0x10 */ - unsigned int csc5; /* 0x14 */ - unsigned int csc6; /* 0x18 */ - - union { - unsigned int val; - struct { - unsigned int enable:1; - unsigned int _01_07:7; - unsigned int data:8; - } b; - } argb_alpha; /* 0x1c */ - - union { - unsigned int val; - struct { - unsigned int mode:2; /* 0-888,1-555,2-666,3-565 */ - } b; - } igs; /* 0x20 */ - - union { - unsigned int val; - struct { - unsigned int mode:1; /* 0-CCIR/ITU-601 */ - unsigned int _01_07:7; - unsigned int clamp:1; /* 0-direct,1-16-235 */ - unsigned int _09_15:7; - unsigned int enable:1; - } b; - } r2_csc; /* 0x24 */ - - unsigned int r2_csc1; /* 0x28 */ - unsigned int r2_csc2; /* 0x2c */ - unsigned int r2_csc3; /* 0x30 */ - unsigned int r2_csc4; /* 0x34 */ - unsigned int r2_csc5; /* 0x38 */ - unsigned int r2_csc6; /* 0x3c */ - unsigned int _40_9c[24]; - - union { - unsigned int val; - struct { - unsigned int h:1; - unsigned int _01_07:7; - unsigned int v:1; - } b; - } recursive_mode; /* 0xa0 */ - - unsigned int _a4_bc[7]; - - union { - unsigned int val; - struct { - unsigned int deblock:1; - unsigned int field_deflicker:1; - unsigned int frame_deflicker:1; - } b; - } field_mode; /* 0xc0 */ - - union { - unsigned int val; - struct { - unsigned int layer1_boundary:8; - unsigned int layer2_boundary:8; - } b; - } dblk_threshold; /* 0xc4 */ - - union { - unsigned int val; - struct { - unsigned int condition:1; /* 0-up or down,1-up & down */ - unsigned int _01_07:7; - unsigned int y_thd:8; - unsigned int c_thd:8; - } b; - } field_flicker; /* 0xc8 */ - union { - unsigned int val; - struct { - unsigned int rgb:1; /* 0-Y,1-RGB */ - unsigned int _01_07:7; - unsigned int sampler:5; /* 2^x */ - unsigned int _13_15:3; - unsigned int scene_chg_thd:8; - } b; - } frame_flicker; /* 0xcc */ - - union { - unsigned int val; - struct { - unsigned int rdcyc_1t:1; - } b; - } readcyc_1t; /* 0xd0 */ - - unsigned int _d4_e0[4]; -}; +#define WMT_SCL_SCALE_DST_H_MAX 1920 /* bypass no limit */ +/* registers */ #define REG_SCL_BASE1_BEGIN (SCL_BASE_ADDR + 0x00) +#define REG_SCL_EN (SCL_BASE_ADDR + 0x00) +#define REG_SCL_UPD (SCL_BASE_ADDR + 0x04) +#define REG_SCL_SEL (SCL_BASE_ADDR + 0x08) +#define REG_SCL_HXWIDTH (SCL_BASE_ADDR + 0x3c) +#define REG_SCLR2_CTL (SCL_BASE_ADDR + 0x40) +#define REG_SCLR2_YSA (SCL_BASE_ADDR + 0x44) +#define REG_SCLR2_CSA (SCL_BASE_ADDR + 0x48) +#define REG_SCLR2_H_SIZE (SCL_BASE_ADDR + 0x4C) +#define REG_SCLR2_CROP (SCL_BASE_ADDR + 0x50) +#define REG_ALFA_MD (SCL_BASE_ADDR + 0x54) +#define REG_ALFA_FXD (SCL_BASE_ADDR + 0x58) +#define REG_ALFA_COLORKEY (SCL_BASE_ADDR + 0x5C) +#define REG_ALFA_COLORKEY_RGB (SCL_BASE_ADDR + 0x60) +#define REG_SCL_VXWIDTH (SCL_BASE_ADDR + 0x70) +#define REG_SCL_SCLUP_EN (SCL_BASE_ADDR + 0x74) + +#define REG_SCL_VSCALE1 (SCL_BASE_ADDR + 0x78) +#define REG_SCL_VSCALE2 (SCL_BASE_ADDR + 0x7c) +#define REG_SCL_VSCALE3 (SCL_BASE_ADDR + 0x80) +#define REG_SCL_HSCALE1 (SCL_BASE_ADDR + 0x84) +#define REG_SCL_HSCALE2 (SCL_BASE_ADDR + 0x88) +#define REG_SCL_HSCALE3 (SCL_BASE_ADDR + 0x8c) +#define REG_SCLR_REQ_NUM (SCL_BASE_ADDR + 0x90) +#define REG_SCL_SCLDW (SCL_BASE_ADDR + 0x94) +#define REG_SCL_426_SW (SCL_BASE_ADDR + 0x98) +#define REG_SCL_VBYPASS (SCL_BASE_ADDR + 0x9C) +/* SCL_TG */ +#define REG_SCL_TG_CTL (SCL_BASE_ADDR + 0xa0) +#define REG_SCL_TG_TOTAL (SCL_BASE_ADDR + 0xa4) +#define REG_SCL_TG_V_ACTIVE (SCL_BASE_ADDR + 0xa8) +#define REG_SCL_TG_H_ACTIVE (SCL_BASE_ADDR + 0xac) +#define REG_SCL_TG_VBI (SCL_BASE_ADDR + 0xb0) +#define REG_SCL_TG_WATCHDOG (SCL_BASE_ADDR + 0xb4) +#define REG_SCL_TG_STS (SCL_BASE_ADDR + 0xb8) +#define REG_SCL_TG_GOVW (SCL_BASE_ADDR + 0xbc) +/* SCLR */ +#define REG_SCLR_CTL (SCL_BASE_ADDR + 0xc0) +#define REG_SCLR_YSA (SCL_BASE_ADDR + 0xc4) +#define REG_SCLR_CSA (SCL_BASE_ADDR + 0xc8) +#define REG_SCLR_H_SIZE (SCL_BASE_ADDR + 0xcc) +#define REG_SCLR_CROP (SCL_BASE_ADDR + 0xd0) +#define REG_SCLR_FIFO_CTL (SCL_BASE_ADDR + 0xd4) +/* SCLW */ +#define REG_SCLW_CTL (SCL_BASE_ADDR + 0xe0) +#define REG_SCLW_YSA (SCL_BASE_ADDR + 0xe4) +#define REG_SCLW_CSA (SCL_BASE_ADDR + 0xe8) +#define REG_SCLW_Y_TIME (SCL_BASE_ADDR + 0xec) +#define REG_SCLW_C_TIME (SCL_BASE_ADDR + 0xf0) +#define REG_SCLW_FF_CTL (SCL_BASE_ADDR + 0xf4) +#define REG_SCLW_INT (SCL_BASE_ADDR + 0xf8) +#define REG_SCL_TRUE_BILINEAR (SCL_BASE_ADDR + 0xfc) + #define REG_SCL_BASE1_END (SCL_BASE_ADDR + 0xFC) + +/* SCL444 CSC */ #define REG_SCL_BASE2_BEGIN (SCL_BASE2_ADDR + 0x00) +#define REG_SCL_CSC_CTL (SCL_BASE2_ADDR + 0x00) +#define REG_SCL_CSC1 (SCL_BASE2_ADDR + 0x04) +#define REG_SCL_CSC2 (SCL_BASE2_ADDR + 0x08) +#define REG_SCL_CSC3 (SCL_BASE2_ADDR + 0x0c) +#define REG_SCL_CSC4 (SCL_BASE2_ADDR + 0x10) +#define REG_SCL_CSC5 (SCL_BASE2_ADDR + 0x14) +#define REG_SCL_CSC6 (SCL_BASE2_ADDR + 0x18) +#define REG_SCL_ARGB_ALPHA (SCL_BASE2_ADDR + 0x1C) +#define REG_SCL_IGS (SCL_BASE2_ADDR + 0x20) +#define REG_SCL_R2_CSC (SCL_BASE2_ADDR + 0x24) +#define REG_SCL_R2_CSC1 (SCL_BASE2_ADDR + 0x28) +#define REG_SCL_R2_CSC2 (SCL_BASE2_ADDR + 0x2C) +#define REG_SCL_R2_CSC3 (SCL_BASE2_ADDR + 0x30) +#define REG_SCL_R2_CSC4 (SCL_BASE2_ADDR + 0x34) +#define REG_SCL_R2_CSC5 (SCL_BASE2_ADDR + 0x38) +#define REG_SCL_R2_CSC6 (SCL_BASE2_ADDR + 0x3C) +#define REG_SCL_RECURSIVE_MODE (SCL_BASE2_ADDR + 0xA0) +#define REG_SCL_FIELD_MODE (SCL_BASE2_ADDR + 0xC0) +#define REG_SCL_DBLK_THRESHOLD (SCL_BASE2_ADDR + 0xC4) +#define REG_SCL_FIELD_FLICKER (SCL_BASE2_ADDR + 0xC8) +#define REG_SCL_FRAME_FLICKER (SCL_BASE2_ADDR + 0xCC) +#define REG_SCL_READCYC_1T (SCL_BASE2_ADDR + 0xD0) #define REG_SCL_BASE2_END (SCL_BASE2_ADDR + 0xE0) -#ifndef SCL_C -extern HW_REG struct scl_base1_regs *scl_regs1; -extern HW_REG struct scl_base2_regs *scl_regs2; -#endif +/* REG_SCL_EN,0x00 */ +#define SCL_ALU_ENABLE REG_SCL_EN, BIT0, 0 + +/* REG_SCL_UPD,0x04 */ +#define SCL_REG_UPDATE REG_SCL_UPD, BIT0, 0 + +/* REG_SCL_SEL,0x08 */ +#define SCL_REG_LEVEL REG_SCL_SEL, BIT0, 0 + +/* REG_SCL_HXWIDTH,0x3c */ +#define SCL_HXWIDTH REG_SCL_HXWIDTH, 0x1FFF, 0 + +/* REG_SCLR2_CTL,0x40 */ +#define SCL_R2_MIF_EN REG_SCLR2_CTL, BIT0, 0 +#define SCL_R2_RGB_MODE REG_SCLR2_CTL, 0x30, 4 /* 0-YUV,1-RGB565,3-RGB32 */ +#define SCL_R2_420C_FMT REG_SCLR2_CTL, BIT8, 8 /* 0-frame,1-field */ +#define SCL_R2_VFMT REG_SCLR2_CTL, 0xE00, 9 /* 0-YUV422,1-YUV420,2-YUV444,4-RGB32 */ +#define SCL_R2_H264_FMT REG_SCLR2_CTL, BIT12, 12 /* 0-MPEG,1-H264 */ +#define SCL_R2_IOFMT REG_SCLR2_CTL, BIT16, 16 /* 0-frame,1-field */ +#define SCL_R2_COLOR_EN REG_SCLR2_CTL, BIT24, 24 /* 0-disable,1-enable */ +#define SCL_R2_COLOR_WIDE REG_SCLR2_CTL, BIT25, 25 /* 0-Normal,1-Wider */ +#define SCL_R2_COLOR_INV REG_SCLR2_CTL, BIT26, 26 /* 0-Normal,1-Opposite color */ + +/* REG_SCLR2_YSA,0x44 */ +/* REG_SCLR2_CSA,0x48 */ + +/* REG_SCLR2_H_SIZE,0x4C */ +#define SCL_R2_FBW REG_SCLR2_H_SIZE, 0x1FFF, 0 /* frame buffer width pixel */ +#define SCL_R2_LNSIZE REG_SCLR2_H_SIZE, 0x1FFF0000, 16 /* line width pixel */ + +/* REG_SCLR2_CROP,0x50 */ +#define SCL_R2_HCROP REG_SCLR2_CROP, 0x1FFF, 0 +#define SCL_R2_VCROP REG_SCLR2_CROP, 0x1FFF0000, 16 + +/* REG_ALFA_MD,0x54 */ +#define SCL_ALPHA_SRC REG_ALFA_MD, 0x3, 0 /* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */ +#define SCL_ALPHA_DST REG_ALFA_MD, 0x300, 8 /* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */ +#define SCL_ALPHA_SWAP REG_ALFA_MD, 0x10000, 16 /* 0-(alpha,1-alpha),1:(1-alpha,alpha) */ + +/* REG_ALFA_FXD,0x58 */ +#define SCL_ALPHA_SRC_FIXED REG_ALFA_FXD, 0xFF, 0 +#define SCL_ALPHA_DST_FIXED REG_ALFA_FXD, 0xFF00, 8 + +/* REG_ALFA_COLORKEY,0x5C */ +#define SCL_ALPHA_COLORKEY_ENABLE REG_ALFA_COLORKEY, BIT0, 0 +#define SCL_ALPHA_COLORKEY_FROM REG_ALFA_COLORKEY, BIT8, 8 /* 0-RMIF1,1-RMIF2 */ +#define SCL_ALPHA_COLORKEY_COMP REG_ALFA_COLORKEY, 0x30000, 16 /* 0-888,1-777,2-666,3-555 */ +#define SCL_ALPHA_COLORKEY_MODE REG_ALFA_COLORKEY, 0x7000000, 24 /* (Non-Hit,Hit):0/1-(alpha,alpha), + 2-(alpha,pix1),3-(pix1,alpha),4-(alpha,pix2), + 5-(pix2,alpha),6-(pix1,pix2),7-(pix2,pix1) */ + +/* REG_ALFA_COLORKEY_RGB,0x60 */ +#define SCL_ALPHA_COLORKEY_R REG_ALFA_COLORKEY_RGB, 0xFF, 0 +#define SCL_ALPHA_COLORKEY_G REG_ALFA_COLORKEY_RGB, 0xFF00, 8 +#define SCL_ALPHA_COLORKEY_B REG_ALFA_COLORKEY_RGB, 0xFF0000, 16 + +/* REG_SCL_VXWIDTH,0x70 */ +#define SCL_VXWIDTH REG_SCL_VXWIDTH, 0x1FFF, 0 +#define SCL_DST_VXWIDTH REG_SCL_VXWIDTH, 0x1FFF0000, 16 + +/* REG_SCL_SCLUP_EN,0x74 */ +#define SCL_VSCLUP_ENABLE REG_SCL_SCLUP_EN, BIT16, 16 +#define SCL_HSCLUP_ENABLE REG_SCL_SCLUP_EN, BIT0, 0 + +/* REG_SCL_VSCALE1,0x78 */ +#define SCL_V_SUBSTEP REG_SCL_VSCALE1, 0x1FFF0000, 16 +#define SCL_V_THR REG_SCL_VSCALE1, 0x1FFF, 0 + +/* REG_SCL_VSCALE2,0x7c */ +#define SCL_V_STEP REG_SCL_VSCALE2, 0x1FFF0000, 16 +#define SCL_V_I_SUBSTEPCNT REG_SCL_VSCALE2, 0x1FFF, 0 + +/* REG_SCL_VSCALE3,0x80 */ +#define SCL_V_I_STEPCNT REG_SCL_VSCALE3, 0x1FFFF, 0 + +/* REG_SCL_HSCALE1,0x84 */ +#define SCL_H_SUBSTEP REG_SCL_HSCALE1, 0x1FFF0000, 16 +#define SCL_H_THR REG_SCL_HSCALE1, 0x1FFF, 0 + +/* REG_SCL_HSCALE2,0x88 */ +#define SCL_H_STEP REG_SCL_HSCALE2, 0x1FFF0000, 16 +#define SCL_H_I_SUBSTEPCNT REG_SCL_HSCALE2, 0x1FFF, 0 + +/* REG_SCL_HSCALE3,0x8c */ +#define SCL_H_I_STEPCNT REG_SCL_HSCALE3, 0x1FFFF, 0 + +/* REG_SCLR_REQ_NUM,0x90 */ +#define SCL_R_C_REQ_NUM REG_SCLR_REQ_NUM, 0xFF, 0 +#define SCL_R_Y_REQ_NUM REG_SCLR_REQ_NUM, 0xFF00, 8 + +/* REG_SCL_SCLDW,0x94 */ +#define SCL_SCLDW_METHOD REG_SCL_SCLDW, BIT0, 0 /* (VPU path, scale dn) 0 - bilinear mode, quality better */ + +/* REG_SCL_426_SW,0x98 */ +#define SCL_426_SW REG_SCL_426_SW, BIT0, 0 /* 1-follow 426, 0-437 */ + +/* REG_SCL_VBYPASS,0x9C */ +#define SCL_VBYPASS REG_SCL_VBYPASS, BIT0, 0 + +/* SCL_TG */ +/* REG_SCL_TG_CTL,0xa0 */ +#define SCL_ONESHOT_ENABLE REG_SCL_TG_CTL, BIT24, 24 /* sacling complete will set SCL tg enable to 0 */ +#define SCL_TG_RDCYC REG_SCL_TG_CTL, 0xFF0000, 16 +#define SCL_TG_WATCHDOG_ENABLE REG_SCL_TG_CTL, BIT8, 8 +#define SCL_TG_ERR_OFF REG_SCL_TG_CTL, BIT4, 4 /* disable TG_EN whtn tg timeout */ +#define SCL_TG_ENABLE REG_SCL_TG_CTL, BIT0, 0 + +/* REG_SCL_TG_TOTAL,0xa4 */ +#define SCL_TG_V_ALLLINE REG_SCL_TG_TOTAL, 0x1FFF0000, 16 +#define SCL_TG_H_ALLPIXEL REG_SCL_TG_TOTAL, 0x1FFF, 0 + +/* REG_SCL_TG_V_ACTIVE,0xa8 */ +#define SCL_TG_V_ACTEND REG_SCL_TG_V_ACTIVE, 0x1FFF0000, 16 +#define SCL_TG_V_ACTBG REG_SCL_TG_V_ACTIVE, 0xFF, 0 + +/* REG_SCL_TG_H_ACTIVE,0xac */ +#define SCL_TG_H_ACTEND REG_SCL_TG_H_ACTIVE, 0x1FFF0000, 16 +#define SCL_TG_H_ACTBG REG_SCL_TG_H_ACTIVE, 0x3FF, 0 + +/* REG_SCL_TG_VBI,0xb0 */ +#define SCL_TG_PVBI REG_SCL_TG_VBI, 0x1F00, 8 +#define SCL_TG_VBIE REG_SCL_TG_VBI, 0x7F, 0 + +/* REG_SCL_TG_WATCHDOG,0xb4 */ +#define SCL_TG_WATCHDOG_VALUE REG_SCL_TG_WATCHDOG, 0xFFFFFFFF, 0 + +/* REG_SCL_TG_STS,0xb8 */ +#define SCL_INTSTS_TGERR REG_SCL_TG_STS, BIT0, 0 + +/* REG_SCL_TG_GOVW,0xbc */ +#define SCL_TG_GOVWTG_ENABLE REG_SCL_TG_GOVW, BIT0, 0 + +/* SCLR */ +/* REG_SCL_MIF_CTL,0xc0 */ +#define SCLR_COLBAR_INVERSION REG_SCLR_CTL, BIT26, 26 +#define SCLR_COLBAR_MODE REG_SCLR_CTL, BIT25, 25 +#define SCLR_COLBAR_ENABLE REG_SCLR_CTL, BIT24, 24 +#define SCLR_TAR_DISP_FMT REG_SCLR_CTL, BIT16, 16 /*0:Frame, 1:Field */ +#define SCLR_MEDIAFMT_H264 REG_SCLR_CTL, BIT12, 12 /*0:MPEG, 1:H264 */ +#define SCLR_COLFMT_RGB REG_SCLR_CTL, BIT11, 11 /*0:YCbCr, 1:RGB32 */ +#define SCLR_COLFMT_YUV REG_SCLR_CTL, 0x600, 9 /*0:422,1:420,2:444*/ +#define SCLR_SRC_DISP_FMT REG_SCLR_CTL, BIT8, 8 /*420C 0:Frame, 1:Field */ +#define SCLR_RGB_MODE REG_SCLR_CTL, 0x30, 4 /*0:YC,1:RGB565,3:RGB32 */ +#define SCLR_MIF_ENABLE REG_SCLR_CTL, BIT0, 0 /*0:Disable, 1:Enable */ + +/* REG_SCLR_YSA,0xc4 */ + +/* REG_SCLR_CSA,0xc8 */ + +/* REG_SCLR_H_SIZE,0xcc */ +#define SCLR_YPXLWID REG_SCLR_H_SIZE, 0x1FFF0000, 16 +#define SCLR_YBUFWID REG_SCLR_H_SIZE, 0x1FFF, 0 + +/* REG_SCLR_CROP,0xd0 */ +#define SCLR_VCROP REG_SCLR_CROP, 0x1FFF0000, 16 +#define SCLR_HCROP REG_SCLR_CROP, 0x1FFF, 0 + +/* REG_SCLR_FIFO_CTL,0xd4 (W:0xf4) */ +#define SCLR_INTSTS_R2MIFERR REG_SCLR_FIFO_CTL, BIT9, 9 +#define SCLR_INTSTS_R1MIFERR REG_SCLR_FIFO_CTL, BIT8, 8 +#define SCLR_FIFO_THR REG_SCLR_FIFO_CTL, 0xF, 0 + +/* SCL_W */ +/* REG_SCLW_CTL,0xe0 */ +#define SCLW_COLFMT_RGB REG_SCLW_CTL, BIT9, 9 /* 0-YC,1-RGB32 */ +#define SCLW_COLFMT_YUV REG_SCLW_CTL, BIT8, 8 /* 0-444,1-422 */ +#define SCLW_MIF_ENABLE REG_SCLW_CTL, BIT0, 0 + +/* REG_SCLW_YSA,0xe4 */ + +/* REG_SCLW_CSA,0xe8 */ + +/* REG_SCLW_Y_TIME,0xec */ +#define SCLW_YPXLWID REG_SCLW_Y_TIME, 0x1FFF0000, 16 +#define SCLW_YBUFWID REG_SCLW_Y_TIME, 0x1FFF, 0 + +/* REG_SCLW_C_TIME,0xf0 */ +#define SCLW_CPXLWID REG_SCLW_C_TIME, 0xFFF0000, 16 +#define SCLW_CBUFWID REG_SCLW_C_TIME, 0x1FFF, 0 + +/* REG_SCLW_FF_CTL,0xf4 (R:0xd4) */ +#define SCLW_INTSTS_MIFRGBERR REG_SCLW_FF_CTL, BIT16, 16 +#define SCLW_INTSTS_MIFYERR REG_SCLW_FF_CTL, BIT8, 8 +#define SCLW_INTSTS_MIFCERR REG_SCLW_FF_CTL, BIT0, 0 + +/* REG_SCLW_INT,0xf8 */ +#define SCLW_INT_TGERR_ENABLE REG_SCLW_INT, BIT16, 16 +#define SCLW_INT_R1MIF_ENABLE REG_SCLW_INT, BIT9, 9 +#define SCLW_INT_R2MIF_ENABLE REG_SCLW_INT, BIT8, 8 +#define SCLW_INT_WMIFRGB_ENABLE REG_SCLW_INT, BIT2, 2 +#define SCLW_INT_WMIFYERR_ENABLE REG_SCLW_INT, BIT1, 1 +#define SCLW_INT_WMIFCERR_ENABLE REG_SCLW_INT, BIT0, 0 + +/* REG_SCL_TRUE_BILINEAR,0xfc */ +#define SCL_BILINEAR_H REG_SCL_TRUE_BILINEAR, BIT0, 0 +#define SCL_BILINEAR_V REG_SCL_TRUE_BILINEAR, BIT8, 8 + +/* SCL Base2 */ +/* REG_SCL_CSC_CTL,0x00 */ +#define SCL_CSC_ENABLE REG_SCL_CSC_CTL, BIT16, 16 +#define SCL_CSC_CLAMP_ENABLE REG_SCL_CSC_CTL, BIT8, 8 /* clamp to 16-235 */ +#define SCL_CSC_MODE REG_SCL_CSC_CTL, BIT0, 0 /* 0-RGB2YC,1-YC2RGB */ + +/* REG_SCL_CSC1,0x04 */ +/* REG_SCL_CSC2,0x08 */ +/* REG_SCL_CSC3,0x0c */ +/* REG_SCL_CSC4,0x10 */ +/* REG_SCL_CSC5,0x14 */ +/* REG_SCL_CSC6,0x18 */ + +/* REG_SCL_ARGB_ALPHA,0x1C */ +#define SCL_FIXED_ALPHA_ENABLE REG_SCL_ARGB_ALPHA, BIT0, 0 +#define SCL_FIXED_ALPHA_DATA REG_SCL_ARGB_ALPHA, 0xFF00, 8 + +/* REG_SCL_IGS,0x20 */ +#define SCL_IGS_MODE REG_SCL_IGS, 0x3, 0 /* 0-888,1-555,2-666,3-565 */ + +/* REG_SCL_R2_CSC,0x24 */ +#define SCL_R2_CSC_MODE REG_SCL_R2_CSC, BIT0, 0 /* 0-CCIR/ITU-601 */ +#define SCL_R2_CSC_CLAMP_EN REG_SCL_R2_CSC, BIT8, 8 /* 0-direct,1-16-235 */ +#define SCL_R2_CSC_EN REG_SCL_R2_CSC, BIT16, 16 + +/* REG_SCL_R2_CSC1,0x28 */ +/* REG_SCL_R2_CSC2,0x2C */ +/* REG_SCL_R2_CSC3,0x30 */ +/* REG_SCL_R2_CSC4,0x34 */ +/* REG_SCL_R2_CSC5,0x38 */ +/* REG_SCL_R2_CSC6,0x3C */ + +/* REG_SCL_RECURSIVE_MODE,0xA0 */ +#define SCL_RECURSIVE_H REG_SCL_RECURSIVE_MODE, BIT0, 0 +#define SCL_RECURSIVE_V REG_SCL_RECURSIVE_MODE, BIT8, 8 + +/* REG_SCL_FIELD_MODE,0xC0 */ +#define SCL_DEBLOCK_ENABLE REG_SCL_FIELD_MODE, BIT0, 0 +#define SCL_FIELD_DEFLICKER REG_SCL_FIELD_MODE, BIT1, 1 +#define SCL_FRAME_DEFLICKER REG_SCL_FIELD_MODE, BIT2, 2 + +/* REG_SCL_DBLK_THRESHOLD,0xC4 */ +#define SCL_1ST_LAYER_BOUNDARY REG_SCL_DBLK_THRESHOLD, 0xFF, 0 +#define SCL_2ND_LAYER_BOUNDARY REG_SCL_DBLK_THRESHOLD, 0xFF00, 8 + +/* REG_SCL_FIELD_FLICKER,0xC8 */ +#define SCL_FIELD_FILTER_CONDITION REG_SCL_FIELD_FLICKER, BIT0, 0 /* 0-up or down,1-up and down */ +#define SCL_FIELD_FILTER_Y_THD REG_SCL_FIELD_FLICKER, 0xFF00, 8 +#define SCL_FIELD_FILTER_C_THD REG_SCL_FIELD_FLICKER, 0xFF0000, 16 + +/* REG_SCL_FRAME_FLICKER,0xCC */ +#define SCL_FRAME_FILTER_RGB REG_SCL_FRAME_FLICKER, BIT0, 0 /* 0-Y,1-RGB */ +#define SCL_FRAME_FILTER_SAMPLER REG_SCL_FRAME_FLICKER, 0x1F00, 8 /* 2^x */ +#define SCL_FR_FILTER_SCENE_CHG_THD REG_SCL_FRAME_FLICKER, 0xFF0000, 16 + +/* REG_SCL_READCYC_1T,0xD0 */ +#define SCL_READCYC_1T REG_SCL_READCYC_1T,BIT0,0 #endif /* WMT_SCL_REG_H */ diff --git a/drivers/video/wmt/hw/wmt-vpp-hw.h b/drivers/video/wmt/hw/wmt-vpp-hw.h index 599ebe03..b3d3a7ad 100755..100644 --- a/drivers/video/wmt/hw/wmt-vpp-hw.h +++ b/drivers/video/wmt/hw/wmt-vpp-hw.h @@ -2,7 +2,7 @@ * linux/drivers/video/wmt/hw/wmt-vpp-hw.h * WonderMedia video post processor (VPP) driver * - * Copyright c 2014 WonderMedia Technologies, Inc. + * Copyright c 2013 WonderMedia Technologies, Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -85,37 +85,35 @@ #define VPP_IRQ_GOVR2_TG IRQ_VPP_IRQ25 /* DVI I2C */ -#define VPP_DVI_I2C_DEFAULT 1 /* default i2c bus */ -#define VPP_DVI_I2C_SW_BIT 0x10 /* hw or sw i2c */ -#define VPP_DVI_I2C_ID_MASK 0x1F -#define VPP_DVI_I2C_ID g_vpp.dvi_i2c_no -#define VPP_DVI_EDID_ID (VPP_DVI_I2C_SW_BIT + 0x1) /* DVO EDID use - sw i2c bus 1 */ +#define VPP_DVI_I2C_BIT 0x80 /* use sw id that can vary */ +#define VPP_DVI_I2C_SW_BIT 0x10 /* hw or sw i2c */ +#define VPP_DVI_I2C_ID_MASK 0x1F +#define VPP_DVI_I2C_ID (VPP_DVI_I2C_BIT + 0x1) +#define VPP_DVI_EDID_ID (VPP_DVI_I2C_SW_BIT + 0x1) /* DVO EDID use sw i2c bus 1 */ /* vout */ -#define VPP_VOUT_INFO_NUM 5 /* linux fb or govr number */ +#define VPP_VOUT_INFO_NUM 2 /* linux fb or govr number */ -#define VPP_VOUT_NUM 2 -#define VPP_VOUT_ALL 0xFFFFFFFF -#define VPP_VOUT_NUM_HDMI 0 -#define VPP_VOUT_NUM_LVDS 1 -#define VPP_VOUT_NUM_DVI 1 +#define VPP_VOUT_NUM 2 +#define VPP_VOUT_ALL 0xFFFFFFFF +#define VPP_VOUT_NUM_HDMI 0 +#define VPP_VOUT_NUM_LVDS 1 +#define VPP_VOUT_NUM_DVI 1 #define WMT_FTBLK_VOUT_DVI #define WMT_FTBLK_VOUT_HDMI #define WMT_FTBLK_VOUT_LVDS /* hw parameter */ -#define VPP_DVI_INT_DEFAULT 0 /* default interrupt gpio */ -#define VPP_VOINT_NO g_vpp.dvi_int_no -#define VPP_UBOOT_COLFMT VDO_COL_FMT_RGB_565 -#define VPP_FB_ADDR_ALIGN 64 -#define VPP_FB_WIDTH_ALIGN 64 /* hw should 4 byte align,android +#define VPP_VOINT_NO 0 /* DVO external board interrupt use GPIOxx */ +#define VPP_UBOOT_COLFMT VDO_COL_FMT_RGB_565 +#define VPP_FB_ADDR_ALIGN 64 +#define VPP_FB_WIDTH_ALIGN 64 /* hw should 4 byte align,android framework 8 byte align modify by aksenxu VPU need 64bytes alignment you need modify FramebufferNativeWindow::FramebufferNativeWindow in android framework together */ -#define VPP_GOVR_DVO_DELAY_24 0x4036 -#define VPP_GOVR_DVO_DELAY_12 0x120 +#define VPP_GOVR_DVO_DELAY_24 0x4036 +#define VPP_GOVR_DVO_DELAY_12 0x120 /*-------------------- DEPENDENCY -------------------------------------*/ #ifdef __KERNEL__ @@ -130,8 +128,8 @@ #ifdef WMT_FTBLK_VOUT_HDMI #include "wmt-hdmi-reg.h" #endif +#ifndef CFG_LOADER #include "wmt-scl-reg.h" -#ifndef CONFIG_UBOOT #include "wmt-cec-reg.h" #endif #endif /* WMT_VPP_HW_H */ diff --git a/drivers/video/wmt/hw/wmt-vpp-reg.h b/drivers/video/wmt/hw/wmt-vpp-reg.h index b96e64db..ffd02b87 100755..100644 --- a/drivers/video/wmt/hw/wmt-vpp-reg.h +++ b/drivers/video/wmt/hw/wmt-vpp-reg.h @@ -1,8 +1,8 @@ /*++ - * linux/drivers/video/wmt/hw/wmt-vpp-reg.h + * linux/drivers/video/wmt/register/wm8710/wmt-vpp-reg.h * WonderMedia video post processor (VPP) driver * - * Copyright c 2014 WonderMedia Technologies, Inc. + * Copyright c 2013 WonderMedia Technologies, Inc. * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,109 +24,75 @@ #ifndef WMT_VPP_REG_H #define WMT_VPP_REG_H -#define VPP_DAC_SEL_TV 1 -#define VPP_DAC_SEL_VGA 0 - -struct vppm_base_regs { - unsigned int _00; /* 0x00 */ - - union { - unsigned int val; - struct { - unsigned int _0_7:8; - unsigned int govrh_pvbi:1; - unsigned int govrh_vbis:1; - unsigned int govrh_vbie:1; - unsigned int _11:1; - unsigned int govrh2_pvbi:1; - unsigned int govrh2_vbis:1; - unsigned int govrh2_vbie:1; - unsigned int _15:1; - unsigned int scl_pvbi:1; - unsigned int scl_vbis:1; - unsigned int scl_vbie:1; - unsigned int _19:1; - unsigned int ge_tg:1; - } b; - } int_sts; /* 0x4 */ - - union { - unsigned int val; - struct { - unsigned int _0_7:8; - unsigned int govrh_pvbi:1; - unsigned int govrh_vbis:1; - unsigned int govrh_vbie:1; - unsigned int _11:1; - unsigned int govrh2_pvbi:1; - unsigned int govrh2_vbis:1; - unsigned int govrh2_vbie:1; - unsigned int _15:1; - unsigned int scl_pvbi:1; - unsigned int scl_vbis:1; - unsigned int scl_vbie:1; - unsigned int _19:1; - unsigned int ge_tg:1; - } b; - } int_en; /* 0x8 */ - - unsigned int watch_sel; /* 0x0C */ - - union { - unsigned int val; - struct { - unsigned int scl:1; - unsigned int _1_7:7; - unsigned int vid:1; - unsigned int _9_15:7; - unsigned int ge:1; - } b; - } sw_reset1; /* 0x10 */ - - union { - unsigned int val; - struct { - unsigned int govrh:1; - unsigned int _1_3:3; - unsigned int lvds:1; - unsigned int _5_7:3; - unsigned int dvo:1; - unsigned int dvo2:1; - unsigned int _10_11:2; - unsigned int cec:1; - } b; - } sw_reset2; /* 0x14 */ - - unsigned int dac_sel; /* 0x18 */ - - union { - unsigned int val; - struct { - unsigned int hdmi:1; - unsigned int _1_7:7; - unsigned int ddc:1; - unsigned int _9_15:7; - unsigned int hdmi2:1; - } b; - } sw_reset3; /* 0x1C */ - - union { - unsigned int val; - struct { - unsigned int disable:1; - unsigned int _1_7:7; - unsigned int csi_act_lane_sel:1; /*0-lane 0/1,1-2/3*/ - } b; - } sscg; /* 0x20 */ -}; - #define REG_VPP_BEGIN (VPP_BASE_ADDR + 0x00) +#define REG_VPP_INTSTS (VPP_BASE_ADDR + 0x04) +#define REG_VPP_INTEN (VPP_BASE_ADDR + 0x08) +#define REG_VPP_WATCH_SEL (VPP_BASE_ADDR + 0x0c) +#define REG_VPP_SWRST1_SEL (VPP_BASE_ADDR + 0x10) +#define REG_VPP_SWRST2_SEL (VPP_BASE_ADDR + 0x14) +#define REG_VPP_DAC_SEL (VPP_BASE_ADDR + 0x18) +#define REG_VPP_SWRST3_SEL (VPP_BASE_ADDR + 0x1C) +#define REG_VPP_SSCG (VPP_BASE_ADDR + 0x20) #define REG_VPP_END (VPP_BASE_ADDR + 0x28) -#ifndef VPPM_C -extern HW_REG struct vppm_base_regs *vppm_regs; -#endif +/* REG_VPP_INTSTS,0x04 */ +#define VPP_GE_INTSTS_TG REG_VPP_INTSTS, BIT20, 20 +#define VPP_SCL_INTSTS_VBIE REG_VPP_INTSTS, BIT18, 18 +#define VPP_SCL_INTSTS_VBIS REG_VPP_INTSTS, BIT17, 17 +#define VPP_SCL_INTSTS_PVBI REG_VPP_INTSTS, BIT16, 16 +#define VPP_SCL_INTSTS REG_VPP_INTSTS, 0x70000, 16 +#define VPP_GOVRH2_INTSTS_VBIE REG_VPP_INTSTS, BIT14, 14 +#define VPP_GOVRH2_INTSTS_VBIS REG_VPP_INTSTS, BIT13, 13 +#define VPP_GOVRH2_INTSTS_PVBI REG_VPP_INTSTS, BIT12, 12 +#define VPP_GOVRH2_INTSTS REG_VPP_INTSTS, 0x7000, 12 +#define VPP_GOVRH_INTSTS_VBIE REG_VPP_INTSTS, BIT10, 10 +#define VPP_GOVRH_INTSTS_VBIS REG_VPP_INTSTS, BIT9, 9 +#define VPP_GOVRH_INTSTS_PVBI REG_VPP_INTSTS, BIT8, 8 +#define VPP_GOVRH_INTSTS REG_VPP_INTSTS, 0x700, 8 + +/* REG_VPP_INTEN,0x08 */ +#define VPP_GE_INTEN_TG REG_VPP_INTEN, BIT20, 20 +#define VPP_SCL_INTEN_VBIE REG_VPP_INTEN, BIT18, 18 +#define VPP_SCL_INTEN_VBIS REG_VPP_INTEN, BIT17, 17 +#define VPP_SCL_INTEN_PVBI REG_VPP_INTEN, BIT16, 16 +#define VPP_SCL_INTEN REG_VPP_INTEN, 0x70000, 16 +#define VPP_GOVRH2_INTEN_VBIE REG_VPP_INTEN, BIT14, 14 +#define VPP_GOVRH2_INTEN_VBIS REG_VPP_INTEN, BIT13, 13 +#define VPP_GOVRH2_INTEN_PVBI REG_VPP_INTEN, BIT12, 12 +#define VPP_GOVRH2_INTEN REG_VPP_INTEN, 0x7000, 12 +#define VPP_GOVRH_INTEN_VBIE REG_VPP_INTEN, BIT10, 10 +#define VPP_GOVRH_INTEN_VBIS REG_VPP_INTEN, BIT9, 9 +#define VPP_GOVRH_INTEN_PVBI REG_VPP_INTEN, BIT8, 8 +#define VPP_GOVRH_INTEN REG_VPP_INTEN, 0x700, 8 + +/* REG_VPP_WATCH_SEL,0x0c */ +#define VPP_WATCH_SEL REG_VPP_WATCH_SEL, 0x1F, 0 + +/* REG_VPP_SWRST1_SEL,0x10 */ +#define VPP_GE_RST REG_VPP_SWRST1_SEL, BIT16, 16 +#define VPP_VID_RST REG_VPP_SWRST1_SEL, BIT8, 8 +#define VPP_SCL_RST REG_VPP_SWRST1_SEL, BIT0, 0 + +/* REG_VPP_SWRST2_SEL,0x14 */ +#define VPP_CEC_RST REG_VPP_SWRST2_SEL, BIT12,12 +#define VPP_DVO2_RST REG_VPP_SWRST2_SEL, BIT9, 9 +#define VPP_DVO_RST REG_VPP_SWRST2_SEL, BIT8, 8 +#define VPP_LVDS_RST REG_VPP_SWRST2_SEL, BIT4, 4 +#define VPP_GOVRH_RST REG_VPP_SWRST2_SEL, BIT0, 0 + +/* REG_VPP_DAC_SEL,0x18 */ +#define VPP_DAC_SEL REG_VPP_DAC_SEL, BIT0, 0 +#define VPP_DAC_SEL_TV 1 +#define VPP_DAC_SEL_VGA 0 + +/* REG_VPP_SWRST3_SEL,0x1C */ +#define VPP_HDMI_RST REG_VPP_SWRST3_SEL, BIT0, 0 +#define VPP_DDC_RST REG_VPP_SWRST3_SEL, BIT8, 8 +#define VPP_HDMI2_RST REG_VPP_SWRST3_SEL, BIT16, 16 +/* REG_VPP_SSCG,0x20 */ +#define VPP_SSCG_DISABLE REG_VPP_SSCG, BIT0, 0 +#define VPP_CSI_ACT_LANE_SELECT REG_VPP_SSCG, BIT8, 8 /* 0-Active lane 0/1, 1-Active lane 2/3 */ #endif /* WMT_VPP_REG_H */ |