diff options
Diffstat (limited to 'arch/mips/mipssim')
| -rw-r--r-- | arch/mips/mipssim/Makefile | 23 | ||||
| -rw-r--r-- | arch/mips/mipssim/Platform | 6 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_console.c | 40 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_int.c | 87 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_mem.c | 115 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_platform.c | 35 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_setup.c | 99 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_smtc.c | 116 | ||||
| -rw-r--r-- | arch/mips/mipssim/sim_time.c | 117 |
9 files changed, 638 insertions, 0 deletions
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile new file mode 100644 index 00000000..01410a3f --- /dev/null +++ b/arch/mips/mipssim/Makefile @@ -0,0 +1,23 @@ +# +# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. +# Copyright (C) 2007 MIPS Technologies, Inc. +# written by Ralf Baechle (ralf@linux-mips.org) +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# + +obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o + +obj-$(CONFIG_EARLY_PRINTK) += sim_console.o +obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform new file mode 100644 index 00000000..3df60b8a --- /dev/null +++ b/arch/mips/mipssim/Platform @@ -0,0 +1,6 @@ +# +# MIPS SIM +# +platform-$(CONFIG_MIPS_SIM) += mipssim/ +cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim +load-$(CONFIG_MIPS_SIM) += 0x80100000 diff --git a/arch/mips/mipssim/sim_console.c b/arch/mips/mipssim/sim_console.c new file mode 100644 index 00000000..a2f41672 --- /dev/null +++ b/arch/mips/mipssim/sim_console.c @@ -0,0 +1,40 @@ +/* + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle + */ +#include <linux/init.h> +#include <linux/io.h> +#include <linux/serial_reg.h> + +static inline unsigned int serial_in(int offset) +{ + return inb(0x3f8 + offset); +} + +static inline void serial_out(int offset, int value) +{ + outb(value, 0x3f8 + offset); +} + +void __init prom_putchar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); +} diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c new file mode 100644 index 00000000..5c779be6 --- /dev/null +++ b/arch/mips/mipssim/sim_int.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <asm/mips-boards/simint.h> +#include <asm/irq_cpu.h> + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return -clz(pending) + 31 - CAUSEB_IP; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = s0 & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + s0 = s0 << t0; + + t0 = s0 & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + s0 = s0 << t0; + + t0 = s0 & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* s0 = s0 << t0; */ + + return a0; +#endif +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq > 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); +} diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c new file mode 100644 index 00000000..953d836a --- /dev/null +++ b/arch/mips/mipssim/sim_mem.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/bootmem.h> +#include <linux/pfn.h> + +#include <asm/bootinfo.h> +#include <asm/page.h> +#include <asm/sections.h> + +#include <asm/mips-boards/prom.h> + +/*#define DEBUG*/ + +enum simmem_memtypes { + simmem_reserved = 0, + simmem_free, +}; +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "SIM reserved memory", + "SIM free memory", +}; +#endif + +struct prom_pmemblock * __init prom_getmdesc(void) +{ + unsigned int memsize; + + memsize = 0x02000000; + pr_info("Setting default memory size 0x%08x\n", memsize); + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = simmem_reserved; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = simmem_free; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ff000; + + mdesc[2].type = simmem_reserved; + mdesc[2].base = 0x00100000; + mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base; + + mdesc[3].type = simmem_free; + mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[3].size = memsize - mdesc[3].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case simmem_free: + return BOOT_MEM_RAM; + case simmem_reserved: + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + int i; + unsigned long addr; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mipssim/sim_platform.c b/arch/mips/mipssim/sim_platform.c new file mode 100644 index 00000000..53210a8c --- /dev/null +++ b/arch/mips/mipssim/sim_platform.c @@ -0,0 +1,35 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org) + */ +#include <linux/init.h> +#include <linux/if_ether.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> + +static char mipsnet_string[] = "mipsnet"; + +static struct platform_device eth1_device = { + .name = mipsnet_string, + .id = 0, +}; + +/* + * Create a platform device for the GPI port that receives the + * image data from the embedded camera. + */ +static int __init mipsnet_devinit(void) +{ + int err; + + err = platform_device_register(ð1_device); + if (err) + printk(KERN_ERR "%s: registration failed\n", mipsnet_string); + + return err; +} + +device_initcall(mipsnet_devinit); diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c new file mode 100644 index 00000000..256e0cda --- /dev/null +++ b/arch/mips/mipssim/sim_setup.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/ioport.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/serial_8250.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> +#include <asm/time.h> +#include <asm/mips-boards/sim.h> +#include <asm/mips-boards/simint.h> +#include <asm/smp-ops.h> + + +static void __init serial_init(void); +unsigned int _isbonito; + +const char *get_system_type(void) +{ + return "MIPSsim"; +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(0xbfd00000); + + serial_init(); +} + +extern struct plat_smp_ops ssmtc_smp_ops; + +void __init prom_init(void) +{ + set_io_port_base(0xbfd00000); + + prom_meminit(); + + if (cpu_has_mipsmt) { + if (!register_vsmp_smp_ops()) + return; + +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&ssmtc_smp_ops); + return; +#endif + } + + register_up_smp_ops(); +} + +static void __init serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct uart_port s; + + memset(&s, 0, sizeof(s)); + + s.iobase = 0x3f8; + + /* hardware int 4 - the serial int, is CPU int 6 + but poll for now */ + s.irq = 0; + s.uartclk = 1843200; + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; + s.iotype = UPIO_PORT; + s.regshift = 0; + s.timeout = 4; + + if (early_serial_setup(&s) != 0) { + printk(KERN_ERR "Serial setup failed!\n"); + } + +#endif +} diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c new file mode 100644 index 00000000..3c104abd --- /dev/null +++ b/arch/mips/mipssim/sim_smtc.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +/* + * Simulator Platform-specific hooks for SMTC operation + */ +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/cpumask.h> +#include <linux/interrupt.h> +#include <linux/smp.h> + +#include <linux/atomic.h> +#include <asm/cpu.h> +#include <asm/processor.h> +#include <asm/smtc.h> +#include <asm/mmu_context.h> +#include <asm/smtc_ipi.h> + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void ssmtc_send_ipi_single(int cpu, unsigned int action) +{ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ +} + +static inline void ssmtc_send_ipi_mask(const struct cpumask *mask, + unsigned int action) +{ + unsigned int i; + + for_each_cpu(i, mask) + ssmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit ssmtc_init_secondary(void) +{ + smtc_init_secondary(); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit ssmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ +static void ssmtc_cpus_done(void) +{ +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +static void __init ssmtc_smp_setup(void) +{ + if (read_c0_config3() & (1 << 2)) + mipsmt_build_cpu_map(0); +} + +/* + * Platform SMP pre-initialization + */ +static void ssmtc_prepare_cpus(unsigned int max_cpus) +{ + /* + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + + if (read_c0_config3() & (1 << 2)) { + mipsmt_prepare_cpus(); + } +} + +struct plat_smp_ops ssmtc_smp_ops = { + .send_ipi_single = ssmtc_send_ipi_single, + .send_ipi_mask = ssmtc_send_ipi_mask, + .init_secondary = ssmtc_init_secondary, + .smp_finish = ssmtc_smp_finish, + .cpus_done = ssmtc_cpus_done, + .boot_secondary = ssmtc_boot_secondary, + .smp_setup = ssmtc_smp_setup, + .prepare_cpus = ssmtc_prepare_cpus, +}; diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c new file mode 100644 index 00000000..77bad3c0 --- /dev/null +++ b/arch/mips/mipssim/sim_time.c @@ -0,0 +1,117 @@ +#include <linux/types.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> +#include <linux/mc146818rtc.h> +#include <linux/smp.h> +#include <linux/timex.h> + +#include <asm/hardirq.h> +#include <asm/div64.h> +#include <asm/cpu.h> +#include <asm/setup.h> +#include <asm/time.h> +#include <asm/irq.h> +#include <asm/mc146818-time.h> +#include <asm/msc01_ic.h> + +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/prom.h> +#include <asm/mips-boards/simint.h> + + +unsigned long cpu_khz; + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int count; + +#if 1 + /* + * hardwire the board frequency to 12MHz. + */ + + if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || + (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) + count = 12000000; + else + count = 6000000; +#else + unsigned int flags; + + local_irq_save(flags); + + /* Start counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + /* Start r4k counter. */ + write_c0_count(0); + + /* Read counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + count = read_c0_count(); + + /* restore interrupts */ + local_irq_restore(flags); +#endif + + mips_hpt_frequency = count; + + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + count *= 2; + + count += 5000; /* round */ + count -= count%10000; + + return count; +} + +static int mips_cpu_timer_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + + +unsigned __cpuinit get_c0_compare_int(void) +{ +#ifdef MSC01E_INT_BASE + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + + return mips_cpu_timer_irq; + } +#endif + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + /* Set Data mode - binary. */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); + + est_freq = estimate_cpu_frequency(); + + printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, + (est_freq % 1000000) * 100 / 1000000); + + cpu_khz = est_freq / 1000; +} |