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-rw-r--r--arch/m68k/platform/520x/Makefile17
-rw-r--r--arch/m68k/platform/520x/config.c87
-rw-r--r--arch/m68k/platform/520x/gpio.c175
3 files changed, 279 insertions, 0 deletions
diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
new file mode 100644
index 00000000..ad3f4e5a
--- /dev/null
+++ b/arch/m68k/platform/520x/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile for the M5208 specific file.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this, which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# ccflags-y := -DTRAP_DBG_INTERRUPT
+# asflags-y := -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
new file mode 100644
index 00000000..09df4b89
--- /dev/null
+++ b/arch/m68k/platform/520x/config.c
@@ -0,0 +1,87 @@
+/***************************************************************************/
+
+/*
+ * linux/arch/m68knommu/platform/520x/config.c
+ *
+ * Copyright (C) 2005, Freescale (www.freescale.com)
+ * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
+ * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+
+/***************************************************************************/
+
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+
+static void __init m520x_qspi_init(void)
+{
+ u16 par;
+ /* setup Port QS for QSPI with gpio CS control */
+ writeb(0x3f, MCF_GPIO_PAR_QSPI);
+ /* make U1CTS and U2RTS gpio for cs_control */
+ par = readw(MCF_GPIO_PAR_UART);
+ par &= 0x00ff;
+ writew(par, MCF_GPIO_PAR_UART);
+}
+
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
+
+/***************************************************************************/
+
+static void __init m520x_uarts_init(void)
+{
+ u16 par;
+ u8 par2;
+
+ /* UART0 and UART1 GPIO pin setup */
+ par = readw(MCF_GPIO_PAR_UART);
+ par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
+ par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
+ writew(par, MCF_GPIO_PAR_UART);
+
+ /* UART1 GPIO pin setup */
+ par2 = readb(MCF_GPIO_PAR_FECI2C);
+ par2 &= ~0x0F;
+ par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
+ MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
+ writeb(par2, MCF_GPIO_PAR_FECI2C);
+}
+
+/***************************************************************************/
+
+static void __init m520x_fec_init(void)
+{
+ u8 v;
+
+ /* Set multi-function pins to ethernet mode */
+ v = readb(MCF_GPIO_PAR_FEC);
+ writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
+
+ v = readb(MCF_GPIO_PAR_FECI2C);
+ writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+ mach_sched_init = hw_timer_init;
+ m520x_uarts_init();
+ m520x_fec_init();
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+ m520x_qspi_init();
+#endif
+}
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c
new file mode 100644
index 00000000..9bcc3e4b
--- /dev/null
+++ b/arch/m68k/platform/520x/gpio.c
@@ -0,0 +1,175 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+ {
+ .gpio_chip = {
+ .label = "PIRQ",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value,
+ .ngpio = 8,
+ },
+ .pddr = (void __iomem *) MCFEPORT_EPDDR,
+ .podr = (void __iomem *) MCFEPORT_EPDR,
+ .ppdr = (void __iomem *) MCFEPORT_EPPDR,
+ },
+ {
+ .gpio_chip = {
+ .label = "CS",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 9,
+ .ngpio = 3,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_CS,
+ .podr = (void __iomem *) MCFGPIO_PODR_CS,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
+ },
+ {
+ .gpio_chip = {
+ .label = "FECI2C",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 16,
+ .ngpio = 4,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
+ .podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
+ },
+ {
+ .gpio_chip = {
+ .label = "QSPI",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 24,
+ .ngpio = 4,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
+ .podr = (void __iomem *) MCFGPIO_PODR_QSPI,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
+ },
+ {
+ .gpio_chip = {
+ .label = "TIMER",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 32,
+ .ngpio = 4,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
+ .podr = (void __iomem *) MCFGPIO_PODR_TIMER,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
+ },
+ {
+ .gpio_chip = {
+ .label = "UART",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 40,
+ .ngpio = 8,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_UART,
+ .podr = (void __iomem *) MCFGPIO_PODR_UART,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
+ },
+ {
+ .gpio_chip = {
+ .label = "FECH",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 48,
+ .ngpio = 8,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
+ .podr = (void __iomem *) MCFGPIO_PODR_FECH,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
+ },
+ {
+ .gpio_chip = {
+ .label = "FECL",
+ .request = mcf_gpio_request,
+ .free = mcf_gpio_free,
+ .direction_input = mcf_gpio_direction_input,
+ .direction_output = mcf_gpio_direction_output,
+ .get = mcf_gpio_get_value,
+ .set = mcf_gpio_set_value_fast,
+ .base = 56,
+ .ngpio = 8,
+ },
+ .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
+ .podr = (void __iomem *) MCFGPIO_PODR_FECL,
+ .ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
+ .setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
+ .clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
+ },
+};
+
+static int __init mcf_gpio_init(void)
+{
+ unsigned i = 0;
+ while (i < ARRAY_SIZE(mcf_gpio_chips))
+ (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+ return 0;
+}
+
+core_initcall(mcf_gpio_init);
generated by cgit (git 2.34.1) at 2025-01-31 04:30:59 +0000