diff options
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c')
| -rwxr-xr-x | ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c | 202 |
1 files changed, 0 insertions, 202 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c b/ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c deleted file mode 100755 index 4f781017..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c +++ /dev/null @@ -1,202 +0,0 @@ -/*++ - linux/arch/arm/mach-wmt/platsmp.c - - Copyright (c) 2013 WonderMedia Technologies, Inc. - - Copyright (C) 2002 ARM Ltd. - All Rights Reserved - - This program is free software: you can redistribute it and/or modify it under the - terms of the GNU General Public License as published by the Free Software Foundation, - either version 2 of the License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A - PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License along with - this program. If not, see <http://www.gnu.org/licenses/>. - - WonderMedia Technologies, Inc. - 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C. ---*/ -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/jiffies.h> -#include <linux/smp.h> -#include <linux/io.h> - -#include <linux/syscore_ops.h> - -#include <asm/cacheflush.h> -#include <asm/hardware/gic.h> -#include <asm/smp_plat.h> -#include <asm/smp_scu.h> - -#include <mach/hardware.h> - -extern void wmt_secondary_startup(void); - -#define CPU1_BOOT_REG HSP7_ADDR -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ - -volatile int __cpuinitdata pen_release = -1; - -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static void __iomem *scu_base_addr(void) -{ - return (void __iomem *)(MPCORE_PRIVATE_MEM); -} - -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * This is really belt and braces; we hold unintended secondary - * CPUs in the holding pen until we're ready for them. However, - * since we haven't sent them a soft interrupt, they shouldn't - * be there. - */ - write_pen_release(cpu_logical_map(cpu)); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - - __raw_writel(virt_to_phys(wmt_secondary_startup), - CPU1_BOOT_REG); - gic_raise_softirq(cpumask_of(cpu), 1); - - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ - -void __init smp_init_cpus(void) -{ - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - - /* sanity check */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); -} - -void __init platform_smp_prepare_cpus(unsigned int max_cpus) -{ - *(volatile unsigned int *)MPCORE_PRIVATE_MEM |= BIT5 | BIT6; - scu_enable(scu_base_addr()); - - /* - * Write the address of secondary startup into the - * system-wide flags register. The boot monitor waits - * until it receives a soft interrupt, and then the - * secondary CPU branches to this address. - */ - __raw_writel(virt_to_phys(wmt_secondary_startup), - CPU1_BOOT_REG); -} - -static int wmt_pm_suspend(void) -{ - return 0; -} - -static void wmt_pm_resume(void) -{ -#ifdef CONFIG_SMP - *(volatile unsigned int *)MPCORE_PRIVATE_MEM |= BIT5 | BIT6; - scu_enable(scu_base_addr()); -#endif - return; -} - -static struct syscore_ops wmt_pm_syscore_ops = { - .suspend = wmt_pm_suspend, - .resume = wmt_pm_resume, -}; - -static __init int wmt_pm_syscore_init(void) -{ - register_syscore_ops(&wmt_pm_syscore_ops); - return 0; -} -arch_initcall(wmt_pm_syscore_init); |