diff options
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-ux500')
56 files changed, 0 insertions, 9188 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/Kconfig b/ANDROID_3.4.5/arch/arm/mach-ux500/Kconfig deleted file mode 100644 index ef7099ee..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/Kconfig +++ /dev/null @@ -1,91 +0,0 @@ -if ARCH_U8500 - -config UX500_SOC_COMMON - bool - default y - select ARM_GIC - select HAS_MTU - select PL310_ERRATA_753970 - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 - select CACHE_L2X0 - -config UX500_SOC_DB5500 - bool - select MFD_DB5500_PRCMU - -config UX500_SOC_DB8500 - bool - select MFD_DB8500_PRCMU - select REGULATOR - select REGULATOR_DB8500_PRCMU - select CPU_FREQ_TABLE if CPU_FREQ - -menu "Ux500 target platform (boards)" - -config MACH_MOP500 - bool "U8500 Development platform, MOP500 versions" - select UX500_SOC_DB8500 - select I2C - select I2C_NOMADIK - select SOC_BUS - help - Include support for the MOP500 development platform. - -config MACH_HREFV60 - bool "U8500 Development platform, HREFv60 version" - select MACH_MOP500 - help - Include support for the HREFv60 new development platform. - Includes HREFv70, v71 etc. - -config MACH_SNOWBALL - bool "U8500 Snowball platform" - select MACH_MOP500 - help - Include support for the snowball development platform. - -config MACH_U5500 - bool "U5500 Development platform" - select UX500_SOC_DB5500 - help - Include support for the U5500 development platform. - -config UX500_AUTO_PLATFORM - def_bool y - depends on !MACH_U5500 - select MACH_MOP500 - help - At least one platform needs to be selected in order to build - a working kernel. If everything else is disabled, this - automatically enables MACH_MOP500. - -config MACH_UX500_DT - bool "Generic U8500 support using device tree" - depends on MACH_MOP500 - select USE_OF - -endmenu - -config UX500_DEBUG_UART - int "Ux500 UART to use for low-level debug" - default 2 - help - Choose the UART on which kernel low-level debug messages should be - output. - -config U5500_MODEM_IRQ - bool "Modem IRQ support" - depends on UX500_SOC_DB5500 - default y - help - Add support for handling IRQ:s from modem side - -config U5500_MBOX - bool "Mailbox support" - depends on U5500_MODEM_IRQ - default y - help - Add support for U5500 mailbox communication with modem side - -endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/Makefile b/ANDROID_3.4.5/arch/arm/mach-ux500/Makefile deleted file mode 100644 index 465b9ec9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# Makefile for the linux kernel, U8500 machine. -# - -obj-y := clock.o cpu.o devices.o devices-common.o \ - id.o usb.o timer.o -obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o -obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o -obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o -obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ - board-mop500-regulators.o \ - board-mop500-uib.o board-mop500-stuib.o \ - board-mop500-u8500uib.o \ - board-mop500-pins.o -obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o -obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o - diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/Makefile.boot b/ANDROID_3.4.5/arch/arm/mach-ux500/Makefile.boot deleted file mode 100644 index dd5cd00e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/Makefile.boot +++ /dev/null @@ -1,5 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 - -dtb-$(CONFIG_MACH_SNOWBALL) += snowball.dtb diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-pins.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-pins.c deleted file mode 100644 index f5413dca..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-pins.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/bug.h> - -#include <asm/mach-types.h> -#include <plat/pincfg.h> -#include <plat/gpio-nomadik.h> -#include <mach/hardware.h> - -#include "pins-db8500.h" - -static pin_cfg_t mop500_pins_common[] = { - /* I2C */ - GPIO147_I2C0_SCL, - GPIO148_I2C0_SDA, - GPIO16_I2C1_SCL, - GPIO17_I2C1_SDA, - GPIO10_I2C2_SDA, - GPIO11_I2C2_SCL, - GPIO229_I2C3_SDA, - GPIO230_I2C3_SCL, - - /* MSP0 */ - GPIO12_MSP0_TXD, - GPIO13_MSP0_TFS, - GPIO14_MSP0_TCK, - GPIO15_MSP0_RXD, - - /* MSP2: HDMI */ - GPIO193_MSP2_TXD, - GPIO194_MSP2_TCK, - GPIO195_MSP2_TFS, - GPIO196_MSP2_RXD | PIN_OUTPUT_LOW, - - /* Touch screen INTERFACE */ - GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */ - - /* STMPE1601/tc35893 keypad IRQ */ - GPIO218_GPIO | PIN_INPUT_PULLUP, - - /* MMC0 (MicroSD card) */ - GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, - GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, - GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, - - GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, - GPIO23_MC0_CLK | PIN_OUTPUT_LOW, - GPIO24_MC0_CMD | PIN_INPUT_PULLUP, - GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, - GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, - GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, - GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, - - /* SDI1 (SDIO) */ - GPIO208_MC1_CLK | PIN_OUTPUT_LOW, - GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL, - GPIO210_MC1_CMD | PIN_INPUT_PULLUP, - GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP, - GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP, - GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP, - GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP, - - /* MMC2 (On-board DATA INTERFACE eMMC) */ - GPIO128_MC2_CLK | PIN_OUTPUT_LOW, - GPIO129_MC2_CMD | PIN_INPUT_PULLUP, - GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL, - GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP, - GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP, - GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP, - GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP, - GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP, - GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP, - GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP, - GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP, - - /* MMC4 (On-board STORAGE INTERFACE eMMC) */ - GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, - GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, - GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, - GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, - GPIO201_MC4_CMD | PIN_INPUT_PULLUP, - GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, - GPIO203_MC4_CLK | PIN_OUTPUT_LOW, - GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, - GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, - GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, - GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, - - /* SKE keypad */ - GPIO153_KP_I7, - GPIO154_KP_I6, - GPIO155_KP_I5, - GPIO156_KP_I4, - GPIO157_KP_O7, - GPIO158_KP_O6, - GPIO159_KP_O5, - GPIO160_KP_O4, - GPIO161_KP_I3, - GPIO162_KP_I2, - GPIO163_KP_I1, - GPIO164_KP_I0, - GPIO165_KP_O3, - GPIO166_KP_O2, - GPIO167_KP_O1, - GPIO168_KP_O0, - - /* UART */ - /* uart-0 pins gpio configuration should be - * kept intact to prevent glitch in tx line - * when tty dev is opened. Later these pins - * are configured to uart mop500_pins_uart0 - * - * It will be replaced with uart configuration - * once the issue is solved. - */ - GPIO0_GPIO | PIN_INPUT_PULLUP, - GPIO1_GPIO | PIN_OUTPUT_HIGH, - GPIO2_GPIO | PIN_INPUT_PULLUP, - GPIO3_GPIO | PIN_OUTPUT_HIGH, - - GPIO29_U2_RXD | PIN_INPUT_PULLUP, - GPIO30_U2_TXD | PIN_OUTPUT_HIGH, - GPIO31_U2_CTSn | PIN_INPUT_PULLUP, - GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, - - /* Display & HDMI HW sync */ - GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP, - GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP, -}; - -static pin_cfg_t mop500_pins_default[] = { - /* SSP0 */ - GPIO143_SSP0_CLK, - GPIO144_SSP0_FRM, - GPIO145_SSP0_RXD | PIN_PULL_DOWN, - GPIO146_SSP0_TXD, - - - GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */ - - /* SDI0 (MicroSD card) */ - GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, - - /* UART */ - GPIO4_U1_RXD | PIN_INPUT_PULLUP, - GPIO5_U1_TXD | PIN_OUTPUT_HIGH, - GPIO6_U1_CTSn | PIN_INPUT_PULLUP, - GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, -}; - -static pin_cfg_t hrefv60_pins[] = { - /* WLAN */ - GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ - GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ - - /* XENON Flashgun INTERFACE */ - GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */ - GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */ - GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */ - - /* Assistant LED INTERFACE */ - GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */ - GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */ - - /* Magnetometer */ - GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */ - GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */ - - /* Display Interface */ - GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */ - GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */ - - /* Touch screen INTERFACE */ - GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */ - - /* Touch screen INTERFACE 2 */ - GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */ - GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */ - - /* ETM_PTM_TRACE INTERFACE */ - GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */ - GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */ - GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */ - GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */ - GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */ - - /* NAHJ INTERFACE */ - GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */ - GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */ - - /* NFC INTERFACE */ - GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */ - GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */ - GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */ - - /* Keyboard MATRIX INTERFACE */ - GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */ - GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */ - GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */ - GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */ - GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */ - GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */ - GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */ - GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */ - GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */ - GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */ - GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */ - - /* DiPro Sensor Interface */ - GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */ - - /* HAL SWITCH INTERFACE */ - GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */ - - /* Audio Amplifier Interface */ - GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */ - - /* GBF INTERFACE */ - GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */ - - /* MSP : HDTV INTERFACE */ - GPIO192_GPIO | PIN_INPUT_PULLDOWN, - - /* ACCELEROMETER_INTERFACE */ - GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */ - GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */ - - /* Proximity Sensor */ - GPIO217_GPIO | PIN_INPUT_PULLUP, - - -}; - -static pin_cfg_t snowball_pins[] = { - /* SSP0, to AB8500 */ - GPIO143_SSP0_CLK, - GPIO144_SSP0_FRM, - GPIO145_SSP0_RXD | PIN_PULL_DOWN, - GPIO146_SSP0_TXD, - - /* MMC0: MicroSD card */ - GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, - - /* MMC2: LAN */ - GPIO86_SM_ADQ0, - GPIO87_SM_ADQ1, - GPIO88_SM_ADQ2, - GPIO89_SM_ADQ3, - GPIO90_SM_ADQ4, - GPIO91_SM_ADQ5, - GPIO92_SM_ADQ6, - GPIO93_SM_ADQ7, - - GPIO94_SM_ADVn, - GPIO95_SM_CS0n, - GPIO96_SM_OEn, - GPIO97_SM_WEn, - - GPIO128_SM_CKO, - GPIO130_SM_FBCLK, - GPIO131_SM_ADQ8, - GPIO132_SM_ADQ9, - GPIO133_SM_ADQ10, - GPIO134_SM_ADQ11, - GPIO135_SM_ADQ12, - GPIO136_SM_ADQ13, - GPIO137_SM_ADQ14, - GPIO138_SM_ADQ15, - - /* RSTn_LAN */ - GPIO141_GPIO | PIN_OUTPUT_HIGH, -}; - -void __init mop500_pins_init(void) -{ - nmk_config_pins(mop500_pins_common, - ARRAY_SIZE(mop500_pins_common)); - - nmk_config_pins(mop500_pins_default, - ARRAY_SIZE(mop500_pins_default)); -} - -void __init snowball_pins_init(void) -{ - nmk_config_pins(mop500_pins_common, - ARRAY_SIZE(mop500_pins_common)); - - nmk_config_pins(snowball_pins, - ARRAY_SIZE(snowball_pins)); -} - -void __init hrefv60_pins_init(void) -{ - nmk_config_pins(mop500_pins_common, - ARRAY_SIZE(mop500_pins_common)); - - nmk_config_pins(hrefv60_pins, - ARRAY_SIZE(hrefv60_pins)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-regulators.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-regulators.c deleted file mode 100644 index 52426a42..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-regulators.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License v2 - * - * Authors: Sundar Iyer <sundar.iyer@stericsson.com> - * Bengt Jonsson <bengt.g.jonsson@stericsson.com> - * - * MOP500 board specific initialization for regulators - */ -#include <linux/kernel.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/ab8500.h> -#include "board-mop500-regulators.h" - -/* - * TPS61052 regulator - */ -static struct regulator_consumer_supply tps61052_vaudio_consumers[] = { - /* - * Boost converter supply to raise voltage on audio speaker, this - * is actually connected to three pins, VInVhfL (left amplifier) - * VInVhfR (right amplifier) and VIntDClassInt - all three must - * be connected to the same voltage. - */ - REGULATOR_SUPPLY("vintdclassint", "ab8500-codec.0"), -}; - -struct regulator_init_data tps61052_regulator = { - .constraints = { - .name = "vaudio-hf", - .min_uV = 4500000, - .max_uV = 4500000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(tps61052_vaudio_consumers), - .consumer_supplies = tps61052_vaudio_consumers, -}; - -static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { - /* External displays, connector on board 2v5 power supply */ - REGULATOR_SUPPLY("vaux12v5", "mcde.0"), - /* SFH7741 proximity sensor */ - REGULATOR_SUPPLY("vcc", "gpio-keys.0"), - /* BH1780GLS ambient light sensor */ - REGULATOR_SUPPLY("vcc", "2-0029"), - /* lsm303dlh accelerometer */ - REGULATOR_SUPPLY("vdd", "3-0018"), - /* lsm303dlh magnetometer */ - REGULATOR_SUPPLY("vdd", "3-001e"), - /* Rohm BU21013 Touchscreen devices */ - REGULATOR_SUPPLY("avdd", "3-005c"), - REGULATOR_SUPPLY("avdd", "3-005d"), - /* Synaptics RMI4 Touchscreen device */ - REGULATOR_SUPPLY("vdd", "3-004b"), -}; - -static struct regulator_consumer_supply ab8500_vaux2_consumers[] = { - /* On-board eMMC power */ - REGULATOR_SUPPLY("vmmc", "sdi4"), - /* AB8500 audio codec */ - REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vaux3_consumers[] = { - /* External MMC slot power */ - REGULATOR_SUPPLY("vmmc", "sdi0"), -}; - -static struct regulator_consumer_supply ab8500_vtvout_consumers[] = { - /* TV-out DENC supply */ - REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"), - /* Internal general-purpose ADC */ - REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"), -}; - -static struct regulator_consumer_supply ab8500_vaud_consumers[] = { - /* AB8500 audio-codec main supply */ - REGULATOR_SUPPLY("vaud", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vamic1_consumers[] = { - /* AB8500 audio-codec Mic1 supply */ - REGULATOR_SUPPLY("vamic1", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vamic2_consumers[] = { - /* AB8500 audio-codec Mic2 supply */ - REGULATOR_SUPPLY("vamic2", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vdmic_consumers[] = { - /* AB8500 audio-codec DMic supply */ - REGULATOR_SUPPLY("vdmic", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vintcore_consumers[] = { - /* SoC core supply, no device */ - REGULATOR_SUPPLY("v-intcore", NULL), - /* USB Transceiver */ - REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"), -}; - -static struct regulator_consumer_supply ab8500_vana_consumers[] = { - /* External displays, connector on board, 1v8 power supply */ - REGULATOR_SUPPLY("vsmps2", "mcde.0"), -}; - -/* ab8500 regulator register initialization */ -struct ab8500_regulator_reg_init -ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = { - /* - * VanaRequestCtrl = HP/LP depending on VxRequest - * VextSupply1RequestCtrl = HP/LP depending on VxRequest - */ - INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00), - /* - * VextSupply2RequestCtrl = HP/LP depending on VxRequest - * VextSupply3RequestCtrl = HP/LP depending on VxRequest - * Vaux1RequestCtrl = HP/LP depending on VxRequest - * Vaux2RequestCtrl = HP/LP depending on VxRequest - */ - INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00), - /* - * Vaux3RequestCtrl = HP/LP depending on VxRequest - * SwHPReq = Control through SWValid disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00), - /* - * VanaSysClkReq1HPValid = disabled - * Vaux1SysClkReq1HPValid = disabled - * Vaux2SysClkReq1HPValid = disabled - * Vaux3SysClkReq1HPValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00), - /* - * VextSupply1SysClkReq1HPValid = disabled - * VextSupply2SysClkReq1HPValid = disabled - * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40), - /* - * VanaHwHPReq1Valid = disabled - * Vaux1HwHPreq1Valid = disabled - * Vaux2HwHPReq1Valid = disabled - * Vaux3HwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00), - /* - * VextSupply1HwHPReq1Valid = disabled - * VextSupply2HwHPReq1Valid = disabled - * VextSupply3HwHPReq1Valid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00), - /* - * VanaHwHPReq2Valid = disabled - * Vaux1HwHPReq2Valid = disabled - * Vaux2HwHPReq2Valid = disabled - * Vaux3HwHPReq2Valid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00), - /* - * VextSupply1HwHPReq2Valid = disabled - * VextSupply2HwHPReq2Valid = disabled - * VextSupply3HwHPReq2Valid = HWReq2 controlled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04), - /* - * VanaSwHPReqValid = disabled - * Vaux1SwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00), - /* - * Vaux2SwHPReqValid = disabled - * Vaux3SwHPReqValid = disabled - * VextSupply1SwHPReqValid = disabled - * VextSupply2SwHPReqValid = disabled - * VextSupply3SwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00), - /* - * SysClkReq2Valid1 = SysClkReq2 controlled - * SysClkReq3Valid1 = disabled - * SysClkReq4Valid1 = SysClkReq4 controlled - * SysClkReq5Valid1 = disabled - * SysClkReq6Valid1 = SysClkReq6 controlled - * SysClkReq7Valid1 = disabled - * SysClkReq8Valid1 = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a), - /* - * SysClkReq2Valid2 = disabled - * SysClkReq3Valid2 = disabled - * SysClkReq4Valid2 = disabled - * SysClkReq5Valid2 = disabled - * SysClkReq6Valid2 = SysClkReq6 controlled - * SysClkReq7Valid2 = disabled - * SysClkReq8Valid2 = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20), - /* - * VTVoutEna = disabled - * Vintcore12Ena = disabled - * Vintcore12Sel = 1.25 V - * Vintcore12LP = inactive (HP) - * VTVoutLP = inactive (HP) - */ - INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10), - /* - * VaudioEna = disabled - * VdmicEna = disabled - * Vamic1Ena = disabled - * Vamic2Ena = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00), - /* - * Vamic1_dzout = high-Z when Vamic1 is disabled - * Vamic2_dzout = high-Z when Vamic2 is disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00), - /* - * VPll = Hw controlled - * VanaRegu = force off - */ - INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02), - /* - * VrefDDREna = disabled - * VrefDDRSleepMode = inactive (no pulldown) - */ - INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00), - /* - * VextSupply1Regu = HW control - * VextSupply2Regu = HW control - * VextSupply3Regu = HW control - * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 - * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 - */ - INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a), - /* - * Vaux1Regu = force HP - * Vaux2Regu = force off - */ - INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01), - /* - * Vaux3regu = force off - */ - INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00), - /* - * Vsmps1 = 1.15V - */ - INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24), - /* - * Vaux1Sel = 2.5 V - */ - INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08), - /* - * Vaux2Sel = 2.9 V - */ - INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d), - /* - * Vaux3Sel = 2.91 V - */ - INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07), - /* - * VextSupply12LP = disabled (no LP) - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00), - /* - * Vaux1Disch = short discharge time - * Vaux2Disch = short discharge time - * Vaux3Disch = short discharge time - * Vintcore12Disch = short discharge time - * VTVoutDisch = short discharge time - * VaudioDisch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00), - /* - * VanaDisch = short discharge time - * VdmicPullDownEna = pulldown disabled when Vdmic is disabled - * VdmicDisch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00), -}; - -/* AB8500 regulators */ -struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { - /* supplies to the display/camera */ - [AB8500_LDO_AUX1] = { - .constraints = { - .name = "V-DISPLAY", - .min_uV = 2500000, - .max_uV = 2900000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, /* display is on at boot */ - /* - * This voltage cannot be disabled right now because - * it is somehow affecting the external MMC - * functionality, though that typically will use - * AUX3. - */ - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), - .consumer_supplies = ab8500_vaux1_consumers, - }, - /* supplies to the on-board eMMC */ - [AB8500_LDO_AUX2] = { - .constraints = { - .name = "V-eMMC1", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers), - .consumer_supplies = ab8500_vaux2_consumers, - }, - /* supply for VAUX3, supplies to SDcard slots */ - [AB8500_LDO_AUX3] = { - .constraints = { - .name = "V-MMC-SD", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers), - .consumer_supplies = ab8500_vaux3_consumers, - }, - /* supply for tvout, gpadc, TVOUT LDO */ - [AB8500_LDO_TVOUT] = { - .constraints = { - .name = "V-TVOUT", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers), - .consumer_supplies = ab8500_vtvout_consumers, - }, - /* supply for ab8500-vaudio, VAUDIO LDO */ - [AB8500_LDO_AUDIO] = { - .constraints = { - .name = "V-AUD", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers), - .consumer_supplies = ab8500_vaud_consumers, - }, - /* supply for v-anamic1 VAMic1-LDO */ - [AB8500_LDO_ANAMIC1] = { - .constraints = { - .name = "V-AMIC1", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers), - .consumer_supplies = ab8500_vamic1_consumers, - }, - /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */ - [AB8500_LDO_ANAMIC2] = { - .constraints = { - .name = "V-AMIC2", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers), - .consumer_supplies = ab8500_vamic2_consumers, - }, - /* supply for v-dmic, VDMIC LDO */ - [AB8500_LDO_DMIC] = { - .constraints = { - .name = "V-DMIC", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vdmic_consumers), - .consumer_supplies = ab8500_vdmic_consumers, - }, - /* supply for v-intcore12, VINTCORE12 LDO */ - [AB8500_LDO_INTCORE] = { - .constraints = { - .name = "V-INTCORE", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers), - .consumer_supplies = ab8500_vintcore_consumers, - }, - /* supply for U8500 CSI/DSI, VANA LDO */ - [AB8500_LDO_ANA] = { - .constraints = { - .name = "V-CSI/DSI", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers), - .consumer_supplies = ab8500_vana_consumers, - }, -}; diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-regulators.h b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-regulators.h deleted file mode 100644 index 94992158..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-regulators.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License v2 - * - * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson - * - * MOP500 board specific initialization for regulators - */ - -#ifndef __BOARD_MOP500_REGULATORS_H -#define __BOARD_MOP500_REGULATORS_H - -#include <linux/regulator/machine.h> -#include <linux/regulator/ab8500.h> - -extern struct ab8500_regulator_reg_init -ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; -extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS]; -extern struct regulator_init_data tps61052_regulator; - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-sdi.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-sdi.c deleted file mode 100644 index 920251cf..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-sdi.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/amba/bus.h> -#include <linux/amba/mmci.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <plat/ste_dma40.h> -#include <mach/devices.h> -#include <mach/hardware.h> - -#include "devices-db8500.h" -#include "board-mop500.h" -#include "ste-dma40-db8500.h" - -/* - * v2 has a new version of this block that need to be forced, the number found - * in hardware is incorrect - */ -#define U8500_SDI_V2_PERIPHID 0x10480180 - -/* - * SDI 0 (MicroSD slot) - */ - -/* GPIO pins used by the sdi0 level shifter */ -static int sdi0_en = -1; -static int sdi0_vsel = -1; - -static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios) -{ - switch (ios->power_mode) { - case MMC_POWER_UP: - case MMC_POWER_ON: - /* - * Level shifter voltage should depend on vdd to when deciding - * on either 1.8V or 2.9V. Once the decision has been made the - * level shifter must be disabled and re-enabled with a changed - * select signal in order to switch the voltage. Since there is - * no framework support yet for indicating 1.8V in vdd, use the - * default 2.9V. - */ - gpio_direction_output(sdi0_vsel, 0); - gpio_direction_output(sdi0_en, 1); - break; - case MMC_POWER_OFF: - gpio_direction_output(sdi0_vsel, 0); - gpio_direction_output(sdi0_en, 0); - break; - } - - return 0; -} - -#ifdef CONFIG_STE_DMA40 -struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data mop500_sdi0_data = { - .ios_handler = mop500_sdi0_ios_handler, - .ocr_mask = MMC_VDD_29_30, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | - MMC_CAP_SD_HIGHSPEED | - MMC_CAP_MMC_HIGHSPEED, - .gpio_wp = -1, - .sigdir = MCI_ST_FBCLKEN | - MCI_ST_CMDDIREN | - MCI_ST_DATA0DIREN | - MCI_ST_DATA2DIREN, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &mop500_sdi0_dma_cfg_rx, - .dma_tx_param = &mop500_sdi0_dma_cfg_tx, -#endif -}; - -static void sdi0_configure(struct device *parent) -{ - int ret; - - ret = gpio_request(sdi0_en, "level shifter enable"); - if (!ret) - ret = gpio_request(sdi0_vsel, - "level shifter 1v8-3v select"); - - if (ret) { - pr_warning("unable to config sdi0 gpios for level shifter.\n"); - return; - } - - /* Select the default 2.9V and enable level shifter */ - gpio_direction_output(sdi0_vsel, 0); - gpio_direction_output(sdi0_en, 1); - - /* Add the device, force v2 to subrevision 1 */ - db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID); -} - -void mop500_sdi_tc35892_init(struct device *parent) -{ - mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD; - sdi0_en = GPIO_SDMMC_EN; - sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL; - sdi0_configure(parent); -} - -/* - * SDI1 (SDIO WLAN) - */ -#ifdef CONFIG_STE_DMA40 -static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data mop500_sdi1_data = { - .ocr_mask = MMC_VDD_29_30, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA, - .gpio_cd = -1, - .gpio_wp = -1, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &sdi1_dma_cfg_rx, - .dma_tx_param = &sdi1_dma_cfg_tx, -#endif -}; - -/* - * SDI 2 (POP eMMC, not on DB8500ed) - */ - -#ifdef CONFIG_STE_DMA40 -struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data mop500_sdi2_data = { - .ocr_mask = MMC_VDD_165_195, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, - .gpio_cd = -1, - .gpio_wp = -1, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &mop500_sdi2_dma_cfg_rx, - .dma_tx_param = &mop500_sdi2_dma_cfg_tx, -#endif -}; - -/* - * SDI 4 (on-board eMMC) - */ - -#ifdef CONFIG_STE_DMA40 -struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data mop500_sdi4_data = { - .ocr_mask = MMC_VDD_29_30, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, - .gpio_cd = -1, - .gpio_wp = -1, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &mop500_sdi4_dma_cfg_rx, - .dma_tx_param = &mop500_sdi4_dma_cfg_tx, -#endif -}; - -void __init mop500_sdi_init(struct device *parent) -{ - /* PoP:ed eMMC */ - db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID); - /* On-board eMMC */ - db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); - - /* - * On boards with the TC35892 GPIO expander, sdi0 will finally - * be added when the TC35892 initializes and calls - * mop500_sdi_tc35892_init() above. - */ -} - -void __init snowball_sdi_init(struct device *parent) -{ - /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */ - mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED; - /* On-board eMMC */ - db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); - /* External Micro SD slot */ - mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; - mop500_sdi0_data.cd_invert = true; - sdi0_en = SNOWBALL_SDMMC_EN_GPIO; - sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; - sdi0_configure(parent); -} - -void __init hrefv60_sdi_init(struct device *parent) -{ - /* PoP:ed eMMC */ - db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID); - /* On-board eMMC */ - db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); - /* External Micro SD slot */ - mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; - sdi0_en = HREFV60_SDMMC_EN_GPIO; - sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; - sdi0_configure(parent); - /* WLAN SDIO channel */ - db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-stuib.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-stuib.c deleted file mode 100644 index 8c979770..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-stuib.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL), version 2 - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mfd/stmpe.h> -#include <linux/input/bu21013.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/input/matrix_keypad.h> -#include <asm/mach-types.h> - -#include "board-mop500.h" - -/* STMPE/SKE keypad use this key layout */ -static const unsigned int mop500_keymap[] = { - KEY(2, 5, KEY_END), - KEY(4, 1, KEY_POWER), - KEY(3, 5, KEY_VOLUMEDOWN), - KEY(1, 3, KEY_3), - KEY(5, 2, KEY_RIGHT), - KEY(5, 0, KEY_9), - - KEY(0, 5, KEY_MENU), - KEY(7, 6, KEY_ENTER), - KEY(4, 5, KEY_0), - KEY(6, 7, KEY_2), - KEY(3, 4, KEY_UP), - KEY(3, 3, KEY_DOWN), - - KEY(6, 4, KEY_SEND), - KEY(6, 2, KEY_BACK), - KEY(4, 2, KEY_VOLUMEUP), - KEY(5, 5, KEY_1), - KEY(4, 3, KEY_LEFT), - KEY(3, 2, KEY_7), -}; - -static const struct matrix_keymap_data mop500_keymap_data = { - .keymap = mop500_keymap, - .keymap_size = ARRAY_SIZE(mop500_keymap), -}; -/* - * STMPE1601 - */ -static struct stmpe_keypad_platform_data stmpe1601_keypad_data = { - .debounce_ms = 64, - .scan_count = 8, - .no_autorepeat = true, - .keymap_data = &mop500_keymap_data, -}; - -static struct stmpe_platform_data stmpe1601_data = { - .id = 1, - .blocks = STMPE_BLOCK_KEYPAD, - .irq_trigger = IRQF_TRIGGER_FALLING, - .irq_base = MOP500_STMPE1601_IRQ(0), - .keypad = &stmpe1601_keypad_data, - .autosleep = true, - .autosleep_timeout = 1024, -}; - -static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = { - { - I2C_BOARD_INFO("stmpe1601", 0x40), - .irq = NOMADIK_GPIO_TO_IRQ(218), - .platform_data = &stmpe1601_data, - .flags = I2C_CLIENT_WAKE, - }, -}; - -/* - * BU21013 ROHM touchscreen interface on the STUIBs - */ - -/* tracks number of bu21013 devices being enabled */ -static int bu21013_devices; - -#define TOUCH_GPIO_PIN 84 - -#define TOUCH_XMAX 384 -#define TOUCH_YMAX 704 - -#define PRCMU_CLOCK_OCR 0x1CC -#define TSC_EXT_CLOCK_9_6MHZ 0x840000 - -/** - * bu21013_gpio_board_init : configures the touch panel. - * @reset_pin: reset pin number - * This function can be used to configures - * the voltage and reset the touch panel controller. - */ -static int bu21013_gpio_board_init(int reset_pin) -{ - int retval = 0; - - bu21013_devices++; - if (bu21013_devices == 1) { - retval = gpio_request(reset_pin, "touchp_reset"); - if (retval) { - printk(KERN_ERR "Unable to request gpio reset_pin"); - return retval; - } - retval = gpio_direction_output(reset_pin, 1); - if (retval < 0) { - printk(KERN_ERR "%s: gpio direction failed\n", - __func__); - return retval; - } - } - - return retval; -} - -/** - * bu21013_gpio_board_exit : deconfigures the touch panel controller - * @reset_pin: reset pin number - * This function can be used to deconfigures the chip selection - * for touch panel controller. - */ -static int bu21013_gpio_board_exit(int reset_pin) -{ - int retval = 0; - - if (bu21013_devices == 1) { - retval = gpio_direction_output(reset_pin, 0); - if (retval < 0) { - printk(KERN_ERR "%s: gpio direction failed\n", - __func__); - return retval; - } - gpio_set_value(reset_pin, 0); - } - bu21013_devices--; - - return retval; -} - -/** - * bu21013_read_pin_val : get the interrupt pin value - * This function can be used to get the interrupt pin value for touch panel - * controller. - */ -static int bu21013_read_pin_val(void) -{ - return gpio_get_value(TOUCH_GPIO_PIN); -} - -static struct bu21013_platform_device tsc_plat_device = { - .cs_en = bu21013_gpio_board_init, - .cs_dis = bu21013_gpio_board_exit, - .irq_read_val = bu21013_read_pin_val, - .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN), - .touch_x_max = TOUCH_XMAX, - .touch_y_max = TOUCH_YMAX, - .ext_clk = false, - .x_flip = false, - .y_flip = true, -}; - -static struct bu21013_platform_device tsc_plat2_device = { - .cs_en = bu21013_gpio_board_init, - .cs_dis = bu21013_gpio_board_exit, - .irq_read_val = bu21013_read_pin_val, - .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN), - .touch_x_max = TOUCH_XMAX, - .touch_y_max = TOUCH_YMAX, - .ext_clk = false, - .x_flip = false, - .y_flip = true, -}; - -static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { - { - I2C_BOARD_INFO("bu21013_tp", 0x5C), - .platform_data = &tsc_plat_device, - }, - { - I2C_BOARD_INFO("bu21013_tp", 0x5D), - .platform_data = &tsc_plat2_device, - }, - -}; - -void __init mop500_stuib_init(void) -{ - if (machine_is_hrefv60()) { - tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO; - tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO; - } else { - tsc_plat_device.cs_pin = GPIO_BU21013_CS; - tsc_plat2_device.cs_pin = GPIO_BU21013_CS; - - } - - mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib, - ARRAY_SIZE(mop500_i2c0_devices_stuib)); - - mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib, - ARRAY_SIZE(u8500_i2c3_devices_stuib)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-u8500uib.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-u8500uib.c deleted file mode 100644 index ead91c96..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-u8500uib.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Board data for the U8500 UIB, also known as the New UIB - * License terms: GNU General Public License (GPL), version 2 - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/i2c.h> -#include <linux/interrupt.h> -#include <linux/mfd/tc3589x.h> -#include <linux/input/matrix_keypad.h> - -#include <mach/irqs.h> - -#include "board-mop500.h" - -/* Dummy data that can be overridden by staging driver */ -struct i2c_board_info __initdata __weak mop500_i2c3_devices_u8500[] = { -}; - -/* - * TC35893 - */ -static const unsigned int u8500_keymap[] = { - KEY(3, 1, KEY_END), - KEY(4, 1, KEY_POWER), - KEY(6, 4, KEY_VOLUMEDOWN), - KEY(4, 2, KEY_EMAIL), - KEY(3, 3, KEY_RIGHT), - KEY(2, 5, KEY_BACKSPACE), - - KEY(6, 7, KEY_MENU), - KEY(5, 0, KEY_ENTER), - KEY(4, 3, KEY_0), - KEY(3, 4, KEY_DOT), - KEY(5, 2, KEY_UP), - KEY(3, 5, KEY_DOWN), - - KEY(4, 5, KEY_SEND), - KEY(0, 5, KEY_BACK), - KEY(6, 2, KEY_VOLUMEUP), - KEY(1, 3, KEY_SPACE), - KEY(7, 6, KEY_LEFT), - KEY(5, 5, KEY_SEARCH), -}; - -static struct matrix_keymap_data u8500_keymap_data = { - .keymap = u8500_keymap, - .keymap_size = ARRAY_SIZE(u8500_keymap), -}; - -static struct tc3589x_keypad_platform_data tc35893_data = { - .krow = TC_KPD_ROWS, - .kcol = TC_KPD_COLUMNS, - .debounce_period = TC_KPD_DEBOUNCE_PERIOD, - .settle_time = TC_KPD_SETTLE_TIME, - .irqtype = IRQF_TRIGGER_FALLING, - .enable_wakeup = true, - .keymap_data = &u8500_keymap_data, - .no_autorepeat = true, -}; - -static struct tc3589x_platform_data tc3589x_keypad_data = { - .block = TC3589x_BLOCK_KEYPAD, - .keypad = &tc35893_data, - .irq_base = MOP500_EGPIO_IRQ_BASE, -}; - -static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = { - { - I2C_BOARD_INFO("tc3589x", 0x44), - .platform_data = &tc3589x_keypad_data, - .irq = NOMADIK_GPIO_TO_IRQ(218), - .flags = I2C_CLIENT_WAKE, - }, -}; - - -void __init mop500_u8500uib_init(void) -{ - mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500, - ARRAY_SIZE(mop500_i2c3_devices_u8500)); - - mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500, - ARRAY_SIZE(mop500_i2c0_devices_u8500)); - -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-uib.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-uib.c deleted file mode 100644 index 5af36aa5..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500-uib.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2 - */ - -#define pr_fmt(fmt) "mop500-uib: " fmt - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/i2c.h> - -#include <mach/hardware.h> -#include "board-mop500.h" - -enum mop500_uib { - STUIB, - U8500UIB, -}; - -struct uib { - const char *name; - const char *option; - void (*init)(void); -}; - -static struct uib __initdata mop500_uibs[] = { - [STUIB] = { - .name = "ST-UIB", - .option = "stuib", - .init = mop500_stuib_init, - }, - [U8500UIB] = { - .name = "U8500-UIB", - .option = "u8500uib", - .init = mop500_u8500uib_init, - }, -}; - -static struct uib *mop500_uib; - -static int __init mop500_uib_setup(char *str) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) { - struct uib *uib = &mop500_uibs[i]; - - if (!strcmp(str, uib->option)) { - mop500_uib = uib; - break; - } - } - - if (i == ARRAY_SIZE(mop500_uibs)) - pr_err("invalid uib= option (%s)\n", str); - - return 1; -} -__setup("uib=", mop500_uib_setup); - -/* - * The UIBs are detected after the I2C host controllers are registered, so - * i2c_register_board_info() can't be used. - */ -void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, - unsigned n) -{ - struct i2c_adapter *adap; - struct i2c_client *client; - int i; - - adap = i2c_get_adapter(busnum); - if (!adap) { - pr_err("failed to get adapter i2c%d\n", busnum); - return; - } - - for (i = 0; i < n; i++) { - client = i2c_new_device(adap, &info[i]); - if (!client) - pr_err("failed to register %s to i2c%d\n", - info[i].type, busnum); - } - - i2c_put_adapter(adap); -} - -static void __init __mop500_uib_init(struct uib *uib, const char *why) -{ - pr_info("%s (%s)\n", uib->name, why); - uib->init(); -} - -/* - * Detect the UIB attached based on the presence or absence of i2c devices. - */ -static int __init mop500_uib_init(void) -{ - struct uib *uib = mop500_uib; - struct i2c_adapter *i2c0; - int ret; - - if (!cpu_is_u8500()) - return -ENODEV; - - if (uib) { - __mop500_uib_init(uib, "from uib= boot argument"); - return 0; - } - - i2c0 = i2c_get_adapter(0); - if (!i2c0) { - __mop500_uib_init(&mop500_uibs[STUIB], - "fallback, could not get i2c0"); - return -ENODEV; - } - - /* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */ - ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0, - I2C_SMBUS_QUICK, NULL); - i2c_put_adapter(i2c0); - - if (ret == 0) - uib = &mop500_uibs[U8500UIB]; - else - uib = &mop500_uibs[STUIB]; - - __mop500_uib_init(uib, "detected"); - - return 0; -} - -module_init(mop500_uib_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500.c deleted file mode 100644 index 77d03c1f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500.c +++ /dev/null @@ -1,835 +0,0 @@ -/* - * Copyright (C) 2008-2009 ST-Ericsson - * - * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/amba/bus.h> -#include <linux/amba/pl022.h> -#include <linux/amba/serial.h> -#include <linux/spi/spi.h> -#include <linux/mfd/abx500/ab8500.h> -#include <linux/regulator/ab8500.h> -#include <linux/mfd/tc3589x.h> -#include <linux/mfd/tps6105x.h> -#include <linux/mfd/abx500/ab8500-gpio.h> -#include <linux/leds-lp5521.h> -#include <linux/input.h> -#include <linux/smsc911x.h> -#include <linux/gpio_keys.h> -#include <linux/delay.h> - -#include <linux/of.h> -#include <linux/of_platform.h> - -#include <linux/leds.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/hardware/gic.h> - -#include <plat/i2c.h> -#include <plat/ste_dma40.h> -#include <plat/pincfg.h> -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/devices.h> -#include <mach/irqs.h> - -#include "pins-db8500.h" -#include "ste-dma40-db8500.h" -#include "devices-db8500.h" -#include "board-mop500.h" -#include "board-mop500-regulators.h" - -static struct gpio_led snowball_led_array[] = { - { - .name = "user_led", - .default_trigger = "none", - .gpio = 142, - }, -}; - -static struct gpio_led_platform_data snowball_led_data = { - .leds = snowball_led_array, - .num_leds = ARRAY_SIZE(snowball_led_array), -}; - -static struct platform_device snowball_led_dev = { - .name = "leds-gpio", - .dev = { - .platform_data = &snowball_led_data, - }, -}; - -static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { - .gpio_base = MOP500_AB8500_PIN_GPIO(1), - .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, - /* config_reg is the initial configuration of ab8500 pins. - * The pins can be configured as GPIO or alt functions based - * on value present in GpioSel1 to GpioSel6 and AlternatFunction - * register. This is the array of 7 configuration settings. - * One has to compile time decide these settings. Below is the - * explanation of these setting - * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO - * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO - * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO - * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO - * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO - * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO - * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured - * as GPIO then this register selectes the alternate fucntions - */ - .config_reg = {0x00, 0x1E, 0x80, 0x01, - 0x7A, 0x00, 0x00}, -}; - -static struct gpio_keys_button snowball_key_array[] = { - { - .gpio = 32, - .type = EV_KEY, - .code = KEY_1, - .desc = "userpb", - .active_low = 1, - .debounce_interval = 50, - .wakeup = 1, - }, - { - .gpio = 151, - .type = EV_KEY, - .code = KEY_2, - .desc = "extkb1", - .active_low = 1, - .debounce_interval = 50, - .wakeup = 1, - }, - { - .gpio = 152, - .type = EV_KEY, - .code = KEY_3, - .desc = "extkb2", - .active_low = 1, - .debounce_interval = 50, - .wakeup = 1, - }, - { - .gpio = 161, - .type = EV_KEY, - .code = KEY_4, - .desc = "extkb3", - .active_low = 1, - .debounce_interval = 50, - .wakeup = 1, - }, - { - .gpio = 162, - .type = EV_KEY, - .code = KEY_5, - .desc = "extkb4", - .active_low = 1, - .debounce_interval = 50, - .wakeup = 1, - }, -}; - -static struct gpio_keys_platform_data snowball_key_data = { - .buttons = snowball_key_array, - .nbuttons = ARRAY_SIZE(snowball_key_array), -}; - -static struct platform_device snowball_key_dev = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &snowball_key_data, - } -}; - -static struct smsc911x_platform_config snowball_sbnet_cfg = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .shift = 1, -}; - -static struct resource sbnet_res[] = { - { - .name = "smsc911x-memory", - .start = (0x5000 << 16), - .end = (0x5000 << 16) + 0xffff, - .flags = IORESOURCE_MEM, - }, - { - .start = NOMADIK_GPIO_TO_IRQ(140), - .end = NOMADIK_GPIO_TO_IRQ(140), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device snowball_sbnet_dev = { - .name = "smsc911x", - .num_resources = ARRAY_SIZE(sbnet_res), - .resource = sbnet_res, - .dev = { - .platform_data = &snowball_sbnet_cfg, - }, -}; - -static struct ab8500_platform_data ab8500_platdata = { - .irq_base = MOP500_AB8500_IRQ_BASE, - .regulator_reg_init = ab8500_regulator_reg_init, - .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init), - .regulator = ab8500_regulators, - .num_regulator = ARRAY_SIZE(ab8500_regulators), - .gpio = &ab8500_gpio_pdata, -}; - -static struct resource ab8500_resources[] = { - [0] = { - .start = IRQ_DB8500_AB8500, - .end = IRQ_DB8500_AB8500, - .flags = IORESOURCE_IRQ - } -}; - -struct platform_device ab8500_device = { - .name = "ab8500-i2c", - .id = 0, - .dev = { - .platform_data = &ab8500_platdata, - }, - .num_resources = 1, - .resource = ab8500_resources, -}; - -/* - * TPS61052 - */ - -static struct tps6105x_platform_data mop500_tps61052_data = { - .mode = TPS6105X_MODE_VOLTAGE, - .regulator_data = &tps61052_regulator, -}; - -/* - * TC35892 - */ - -static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) -{ - struct device *parent = NULL; -#if 0 - /* FIXME: Is the sdi actually part of tc3589x? */ - parent = tc3589x->dev; -#endif - mop500_sdi_tc35892_init(parent); -} - -static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { - .gpio_base = MOP500_EGPIO(0), - .setup = mop500_tc35892_init, -}; - -static struct tc3589x_platform_data mop500_tc35892_data = { - .block = TC3589x_BLOCK_GPIO, - .gpio = &mop500_tc35892_gpio_data, - .irq_base = MOP500_EGPIO_IRQ_BASE, -}; - -static struct lp5521_led_config lp5521_pri_led[] = { - [0] = { - .chan_nr = 0, - .led_current = 0x2f, - .max_current = 0x5f, - }, - [1] = { - .chan_nr = 1, - .led_current = 0x2f, - .max_current = 0x5f, - }, - [2] = { - .chan_nr = 2, - .led_current = 0x2f, - .max_current = 0x5f, - }, -}; - -static struct lp5521_platform_data __initdata lp5521_pri_data = { - .label = "lp5521_pri", - .led_config = &lp5521_pri_led[0], - .num_channels = 3, - .clock_mode = LP5521_CLOCK_EXT, -}; - -static struct lp5521_led_config lp5521_sec_led[] = { - [0] = { - .chan_nr = 0, - .led_current = 0x2f, - .max_current = 0x5f, - }, - [1] = { - .chan_nr = 1, - .led_current = 0x2f, - .max_current = 0x5f, - }, - [2] = { - .chan_nr = 2, - .led_current = 0x2f, - .max_current = 0x5f, - }, -}; - -static struct lp5521_platform_data __initdata lp5521_sec_data = { - .label = "lp5521_sec", - .led_config = &lp5521_sec_led[0], - .num_channels = 3, - .clock_mode = LP5521_CLOCK_EXT, -}; - -static struct i2c_board_info __initdata mop500_i2c0_devices[] = { - { - I2C_BOARD_INFO("tc3589x", 0x42), - .irq = NOMADIK_GPIO_TO_IRQ(217), - .platform_data = &mop500_tc35892_data, - }, - /* I2C0 devices only available prior to HREFv60 */ - { - I2C_BOARD_INFO("tps61052", 0x33), - .platform_data = &mop500_tps61052_data, - }, -}; - -#define NUM_PRE_V60_I2C0_DEVICES 1 - -static struct i2c_board_info __initdata mop500_i2c2_devices[] = { - { - /* lp5521 LED driver, 1st device */ - I2C_BOARD_INFO("lp5521", 0x33), - .platform_data = &lp5521_pri_data, - }, - { - /* lp5521 LED driver, 2st device */ - I2C_BOARD_INFO("lp5521", 0x34), - .platform_data = &lp5521_sec_data, - }, - { - /* Light sensor Rohm BH1780GLI */ - I2C_BOARD_INFO("bh1780", 0x29), - }, -}; - -#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm) \ -static struct nmk_i2c_controller u8500_i2c##id##_data = { \ - /* \ - * slave data setup time, which is \ - * 250 ns,100ns,10ns which is 14,6,2 \ - * respectively for a 48 Mhz \ - * i2c clock \ - */ \ - .slsu = _slsu, \ - /* Tx FIFO threshold */ \ - .tft = _tft, \ - /* Rx FIFO threshold */ \ - .rft = _rft, \ - /* std. mode operation */ \ - .clk_freq = clk, \ - /* Slave response timeout(ms) */\ - .timeout = t_out, \ - .sm = _sm, \ -} - -/* - * The board uses 4 i2c controllers, initialize all of - * them with slave data setup time of 250 ns, - * Tx & Rx FIFO threshold values as 8 and standard - * mode of operation - */ -U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); - -static void __init mop500_i2c_init(struct device *parent) -{ - db8500_add_i2c0(parent, &u8500_i2c0_data); - db8500_add_i2c1(parent, &u8500_i2c1_data); - db8500_add_i2c2(parent, &u8500_i2c2_data); - db8500_add_i2c3(parent, &u8500_i2c3_data); -} - -static struct gpio_keys_button mop500_gpio_keys[] = { - { - .desc = "SFH7741 Proximity Sensor", - .type = EV_SW, - .code = SW_FRONT_PROXIMITY, - .active_low = 0, - .can_disable = 1, - } -}; - -static struct regulator *prox_regulator; -static int mop500_prox_activate(struct device *dev); -static void mop500_prox_deactivate(struct device *dev); - -static struct gpio_keys_platform_data mop500_gpio_keys_data = { - .buttons = mop500_gpio_keys, - .nbuttons = ARRAY_SIZE(mop500_gpio_keys), - .enable = mop500_prox_activate, - .disable = mop500_prox_deactivate, -}; - -static struct platform_device mop500_gpio_keys_device = { - .name = "gpio-keys", - .id = 0, - .dev = { - .platform_data = &mop500_gpio_keys_data, - }, -}; - -static int mop500_prox_activate(struct device *dev) -{ - prox_regulator = regulator_get(&mop500_gpio_keys_device.dev, - "vcc"); - if (IS_ERR(prox_regulator)) { - dev_err(&mop500_gpio_keys_device.dev, - "no regulator\n"); - return PTR_ERR(prox_regulator); - } - regulator_enable(prox_regulator); - return 0; -} - -static void mop500_prox_deactivate(struct device *dev) -{ - regulator_disable(prox_regulator); - regulator_put(prox_regulator); -} - -/* add any platform devices here - TODO */ -static struct platform_device *mop500_platform_devs[] __initdata = { - &mop500_gpio_keys_device, - &ab8500_device, -}; - -#ifdef CONFIG_STE_DMA40 -static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV8_SSP0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; - -static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; -#endif - -static struct pl022_ssp_controller ssp0_plat = { - .bus_id = 0, -#ifdef CONFIG_STE_DMA40 - .enable_dma = 1, - .dma_filter = stedma40_filter, - .dma_rx_param = &ssp0_dma_cfg_rx, - .dma_tx_param = &ssp0_dma_cfg_tx, -#else - .enable_dma = 0, -#endif - /* on this platform, gpio 31,142,144,214 & - * 224 are connected as chip selects - */ - .num_chipselect = 5, -}; - -static void __init mop500_spi_init(struct device *parent) -{ - db8500_add_ssp0(parent, &ssp0_plat); -} - -#ifdef CONFIG_STE_DMA40 -static struct stedma40_chan_cfg uart0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV13_UART0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; - -static struct stedma40_chan_cfg uart0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV13_UART0_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; - -static struct stedma40_chan_cfg uart1_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV12_UART1_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; - -static struct stedma40_chan_cfg uart1_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV12_UART1_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; - -static struct stedma40_chan_cfg uart2_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV11_UART2_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; - -static struct stedma40_chan_cfg uart2_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV11_UART2_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, -}; -#endif - - -static pin_cfg_t mop500_pins_uart0[] = { - GPIO0_U0_CTSn | PIN_INPUT_PULLUP, - GPIO1_U0_RTSn | PIN_OUTPUT_HIGH, - GPIO2_U0_RXD | PIN_INPUT_PULLUP, - GPIO3_U0_TXD | PIN_OUTPUT_HIGH, -}; - -#define PRCC_K_SOFTRST_SET 0x18 -#define PRCC_K_SOFTRST_CLEAR 0x1C -static void ux500_uart0_reset(void) -{ - void __iomem *prcc_rst_set, *prcc_rst_clr; - - prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + - PRCC_K_SOFTRST_SET); - prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + - PRCC_K_SOFTRST_CLEAR); - - /* Activate soft reset PRCC_K_SOFTRST_CLEAR */ - writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr); - udelay(1); - - /* Release soft reset PRCC_K_SOFTRST_SET */ - writel((readl(prcc_rst_set) | 0x1), prcc_rst_set); - udelay(1); -} - -static void ux500_uart0_init(void) -{ - int ret; - - ret = nmk_config_pins(mop500_pins_uart0, - ARRAY_SIZE(mop500_pins_uart0)); - if (ret < 0) - pr_err("pl011: uart pins_enable failed\n"); -} - -static void ux500_uart0_exit(void) -{ - int ret; - - ret = nmk_config_pins_sleep(mop500_pins_uart0, - ARRAY_SIZE(mop500_pins_uart0)); - if (ret < 0) - pr_err("pl011: uart pins_disable failed\n"); -} - -static struct amba_pl011_data uart0_plat = { -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &uart0_dma_cfg_rx, - .dma_tx_param = &uart0_dma_cfg_tx, -#endif - .init = ux500_uart0_init, - .exit = ux500_uart0_exit, - .reset = ux500_uart0_reset, -}; - -static struct amba_pl011_data uart1_plat = { -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &uart1_dma_cfg_rx, - .dma_tx_param = &uart1_dma_cfg_tx, -#endif -}; - -static struct amba_pl011_data uart2_plat = { -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &uart2_dma_cfg_rx, - .dma_tx_param = &uart2_dma_cfg_tx, -#endif -}; - -static void __init mop500_uart_init(struct device *parent) -{ - db8500_add_uart0(parent, &uart0_plat); - db8500_add_uart1(parent, &uart1_plat); - db8500_add_uart2(parent, &uart2_plat); -} - -static struct platform_device *snowball_platform_devs[] __initdata = { - &snowball_led_dev, - &snowball_key_dev, - &snowball_sbnet_dev, - &ab8500_device, -}; - -static void __init mop500_init_machine(void) -{ - struct device *parent = NULL; - int i2c0_devs; - int i; - - mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; - - parent = u8500_init_devices(); - - mop500_pins_init(); - - /* FIXME: parent of ab8500 should be prcmu */ - for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) - mop500_platform_devs[i]->dev.parent = parent; - - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); - - mop500_i2c_init(parent); - mop500_sdi_init(parent); - mop500_spi_init(parent); - mop500_uart_init(parent); - - i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - - i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); - i2c_register_board_info(2, mop500_i2c2_devices, - ARRAY_SIZE(mop500_i2c2_devices)); - - /* This board has full regulator constraints */ - regulator_has_full_constraints(); -} - -static void __init snowball_init_machine(void) -{ - struct device *parent = NULL; - int i2c0_devs; - int i; - - parent = u8500_init_devices(); - - snowball_pins_init(); - - for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) - snowball_platform_devs[i]->dev.parent = parent; - - platform_add_devices(snowball_platform_devs, - ARRAY_SIZE(snowball_platform_devs)); - - mop500_i2c_init(parent); - snowball_sdi_init(parent); - mop500_spi_init(parent); - mop500_uart_init(parent); - - i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); - i2c_register_board_info(2, mop500_i2c2_devices, - ARRAY_SIZE(mop500_i2c2_devices)); - - /* This board has full regulator constraints */ - regulator_has_full_constraints(); -} - -static void __init hrefv60_init_machine(void) -{ - struct device *parent = NULL; - int i2c0_devs; - int i; - - /* - * The HREFv60 board removed a GPIO expander and routed - * all these GPIO pins to the internal GPIO controller - * instead. - */ - mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; - - parent = u8500_init_devices(); - - hrefv60_pins_init(); - - for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) - mop500_platform_devs[i]->dev.parent = parent; - - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); - - mop500_i2c_init(parent); - hrefv60_sdi_init(parent); - mop500_spi_init(parent); - mop500_uart_init(parent); - - i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - - i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; - - i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); - i2c_register_board_info(2, mop500_i2c2_devices, - ARRAY_SIZE(mop500_i2c2_devices)); - - /* This board has full regulator constraints */ - regulator_has_full_constraints(); -} - -MACHINE_START(U8500, "ST-Ericsson MOP500 platform") - /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ - .atag_offset = 0x100, - .map_io = u8500_map_io, - .init_irq = ux500_init_irq, - /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = mop500_init_machine, -MACHINE_END - -MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") - .atag_offset = 0x100, - .map_io = u8500_map_io, - .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = hrefv60_init_machine, -MACHINE_END - -MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") - .atag_offset = 0x100, - .map_io = u8500_map_io, - .init_irq = ux500_init_irq, - /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = snowball_init_machine, -MACHINE_END - -#ifdef CONFIG_MACH_UX500_DT - -struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), - OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), - OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), - OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), - {}, -}; - -static const struct of_device_id u8500_soc_node[] = { - /* only create devices below soc node */ - { .compatible = "stericsson,db8500", }, - { }, -}; - -static void __init u8500_init_machine(void) -{ - struct device *parent = NULL; - int i2c0_devs; - int i; - - parent = u8500_init_devices(); - i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - - for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) - mop500_platform_devs[i]->dev.parent = parent; - for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) - snowball_platform_devs[i]->dev.parent = parent; - - /* automatically probe child nodes of db8500 device */ - of_platform_populate(NULL, u8500_soc_node, u8500_auxdata_lookup, parent); - - if (of_machine_is_compatible("st-ericsson,mop500")) { - mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; - mop500_pins_init(); - - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); - - mop500_sdi_init(parent); - } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { - snowball_pins_init(); - platform_add_devices(snowball_platform_devs, - ARRAY_SIZE(snowball_platform_devs)); - - snowball_sdi_init(parent); - } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { - /* - * The HREFv60 board removed a GPIO expander and routed - * all these GPIO pins to the internal GPIO controller - * instead. - */ - mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; - i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; - hrefv60_pins_init(); - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); - - hrefv60_sdi_init(parent); - } - mop500_i2c_init(parent); - - i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); - i2c_register_board_info(2, mop500_i2c2_devices, - ARRAY_SIZE(mop500_i2c2_devices)); - - /* This board has full regulator constraints */ - regulator_has_full_constraints(); -} - -static const char * u8500_dt_board_compat[] = { - "calaosystems,snowball-a9500", - "st-ericsson,hrefv60+", - "st-ericsson,u8500", - "st-ericsson,mop500", - NULL, -}; - - -DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") - .map_io = u8500_map_io, - .init_irq = ux500_init_irq, - /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = u8500_init_machine, - .dt_compat = u8500_dt_board_compat, -MACHINE_END -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500.h deleted file mode 100644 index fdcfa872..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-mop500.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __BOARD_MOP500_H -#define __BOARD_MOP500_H - -/* Snowball specific GPIO assignments, this board has no GPIO expander */ -#define SNOWBALL_ACCEL_INT1_GPIO 163 -#define SNOWBALL_ACCEL_INT2_GPIO 164 -#define SNOWBALL_MAGNET_DRDY_GPIO 165 -#define SNOWBALL_SDMMC_EN_GPIO 217 -#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 -#define SNOWBALL_SDMMC_CD_GPIO 218 - -/* HREFv60-specific GPIO assignments, this board has no GPIO expander */ -#define HREFV60_SDMMC_1V8_3V_GPIO 5 -#define HREFV60_CAMERA_FLASH_ENABLE 21 -#define HREFV60_MAGNET_DRDY_GPIO 32 -#define HREFV60_DISP1_RST_GPIO 65 -#define HREFV60_DISP2_RST_GPIO 66 -#define HREFV60_ACCEL_INT1_GPIO 82 -#define HREFV60_ACCEL_INT2_GPIO 83 -#define HREFV60_SDMMC_CD_GPIO 95 -#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140 -#define HREFV60_TOUCH_RST_GPIO 143 -#define HREFV60_HAL_SW_GPIO 145 -#define HREFV60_SDMMC_EN_GPIO 169 -#define HREFV60_MMIO_XENON_CHARGE 170 -#define HREFV60_PROX_SENSE_GPIO 217 - -/* MOP500 generic GPIOs */ -#define CAMERA_FLASH_INT_PIN 7 -#define CYPRESS_TOUCH_INT_PIN 84 -#define XSHUTDOWN_PRIMARY_SENSOR 141 -#define XSHUTDOWN_SECONDARY_SENSOR 142 -#define CYPRESS_TOUCH_RST_GPIO 143 -#define MOP500_HDMI_RST_GPIO 196 -#define CYPRESS_SLAVE_SELECT_GPIO 216 - -/* GPIOs on the TC35892 expander */ -#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) -#define GPIO_MAGNET_DRDY MOP500_EGPIO(1) -#define GPIO_SDMMC_CD MOP500_EGPIO(3) -#define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4) -#define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5) -#define GPIO_PROX_SENSOR MOP500_EGPIO(7) -#define GPIO_HAL_SENSOR MOP500_EGPIO(8) -#define GPIO_ACCEL_INT1 MOP500_EGPIO(10) -#define GPIO_ACCEL_INT2 MOP500_EGPIO(11) -#define GPIO_BU21013_CS MOP500_EGPIO(13) -#define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14) -#define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15) -#define GPIO_SDMMC_EN MOP500_EGPIO(17) -#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) -#define MOP500_EGPIO_END MOP500_EGPIO(24) - -/* - * GPIOs on the AB8500 mixed-signals circuit - * Notice that we subtract 1 from the number passed into the macro, this is - * because the AB8500 GPIO pins are enumbered starting from 1, so the value in - * parens matches the GPIO pin number in the data sheet. - */ -#define MOP500_AB8500_PIN_GPIO(x) (MOP500_EGPIO_END + (x) - 1) -/*Snowball AB8500 GPIO */ -#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */ -#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */ -#define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */ -#define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */ -#define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */ -#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ -#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ - -struct i2c_board_info; - -extern void mop500_sdi_init(struct device *parent); -extern void snowball_sdi_init(struct device *parent); -extern void hrefv60_sdi_init(struct device *parent); -extern void mop500_sdi_tc35892_init(struct device *parent); -void __init mop500_u8500uib_init(void); -void __init mop500_stuib_init(void); -void __init mop500_pins_init(void); -void __init hrefv60_pins_init(void); -void __init snowball_pins_init(void); - -void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, - unsigned n); - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-u5500-sdi.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-u5500-sdi.c deleted file mode 100644 index 836112ee..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-u5500-sdi.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Hanumath Prasad <ulf.hansson@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/amba/mmci.h> -#include <linux/mmc/host.h> - -#include <plat/pincfg.h> -#include <plat/gpio-nomadik.h> -#include <mach/db5500-regs.h> -#include <plat/ste_dma40.h> - -#include "pins-db5500.h" -#include "devices-db5500.h" -#include "ste-dma40-db5500.h" - -static pin_cfg_t u5500_sdi_pins[] = { - /* SDI0 (POP eMMC) */ - GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW, -}; - -#ifdef CONFIG_STE_DMA40 -struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data u5500_sdi0_data = { - .ocr_mask = MMC_VDD_165_195, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | - MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, - .gpio_cd = -1, - .gpio_wp = -1, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &u5500_sdi0_dma_cfg_rx, - .dma_tx_param = &u5500_sdi0_dma_cfg_tx, -#endif -}; - -void __init u5500_sdi_init(struct device *parent) -{ - nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); - - db5500_add_sdi0(parent, &u5500_sdi0_data); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/board-u5500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/board-u5500.c deleted file mode 100644 index 0ff4be72..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/board-u5500.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/mfd/abx500/ab5500.h> - -#include <asm/hardware/gic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/pincfg.h> -#include <plat/i2c.h> -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/devices.h> -#include <mach/setup.h> - -#include "pins-db5500.h" -#include "devices-db5500.h" -#include <linux/led-lm3530.h> - -/* - * GPIO - */ - -static pin_cfg_t u5500_pins[] = { - /* I2C */ - GPIO218_I2C2_SCL | PIN_INPUT_PULLUP, - GPIO219_I2C2_SDA | PIN_INPUT_PULLUP, - - /* DISPLAY_ENABLE */ - GPIO226_GPIO | PIN_OUTPUT_LOW, - - /* Backlight Enbale */ - GPIO224_GPIO | PIN_OUTPUT_HIGH, -}; -/* - * I2C - */ - -#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ -static struct nmk_i2c_controller u5500_i2c##id##_data = { \ - /* \ - * slave data setup time, which is \ - * 250 ns,100ns,10ns which is 14,6,2 \ - * respectively for a 48 Mhz \ - * i2c clock \ - */ \ - .slsu = _slsu, \ - /* Tx FIFO threshold */ \ - .tft = _tft, \ - /* Rx FIFO threshold */ \ - .rft = _rft, \ - /* std. mode operation */ \ - .clk_freq = clk, \ - .sm = _sm, \ -} -/* - * The board uses TODO <3> i2c controllers, initialize all of - * them with slave data setup time of 250 ns, - * Tx & Rx FIFO threshold values as 1 and standard - * mode of operation - */ - -U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST); - -static struct lm3530_platform_data u5500_als_platform_data = { - .mode = LM3530_BL_MODE_MANUAL, - .als_input_mode = LM3530_INPUT_ALS1, - .max_current = LM3530_FS_CURR_26mA, - .pwm_pol_hi = true, - .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms, - .brt_ramp_law = 1, /* Linear */ - .brt_ramp_fall = LM3530_RAMP_TIME_8s, - .brt_ramp_rise = LM3530_RAMP_TIME_8s, - .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm, - .als2_resistor_sel = LM3530_ALS_IMPD_Z, - .als_vmin = 730, /* mV */ - .als_vmax = 1020, /* mV */ - .brt_val = 0x7F, /* Max brightness */ -}; - -static struct i2c_board_info __initdata u5500_i2c2_devices[] = { - { - /* Backlight */ - I2C_BOARD_INFO("lm3530-led", 0x36), - .platform_data = &u5500_als_platform_data, - }, -}; - -static void __init u5500_i2c_init(struct device *parent) -{ - db5500_add_i2c2(parent, &u5500_i2c2_data); - i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices)); -} - -static struct ab5500_platform_data ab5500_plf_data = { - .irq = { - .base = 0, - .count = 0, - }, - .init_settings = NULL, - .init_settings_sz = 0, - .pm_power_off = false, -}; - -static struct platform_device ab5500_device = { - .name = "ab5500-core", - .id = 0, - .dev = { - .platform_data = &ab5500_plf_data, - }, - .num_resources = 0, -}; - -static struct platform_device *u5500_platform_devices[] __initdata = { - &ab5500_device, -}; - -static void __init u5500_uart_init(struct device *parent) -{ - db5500_add_uart0(parent, NULL); - db5500_add_uart1(parent, NULL); - db5500_add_uart2(parent, NULL); -} - -static void __init u5500_init_machine(void) -{ - struct device *parent = NULL; - int i; - - parent = u5500_init_devices(); - nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins)); - - u5500_i2c_init(parent); - u5500_sdi_init(parent); - u5500_uart_init(parent); - - for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++) - u5500_platform_devices[i]->dev.parent = parent; - - platform_add_devices(u5500_platform_devices, - ARRAY_SIZE(u5500_platform_devices)); -} - -MACHINE_START(U5500, "ST-Ericsson U5500 Platform") - .atag_offset = 0x100, - .map_io = u5500_map_io, - .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = u5500_init_machine, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/cache-l2x0.c b/ANDROID_3.4.5/arch/arm/mach-ux500/cache-l2x0.c deleted file mode 100644 index 77a75ed0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/cache-l2x0.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2011 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/io.h> -#include <linux/of.h> - -#include <asm/cacheflush.h> -#include <asm/hardware/cache-l2x0.h> -#include <mach/hardware.h> -#include <mach/id.h> - -static void __iomem *l2x0_base; - -static int __init ux500_l2x0_unlock(void) -{ - int i; - - /* - * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions - * apparently locks both caches before jumping to the kernel. The - * l2x0 core will not touch the unlock registers if the l2x0 is - * already enabled, so we do it right here instead. The PL310 has - * 8 sets of registers, one per possible CPU. - */ - for (i = 0; i < 8; i++) { - writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + - i * L2X0_LOCKDOWN_STRIDE); - writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + - i * L2X0_LOCKDOWN_STRIDE); - } - return 0; -} - -static int __init ux500_l2x0_init(void) -{ - if (cpu_is_u5500()) - l2x0_base = __io_address(U5500_L2CC_BASE); - else if (cpu_is_u8500()) - l2x0_base = __io_address(U8500_L2CC_BASE); - else - ux500_unknown_soc(); - - /* Unlock before init */ - ux500_l2x0_unlock(); - - /* 64KB way size, 8 way associativity, force WA */ - if (of_have_populated_dt()) - l2x0_of_init(0x3e060000, 0xc0000fff); - else - l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); - - /* - * We can't disable l2 as we are in non secure mode, currently - * this seems be called only during kexec path. So let's - * override outer.disable with nasty assignment until we have - * some SMI service available. - */ - outer_cache.disable = NULL; - - return 0; -} - -early_initcall(ux500_l2x0_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/clock.c b/ANDROID_3.4.5/arch/arm/mach-ux500/clock.c deleted file mode 100644 index ec35f0aa..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/clock.c +++ /dev/null @@ -1,723 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * Copyright (C) 2009 STMicroelectronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/cpufreq.h> - -#include <plat/mtu.h> -#include <mach/hardware.h> -#include "clock.h" - -#ifdef CONFIG_DEBUG_FS -#include <linux/debugfs.h> -#include <linux/uaccess.h> /* for copy_from_user */ -static LIST_HEAD(clk_list); -#endif - -#define PRCC_PCKEN 0x00 -#define PRCC_PCKDIS 0x04 -#define PRCC_KCKEN 0x08 -#define PRCC_KCKDIS 0x0C - -#define PRCM_YYCLKEN0_MGT_SET 0x510 -#define PRCM_YYCLKEN1_MGT_SET 0x514 -#define PRCM_YYCLKEN0_MGT_CLR 0x518 -#define PRCM_YYCLKEN1_MGT_CLR 0x51C -#define PRCM_YYCLKEN0_MGT_VAL 0x520 -#define PRCM_YYCLKEN1_MGT_VAL 0x524 - -#define PRCM_SVAMMDSPCLK_MGT 0x008 -#define PRCM_SIAMMDSPCLK_MGT 0x00C -#define PRCM_SGACLK_MGT 0x014 -#define PRCM_UARTCLK_MGT 0x018 -#define PRCM_MSP02CLK_MGT 0x01C -#define PRCM_MSP1CLK_MGT 0x288 -#define PRCM_I2CCLK_MGT 0x020 -#define PRCM_SDMMCCLK_MGT 0x024 -#define PRCM_SLIMCLK_MGT 0x028 -#define PRCM_PER1CLK_MGT 0x02C -#define PRCM_PER2CLK_MGT 0x030 -#define PRCM_PER3CLK_MGT 0x034 -#define PRCM_PER5CLK_MGT 0x038 -#define PRCM_PER6CLK_MGT 0x03C -#define PRCM_PER7CLK_MGT 0x040 -#define PRCM_LCDCLK_MGT 0x044 -#define PRCM_BMLCLK_MGT 0x04C -#define PRCM_HSITXCLK_MGT 0x050 -#define PRCM_HSIRXCLK_MGT 0x054 -#define PRCM_HDMICLK_MGT 0x058 -#define PRCM_APEATCLK_MGT 0x05C -#define PRCM_APETRACECLK_MGT 0x060 -#define PRCM_MCDECLK_MGT 0x064 -#define PRCM_IPI2CCLK_MGT 0x068 -#define PRCM_DSIALTCLK_MGT 0x06C -#define PRCM_DMACLK_MGT 0x074 -#define PRCM_B2R2CLK_MGT 0x078 -#define PRCM_TVCLK_MGT 0x07C -#define PRCM_TCR 0x1C8 -#define PRCM_TCR_STOPPED (1 << 16) -#define PRCM_TCR_DOZE_MODE (1 << 17) -#define PRCM_UNIPROCLK_MGT 0x278 -#define PRCM_SSPCLK_MGT 0x280 -#define PRCM_RNGCLK_MGT 0x284 -#define PRCM_UICCCLK_MGT 0x27C - -#define PRCM_MGT_ENABLE (1 << 8) - -static DEFINE_SPINLOCK(clocks_lock); - -static void __clk_enable(struct clk *clk) -{ - if (clk->enabled++ == 0) { - if (clk->parent_cluster) - __clk_enable(clk->parent_cluster); - - if (clk->parent_periph) - __clk_enable(clk->parent_periph); - - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - } -} - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - __clk_enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void __clk_disable(struct clk *clk) -{ - if (--clk->enabled == 0) { - if (clk->ops && clk->ops->disable) - clk->ops->disable(clk); - - if (clk->parent_periph) - __clk_disable(clk->parent_periph); - - if (clk->parent_cluster) - __clk_disable(clk->parent_cluster); - } -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - WARN_ON(!clk->enabled); - - spin_lock_irqsave(&clocks_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -/* - * The MTU has a separate, rather complex muxing setup - * with alternative parents (peripheral cluster or - * ULP or fixed 32768 Hz) depending on settings - */ -static unsigned long clk_mtu_get_rate(struct clk *clk) -{ - void __iomem *addr; - u32 tcr; - int mtu = (int) clk->data; - /* - * One of these is selected eventually - * TODO: Replace the constant with a reference - * to the ULP source once this is modeled. - */ - unsigned long clk32k = 32768; - unsigned long mturate; - unsigned long retclk; - - if (cpu_is_u5500()) - addr = __io_address(U5500_PRCMU_BASE); - else if (cpu_is_u8500()) - addr = __io_address(U8500_PRCMU_BASE); - else - ux500_unknown_soc(); - - /* - * On a startup, always conifgure the TCR to the doze mode; - * bootloaders do it for us. Do this in the kernel too. - */ - writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); - - tcr = readl(addr + PRCM_TCR); - - /* Get the rate from the parent as a default */ - if (clk->parent_periph) - mturate = clk_get_rate(clk->parent_periph); - else if (clk->parent_cluster) - mturate = clk_get_rate(clk->parent_cluster); - else - /* We need to be connected SOMEWHERE */ - BUG(); - - /* Return the clock selected for this MTU */ - if (tcr & (1 << mtu)) - retclk = clk32k; - else - retclk = mturate; - - pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); - return retclk; -} - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long rate; - - /* - * If there is a custom getrate callback for this clock, - * it will take precedence. - */ - if (clk->get_rate) - return clk->get_rate(clk); - - if (clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - rate = clk->rate; - if (!rate) { - if (clk->parent_periph) - rate = clk_get_rate(clk->parent_periph); - else if (clk->parent_cluster) - rate = clk_get_rate(clk->parent_cluster); - } - - return rate; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - /*TODO*/ - return rate; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - /*TODO*/ - return -ENOSYS; -} -EXPORT_SYMBOL(clk_set_parent); - -static void clk_prcmu_enable(struct clk *clk) -{ - void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) - + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; - - writel(1 << clk->prcmu_cg_bit, cg_set_reg); -} - -static void clk_prcmu_disable(struct clk *clk) -{ - void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) - + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; - - writel(1 << clk->prcmu_cg_bit, cg_clr_reg); -} - -static struct clkops clk_prcmu_ops = { - .enable = clk_prcmu_enable, - .disable = clk_prcmu_disable, -}; - -static unsigned int clkrst_base[] = { - [1] = U8500_CLKRST1_BASE, - [2] = U8500_CLKRST2_BASE, - [3] = U8500_CLKRST3_BASE, - [5] = U8500_CLKRST5_BASE, - [6] = U8500_CLKRST6_BASE, -}; - -static void clk_prcc_enable(struct clk *clk) -{ - void __iomem *addr = __io_address(clkrst_base[clk->cluster]); - - if (clk->prcc_kernel != -1) - writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); - - if (clk->prcc_bus != -1) - writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); -} - -static void clk_prcc_disable(struct clk *clk) -{ - void __iomem *addr = __io_address(clkrst_base[clk->cluster]); - - if (clk->prcc_bus != -1) - writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); - - if (clk->prcc_kernel != -1) - writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); -} - -static struct clkops clk_prcc_ops = { - .enable = clk_prcc_enable, - .disable = clk_prcc_disable, -}; - -static struct clk clk_32khz = { - .name = "clk_32khz", - .rate = 32000, -}; - -/* - * PRCMU level clock gating - */ - -/* Bank 0 */ -static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); -static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); -static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); -static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); -static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); -static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ -static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); -static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000); -static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); -static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); -static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); -static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); -static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); -static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); -static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); -static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); -static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); -static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); -static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); -static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); -static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); -static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); -static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); -static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ -static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); -static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); -static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); -static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ -static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ - -/* Bank 1 */ -static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ -static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ - -/* - * PRCC level clock gating - * Format: per#, clk, PCKEN bit, KCKEN bit, parent - */ - -/* Peripheral Cluster #1 */ -static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); -static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); -static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); -static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); -static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); -static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); - -/* Peripheral Cluster #2 */ -static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); -static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); -static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); - -/* Peripheral Cluster #3 */ -static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); -static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); -static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); -static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); -static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); -static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); - -/* Peripheral Cluster #4 is in the always on domain */ - -/* Peripheral Cluster #5 */ -static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); -static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); - -/* Peripheral Cluster #6 */ - -/* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); -static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); -static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); -static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); - -static struct clk clk_dummy_apb_pclk = { - .name = "apb_pclk", -}; - -static struct clk_lookup u8500_clks[] = { - CLK(dummy_apb_pclk, NULL, "apb_pclk"), - - /* Peripheral Cluster #1 */ - CLK(gpio0, "gpio.0", NULL), - CLK(gpio0, "gpio.1", NULL), - CLK(slimbus0, "slimbus0", NULL), - CLK(i2c2, "nmk-i2c.2", NULL), - CLK(sdi0, "sdi0", NULL), - CLK(msp0, "msp0", NULL), - CLK(i2c1, "nmk-i2c.1", NULL), - CLK(uart1, "uart1", NULL), - CLK(uart0, "uart0", NULL), - - /* Peripheral Cluster #3 */ - CLK(gpio2, "gpio.2", NULL), - CLK(gpio2, "gpio.3", NULL), - CLK(gpio2, "gpio.4", NULL), - CLK(gpio2, "gpio.5", NULL), - CLK(sdi5, "sdi5", NULL), - CLK(uart2, "uart2", NULL), - CLK(ske, "ske", NULL), - CLK(ske, "nmk-ske-keypad", NULL), - CLK(sdi2, "sdi2", NULL), - CLK(i2c0, "nmk-i2c.0", NULL), - CLK(fsmc, "fsmc", NULL), - - /* Peripheral Cluster #5 */ - CLK(gpio3, "gpio.8", NULL), - - /* Peripheral Cluster #6 */ - CLK(hash1, "hash1", NULL), - CLK(pka, "pka", NULL), - CLK(hash0, "hash0", NULL), - CLK(cryp0, "cryp0", NULL), - - /* PRCMU level clock gating */ - - /* Bank 0 */ - CLK(svaclk, "sva", NULL), - CLK(siaclk, "sia", NULL), - CLK(sgaclk, "sga", NULL), - CLK(slimclk, "slim", NULL), - CLK(lcdclk, "lcd", NULL), - CLK(bmlclk, "bml", NULL), - CLK(hsitxclk, "stm-hsi.0", NULL), - CLK(hsirxclk, "stm-hsi.1", NULL), - CLK(hdmiclk, "hdmi", NULL), - CLK(apeatclk, "apeat", NULL), - CLK(apetraceclk, "apetrace", NULL), - CLK(mcdeclk, "mcde", NULL), - CLK(ipi2clk, "ipi2", NULL), - CLK(dmaclk, "dma40.0", NULL), - CLK(b2r2clk, "b2r2", NULL), - CLK(tvclk, "tv", NULL), - - /* Peripheral Cluster #1 */ - CLK(i2c4, "nmk-i2c.4", NULL), - CLK(spi3, "spi3", NULL), - CLK(msp1, "msp1", NULL), - - /* Peripheral Cluster #2 */ - CLK(gpio1, "gpio.6", NULL), - CLK(gpio1, "gpio.7", NULL), - CLK(ssitx, "ssitx", NULL), - CLK(ssirx, "ssirx", NULL), - CLK(spi0, "spi0", NULL), - CLK(sdi3, "sdi3", NULL), - CLK(sdi1, "sdi1", NULL), - CLK(msp2, "msp2", NULL), - CLK(sdi4, "sdi4", NULL), - CLK(pwl, "pwl", NULL), - CLK(spi1, "spi1", NULL), - CLK(spi2, "spi2", NULL), - CLK(i2c3, "nmk-i2c.3", NULL), - - /* Peripheral Cluster #3 */ - CLK(ssp1, "ssp1", NULL), - CLK(ssp0, "ssp0", NULL), - - /* Peripheral Cluster #5 */ - CLK(usb, "musb-ux500.0", "usb"), - - /* Peripheral Cluster #6 */ - CLK(mtu1, "mtu1", NULL), - CLK(mtu0, "mtu0", NULL), - CLK(cfgreg, "cfgreg", NULL), - CLK(hash1, "hash1", NULL), - CLK(unipro, "unipro", NULL), - CLK(rng, "rng", NULL), - - /* PRCMU level clock gating */ - - /* Bank 0 */ - CLK(uniproclk, "uniproclk", NULL), - CLK(dsialtclk, "dsialt", NULL), - - /* Bank 1 */ - CLK(rngclk, "rng", NULL), - CLK(uiccclk, "uicc", NULL), -}; - -#ifdef CONFIG_DEBUG_FS -/* - * debugfs support to trace clock tree hierarchy and attributes with - * powerdebug - */ -static struct dentry *clk_debugfs_root; - -void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) -{ - while (num--) { - /* Check that the clock has not been already registered */ - if (!(cl->clk->list.prev != cl->clk->list.next)) - list_add_tail(&cl->clk->list, &clk_list); - - cl++; - } -} - -static ssize_t usecount_dbg_read(struct file *file, char __user *buf, - size_t size, loff_t *off) -{ - struct clk *clk = file->f_dentry->d_inode->i_private; - char cusecount[128]; - unsigned int len; - - len = sprintf(cusecount, "%u\n", clk->enabled); - return simple_read_from_buffer(buf, size, off, cusecount, len); -} - -static ssize_t rate_dbg_read(struct file *file, char __user *buf, - size_t size, loff_t *off) -{ - struct clk *clk = file->f_dentry->d_inode->i_private; - char crate[128]; - unsigned int rate; - unsigned int len; - - rate = clk_get_rate(clk); - len = sprintf(crate, "%u\n", rate); - return simple_read_from_buffer(buf, size, off, crate, len); -} - -static const struct file_operations usecount_fops = { - .read = usecount_dbg_read, -}; - -static const struct file_operations set_rate_fops = { - .read = rate_dbg_read, -}; - -static struct dentry *clk_debugfs_register_dir(struct clk *c, - struct dentry *p_dentry) -{ - struct dentry *d, *clk_d; - const char *p = c->name; - - if (!p) - p = "BUG"; - - clk_d = debugfs_create_dir(p, p_dentry); - if (!clk_d) - return NULL; - - d = debugfs_create_file("usecount", S_IRUGO, - clk_d, c, &usecount_fops); - if (!d) - goto err_out; - d = debugfs_create_file("rate", S_IRUGO, - clk_d, c, &set_rate_fops); - if (!d) - goto err_out; - /* - * TODO : not currently available in ux500 - * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); - * if (!d) - * goto err_out; - */ - - return clk_d; - -err_out: - debugfs_remove_recursive(clk_d); - return NULL; -} - -static int clk_debugfs_register_one(struct clk *c) -{ - struct clk *pa = c->parent_periph; - struct clk *bpa = c->parent_cluster; - - if (!(bpa && !pa)) { - c->dent = clk_debugfs_register_dir(c, - pa ? pa->dent : clk_debugfs_root); - if (!c->dent) - return -ENOMEM; - } - - if (bpa) { - c->dent_bus = clk_debugfs_register_dir(c, - bpa->dent_bus ? bpa->dent_bus : bpa->dent); - if ((!c->dent_bus) && (c->dent)) { - debugfs_remove_recursive(c->dent); - c->dent = NULL; - return -ENOMEM; - } - } - return 0; -} - -static int clk_debugfs_register(struct clk *c) -{ - int err; - struct clk *pa = c->parent_periph; - struct clk *bpa = c->parent_cluster; - - if (pa && (!pa->dent && !pa->dent_bus)) { - err = clk_debugfs_register(pa); - if (err) - return err; - } - - if (bpa && (!bpa->dent && !bpa->dent_bus)) { - err = clk_debugfs_register(bpa); - if (err) - return err; - } - - if ((!c->dent) && (!c->dent_bus)) { - err = clk_debugfs_register_one(c); - if (err) - return err; - } - return 0; -} - -static int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - int err; - - d = debugfs_create_dir("clock", NULL); - if (!d) - return -ENOMEM; - clk_debugfs_root = d; - - list_for_each_entry(c, &clk_list, list) { - err = clk_debugfs_register(c); - if (err) - goto err_out; - } - return 0; -err_out: - debugfs_remove_recursive(clk_debugfs_root); - return err; -} - -late_initcall(clk_debugfs_init); -#endif /* defined(CONFIG_DEBUG_FS) */ - -unsigned long clk_smp_twd_rate = 500000000; - -unsigned long clk_smp_twd_get_rate(struct clk *clk) -{ - return clk_smp_twd_rate; -} - -static struct clk clk_smp_twd = { - .get_rate = clk_smp_twd_get_rate, - .name = "smp_twd", -}; - -static struct clk_lookup clk_smp_twd_lookup = { - .dev_id = "smp_twd", - .clk = &clk_smp_twd, -}; - -#ifdef CONFIG_CPU_FREQ - -static int clk_twd_cpufreq_transition(struct notifier_block *nb, - unsigned long state, void *data) -{ - struct cpufreq_freqs *f = data; - - if (state == CPUFREQ_PRECHANGE) { - /* Save frequency in simple Hz */ - clk_smp_twd_rate = (f->new * 1000) / 2; - } - - return NOTIFY_OK; -} - -static struct notifier_block clk_twd_cpufreq_nb = { - .notifier_call = clk_twd_cpufreq_transition, -}; - -static int clk_init_smp_twd_cpufreq(void) -{ - return cpufreq_register_notifier(&clk_twd_cpufreq_nb, - CPUFREQ_TRANSITION_NOTIFIER); -} -late_initcall(clk_init_smp_twd_cpufreq); - -#endif - -int __init clk_init(void) -{ - if (cpu_is_u5500()) { - /* Clock tree for U5500 not implemented yet */ - clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; - clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; - clk_uartclk.rate = 36360000; - clk_sdmmcclk.rate = 99900000; - } - - clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); - clkdev_add(&clk_smp_twd_lookup); - -#ifdef CONFIG_DEBUG_FS - clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); -#endif - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/clock.h b/ANDROID_3.4.5/arch/arm/mach-ux500/clock.h deleted file mode 100644 index d776ada0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/clock.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2010 ST-Ericsson - * Copyright (C) 2009 STMicroelectronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/** - * struct clkops - ux500 clock operations - * @enable: function to enable the clock - * @disable: function to disable the clock - * @get_rate: function to get the current clock rate - * - * This structure contains function pointers to functions that will be used to - * control the clock. All of these functions are optional. If get_rate is - * NULL, the rate in the struct clk will be used. - */ -struct clkops { - void (*enable) (struct clk *); - void (*disable) (struct clk *); - unsigned long (*get_rate) (struct clk *); - int (*set_parent)(struct clk *, struct clk *); -}; - -/** - * struct clk - ux500 clock structure - * @ops: pointer to clkops struct used to control this clock - * @name: name, for debugging - * @enabled: refcount. positive if enabled, zero if disabled - * @get_rate: custom callback for getting the clock rate - * @data: custom per-clock data for example for the get_rate - * callback - * @rate: fixed rate for clocks which don't implement - * ops->getrate - * @prcmu_cg_off: address offset of the combined enable/disable register - * (used on u8500v1) - * @prcmu_cg_bit: bit in the combined enable/disable register (used on - * u8500v1) - * @prcmu_cg_mgt: address of the enable/disable register (used on - * u8500ed) - * @cluster: peripheral cluster number - * @prcc_bus: bit for the bus clock in the peripheral's CLKRST - * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. - * -1 if no kernel clock exists. - * @parent_cluster: pointer to parent's cluster clk struct - * @parent_periph: pointer to parent's peripheral clk struct - * - * Peripherals are organised into clusters, and each cluster has an associated - * bus clock. Some peripherals also have a parent peripheral clock. - * - * In order to enable a clock for a peripheral, we need to enable: - * (1) the parent cluster (bus) clock at the PRCMU level - * (2) the parent peripheral clock (if any) at the PRCMU level - * (3) the peripheral's bus & kernel clock at the PRCC level - * - * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each - * of the cluster and peripheral clocks, and hooking these as the parents of - * the individual peripheral clocks. - * - * (3) is handled by specifying the bits in the PRCC control registers required - * to enable these clocks and modifying them in the ->enable and - * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). - * - * This structure describes both the PRCMU-level clocks and PRCC-level clocks. - * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, - * prcc, and parent pointers are only used for the PRCC-level clocks. - */ -struct clk { - const struct clkops *ops; - const char *name; - unsigned int enabled; - unsigned long (*get_rate)(struct clk *); - void *data; - - unsigned long rate; - struct list_head list; - - /* These three are only for PRCMU clks */ - - unsigned int prcmu_cg_off; - unsigned int prcmu_cg_bit; - unsigned int prcmu_cg_mgt; - - /* The rest are only for PRCC clks */ - - int cluster; - unsigned int prcc_bus; - unsigned int prcc_kernel; - - struct clk *parent_cluster; - struct clk *parent_periph; -#if defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ - struct dentry *dent_bus; /* For visible tree hierarchy */ -#endif -}; - -#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcmu_ops, \ - .prcmu_cg_off = _cg_off, \ - .prcmu_cg_bit = _cg_bit, \ - .prcmu_cg_mgt = PRCM_##_reg##_MGT \ - } - -#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcmu_ops, \ - .prcmu_cg_off = _cg_off, \ - .prcmu_cg_bit = _cg_bit, \ - .rate = _rate, \ - .prcmu_cg_mgt = PRCM_##_reg##_MGT \ - } - -#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcc_ops, \ - .cluster = _pclust, \ - .prcc_bus = _bus_en, \ - .prcc_kernel = _kernel_en, \ - .parent_cluster = &clk_per##_pclust##clk, \ - .parent_periph = _kernclk \ - } - -#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcc_ops, \ - .cluster = _pclust, \ - .prcc_bus = _bus_en, \ - .prcc_kernel = _kernel_en, \ - .parent_cluster = &clk_per##_pclust##clk, \ - .parent_periph = _kernclk, \ - .get_rate = _callback, \ - .data = (void *) _data \ - } - - -#define CLK(_clk, _devname, _conname) \ - { \ - .clk = &clk_##_clk, \ - .dev_id = _devname, \ - .con_id = _conname, \ - } - -int __init clk_db8500_ed_fixup(void); -int __init clk_init(void); diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/cpu-db5500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/cpu-db5500.c deleted file mode 100644 index bca47f32..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/cpu-db5500.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/io.h> -#include <linux/irq.h> - -#include <asm/mach/map.h> -#include <asm/pmu.h> - -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/devices.h> -#include <mach/setup.h> -#include <mach/irqs.h> -#include <mach/usb.h> - -#include "devices-db5500.h" -#include "ste-dma40-db5500.h" - -static struct map_desc u5500_uart_io_desc[] __initdata = { - __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K), -}; - -static struct map_desc u5500_io_desc[] __initdata = { - /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ - __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K), - __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K), - - __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), - __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), - __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), -}; - -static struct resource mbox0_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX0_PEER_START, - .end = U5500_MBOX0_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX0_LOCAL_START, - .end = U5500_MBOX0_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR0_VIRT_IRQ, - .end = MBOX_PAIR0_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource mbox1_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX1_PEER_START, - .end = U5500_MBOX1_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX1_LOCAL_START, - .end = U5500_MBOX1_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR1_VIRT_IRQ, - .end = MBOX_PAIR1_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource mbox2_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX2_PEER_START, - .end = U5500_MBOX2_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX2_LOCAL_START, - .end = U5500_MBOX2_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR2_VIRT_IRQ, - .end = MBOX_PAIR2_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device mbox0_device = { - .id = 0, - .name = "mbox", - .resource = mbox0_resources, - .num_resources = ARRAY_SIZE(mbox0_resources), -}; - -static struct platform_device mbox1_device = { - .id = 1, - .name = "mbox", - .resource = mbox1_resources, - .num_resources = ARRAY_SIZE(mbox1_resources), -}; - -static struct platform_device mbox2_device = { - .id = 2, - .name = "mbox", - .resource = mbox2_resources, - .num_resources = ARRAY_SIZE(mbox2_resources), -}; - -static struct platform_device *db5500_platform_devs[] __initdata = { - &mbox0_device, - &mbox1_device, - &mbox2_device, -}; - -static resource_size_t __initdata db5500_gpio_base[] = { - U5500_GPIOBANK0_BASE, - U5500_GPIOBANK1_BASE, - U5500_GPIOBANK2_BASE, - U5500_GPIOBANK3_BASE, - U5500_GPIOBANK4_BASE, - U5500_GPIOBANK5_BASE, - U5500_GPIOBANK6_BASE, - U5500_GPIOBANK7_BASE, -}; - -static void __init db5500_add_gpios(struct device *parent) -{ - struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ - }; - - dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base), - IRQ_DB5500_GPIO0, &pdata); -} - -void __init u5500_map_io(void) -{ - /* - * Map the UARTs early so that the DEBUG_LL stuff continues to work. - */ - iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc)); - - ux500_map_io(); - - iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); - - _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); -} - -static void __init db5500_pmu_init(void) -{ - struct resource res[] = { - [0] = { - .start = IRQ_DB5500_PMU0, - .end = IRQ_DB5500_PMU0, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = IRQ_DB5500_PMU1, - .end = IRQ_DB5500_PMU1, - .flags = IORESOURCE_IRQ, - }, - }; - - platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU, - res, ARRAY_SIZE(res)); -} - -static int usb_db5500_rx_dma_cfg[] = { - DB5500_DMA_DEV4_USB_OTG_IEP_1_9, - DB5500_DMA_DEV5_USB_OTG_IEP_2_10, - DB5500_DMA_DEV6_USB_OTG_IEP_3_11, - DB5500_DMA_DEV20_USB_OTG_IEP_4_12, - DB5500_DMA_DEV21_USB_OTG_IEP_5_13, - DB5500_DMA_DEV22_USB_OTG_IEP_6_14, - DB5500_DMA_DEV23_USB_OTG_IEP_7_15, - DB5500_DMA_DEV38_USB_OTG_IEP_8 -}; - -static int usb_db5500_tx_dma_cfg[] = { - DB5500_DMA_DEV4_USB_OTG_OEP_1_9, - DB5500_DMA_DEV5_USB_OTG_OEP_2_10, - DB5500_DMA_DEV6_USB_OTG_OEP_3_11, - DB5500_DMA_DEV20_USB_OTG_OEP_4_12, - DB5500_DMA_DEV21_USB_OTG_OEP_5_13, - DB5500_DMA_DEV22_USB_OTG_OEP_6_14, - DB5500_DMA_DEV23_USB_OTG_OEP_7_15, - DB5500_DMA_DEV38_USB_OTG_OEP_8 -}; - -static const char *db5500_read_soc_id(void) -{ - return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n"); -} - -static struct device * __init db5500_soc_device_init(void) -{ - const char *soc_id = db5500_read_soc_id(); - - return ux500_soc_device_init(soc_id); -} - -struct device * __init u5500_init_devices(void) -{ - struct device *parent; - int i; - - parent = db5500_soc_device_init(); - - db5500_add_gpios(parent); - db5500_pmu_init(); - db5500_dma_init(parent); - db5500_add_rtc(parent); - db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); - - for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++) - db5500_platform_devs[i]->dev.parent = parent; - - platform_add_devices(db5500_platform_devs, - ARRAY_SIZE(db5500_platform_devs)); - - return parent; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/cpu-db8500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/cpu-db8500.c deleted file mode 100644 index 9bd81638..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/cpu-db8500.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (C) 2008-2009 ST-Ericsson SA - * - * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -#include <linux/types.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/amba/bus.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/mach/map.h> -#include <asm/pmu.h> -#include <plat/gpio-nomadik.h> -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/devices.h> -#include <mach/usb.h> -#include <mach/db8500-regs.h> - -#include "devices-db8500.h" -#include "ste-dma40-db8500.h" - -/* minimum static i/o mapping required to boot U8500 platforms */ -static struct map_desc u8500_uart_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), -}; - -static struct map_desc u8500_io_desc[] __initdata = { - /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ - __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), - __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), - - __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), - - __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), - __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), - __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), -}; - -void __init u8500_map_io(void) -{ - /* - * Map the UARTs early so that the DEBUG_LL stuff continues to work. - */ - iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); - - ux500_map_io(); - - iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); - - _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); -} - -static struct resource db8500_pmu_resources[] = { - [0] = { - .start = IRQ_DB8500_PMU, - .end = IRQ_DB8500_PMU, - .flags = IORESOURCE_IRQ, - }, -}; - -/* - * The PMU IRQ lines of two cores are wired together into a single interrupt. - * Bounce the interrupt to the other core if it's not ours. - */ -static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) -{ - irqreturn_t ret = handler(irq, dev); - int other = !smp_processor_id(); - - if (ret == IRQ_NONE && cpu_online(other)) - irq_set_affinity(irq, cpumask_of(other)); - - /* - * We should be able to get away with the amount of IRQ_NONEs we give, - * while still having the spurious IRQ detection code kick in if the - * interrupt really starts hitting spuriously. - */ - return ret; -} - -static struct arm_pmu_platdata db8500_pmu_platdata = { - .handle_irq = db8500_pmu_handler, -}; - -static struct platform_device db8500_pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = ARRAY_SIZE(db8500_pmu_resources), - .resource = db8500_pmu_resources, - .dev.platform_data = &db8500_pmu_platdata, -}; - -static struct platform_device db8500_prcmu_device = { - .name = "db8500-prcmu", -}; - -static struct platform_device *platform_devs[] __initdata = { - &u8500_dma40_device, - &db8500_pmu_device, - &db8500_prcmu_device, -}; - -static resource_size_t __initdata db8500_gpio_base[] = { - U8500_GPIOBANK0_BASE, - U8500_GPIOBANK1_BASE, - U8500_GPIOBANK2_BASE, - U8500_GPIOBANK3_BASE, - U8500_GPIOBANK4_BASE, - U8500_GPIOBANK5_BASE, - U8500_GPIOBANK6_BASE, - U8500_GPIOBANK7_BASE, - U8500_GPIOBANK8_BASE, -}; - -static void __init db8500_add_gpios(struct device *parent) -{ - struct nmk_gpio_platform_data pdata = { - .supports_sleepmode = true, - }; - - dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), - IRQ_DB8500_GPIO0, &pdata); -} - -static int usb_db8500_rx_dma_cfg[] = { - DB8500_DMA_DEV38_USB_OTG_IEP_1_9, - DB8500_DMA_DEV37_USB_OTG_IEP_2_10, - DB8500_DMA_DEV36_USB_OTG_IEP_3_11, - DB8500_DMA_DEV19_USB_OTG_IEP_4_12, - DB8500_DMA_DEV18_USB_OTG_IEP_5_13, - DB8500_DMA_DEV17_USB_OTG_IEP_6_14, - DB8500_DMA_DEV16_USB_OTG_IEP_7_15, - DB8500_DMA_DEV39_USB_OTG_IEP_8 -}; - -static int usb_db8500_tx_dma_cfg[] = { - DB8500_DMA_DEV38_USB_OTG_OEP_1_9, - DB8500_DMA_DEV37_USB_OTG_OEP_2_10, - DB8500_DMA_DEV36_USB_OTG_OEP_3_11, - DB8500_DMA_DEV19_USB_OTG_OEP_4_12, - DB8500_DMA_DEV18_USB_OTG_OEP_5_13, - DB8500_DMA_DEV17_USB_OTG_OEP_6_14, - DB8500_DMA_DEV16_USB_OTG_OEP_7_15, - DB8500_DMA_DEV39_USB_OTG_OEP_8 -}; - -static const char *db8500_read_soc_id(void) -{ - void __iomem *uid = __io_address(U8500_BB_UID_BASE); - - return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x", - readl((u32 *)uid+1), - readl((u32 *)uid+1), readl((u32 *)uid+2), - readl((u32 *)uid+3), readl((u32 *)uid+4)); -} - -static struct device * __init db8500_soc_device_init(void) -{ - const char *soc_id = db8500_read_soc_id(); - - return ux500_soc_device_init(soc_id); -} - -/* - * This function is called from the board init - */ -struct device * __init u8500_init_devices(void) -{ - struct device *parent; - int i; - - parent = db8500_soc_device_init(); - - db8500_add_rtc(parent); - db8500_add_gpios(parent); - db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); - - platform_device_register_data(parent, - "cpufreq-u8500", -1, NULL, 0); - - for (i = 0; i < ARRAY_SIZE(platform_devs); i++) - platform_devs[i]->dev.parent = parent; - - platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); - - return parent; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/cpu.c b/ANDROID_3.4.5/arch/arm/mach-ux500/cpu.c deleted file mode 100644 index d11f3892..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/cpu.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/mfd/db8500-prcmu.h> -#include <linux/mfd/db5500-prcmu.h> -#include <linux/clksrc-dbx500-prcmu.h> -#include <linux/sys_soc.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/stat.h> -#include <linux/of.h> -#include <linux/of_irq.h> - -#include <asm/hardware/gic.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/devices.h> - -#include "clock.h" - -void __iomem *_PRCMU_BASE; - -static const struct of_device_id ux500_dt_irq_match[] = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {}, -}; - -void __init ux500_init_irq(void) -{ - void __iomem *dist_base; - void __iomem *cpu_base; - - if (cpu_is_u5500()) { - dist_base = __io_address(U5500_GIC_DIST_BASE); - cpu_base = __io_address(U5500_GIC_CPU_BASE); - } else if (cpu_is_u8500()) { - dist_base = __io_address(U8500_GIC_DIST_BASE); - cpu_base = __io_address(U8500_GIC_CPU_BASE); - } else - ux500_unknown_soc(); - -#ifdef CONFIG_OF - if (of_have_populated_dt()) - of_irq_init(ux500_dt_irq_match); - else -#endif - gic_init(0, 29, dist_base, cpu_base); - - /* - * Init clocks here so that they are available for system timer - * initialization. - */ - if (cpu_is_u5500()) - db5500_prcmu_early_init(); - if (cpu_is_u8500()) - db8500_prcmu_early_init(); - clk_init(); -} - -static const char * __init ux500_get_machine(void) -{ - return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber()); -} - -static const char * __init ux500_get_family(void) -{ - return kasprintf(GFP_KERNEL, "ux500"); -} - -static const char * __init ux500_get_revision(void) -{ - unsigned int rev = dbx500_revision(); - - if (rev == 0x01) - return kasprintf(GFP_KERNEL, "%s", "ED"); - else if (rev >= 0xA0) - return kasprintf(GFP_KERNEL, "%d.%d", - (rev >> 4) - 0xA + 1, rev & 0xf); - - return kasprintf(GFP_KERNEL, "%s", "Unknown"); -} - -static ssize_t ux500_get_process(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - if (dbx500_id.process == 0x00) - return sprintf(buf, "Standard\n"); - - return sprintf(buf, "%02xnm\n", dbx500_id.process); -} - -static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr, - const char *soc_id) -{ - soc_dev_attr->soc_id = soc_id; - soc_dev_attr->machine = ux500_get_machine(); - soc_dev_attr->family = ux500_get_family(); - soc_dev_attr->revision = ux500_get_revision(); -} - -struct device_attribute ux500_soc_attr = - __ATTR(process, S_IRUGO, ux500_get_process, NULL); - -struct device * __init ux500_soc_device_init(const char *soc_id) -{ - struct device *parent; - struct soc_device *soc_dev; - struct soc_device_attribute *soc_dev_attr; - - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return ERR_PTR(-ENOMEM); - - soc_info_populate(soc_dev_attr, soc_id); - - soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR_OR_NULL(soc_dev)) { - kfree(soc_dev_attr); - return NULL; - } - - parent = soc_device_to_device(soc_dev); - if (!IS_ERR_OR_NULL(parent)) - device_create_file(parent, &ux500_soc_attr); - - return parent; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-common.c b/ANDROID_3.4.5/arch/arm/mach-ux500/devices-common.c deleted file mode 100644 index c5312a4b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-common.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/err.h> -#include <linux/irq.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> - -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> - -#include "devices-common.h" - -struct amba_device * -dbx500_add_amba_device(struct device *parent, const char *name, - resource_size_t base, int irq, void *pdata, - unsigned int periphid) -{ - struct amba_device *dev; - int ret; - - dev = amba_device_alloc(name, base, SZ_4K); - if (!dev) - return ERR_PTR(-ENOMEM); - - dev->dma_mask = DMA_BIT_MASK(32); - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - dev->irq[0] = irq; - - dev->periphid = periphid; - - dev->dev.platform_data = pdata; - - dev->dev.parent = parent; - - ret = amba_device_add(dev, &iomem_resource); - if (ret) { - amba_device_put(dev); - return ERR_PTR(ret); - } - - return dev; -} - -static struct platform_device * -dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq, - struct nmk_gpio_platform_data *pdata) -{ - struct resource resources[] = { - { - .start = addr, - .end = addr + 127, - .flags = IORESOURCE_MEM, - }, - { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - } - }; - - return platform_device_register_resndata( - parent, - "gpio", - id, - resources, - ARRAY_SIZE(resources), - pdata, - sizeof(*pdata)); -} - -void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, - int irq, struct nmk_gpio_platform_data *pdata) -{ - int first = 0; - int i; - - for (i = 0; i < num; i++, first += 32, irq++) { - pdata->first_gpio = first; - pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); - pdata->num_gpio = 32; - - dbx500_add_gpio(parent, i, base[i], irq, pdata); - } -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-common.h b/ANDROID_3.4.5/arch/arm/mach-ux500/devices-common.h deleted file mode 100644 index 39c74ec8..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-common.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_COMMON_H -#define __DEVICES_COMMON_H - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/sys_soc.h> -#include <plat/i2c.h> - -extern struct amba_device * -dbx500_add_amba_device(struct device *parent, const char *name, - resource_size_t base, int irq, void *pdata, - unsigned int periphid); - -struct spi_master_cntlr; - -static inline struct amba_device * -dbx500_add_msp_spi(struct device *parent, const char *name, - resource_size_t base, int irq, - struct spi_master_cntlr *pdata) -{ - return dbx500_add_amba_device(parent, name, base, irq, - pdata, 0); -} - -static inline struct amba_device * -dbx500_add_spi(struct device *parent, const char *name, resource_size_t base, - int irq, struct spi_master_cntlr *pdata, - u32 periphid) -{ - return dbx500_add_amba_device(parent, name, base, irq, - pdata, periphid); -} - -struct mmci_platform_data; - -static inline struct amba_device * -dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base, - int irq, struct mmci_platform_data *pdata, u32 periphid) -{ - return dbx500_add_amba_device(parent, name, base, irq, - pdata, periphid); -} - -struct amba_pl011_data; - -static inline struct amba_device * -dbx500_add_uart(struct device *parent, const char *name, resource_size_t base, - int irq, struct amba_pl011_data *pdata) -{ - return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); -} - -struct nmk_i2c_controller; - -static inline struct platform_device * -dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq, - struct nmk_i2c_controller *data) -{ - struct resource res[] = { - DEFINE_RES_MEM(base, SZ_4K), - DEFINE_RES_IRQ(irq), - }; - - struct platform_device_info pdevinfo = { - .parent = parent, - .name = "nmk-i2c", - .id = id, - .res = res, - .num_res = ARRAY_SIZE(res), - .data = data, - .size_data = sizeof(*data), - .dma_mask = DMA_BIT_MASK(32), - }; - - return platform_device_register_full(&pdevinfo); -} - -static inline struct amba_device * -dbx500_add_rtc(struct device *parent, resource_size_t base, int irq) -{ - return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0); -} - -struct nmk_gpio_platform_data; - -void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, - int irq, struct nmk_gpio_platform_data *pdata); - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db5500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db5500.h deleted file mode 100644 index e7095550..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db5500.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_DB5500_H -#define __DEVICES_DB5500_H - -#include "devices-common.h" - -#define db5500_add_i2c1(parent, pdata) \ - dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata) -#define db5500_add_i2c2(parent, pdata) \ - dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata) -#define db5500_add_i2c3(parent, pdata) \ - dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata) - -#define db5500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \ - IRQ_DB5500_MSP0, pdata) -#define db5500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \ - IRQ_DB5500_MSP1, pdata) -#define db5500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \ - IRQ_DB5500_MSP2, pdata) - -#define db5500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \ - IRQ_DB5500_MSP0, pdata) -#define db5500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \ - IRQ_DB5500_MSP1, pdata) -#define db5500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \ - IRQ_DB5500_MSP2, pdata) - -#define db5500_add_rtc(parent) \ - dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC); - -#define db5500_add_usb(parent, rx_cfg, tx_cfg) \ - ux500_add_usb(parent, U5500_USBOTG_BASE, \ - IRQ_DB5500_USBOTG, rx_cfg, tx_cfg) - -#define db5500_add_sdi0(parent, pdata) \ - dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \ - IRQ_DB5500_SDMMC0, pdata, \ - 0x10480180) -#define db5500_add_sdi1(parent, pdata) \ - dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \ - IRQ_DB5500_SDMMC1, pdata, \ - 0x10480180) -#define db5500_add_sdi2(parent, pdata) \ - dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \ - IRQ_DB5500_SDMMC2, pdata \ - 0x10480180) -#define db5500_add_sdi3(parent, pdata) \ - dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \ - IRQ_DB5500_SDMMC3, pdata \ - 0x10480180) -#define db5500_add_sdi4(parent, pdata) \ - dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \ - IRQ_DB5500_SDMMC4, pdata \ - 0x10480180) - -/* This one has a bad peripheral ID in the U5500 silicon */ -#define db5500_add_spi0(parent, pdata) \ - dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \ - IRQ_DB5500_SPI0, pdata, \ - 0x10080023) -#define db5500_add_spi1(parent, pdata) \ - dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \ - IRQ_DB5500_SPI1, pdata, \ - 0x10080023) -#define db5500_add_spi2(parent, pdata) \ - dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \ - IRQ_DB5500_SPI2, pdata \ - 0x10080023) -#define db5500_add_spi3(parent, pdata) \ - dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \ - IRQ_DB5500_SPI3, pdata \ - 0x10080023) - -#define db5500_add_uart0(parent, plat) \ - dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \ - IRQ_DB5500_UART0, plat) -#define db5500_add_uart1(parent, plat) \ - dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \ - IRQ_DB5500_UART1, plat) -#define db5500_add_uart2(parent, plat) \ - dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \ - IRQ_DB5500_UART2, plat) -#define db5500_add_uart3(parent, plat) \ - dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \ - IRQ_DB5500_UART3, plat) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db8500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db8500.c deleted file mode 100644 index 6e66d377..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db8500.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/amba/bus.h> -#include <linux/amba/pl022.h> - -#include <plat/ste_dma40.h> - -#include <mach/hardware.h> -#include <mach/setup.h> - -#include "ste-dma40-db8500.h" - -static struct resource dma40_resources[] = { - [0] = { - .start = U8500_DMA_BASE, - .end = U8500_DMA_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - .name = "base", - }, - [1] = { - .start = U8500_DMA_LCPA_BASE, - .end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - .name = "lcpa", - }, - [2] = { - .start = IRQ_DB8500_DMA, - .end = IRQ_DB8500_DMA, - .flags = IORESOURCE_IRQ, - } -}; - -/* Default configuration for physcial memcpy */ -struct stedma40_chan_cfg dma40_memcpy_conf_phy = { - .mode = STEDMA40_MODE_PHYSICAL, - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_PHY_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_PHY_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; -/* Default configuration for logical memcpy */ -struct stedma40_chan_cfg dma40_memcpy_conf_log = { - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* - * Mapping between destination event lines and physical device address. - * The event line is tied to a device and therefore the address is constant. - * When the address comes from a primecell it will be configured in runtime - * and we set the address to -1 as a placeholder. - */ -static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { - /* MUSB - these will be runtime-reconfigured */ - [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1, - [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1, - [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1, - [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1, - [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1, - [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1, - [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1, - [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1, - /* PrimeCells - run-time configured */ - [DB8500_DMA_DEV0_SPI0_TX] = -1, - [DB8500_DMA_DEV1_SD_MMC0_TX] = -1, - [DB8500_DMA_DEV2_SD_MMC1_TX] = -1, - [DB8500_DMA_DEV3_SD_MMC2_TX] = -1, - [DB8500_DMA_DEV8_SSP0_TX] = -1, - [DB8500_DMA_DEV9_SSP1_TX] = -1, - [DB8500_DMA_DEV11_UART2_TX] = -1, - [DB8500_DMA_DEV12_UART1_TX] = -1, - [DB8500_DMA_DEV13_UART0_TX] = -1, - [DB8500_DMA_DEV28_SD_MM2_TX] = -1, - [DB8500_DMA_DEV29_SD_MM0_TX] = -1, - [DB8500_DMA_DEV32_SD_MM1_TX] = -1, - [DB8500_DMA_DEV33_SPI2_TX] = -1, - [DB8500_DMA_DEV35_SPI1_TX] = -1, - [DB8500_DMA_DEV40_SPI3_TX] = -1, - [DB8500_DMA_DEV41_SD_MM3_TX] = -1, - [DB8500_DMA_DEV42_SD_MM4_TX] = -1, - [DB8500_DMA_DEV43_SD_MM5_TX] = -1, - [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, -}; - -/* Mapping between source event lines and physical device address */ -static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { - /* MUSB - these will be runtime-reconfigured */ - [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1, - [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1, - [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1, - [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1, - [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1, - [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1, - [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1, - [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1, - /* PrimeCells */ - [DB8500_DMA_DEV0_SPI0_RX] = -1, - [DB8500_DMA_DEV1_SD_MMC0_RX] = -1, - [DB8500_DMA_DEV2_SD_MMC1_RX] = -1, - [DB8500_DMA_DEV3_SD_MMC2_RX] = -1, - [DB8500_DMA_DEV8_SSP0_RX] = -1, - [DB8500_DMA_DEV9_SSP1_RX] = -1, - [DB8500_DMA_DEV11_UART2_RX] = -1, - [DB8500_DMA_DEV12_UART1_RX] = -1, - [DB8500_DMA_DEV13_UART0_RX] = -1, - [DB8500_DMA_DEV28_SD_MM2_RX] = -1, - [DB8500_DMA_DEV29_SD_MM0_RX] = -1, - [DB8500_DMA_DEV32_SD_MM1_RX] = -1, - [DB8500_DMA_DEV33_SPI2_RX] = -1, - [DB8500_DMA_DEV35_SPI1_RX] = -1, - [DB8500_DMA_DEV40_SPI3_RX] = -1, - [DB8500_DMA_DEV41_SD_MM3_RX] = -1, - [DB8500_DMA_DEV42_SD_MM4_RX] = -1, - [DB8500_DMA_DEV43_SD_MM5_RX] = -1, - [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, -}; - -/* Reserved event lines for memcpy only */ -static int dma40_memcpy_event[] = { - DB8500_DMA_MEMCPY_TX_0, - DB8500_DMA_MEMCPY_TX_1, - DB8500_DMA_MEMCPY_TX_2, - DB8500_DMA_MEMCPY_TX_3, - DB8500_DMA_MEMCPY_TX_4, - DB8500_DMA_MEMCPY_TX_5, -}; - -static struct stedma40_platform_data dma40_plat_data = { - .dev_len = DB8500_DMA_NR_DEV, - .dev_rx = dma40_rx_map, - .dev_tx = dma40_tx_map, - .memcpy = dma40_memcpy_event, - .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), - .memcpy_conf_phy = &dma40_memcpy_conf_phy, - .memcpy_conf_log = &dma40_memcpy_conf_log, - .disabled_channels = {-1}, -}; - -struct platform_device u8500_dma40_device = { - .dev = { - .platform_data = &dma40_plat_data, - }, - .name = "dma40", - .id = 0, - .num_resources = ARRAY_SIZE(dma40_resources), - .resource = dma40_resources -}; - -struct resource keypad_resources[] = { - [0] = { - .start = U8500_SKE_BASE, - .end = U8500_SKE_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DB8500_KB, - .end = IRQ_DB8500_KB, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device u8500_ske_keypad_device = { - .name = "nmk-ske-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(keypad_resources), - .resource = keypad_resources, -}; diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db8500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db8500.h deleted file mode 100644 index 9fd93e9d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/devices-db8500.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_DB8500_H -#define __DEVICES_DB8500_H - -#include "devices-common.h" - -struct ske_keypad_platform_data; -struct pl022_ssp_controller; - -static inline struct platform_device * -db8500_add_ske_keypad(struct device *parent, - struct ske_keypad_platform_data *pdata, - size_t size) -{ - struct resource resources[] = { - DEFINE_RES_MEM(U8500_SKE_BASE, SZ_4K), - DEFINE_RES_IRQ(IRQ_DB8500_KB), - }; - - return platform_device_register_resndata(parent, "nmk-ske-keypad", -1, - resources, 2, pdata, size); -} - -static inline struct amba_device * -db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, - int irq, struct pl022_ssp_controller *pdata) -{ - return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); -} - - -#define db8500_add_i2c0(parent, pdata) \ - dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) -#define db8500_add_i2c1(parent, pdata) \ - dbx500_add_i2c(parent, 1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata) -#define db8500_add_i2c2(parent, pdata) \ - dbx500_add_i2c(parent, 2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata) -#define db8500_add_i2c3(parent, pdata) \ - dbx500_add_i2c(parent, 3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata) -#define db8500_add_i2c4(parent, pdata) \ - dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) - -#define db8500_add_msp0_i2s(parent, pdata) \ - dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) -#define db8500_add_msp1_i2s(parent, pdata) \ - dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) -#define db8500_add_msp2_i2s(parent, pdata) \ - dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) -#define db8500_add_msp3_i2s(parent, pdata) \ - dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) - -#define db8500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \ - IRQ_DB8500_MSP0, pdata) -#define db8500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U8500_MSP1_BASE, \ - IRQ_DB8500_MSP1, pdata) -#define db8500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U8500_MSP2_BASE, \ - IRQ_DB8500_MSP2, pdata) -#define db8500_add_msp3_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp3", U8500_MSP3_BASE, \ - IRQ_DB8500_MSP1, pdata) - -#define db8500_add_rtc(parent) \ - dbx500_add_rtc(parent, U8500_RTC_BASE, IRQ_DB8500_RTC); - -#define db8500_add_usb(parent, rx_cfg, tx_cfg) \ - ux500_add_usb(parent, U8500_USBOTG_BASE, \ - IRQ_DB8500_USBOTG, rx_cfg, tx_cfg) - -#define db8500_add_sdi0(parent, pdata, pid) \ - dbx500_add_sdi(parent, "sdi0", U8500_SDI0_BASE, \ - IRQ_DB8500_SDMMC0, pdata, pid) -#define db8500_add_sdi1(parent, pdata, pid) \ - dbx500_add_sdi(parent, "sdi1", U8500_SDI1_BASE, \ - IRQ_DB8500_SDMMC1, pdata, pid) -#define db8500_add_sdi2(parent, pdata, pid) \ - dbx500_add_sdi(parent, "sdi2", U8500_SDI2_BASE, \ - IRQ_DB8500_SDMMC2, pdata, pid) -#define db8500_add_sdi3(parent, pdata, pid) \ - dbx500_add_sdi(parent, "sdi3", U8500_SDI3_BASE, \ - IRQ_DB8500_SDMMC3, pdata, pid) -#define db8500_add_sdi4(parent, pdata, pid) \ - dbx500_add_sdi(parent, "sdi4", U8500_SDI4_BASE, \ - IRQ_DB8500_SDMMC4, pdata, pid) -#define db8500_add_sdi5(parent, pdata, pid) \ - dbx500_add_sdi(parent, "sdi5", U8500_SDI5_BASE, \ - IRQ_DB8500_SDMMC5, pdata, pid) - -#define db8500_add_ssp0(parent, pdata) \ - db8500_add_ssp(parent, "ssp0", U8500_SSP0_BASE, \ - IRQ_DB8500_SSP0, pdata) -#define db8500_add_ssp1(parent, pdata) \ - db8500_add_ssp(parent, "ssp1", U8500_SSP1_BASE, \ - IRQ_DB8500_SSP1, pdata) - -#define db8500_add_spi0(parent, pdata) \ - dbx500_add_spi(parent, "spi0", U8500_SPI0_BASE, \ - IRQ_DB8500_SPI0, pdata, 0) -#define db8500_add_spi1(parent, pdata) \ - dbx500_add_spi(parent, "spi1", U8500_SPI1_BASE, \ - IRQ_DB8500_SPI1, pdata, 0) -#define db8500_add_spi2(parent, pdata) \ - dbx500_add_spi(parent, "spi2", U8500_SPI2_BASE, \ - IRQ_DB8500_SPI2, pdata, 0) -#define db8500_add_spi3(parent, pdata) \ - dbx500_add_spi(parent, "spi3", U8500_SPI3_BASE, \ - IRQ_DB8500_SPI3, pdata, 0) - -#define db8500_add_uart0(parent, pdata) \ - dbx500_add_uart(parent, "uart0", U8500_UART0_BASE, \ - IRQ_DB8500_UART0, pdata) -#define db8500_add_uart1(parent, pdata) \ - dbx500_add_uart(parent, "uart1", U8500_UART1_BASE, \ - IRQ_DB8500_UART1, pdata) -#define db8500_add_uart2(parent, pdata) \ - dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \ - IRQ_DB8500_UART2, pdata) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/devices.c b/ANDROID_3.4.5/arch/arm/mach-ux500/devices.c deleted file mode 100644 index ea0a2f92..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/devices.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/amba/bus.h> - -#include <mach/hardware.h> -#include <mach/setup.h> - -void __init amba_add_devices(struct amba_device *devs[], int num) -{ - int i; - - for (i = 0; i < num; i++) { - struct amba_device *d = devs[i]; - amba_device_register(d, &iomem_resource); - } -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/dma-db5500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/dma-db5500.c deleted file mode 100644 index 41e9470f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/dma-db5500.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson - * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson - * - * License terms: GNU General Public License (GPL), version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <plat/ste_dma40.h> -#include <mach/setup.h> -#include <mach/hardware.h> - -#include "ste-dma40-db5500.h" - -static struct resource dma40_resources[] = { - [0] = { - .start = U5500_DMA_BASE, - .end = U5500_DMA_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - .name = "base", - }, - [1] = { - .start = U5500_DMA_LCPA_BASE, - .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - .name = "lcpa", - }, - [2] = { - .start = IRQ_DB5500_DMA, - .end = IRQ_DB5500_DMA, - .flags = IORESOURCE_IRQ - } -}; - -/* Default configuration for physical memcpy */ -static struct stedma40_chan_cfg dma40_memcpy_conf_phy = { - .mode = STEDMA40_MODE_PHYSICAL, - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_PHY_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_PHY_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* Default configuration for logical memcpy */ -static struct stedma40_chan_cfg dma40_memcpy_conf_log = { - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* - * Mapping between soruce event lines and physical device address This was - * created assuming that the event line is tied to a device and therefore the - * address is constant, however this is not true for at least USB, and the - * values are just placeholders for USB. This table is preserved and used for - * now. - */ -static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = { - [DB5500_DMA_DEV24_SDMMC0_RX] = -1, - [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1, - [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1, - [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1, - [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1, - [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1, - [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1, - [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1, - [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1, -}; - -/* Mapping between destination event lines and physical device address */ -static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = { - [DB5500_DMA_DEV24_SDMMC0_TX] = -1, - [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1, - [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1, - [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1, - [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1, - [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1, - [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1, - [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1, - [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1, -}; - -static int dma40_memcpy_event[] = { - DB5500_DMA_MEMCPY_TX_1, - DB5500_DMA_MEMCPY_TX_2, - DB5500_DMA_MEMCPY_TX_3, - DB5500_DMA_MEMCPY_TX_4, - DB5500_DMA_MEMCPY_TX_5, -}; - -static struct stedma40_platform_data dma40_plat_data = { - .dev_len = ARRAY_SIZE(dma40_rx_map), - .dev_rx = dma40_rx_map, - .dev_tx = dma40_tx_map, - .memcpy = dma40_memcpy_event, - .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), - .memcpy_conf_phy = &dma40_memcpy_conf_phy, - .memcpy_conf_log = &dma40_memcpy_conf_log, - .disabled_channels = {-1}, -}; - -static struct platform_device dma40_device = { - .dev = { - .platform_data = &dma40_plat_data, - }, - .name = "dma40", - .id = 0, - .num_resources = ARRAY_SIZE(dma40_resources), - .resource = dma40_resources -}; - -void __init db5500_dma_init(struct device *parent) -{ - int ret; - - dma40_device.dev.parent = parent; - ret = platform_device_register(&dma40_device); - if (ret) - dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); - -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/headsmp.S b/ANDROID_3.4.5/arch/arm/mach-ux500/headsmp.S deleted file mode 100644 index 08da5589..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/headsmp.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2009 ST-Ericsson - * This file is based ARM Realview platform - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> - - __INIT - -/* - * U8500 specific entry point for secondary CPUs. - */ -ENTRY(u8500_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup -ENDPROC(u8500_secondary_startup) - - .align 2 -1: .long . - .long pen_release diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/hotplug.c b/ANDROID_3.4.5/arch/arm/mach-ux500/hotplug.c deleted file mode 100644 index c76f0f45..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/hotplug.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) STMicroelectronics 2009 - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License v2 - * Based on ARM realview platform - * - * Author: Sundar Iyer <sundar.iyer@stericsson.com> - * - */ -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/smp.h> - -#include <asm/cacheflush.h> -#include <asm/smp_plat.h> - -extern volatile int pen_release; - -static inline void platform_do_lowpower(unsigned int cpu) -{ - flush_cache_all(); - - /* we put the platform to just WFI */ - for (;;) { - __asm__ __volatile__("dsb\n\t" "wfi\n\t" - : : : "memory"); - if (pen_release == cpu_logical_map(cpu)) { - /* - * OK, proper wakeup, we're done - */ - break; - } - } -} - -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void platform_cpu_die(unsigned int cpu) -{ - /* directly enter low power state, skipping secure registers */ - platform_do_lowpower(cpu); -} - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/id.c b/ANDROID_3.4.5/arch/arm/mach-ux500/id.c deleted file mode 100644 index 15a0f63b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/id.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <asm/cputype.h> -#include <asm/tlbflush.h> -#include <asm/cacheflush.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/setup.h> - -struct dbx500_asic_id dbx500_id; - -static unsigned int ux500_read_asicid(phys_addr_t addr) -{ - phys_addr_t base = addr & ~0xfff; - struct map_desc desc = { - .virtual = IO_ADDRESS(base), - .pfn = __phys_to_pfn(base), - .length = SZ_16K, - .type = MT_DEVICE, - }; - - iotable_init(&desc, 1); - - /* As in devicemaps_init() */ - local_flush_tlb_all(); - flush_cache_all(); - - return readl(__io_address(addr)); -} - -static void ux500_print_soc_info(unsigned int asicid) -{ - unsigned int rev = dbx500_revision(); - - pr_info("DB%4x ", dbx500_partnumber()); - - if (rev == 0x01) - pr_cont("Early Drop"); - else if (rev >= 0xA0) - pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); - else - pr_cont("Unknown"); - - pr_cont(" [%#010x]\n", asicid); -} - -static unsigned int partnumber(unsigned int asicid) -{ - return (asicid >> 8) & 0xffff; -} - -/* - * SOC MIDR ASICID ADDRESS ASICID VALUE - * DB8500ed 0x410fc090 0x9001FFF4 0x00850001 - * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 - * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 - * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 - * DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2 - * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 - */ - -void __init ux500_map_io(void) -{ - unsigned int cpuid = read_cpuid_id(); - unsigned int asicid = 0; - phys_addr_t addr = 0; - - switch (cpuid) { - case 0x410fc090: /* DB8500ed */ - case 0x411fc091: /* DB8500v1 */ - addr = 0x9001FFF4; - break; - - case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */ - asicid = ux500_read_asicid(0x9001DBF4); - if (partnumber(asicid) == 0x8500 || - partnumber(asicid) == 0x8520) - /* DB8500v2 */ - break; - - /* DB5500v1 */ - addr = 0x9001FFF4; - break; - } - - if (addr) - asicid = ux500_read_asicid(addr); - - if (!asicid) { - pr_err("Unable to identify SoC\n"); - ux500_unknown_soc(); - } - - dbx500_id.process = asicid >> 24; - dbx500_id.partnumber = partnumber(asicid); - dbx500_id.revision = asicid & 0xff; - - ux500_print_soc_info(asicid); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/db5500-regs.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/db5500-regs.h deleted file mode 100644 index 8e714bcb..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_DB5500_REGS_H -#define __MACH_DB5500_REGS_H - -#define U5500_PER1_BASE 0xA0020000 -#define U5500_PER2_BASE 0xA0010000 -#define U5500_PER3_BASE 0x80140000 -#define U5500_PER4_BASE 0x80150000 -#define U5500_PER5_BASE 0x80100000 -#define U5500_PER6_BASE 0x80120000 - -#define U5500_GIC_DIST_BASE 0xA0411000 -#define U5500_GIC_CPU_BASE 0xA0410100 -#define U5500_DMA_BASE 0x90030000 -#define U5500_STM_BASE 0x90020000 -#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000) -#define U5500_MCDE_BASE 0xA0400000 -#define U5500_MODEM_BASE 0xB0000000 -#define U5500_L2CC_BASE 0xA0412000 -#define U5500_SCU_BASE 0xA0410000 -#define U5500_DSI1_BASE 0xA0401000 -#define U5500_DSI2_BASE 0xA0402000 -#define U5500_SIA_BASE 0xA0100000 -#define U5500_SVA_BASE 0x80200000 -#define U5500_HSEM_BASE 0xA0000000 -#define U5500_NAND0_BASE 0x60000000 -#define U5500_NAND1_BASE 0x70000000 -#define U5500_TWD_BASE 0xa0410600 -#define U5500_ICN_BASE 0xA0040000 -#define U5500_B2R2_BASE 0xa0200000 -#define U5500_BOOT_ROM_BASE 0x90000000 - -#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) -#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) -#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) -#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) -#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) -#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) -#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) -#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) - -#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) -#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) -#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) - -#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) -#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) -#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) -#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) - -#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) -#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) -#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) -#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) -#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) -#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) -#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) -#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) -#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) -#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) -#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) -#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) -#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) -#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) -#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) -#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) -#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) - -#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) -#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) -#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) -#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) -#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) -#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) -#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) -#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) -#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) -#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) -#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) -#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) -#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) -#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) -#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) -#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) -#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) - -#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) -#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) -#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) -#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) -#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100) -#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) -#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) -#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) -#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) -#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) -#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) - -#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE -#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) -#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE -#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE -#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE -#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE -#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) -#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) - -#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000) -#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40) -#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F) -#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60) -#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F) -#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80) -#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F) -#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0) -#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF) -#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00) -#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F) -#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) -#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) - -#define U5500_ACCCON_BASE_SEC (0xBFFF0000) -#define U5500_ACCCON_BASE (0xBFFF1000) -#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) -#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) -#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) - -#define U5500_ESRAM_BASE 0x40000000 -#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 -#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) - -#define U5500_MCDE_SIZE 0x1000 -#define U5500_DSI_LINK_SIZE 0x1000 -#define U5500_DSI_LINK_COUNT 0x2 -#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE) -#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/db8500-regs.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/db8500-regs.h deleted file mode 100644 index 9ec20b96..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_DB8500_REGS_H -#define __MACH_DB8500_REGS_H - -/* Base address and bank offsets for ESRAM */ -#define U8500_ESRAM_BASE 0x40000000 -#define U8500_ESRAM_BANK_SIZE 0x00020000 -#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE -#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) -#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) -#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) -#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) -/* - * on V1 DMA uses 4KB for logical parameters position is right after the 64KB - * reserved for security - */ -#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 - -#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) - -/* This address fulfills the 256k alignment requirement of the lcla base */ -#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 - -#define U8500_PER3_BASE 0x80000000 -#define U8500_STM_BASE 0x80100000 -#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_B2R2_BASE 0x80130000 -#define U8500_HSEM_BASE 0x80140000 -#define U8500_PER4_BASE 0x80150000 -#define U8500_TPIU_BASE 0x80190000 -#define U8500_ICN_BASE 0x81000000 - -#define U8500_BOOT_ROM_BASE 0x90000000 -/* ASIC ID is at 0xbf4 offset within this region */ -#define U8500_ASIC_ID_BASE 0x9001D000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER7_BASE 0xa03d0000 -#define U8500_PER5_BASE 0xa03e0000 - -#define U8500_SVA_BASE 0xa0100000 -#define U8500_SIA_BASE 0xa0200000 - -#define U8500_SGA_BASE 0xa0300000 -#define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE 0x801C0000 /* v1 */ - -#define U8500_SBAG_BASE 0xa0390000 - -#define U8500_SCU_BASE 0xa0410000 -#define U8500_GIC_CPU_BASE 0xa0410100 -#define U8500_TWD_BASE 0xa0410600 -#define U8500_GIC_DIST_BASE 0xa0411000 -#define U8500_L2CC_BASE 0xa0412000 - -#define U8500_MODEM_I2C 0xb7e02000 - -#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) -#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) -#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) -#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) - -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) - -/* per6 base addresses */ -#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) -#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000) -#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000) -#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000) -#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100) -#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ -#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ -#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ -#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000) -#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* per5 base addresses */ -#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* per4 base addresses */ -#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) -#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) -#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) -#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) -#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) -#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) -#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) -#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) -#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) -#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) - -/* per3 base addresses */ -#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) -#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) -#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) -#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) -#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) -#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* per2 base addresses */ -#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) -#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) -#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) -#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) -#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) -#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) -#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) -#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) -#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) -#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) -#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* per1 base addresses */ -#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) -#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) -#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) -#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000) -#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) -#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) -#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) -#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) -#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) - -#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 - -#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE -#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) -#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE -#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) -#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) -#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) -#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE -#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) -#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE - -#define U8500_MCDE_SIZE 0x1000 -#define U8500_DSI_LINK_SIZE 0x1000 -#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE) -#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) -#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) -#define U8500_DSI_LINK_COUNT 0x3 - -/* Modem and APE physical addresses */ -#define U8500_MODEM_BASE 0xe000000 -#define U8500_APE_BASE 0x6000000 - -/* SoC identification number information */ -#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/debug-macro.S b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/debug-macro.S deleted file mode 100644 index 8d74d927..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/debug-macro.S +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <mach/hardware.h> - -#if CONFIG_UX500_DEBUG_UART > 2 -#error Invalid Ux500 debug UART -#endif - -/* - * DEBUG_LL only works if only one SOC is built in. We don't use #else below - * in order to get "__UX500_UART redefined" warnings if more than one SOC is - * built, so that there's some hint during the build that something is wrong. - */ - -#ifdef CONFIG_UX500_SOC_DB5500 -#define __UX500_UART(n) U5500_UART##n##_BASE -#endif - -#ifdef CONFIG_UX500_SOC_DB8500 -#define __UX500_UART(n) U8500_UART##n##_BASE -#endif - -#ifndef __UX500_UART -#error Unknown SOC -#endif - -#define UX500_UART(n) __UX500_UART(n) -#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_BASE @ no, physical address - ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/devices.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/devices.h deleted file mode 100644 index 5f6cb71f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/devices.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __ASM_ARCH_DEVICES_H__ -#define __ASM_ARCH_DEVICES_H__ - -struct platform_device; -struct amba_device; - -extern struct platform_device u5500_gpio_devs[]; -extern struct platform_device u8500_gpio_devs[]; - -extern struct amba_device ux500_pl031_device; - -extern struct platform_device u8500_dma40_device; -extern struct platform_device ux500_ske_keypad_device; - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/gpio.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/gpio.h deleted file mode 100644 index c01ef665..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/gpio.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - - -#endif /* __ASM_ARCH_GPIO_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/hardware.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/hardware.h deleted file mode 100644 index f8469893..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/hardware.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson. - * - * U8500 hardware definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -/* - * Macros to get at IO space when running virtually - * We dont map all the peripherals, let ioremap do - * this for us. We map only very basic peripherals here. - */ -#define U8500_IO_VIRTUAL 0xf0000000 -#define U8500_IO_PHYSICAL 0xa0000000 - -/* This macro is used in assembly, so no cast */ -#define IO_ADDRESS(x) \ - (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) - -/* typesafe io address */ -#define __io_address(n) IOMEM(IO_ADDRESS(n)) -/* Used by some plat-nomadik code */ -#define io_p2v(n) __io_address(n) - -#include <mach/db8500-regs.h> -#include <mach/db5500-regs.h> - -#define MSP_TX_RX_REG_OFFSET 0 - -#ifndef __ASSEMBLY__ - -#include <mach/id.h> -extern void __iomem *_PRCMU_BASE; - -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - -#endif /* __ASSEMBLY__ */ -#endif /* __MACH_HARDWARE_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/id.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/id.h deleted file mode 100644 index 833d6a6e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/id.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_UX500_ID -#define __MACH_UX500_ID - -/** - * struct dbx500_asic_id - fields of the ASIC ID - * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard" - * @partnumber: hithereto 0x8500 for DB8500 - * @revision: version code in the series - */ -struct dbx500_asic_id { - u16 partnumber; - u8 revision; - u8 process; -}; - -extern struct dbx500_asic_id dbx500_id; - -static inline unsigned int __attribute_const__ dbx500_partnumber(void) -{ - return dbx500_id.partnumber; -} - -static inline unsigned int __attribute_const__ dbx500_revision(void) -{ - return dbx500_id.revision; -} - -/* - * SOCs - */ - -static inline bool __attribute_const__ cpu_is_u8500(void) -{ - return dbx500_partnumber() == 0x8500; -} - -static inline bool __attribute_const__ cpu_is_u5500(void) -{ - return dbx500_partnumber() == 0x5500; -} - -/* - * 5500 revisions - */ - -static inline bool __attribute_const__ cpu_is_u5500v1(void) -{ - return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0; -} - -static inline bool __attribute_const__ cpu_is_u5500v2(void) -{ - return (dbx500_id.revision & 0xf0) == 0xB0; -} - -static inline bool __attribute_const__ cpu_is_u5500v20(void) -{ - return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0); -} - -static inline bool __attribute_const__ cpu_is_u5500v21(void) -{ - return cpu_is_u5500() && (dbx500_revision() == 0xB1); -} - -/* - * 8500 revisions - */ - -static inline bool __attribute_const__ cpu_is_u8500ed(void) -{ - return cpu_is_u8500() && dbx500_revision() == 0x00; -} - -static inline bool __attribute_const__ cpu_is_u8500v1(void) -{ - return cpu_is_u8500() && (dbx500_revision() & 0xf0) == 0xA0; -} - -static inline bool __attribute_const__ cpu_is_u8500v10(void) -{ - return cpu_is_u8500() && dbx500_revision() == 0xA0; -} - -static inline bool __attribute_const__ cpu_is_u8500v11(void) -{ - return cpu_is_u8500() && dbx500_revision() == 0xA1; -} - -static inline bool __attribute_const__ cpu_is_u8500v2(void) -{ - return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0); -} - -static inline bool cpu_is_u8500v20(void) -{ - return cpu_is_u8500() && (dbx500_revision() == 0xB0); -} - -static inline bool cpu_is_u8500v21(void) -{ - return cpu_is_u8500() && (dbx500_revision() == 0xB1); -} - -static inline bool cpu_is_u8500v20_or_later(void) -{ - return cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11(); -} - -static inline bool ux500_is_svp(void) -{ - return false; -} - -#define ux500_unknown_soc() BUG() - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h deleted file mode 100644 index 7d34c527..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_BOARD_MOP500_H -#define __MACH_IRQS_BOARD_MOP500_H - -/* Number of AB8500 irqs is taken from header file */ -#include <linux/mfd/abx500/ab8500.h> - -#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START -#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ - + AB8500_MAX_NR_IRQS) - -/* TC35892 */ -#define TC35892_NR_INTERNAL_IRQS 8 -#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) -#define TC35892_NR_GPIOS 24 -#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) - -#define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS - -#define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END -#define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ - + MOP500_EGPIO_NR_IRQS) -/* STMPE1601 irqs */ -#define STMPE_NR_INTERNAL_IRQS 9 -#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) -#define STMPE_NR_GPIOS 24 -#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) - -#define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END -#define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) - -#define MOP500_STMPE1601_IRQ_END \ - MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) - -/* AB8500 virtual gpio IRQ */ -#define AB8500_VIR_GPIO_NR_IRQS 16 - -#define MOP500_AB8500_VIR_GPIO_IRQ_BASE \ - MOP500_STMPE1601_IRQ_END -#define MOP500_AB8500_VIR_GPIO_IRQ_END \ - (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS) - -#define MOP500_NR_IRQS MOP500_AB8500_VIR_GPIO_IRQ_END - -#define MOP500_IRQ_END MOP500_NR_IRQS - -/* - * We may have several boards, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_BOARD_START remains the same for either board. - */ -#if MOP500_IRQ_END > IRQ_BOARD_END -#undef IRQ_BOARD_END -#define IRQ_BOARD_END MOP500_IRQ_END -#endif - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h deleted file mode 100644 index 29d972c7..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_BOARD_U5500_H -#define __MACH_IRQS_BOARD_U5500_H - -#define AB5500_NR_IRQS 5 -#define IRQ_AB5500_BASE IRQ_BOARD_START -#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS) - -#define U5500_IRQ_END IRQ_AB5500_END - -#if IRQ_BOARD_END < U5500_IRQ_END -#undef IRQ_BOARD_END -#define IRQ_BOARD_END U5500_IRQ_END -#endif - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-db5500.h deleted file mode 100644 index 77239776..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-db5500.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_DB5500_H -#define __MACH_IRQS_DB5500_H - -#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4) -#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6) -#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7) -#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8) -#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9) -#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10) -#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11) -#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12) -#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13) -#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14) -#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15) -#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16) -#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17) -#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18) -#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19) -#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20) -#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21) -#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22) -#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23) -#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24) -#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25) -#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26) -#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27) -#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28) -#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29) -#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30) -#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31) -#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33) -#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34) -#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35) -#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36) -#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37) -#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38) -#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39) -#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40) -#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41) -#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42) -#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43) -#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44) -#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45) -#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46) -#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47) -#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48) -#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50) -#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52) -#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53) -#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55) -#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56) -#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57) -#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59) -#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) -#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) -#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) -#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65) -#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) -#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) -#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) -#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108) -#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109) -#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110) -#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112) -#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113) -#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114) -#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115) -#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116) -#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118) -#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119) -#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120) -#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121) -#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122) -#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123) -#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124) -#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) -#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) - -#ifdef CONFIG_UX500_SOC_DB5500 - -/* - * After the GPIO ones we reserve a range of IRQ:s in which virtual - * IRQ:s representing modem IRQ:s can be allocated - */ -#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START -#define IRQ_MODEM_EVENTS_NBR 72 -#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR) - -/* List of virtual IRQ:s that are allocated from the range above */ -#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43) -#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45) -#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41) - -/* - * We may have several SoCs, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_SOC_START remains the same for either SoC. - */ -#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END -#undef IRQ_SOC_END -#define IRQ_SOC_END IRQ_MODEM_EVENTS_END -#endif - -#endif /* CONFIG_UX500_SOC_DB5500 */ - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-db8500.h deleted file mode 100644 index 68bc1497..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs-db8500.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_DB8500_H -#define __MACH_IRQS_DB8500_H - -#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4) -#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6) -#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7) -#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8) -#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9) -#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10) -#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11) -#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12) -#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13) -#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14) -#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15) -#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16) -#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17) -#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18) -#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19) -#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20) -#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21) -#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22) -#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23) -#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24) -#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25) -#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26) -#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27) -#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28) -#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29) -#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31) -#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) -#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) -#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) -#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) -#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36) -#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37) -#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38) -#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39) -#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40) -#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41) -#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42) -#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43) -#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44) -#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45) -#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46) -#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47) -#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48) -#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49) -#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50) -#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51) -#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52) -#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53) -#define IRQ_DB8500_KB (IRQ_SHPI_START + 54) -#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55) -#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56) -#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57) -#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59) -#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60) -#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61) -#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62) -#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63) -#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96) -#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97) -#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98) -#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99) -#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100) -#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104) -#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105) -#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106) -#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107) -#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108) -#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109) -#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110) -#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112) -#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113) -#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114) -#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115) -#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116) -#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118) -#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119) -#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120) -#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121) -#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122) -#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123) -#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124) -#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125) -#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) -#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) - -#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71) -#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66) -#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64) -#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67) -#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65) - -#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83) -#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78) -#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76) -#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79) -#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77) - -#ifdef CONFIG_UX500_SOC_DB8500 - -/* Virtual interrupts corresponding to the PRCMU wakeups. */ -#define IRQ_PRCMU_BASE IRQ_SOC_START -#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE) - -#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE) -#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1) -#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2) -#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3) -#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4) -#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5) -#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6) -#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7) -#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8) -#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9) -#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10) -#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11) -#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12) -#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13) -#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14) -#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15) -#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16) -#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17) -#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18) -#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19) -#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20) -#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21) -#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22) -#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) - -/* - * We may have several SoCs, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_SOC_START remains the same for either SoC. - */ -#if IRQ_SOC_END < IRQ_PRCMU_END -#undef IRQ_SOC_END -#define IRQ_SOC_END IRQ_PRCMU_END -#endif - -#endif /* CONFIG_UX500_SOC_DB8500 */ -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs.h deleted file mode 100644 index c23a6b5f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/irqs.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2008 STMicroelectronics - * Copyright (C) 2009 ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef ASM_ARCH_IRQS_H -#define ASM_ARCH_IRQS_H - -#include <mach/hardware.h> - -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 - -/* Shared Peripheral Interrupt (SHPI) */ -#define IRQ_SHPI_START 32 - -/* - * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't - * add any other IRQs here, use the irqs-dbx500.h files. - */ -#define IRQ_MTU0 (IRQ_SHPI_START + 4) - -#define DBX500_NR_INTERNAL_IRQS 160 - -/* After chip-specific IRQ numbers we have the GPIO ones */ -#define NOMADIK_NR_GPIO 288 -#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) -#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) -#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) - -#define IRQ_SOC_START IRQ_GPIO_END -/* This will be overridden by SoC-specific irq headers */ -#define IRQ_SOC_END IRQ_SOC_START - -#include <mach/irqs-db5500.h> -#include <mach/irqs-db8500.h> - -#define IRQ_BOARD_START IRQ_SOC_END -/* This will be overridden by board-specific irq headers */ -#define IRQ_BOARD_END IRQ_BOARD_START - -#ifdef CONFIG_MACH_MOP500 -#include <mach/irqs-board-mop500.h> -#endif - -#ifdef CONFIG_MACH_U5500 -#include <mach/irqs-board-u5500.h> -#endif - -#define NR_IRQS IRQ_BOARD_END - -#endif /* ASM_ARCH_IRQS_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/mbox-db5500.h deleted file mode 100644 index 7f9da4d2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/mbox-db5500.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __INC_STE_MBOX_H -#define __INC_STE_MBOX_H - -#define MBOX_BUF_SIZE 16 -#define MBOX_NAME_SIZE 8 - -/** - * mbox_recv_cb_t - Definition of the mailbox callback. - * @mbox_msg: The mailbox message. - * @priv: The clients private data as specified in the call to mbox_setup. - * - * This function will be called upon reception of new mailbox messages. - */ -typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv); - -/** - * struct mbox - Mailbox instance struct - * @list: Linked list head. - * @pdev: Pointer to device struct. - * @cb: Callback function. Will be called - * when new data is received. - * @client_data: Clients private data. Will be sent back - * in the callback function. - * @virtbase_peer: Virtual address for outgoing mailbox. - * @virtbase_local: Virtual address for incoming mailbox. - * @buffer: Then internal queue for outgoing messages. - * @name: Name of this mailbox. - * @buffer_available: Completion variable to achieve "blocking send". - * This variable will be signaled when there is - * internal buffer space available. - * @client_blocked: To keep track if any client is currently - * blocked. - * @lock: Spinlock to protect this mailbox instance. - * @write_index: Index in internal buffer to write to. - * @read_index: Index in internal buffer to read from. - * @allocated: Indicates whether this particular mailbox - * id has been allocated by someone. - */ -struct mbox { - struct list_head list; - struct platform_device *pdev; - mbox_recv_cb_t *cb; - void *client_data; - void __iomem *virtbase_peer; - void __iomem *virtbase_local; - u32 buffer[MBOX_BUF_SIZE]; - char name[MBOX_NAME_SIZE]; - struct completion buffer_available; - u8 client_blocked; - spinlock_t lock; - u8 write_index; - u8 read_index; - bool allocated; -}; - -/** - * mbox_setup - Set up a mailbox and return its instance. - * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU, - * 2 for modem DSP. - * @mbox_cb: Pointer to the callback function to be called when a new message - * is received. - * @priv: Client user data which will be returned in the callback. - * - * Returns a mailbox instance to be specified in subsequent calls to mbox_send. - */ -struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv); - -/** - * mbox_send - Send a mailbox message. - * @mbox: Mailbox instance (returned by mbox_setup) - * @mbox_msg: The mailbox message to send. - * @block: Specifies whether this call will block until send is possible, - * or return an error if the mailbox buffer is full. - * - * Returns 0 on success or a negative error code on error. -ENOMEM indicates - * that the internal buffer is full and you have to try again later (or - * specify "block" in order to block until send is possible). - */ -int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block); - -#endif /*INC_STE_MBOX_H*/ diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/setup.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/setup.h deleted file mode 100644 index 3dc00ffa..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/setup.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * These symbols are needed for board-specific files to call their - * own cpu-specific files - */ -#ifndef __ASM_ARCH_SETUP_H -#define __ASM_ARCH_SETUP_H - -#include <asm/mach/time.h> -#include <linux/init.h> - -void __init ux500_map_io(void); -extern void __init u5500_map_io(void); -extern void __init u8500_map_io(void); - -extern struct device * __init u5500_init_devices(void); -extern struct device * __init u8500_init_devices(void); - -extern void __init ux500_init_irq(void); - -extern void __init u5500_sdi_init(struct device *parent); - -extern void __init db5500_dma_init(struct device *parent); - -extern struct device *ux500_soc_device_init(const char *soc_id); - -struct amba_device; -extern void __init amba_add_devices(struct amba_device *devs[], int num); - -struct sys_timer; -extern struct sys_timer ux500_timer; - -#define __IO_DEV_DESC(x, sz) { \ - .virtual = IO_ADDRESS(x), \ - .pfn = __phys_to_pfn(x), \ - .length = sz, \ - .type = MT_DEVICE, \ -} - -#define __MEM_DEV_DESC(x, sz) { \ - .virtual = IO_ADDRESS(x), \ - .pfn = __phys_to_pfn(x), \ - .length = sz, \ - .type = MT_MEMORY, \ -} - -#endif /* __ASM_ARCH_SETUP_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/timex.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/timex.h deleted file mode 100644 index d0942c17..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 110000000 - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/uncompress.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/uncompress.h deleted file mode 100644 index 6fb3c4b0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/uncompress.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <linux/io.h> -#include <linux/amba/serial.h> -#include <mach/hardware.h> - -u32 ux500_uart_base; - -static void putc(const char c) -{ - /* Do nothing if the UART is not enabled. */ - if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) - return; - - if (c == '\n') - putc('\r'); - - while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5)) - barrier(); - __raw_writeb(c, ux500_uart_base + UART01x_DR); -} - -static void flush(void) -{ - if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) - return; - while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3)) - barrier(); -} - -static inline void arch_decomp_setup(void) -{ - /* Check in run time if we run on an U8500 or U5500 */ - if (machine_is_u5500()) - ux500_uart_base = U5500_UART0_BASE; - else - ux500_uart_base = U8500_UART2_BASE; -} - -#define arch_decomp_wdog() /* nothing to do here */ - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/usb.h b/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/usb.h deleted file mode 100644 index 4c1cc50a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/include/mach/usb.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2011 - * - * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ -#ifndef __ASM_ARCH_USB_H -#define __ASM_ARCH_USB_H - -#include <linux/dmaengine.h> - -#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8 -#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8 - -struct ux500_musb_board_data { - void **dma_rx_param_array; - void **dma_tx_param_array; - u32 num_rx_channels; - u32 num_tx_channels; - bool (*dma_filter)(struct dma_chan *chan, void *filter_param); -}; - -void ux500_add_usb(struct device *parent, resource_size_t base, - int irq, int *dma_rx_cfg, int *dma_tx_cfg); -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/mbox-db5500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/mbox-db5500.c deleted file mode 100644 index 01274902..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/mbox-db5500.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -/* - * Mailbox nomenclature: - * - * APE MODEM - * mbox pairX - * .......................... - * . . - * . peer . - * . send ---- . - * . --> | | . - * . | | . - * . ---- . - * . . - * . local . - * . rec ---- . - * . | | <-- . - * . | | . - * . ---- . - * ......................... - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/completion.h> -#include <mach/mbox-db5500.h> - -#define MBOX_NAME "mbox" - -#define MBOX_FIFO_DATA 0x000 -#define MBOX_FIFO_ADD 0x004 -#define MBOX_FIFO_REMOVE 0x008 -#define MBOX_FIFO_THRES_FREE 0x00C -#define MBOX_FIFO_THRES_OCCUP 0x010 -#define MBOX_FIFO_STATUS 0x014 - -#define MBOX_DISABLE_IRQ 0x4 -#define MBOX_ENABLE_IRQ 0x0 -#define MBOX_LATCH 1 - -/* Global list of all mailboxes */ -static struct list_head mboxs = LIST_HEAD_INIT(mboxs); - -static struct mbox *get_mbox_with_id(u8 id) -{ - u8 i; - struct list_head *pos = &mboxs; - for (i = 0; i <= id; i++) - pos = pos->next; - - return (struct mbox *) list_entry(pos, struct mbox, list); -} - -int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block) -{ - int res = 0; - - spin_lock(&mbox->lock); - - dev_dbg(&(mbox->pdev->dev), - "About to buffer 0x%X to mailbox 0x%X." - " ri = %d, wi = %d\n", - mbox_msg, (u32)mbox, mbox->read_index, - mbox->write_index); - - /* Check if write buffer is full */ - while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) { - if (!block) { - dev_dbg(&(mbox->pdev->dev), - "Buffer full in non-blocking call! " - "Returning -ENOMEM!\n"); - res = -ENOMEM; - goto exit; - } - spin_unlock(&mbox->lock); - dev_dbg(&(mbox->pdev->dev), - "Buffer full in blocking call! Sleeping...\n"); - mbox->client_blocked = 1; - wait_for_completion(&mbox->buffer_available); - dev_dbg(&(mbox->pdev->dev), - "Blocking send was woken up! Trying again...\n"); - spin_lock(&mbox->lock); - } - - mbox->buffer[mbox->write_index] = mbox_msg; - mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE; - - /* - * Indicate that we want an IRQ as soon as there is a slot - * in the FIFO - */ - writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - -exit: - spin_unlock(&mbox->lock); - return res; -} -EXPORT_SYMBOL(mbox_send); - -#if defined(CONFIG_DEBUG_FS) -/* - * Expected input: <value> <nbr sends> - * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times - */ -static ssize_t mbox_write_fifo(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - unsigned long mbox_mess; - unsigned long nbr_sends; - unsigned long i; - char int_buf[16]; - char *token; - char *val; - - struct mbox *mbox = (struct mbox *) dev->platform_data; - - strncpy((char *) &int_buf, buf, sizeof(int_buf)); - token = (char *) &int_buf; - - /* Parse message */ - val = strsep(&token, " "); - if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0)) - mbox_mess = 0xDEADBEEF; - - val = strsep(&token, " "); - if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0)) - nbr_sends = 1; - - dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n", - mbox_mess, nbr_sends, (u32) mbox); - - for (i = 0; i < nbr_sends; i++) - mbox_send(mbox, mbox_mess, true); - - return count; -} - -static ssize_t mbox_read_fifo(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - int mbox_value; - struct mbox *mbox = (struct mbox *) dev->platform_data; - - if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0) - return sprintf(buf, "Mailbox is empty\n"); - - mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); - writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); - - return sprintf(buf, "0x%X\n", mbox_value); -} - -static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo); - -static int mbox_show(struct seq_file *s, void *data) -{ - struct list_head *pos; - u8 mbox_index = 0; - - list_for_each(pos, &mboxs) { - struct mbox *m = - (struct mbox *) list_entry(pos, struct mbox, list); - if (m == NULL) { - seq_printf(s, - "Unable to retrieve mailbox %d\n", - mbox_index); - continue; - } - - spin_lock(&m->lock); - if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) { - seq_printf(s, "MAILBOX %d not setup or corrupt\n", - mbox_index); - spin_unlock(&m->lock); - continue; - } - - seq_printf(s, - "===========================\n" - " MAILBOX %d\n" - " PEER MAILBOX DUMP\n" - "---------------------------\n" - "FIFO: 0x%X (%d)\n" - "Free Threshold: 0x%.2X (%d)\n" - "Occupied Threshold: 0x%.2X (%d)\n" - "Status: 0x%.2X (%d)\n" - " Free spaces (ot): %d (%d)\n" - " Occup spaces (ot): %d (%d)\n" - "===========================\n" - " LOCAL MAILBOX DUMP\n" - "---------------------------\n" - "FIFO: 0x%.X (%d)\n" - "Free Threshold: 0x%.2X (%d)\n" - "Occupied Threshold: 0x%.2X (%d)\n" - "Status: 0x%.2X (%d)\n" - " Free spaces (ot): %d (%d)\n" - " Occup spaces (ot): %d (%d)\n" - "===========================\n" - "write_index: %d\n" - "read_index : %d\n" - "===========================\n" - "\n", - mbox_index, - readl(m->virtbase_peer + MBOX_FIFO_DATA), - readl(m->virtbase_peer + MBOX_FIFO_DATA), - readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_peer + MBOX_FIFO_STATUS), - readl(m->virtbase_peer + MBOX_FIFO_STATUS), - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1, - readl(m->virtbase_local + MBOX_FIFO_DATA), - readl(m->virtbase_local + MBOX_FIFO_DATA), - readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_local + MBOX_FIFO_STATUS), - readl(m->virtbase_local + MBOX_FIFO_STATUS), - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1, - m->write_index, m->read_index); - mbox_index++; - spin_unlock(&m->lock); - } - - return 0; -} - -static int mbox_open(struct inode *inode, struct file *file) -{ - return single_open(file, mbox_show, NULL); -} - -static const struct file_operations mbox_operations = { - .owner = THIS_MODULE, - .open = mbox_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - -static irqreturn_t mbox_irq(int irq, void *arg) -{ - u32 mbox_value; - int nbr_occup; - int nbr_free; - struct mbox *mbox = (struct mbox *) arg; - - spin_lock(&mbox->lock); - - dev_dbg(&(mbox->pdev->dev), - "mbox IRQ [%d] received. ri = %d, wi = %d\n", - irq, mbox->read_index, mbox->write_index); - - /* - * Check if we have any outgoing messages, and if there is space for - * them in the FIFO. - */ - if (mbox->read_index != mbox->write_index) { - /* - * Check by reading FREE for LOCAL since that indicates - * OCCUP for PEER - */ - nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS) - >> 4) & 0x7; - dev_dbg(&(mbox->pdev->dev), - "Status indicates %d empty spaces in the FIFO!\n", - nbr_free); - - while ((nbr_free > 0) && - (mbox->read_index != mbox->write_index)) { - /* Write the message and latch it into the FIFO */ - writel(mbox->buffer[mbox->read_index], - (mbox->virtbase_peer + MBOX_FIFO_DATA)); - writel(MBOX_LATCH, - (mbox->virtbase_peer + MBOX_FIFO_ADD)); - dev_dbg(&(mbox->pdev->dev), - "Wrote message 0x%X to addr 0x%X\n", - mbox->buffer[mbox->read_index], - (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA)); - - nbr_free--; - mbox->read_index = - (mbox->read_index + 1) % MBOX_BUF_SIZE; - } - - /* - * Check if we still want IRQ:s when there is free - * space to send - */ - if (mbox->read_index != mbox->write_index) { - dev_dbg(&(mbox->pdev->dev), - "Still have messages to send, but FIFO full. " - "Request IRQ again!\n"); - writel(MBOX_ENABLE_IRQ, - mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - } else { - dev_dbg(&(mbox->pdev->dev), - "No more messages to send. " - "Do not request IRQ again!\n"); - writel(MBOX_DISABLE_IRQ, - mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - } - - /* - * Check if we can signal any blocked clients that it is OK to - * start buffering again - */ - if (mbox->client_blocked && - (((mbox->write_index + 1) % MBOX_BUF_SIZE) - != mbox->read_index)) { - dev_dbg(&(mbox->pdev->dev), - "Waking up blocked client\n"); - complete(&mbox->buffer_available); - mbox->client_blocked = 0; - } - } - - /* Check if we have any incoming messages */ - nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7; - if (nbr_occup == 0) - goto exit; - - if (mbox->cb == NULL) { - dev_dbg(&(mbox->pdev->dev), "No receive callback registered, " - "leaving %d incoming messages in fifo!\n", nbr_occup); - goto exit; - } - - /* Read and acknowledge the message */ - mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); - writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); - - /* Notify consumer of new mailbox message */ - dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n", - mbox_value); - mbox->cb(mbox_value, mbox->client_data); - -exit: - dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n", - mbox->read_index, mbox->write_index); - spin_unlock(&mbox->lock); - - return IRQ_HANDLED; -} - -/* Setup is executed once for each mbox pair */ -struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) -{ - struct resource *resource; - int irq; - int res; - struct mbox *mbox; - - mbox = get_mbox_with_id(mbox_id); - if (mbox == NULL) { - dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n", - mbox_id); - goto exit; - } - - /* - * Check if mailbox has been allocated to someone else, - * otherwise allocate it - */ - if (mbox->allocated) { - dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n", - mbox_id); - mbox = NULL; - goto exit; - } - mbox->allocated = true; - - dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n", - mbox_id, (u32)mbox); - - mbox->client_data = priv; - mbox->cb = mbox_cb; - - /* Get addr for peer mailbox and ioremap it */ - resource = platform_get_resource_byname(mbox->pdev, - IORESOURCE_MEM, - "mbox_peer"); - if (resource == NULL) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox peer resource\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "Resource name: %s start: 0x%X, end: 0x%X\n", - resource->name, resource->start, resource->end); - mbox->virtbase_peer = ioremap(resource->start, resource_size(resource)); - if (!mbox->virtbase_peer) { - dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n", - resource->start, resource->end, (u32) mbox->virtbase_peer); - - /* Get addr for local mailbox and ioremap it */ - resource = platform_get_resource_byname(mbox->pdev, - IORESOURCE_MEM, - "mbox_local"); - if (resource == NULL) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox local resource\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "Resource name: %s start: 0x%X, end: 0x%X\n", - resource->name, resource->start, resource->end); - mbox->virtbase_local = ioremap(resource->start, resource_size(resource)); - if (!mbox->virtbase_local) { - dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n", - resource->start, resource->end, (u32) mbox->virtbase_peer); - - init_completion(&mbox->buffer_available); - mbox->client_blocked = 0; - - /* Get IRQ for mailbox and allocate it */ - irq = platform_get_irq_byname(mbox->pdev, "mbox_irq"); - if (irq < 0) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox irq resource\n"); - mbox = NULL; - goto exit; - } - - dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq); - res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox); - if (res < 0) { - dev_err(&(mbox->pdev->dev), - "Unable to allocate mbox irq %d\n", irq); - mbox = NULL; - goto exit; - } - - /* Set up mailbox to not launch IRQ on free space in mailbox */ - writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - - /* - * Set up mailbox to launch IRQ on new message if we have - * a callback set. If not, do not raise IRQ, but keep message - * in FIFO for manual retrieval - */ - if (mbox_cb != NULL) - writel(MBOX_ENABLE_IRQ, - mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); - else - writel(MBOX_DISABLE_IRQ, - mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); - -#if defined(CONFIG_DEBUG_FS) - res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo); - if (res != 0) - dev_warn(&(mbox->pdev->dev), - "Unable to create mbox sysfs entry"); - - (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL, - NULL, &mbox_operations); -#endif - - dev_info(&(mbox->pdev->dev), - "Mailbox driver with index %d initiated!\n", mbox_id); - -exit: - return mbox; -} -EXPORT_SYMBOL(mbox_setup); - - -int __init mbox_probe(struct platform_device *pdev) -{ - struct mbox local_mbox; - struct mbox *mbox; - int res = 0; - dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev); - - memset(&local_mbox, 0x0, sizeof(struct mbox)); - - /* Associate our mbox data with the platform device */ - res = platform_device_add_data(pdev, - (void *) &local_mbox, - sizeof(struct mbox)); - if (res != 0) { - dev_err(&(pdev->dev), - "Unable to allocate driver platform data!\n"); - goto exit; - } - - mbox = (struct mbox *) pdev->dev.platform_data; - mbox->pdev = pdev; - mbox->write_index = 0; - mbox->read_index = 0; - - INIT_LIST_HEAD(&(mbox->list)); - list_add_tail(&(mbox->list), &mboxs); - - sprintf(mbox->name, "%s", MBOX_NAME); - spin_lock_init(&mbox->lock); - - dev_info(&(pdev->dev), "Mailbox driver loaded\n"); - -exit: - return res; -} - -static struct platform_driver mbox_driver = { - .driver = { - .name = MBOX_NAME, - .owner = THIS_MODULE, - }, -}; - -static int __init mbox_init(void) -{ - return platform_driver_probe(&mbox_driver, mbox_probe); -} - -module_init(mbox_init); - -void __exit mbox_exit(void) -{ - platform_driver_unregister(&mbox_driver); -} - -module_exit(mbox_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("MBOX driver"); diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/modem-irq-db5500.c b/ANDROID_3.4.5/arch/arm/mach-ux500/modem-irq-db5500.c deleted file mode 100644 index 6b86416c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/modem-irq-db5500.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/slab.h> - -#include <mach/id.h> - -#define MODEM_INTCON_BASE_ADDR 0xBFFD3000 -#define MODEM_INTCON_SIZE 0xFFF - -#define DEST_IRQ41_OFFSET 0x2A4 -#define DEST_IRQ43_OFFSET 0x2AC -#define DEST_IRQ45_OFFSET 0x2B4 - -#define PRIO_IRQ41_OFFSET 0x6A4 -#define PRIO_IRQ43_OFFSET 0x6AC -#define PRIO_IRQ45_OFFSET 0x6B4 - -#define ALLOW_IRQ_OFFSET 0x104 - -#define MODEM_INTCON_CPU_NBR 0x1 -#define MODEM_INTCON_PRIO_HIGH 0x0 - -#define MODEM_INTCON_ALLOW_IRQ41 0x0200 -#define MODEM_INTCON_ALLOW_IRQ43 0x0800 -#define MODEM_INTCON_ALLOW_IRQ45 0x2000 - -#define MODEM_IRQ_REG_OFFSET 0x4 - -struct modem_irq { - void __iomem *modem_intcon_base; -}; - - -static void setup_modem_intcon(void __iomem *modem_intcon_base) -{ - /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */ - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET); - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET); - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET); - - /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */ - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET); - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET); - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET); - - /* IC_ALLOW_ARRAY - IRQ enable */ - writel(MODEM_INTCON_ALLOW_IRQ41 | - MODEM_INTCON_ALLOW_IRQ43 | - MODEM_INTCON_ALLOW_IRQ45, - modem_intcon_base + ALLOW_IRQ_OFFSET); -} - -static irqreturn_t modem_cpu_irq_handler(int irq, void *data) -{ - int real_irq; - int virt_irq; - struct modem_irq *mi = (struct modem_irq *)data; - - /* Read modem side IRQ number from modem IRQ controller */ - real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF; - virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq; - - pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X " - "which will be 0x%X (%d) which translates to " - "virtual IRQ 0x%X (%d)!\n", - (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET, - real_irq, - real_irq & 0xFF, - real_irq & 0xFF, - virt_irq, - virt_irq); - - if (virt_irq != 0) - generic_handle_irq(virt_irq); - - pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq); - - return IRQ_HANDLED; -} - -static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) -{ - irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - - pr_debug("modem_irq: Created virtual IRQ %d\n", irq); -} - -static int modem_irq_init(void) -{ - int err; - static struct irq_chip modem_irq_chip; - struct modem_irq *mi; - - if (!cpu_is_u5500()) - return -ENODEV; - - pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", - IRQ_DB5500_MODEM); - - mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL); - if (!mi) { - pr_err("modem_irq: Could not allocate device\n"); - return -ENOMEM; - } - - mi->modem_intcon_base = - ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE); - pr_debug("modem_irq: ioremapped modem_intcon_base from " - "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR, - (u32)mi->modem_intcon_base); - - setup_modem_intcon(mi->modem_intcon_base); - - modem_irq_chip = dummy_irq_chip; - modem_irq_chip.name = "modem_irq"; - - /* Create the virtual IRQ:s needed */ - create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip); - create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip); - create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip); - - err = request_threaded_irq(IRQ_DB5500_MODEM, NULL, - modem_cpu_irq_handler, IRQF_ONESHOT, - "modem_irq", mi); - if (err) - pr_err("modem_irq: Could not register IRQ %d\n", - IRQ_DB5500_MODEM); - - return 0; -} - -arch_initcall(modem_irq_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/pins-db5500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/pins-db5500.h deleted file mode 100644 index bf50c21f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/pins-db5500.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - */ - -#ifndef __MACH_DB5500_PINS_H -#define __MACH_DB5500_PINS_H - -#define GPIO0_GPIO PIN_CFG(0, GPIO) -#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A) - -#define GPIO1_GPIO PIN_CFG(1, GPIO) -#define GPIO1_SM_A3 PIN_CFG(1, ALT_A) - -#define GPIO2_GPIO PIN_CFG(2, GPIO) -#define GPIO2_SM_A4 PIN_CFG(2, ALT_A) -#define GPIO2_SM_AVD PIN_CFG(2, ALT_B) - -#define GPIO3_GPIO PIN_CFG(3, GPIO) -#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A) - -#define GPIO4_GPIO PIN_CFG(4, GPIO) -#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A) - -#define GPIO5_GPIO PIN_CFG(5, GPIO) -#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A) -#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B) - -#define GPIO6_GPIO PIN_CFG(6, GPIO) -#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A) -#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B) - -#define GPIO7_GPIO PIN_CFG(7, GPIO) -#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A) -#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B) - -#define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A) -#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B) - -#define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A) -#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B) - -#define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A) -#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B) - -#define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A) -#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B) - -#define GPIO12_GPIO PIN_CFG(12, GPIO) -#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A) -#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B) - -#define GPIO13_GPIO PIN_CFG(13, GPIO) -#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A) -#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B) -#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C) - -#define GPIO14_GPIO PIN_CFG(14, GPIO) -#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A) -#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B) -#define GPIO14_SM_CKO PIN_CFG(14, ALT_C) - -#define GPIO15_GPIO PIN_CFG(15, GPIO) -#define GPIO15_SM_A5 PIN_CFG(15, ALT_A) -#define GPIO15_SM_CLE PIN_CFG(15, ALT_B) - -#define GPIO16_GPIO PIN_CFG(16, GPIO) -#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A) -#define GPIO16_SM_OEn PIN_CFG(16, ALT_B) - -#define GPIO17_GPIO PIN_CFG(17, GPIO) -#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A) -#define GPIO17_SM_WEn PIN_CFG(17, ALT_B) - -#define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_SM_A6 PIN_CFG(18, ALT_A) -#define GPIO18_SM_ALE PIN_CFG(18, ALT_B) -#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C) - -#define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A) -#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B) - -#define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A) -#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B) - -#define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A) -#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B) - -#define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A) -#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B) - -#define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A) -#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B) -#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C) - -#define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A) -#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B) -#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C) - -#define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A) -#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B) -#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C) - -#define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A) -#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B) - -#define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A) -#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B) - -#define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_U0_TXD PIN_CFG(28, ALT_A) -#define GPIO28_SM_A0 PIN_CFG(28, ALT_B) - -#define GPIO29_GPIO PIN_CFG(29, GPIO) -#define GPIO29_U0_RXD PIN_CFG(29, ALT_A) -#define GPIO29_SM_A1 PIN_CFG(29, ALT_B) -#define GPIO29_PWM_0 PIN_CFG(29, ALT_C) - -#define GPIO30_GPIO PIN_CFG(30, GPIO) -#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) -#define GPIO30_SM_A2 PIN_CFG(30, ALT_B) -#define GPIO30_PWM_1 PIN_CFG(30, ALT_C) - -#define GPIO31_GPIO PIN_CFG(31, GPIO) -#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A) -#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B) -#define GPIO31_PWM_2 PIN_CFG(31, ALT_C) - -#define GPIO32_GPIO PIN_CFG(32, GPIO) -#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A) -#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B) - -#define GPIO33_GPIO PIN_CFG(33, GPIO) -#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A) -#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B) - -#define GPIO34_GPIO PIN_CFG(34, GPIO) -#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A) -#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B) - -#define GPIO35_GPIO PIN_CFG(35, GPIO) -#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A) -#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B) - -#define GPIO64_GPIO PIN_CFG(64, GPIO) -#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A) -#define GPIO64_U0_TXD PIN_CFG(64, ALT_B) - -#define GPIO65_GPIO PIN_CFG(65, GPIO) -#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A) -#define GPIO65_U0_RXD PIN_CFG(65, ALT_B) - -#define GPIO66_GPIO PIN_CFG(66, GPIO) -#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A) - -#define GPIO67_GPIO PIN_CFG(67, GPIO) -#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A) - -#define GPIO68_GPIO PIN_CFG(68, GPIO) -#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A) - -#define GPIO69_GPIO PIN_CFG(69, GPIO) -#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A) - -#define GPIO70_GPIO PIN_CFG(70, GPIO) -#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A) - -#define GPIO71_GPIO PIN_CFG(71, GPIO) -#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A) - -#define GPIO72_GPIO PIN_CFG(72, GPIO) -#define GPIO72_USB_STP PIN_CFG(72, ALT_A) - -#define GPIO73_GPIO PIN_CFG(73, GPIO) -#define GPIO73_USB_DIR PIN_CFG(73, ALT_A) - -#define GPIO74_GPIO PIN_CFG(74, GPIO) -#define GPIO74_USB_NXT PIN_CFG(74, ALT_A) - -#define GPIO75_GPIO PIN_CFG(75, GPIO) -#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A) - -#define GPIO76_GPIO PIN_CFG(76, GPIO) - -#define GPIO77_GPIO PIN_CFG(77, GPIO) -#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A) - -#define GPIO78_GPIO PIN_CFG(78, GPIO) -#define GPIO78_IRQn PIN_CFG(78, ALT_A) - -#define GPIO79_GPIO PIN_CFG(79, GPIO) -#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A) - -#define GPIO80_GPIO PIN_CFG(80, GPIO) -#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A) - -#define GPIO81_GPIO PIN_CFG(81, GPIO) -#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A) - -#define GPIO82_GPIO PIN_CFG(82, GPIO) -#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A) - -#define GPIO96_GPIO PIN_CFG(96, GPIO) -#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A) -#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B) -#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C) - -#define GPIO97_GPIO PIN_CFG(97, GPIO) -#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A) -#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B) -#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C) - -#define GPIO98_GPIO PIN_CFG(98, GPIO) -#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A) -#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B) -#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C) - -#define GPIO99_GPIO PIN_CFG(99, GPIO) -#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A) -#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B) -#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C) - -#define GPIO100_GPIO PIN_CFG(100, GPIO) -#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A) - -#define GPIO101_GPIO PIN_CFG(101, GPIO) -#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A) - -#define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_KP_I0 PIN_CFG(128, ALT_A) -#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B) - -#define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_KP_O0 PIN_CFG(129, ALT_A) -#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B) - -#define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_KP_I1 PIN_CFG(130, ALT_A) -#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B) - -#define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_KP_O1 PIN_CFG(131, ALT_A) -#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B) - -#define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_KP_I2 PIN_CFG(132, ALT_A) -#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B) -#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C) - -#define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_KP_O2 PIN_CFG(133, ALT_A) -#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B) -#define GPIO133_U0_RXD PIN_CFG(133, ALT_C) - -#define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_KP_I3 PIN_CFG(134, ALT_A) -#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B) -#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C) - -#define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_KP_O3 PIN_CFG(135, ALT_A) -#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B) -#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C) - -#define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_KP_I4 PIN_CFG(136, ALT_A) -#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B) -#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C) - -#define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_KP_O4 PIN_CFG(137, ALT_A) -#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B) -#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C) - -#define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_KP_I5 PIN_CFG(138, ALT_A) -#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B) -#define GPIO138_U0_TXD PIN_CFG(138, ALT_C) - -#define GPIO139_GPIO PIN_CFG(139, GPIO) -#define GPIO139_KP_O5 PIN_CFG(139, ALT_A) -#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B) -#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C) - -#define GPIO140_GPIO PIN_CFG(140, GPIO) -#define GPIO140_KP_I6 PIN_CFG(140, ALT_A) -#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B) -#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C) - -#define GPIO141_GPIO PIN_CFG(141, GPIO) -#define GPIO141_KP_O6 PIN_CFG(141, ALT_A) -#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B) -#define GPIO141_U0_RXD PIN_CFG(141, ALT_C) - -#define GPIO142_GPIO PIN_CFG(142, GPIO) -#define GPIO142_KP_I7 PIN_CFG(142, ALT_A) -#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B) -#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C) - -#define GPIO143_GPIO PIN_CFG(143, GPIO) -#define GPIO143_KP_O7 PIN_CFG(143, ALT_A) -#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B) -#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C) - -#define GPIO144_GPIO PIN_CFG(144, GPIO) -#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A) -#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B) -#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C) - -#define GPIO145_GPIO PIN_CFG(145, GPIO) -#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A) -#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B) -#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C) - -#define GPIO146_GPIO PIN_CFG(146, GPIO) -#define GPIO146_PWM_0 PIN_CFG(146, ALT_A) -#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B) - -#define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_PWM_1 PIN_CFG(147, ALT_A) -#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B) - -#define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_PWM_2 PIN_CFG(148, ALT_A) -#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B) - -#define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A) - -#define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A) - -#define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A) - -#define GPIO163_GPIO PIN_CFG(163, GPIO) - -#define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_GPS_START PIN_CFG(164, ALT_A) - -#define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A) -#define GPIO165_U3_RXD PIN_CFG(165, ALT_B) -#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C) - -#define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A) -#define GPIO166_U3_TXD PIN_CFG(166, ALT_B) -#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C) - -#define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A) -#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B) -#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C) - -#define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A) -#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B) -#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C) - -#define GPIO169_GPIO PIN_CFG(169, GPIO) -#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A) -#define GPIO169_DDR_RC PIN_CFG(169, ALT_B) -#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C) - -#define GPIO170_GPIO PIN_CFG(170, GPIO) -#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A) - -#define GPIO171_GPIO PIN_CFG(171, GPIO) -#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A) -#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B) -#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C) - -#define GPIO172_GPIO PIN_CFG(172, GPIO) -#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A) -#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B) -#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C) - -#define GPIO173_GPIO PIN_CFG(173, GPIO) -#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A) -#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B) -#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C) - -#define GPIO174_GPIO PIN_CFG(174, GPIO) -#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A) -#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B) -#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C) - -#define GPIO175_GPIO PIN_CFG(175, GPIO) -#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A) -#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B) -#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C) - -#define GPIO176_GPIO PIN_CFG(176, GPIO) -#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A) -#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B) - -#define GPIO177_GPIO PIN_CFG(177, GPIO) -#define GPIO177_U2_RXD PIN_CFG(177, ALT_A) -#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B) -#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C) - -#define GPIO178_GPIO PIN_CFG(178, GPIO) -#define GPIO178_U2_TXD PIN_CFG(178, ALT_A) -#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B) -#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C) - -#define GPIO179_GPIO PIN_CFG(179, GPIO) -#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A) -#define GPIO179_U3_RXD PIN_CFG(179, ALT_B) -#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C) - -#define GPIO180_GPIO PIN_CFG(180, GPIO) -#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A) -#define GPIO180_U3_TXD PIN_CFG(180, ALT_B) -#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C) - -#define GPIO185_GPIO PIN_CFG(185, GPIO) -#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A) -#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B) - -#define GPIO186_GPIO PIN_CFG(186, GPIO) -#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A) -#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B) - -#define GPIO187_GPIO PIN_CFG(187, GPIO) -#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A) -#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B) - -#define GPIO188_GPIO PIN_CFG(188, GPIO) -#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A) -#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B) - -#define GPIO189_GPIO PIN_CFG(189, GPIO) -#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A) -#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B) - -#define GPIO190_GPIO PIN_CFG(190, GPIO) -#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A) -#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B) - -#define GPIO191_GPIO PIN_CFG(191, GPIO) -#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A) -#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B) -#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C) - -#define GPIO192_GPIO PIN_CFG(192, GPIO) -#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A) -#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B) -#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C) - -#define GPIO193_GPIO PIN_CFG(193, GPIO) -#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A) -#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B) -#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C) - -#define GPIO194_GPIO PIN_CFG(194, GPIO) -#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A) -#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B) -#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C) - -#define GPIO195_GPIO PIN_CFG(195, GPIO) -#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A) -#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B) -#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C) - -#define GPIO196_GPIO PIN_CFG(196, GPIO) -#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A) -#define GPIO196_U0_RXD PIN_CFG(196, ALT_B) -#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C) - -#define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A) -#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B) - -#define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A) - -#define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A) -#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B) - -#define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_U1_TXD PIN_CFG(200, ALT_A) -#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B) - -#define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_U1_RXD PIN_CFG(201, ALT_A) -#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B) - -#define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A) -#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B) - -#define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A) -#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B) - -#define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A) -#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B) -#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C) - -#define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A) -#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B) -#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C) - -#define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A) -#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B) -#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C) - -#define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A) -#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B) -#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C) - -#define GPIO208_GPIO PIN_CFG(208, GPIO) -#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A) -#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B) -#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C) - -#define GPIO209_GPIO PIN_CFG(209, GPIO) -#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A) -#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B) -#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C) - -#define GPIO210_GPIO PIN_CFG(210, GPIO) -#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A) -#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B) - -#define GPIO211_GPIO PIN_CFG(211, GPIO) -#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A) -#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B) - -#define GPIO212_GPIO PIN_CFG(212, GPIO) -#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A) -#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B) - -#define GPIO213_GPIO PIN_CFG(213, GPIO) -#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A) -#define GPIO213_LCD_DE PIN_CFG(213, ALT_B) -#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C) - -#define GPIO214_GPIO PIN_CFG(214, GPIO) -#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A) -#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B) -#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C) - -#define GPIO215_GPIO PIN_CFG(215, GPIO) -#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A) -#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B) -#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C) - -#define GPIO216_GPIO PIN_CFG(216, GPIO) -#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A) -#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B) - -#define GPIO217_GPIO PIN_CFG(217, GPIO) -#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A) -#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B) -#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C) - -#define GPIO218_GPIO PIN_CFG(218, GPIO) -#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A) -#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B) - -#define GPIO219_GPIO PIN_CFG(219, GPIO) -#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A) -#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B) - -#define GPIO220_GPIO PIN_CFG(220, GPIO) -#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A) -#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B) - -#define GPIO221_GPIO PIN_CFG(221, GPIO) -#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A) -#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B) - -#define GPIO222_GPIO PIN_CFG(222, GPIO) -#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A) -#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B) - -#define GPIO223_GPIO PIN_CFG(223, GPIO) -#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A) -#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B) - -#define GPIO224_GPIO PIN_CFG(224, GPIO) -#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A) -#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B) - -#define GPIO225_GPIO PIN_CFG(225, GPIO) -#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A) -#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B) - -#define GPIO226_GPIO PIN_CFG(226, GPIO) -#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A) -#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B) - -#define GPIO227_GPIO PIN_CFG(227, GPIO) -#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A) -#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/pins-db8500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/pins-db8500.h deleted file mode 100644 index 8b1d1a7a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/pins-db8500.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - */ - -#ifndef __MACH_PINS_DB8500_H -#define __MACH_PINS_DB8500_H - -/* - * TODO: Eventually encode all non-board specific pull up/down configuration - * here. - */ - -#define GPIO0_GPIO PIN_CFG(0, GPIO) -#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) -#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) -#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) - -#define GPIO1_GPIO PIN_CFG(1, GPIO) -#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) -#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) -#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) - -#define GPIO2_GPIO PIN_CFG(2, GPIO) -#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) -#define GPIO2_NONE PIN_CFG(2, ALT_B) -#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) - -#define GPIO3_GPIO PIN_CFG(3, GPIO) -#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) -#define GPIO3_NONE PIN_CFG(3, ALT_B) -#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) - -#define GPIO4_GPIO PIN_CFG(4, GPIO) -#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) -#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP) -#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) - -#define GPIO5_GPIO PIN_CFG(5, GPIO) -#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) -#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP) -#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) - -#define GPIO6_GPIO PIN_CFG(6, GPIO) -#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) -#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP) -#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) - -#define GPIO7_GPIO PIN_CFG(7, GPIO) -#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) -#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP) -#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) - -#define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP) -#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP) - -#define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP) -#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP) - -#define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP) -#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP) -#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) - -#define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP) -#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP) -#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) - -#define GPIO12_GPIO PIN_CFG(12, GPIO) -#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) -#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) - -#define GPIO13_GPIO PIN_CFG(13, GPIO) -#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) - -#define GPIO14_GPIO PIN_CFG(14, GPIO) -#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) - -#define GPIO15_GPIO PIN_CFG(15, GPIO) -#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) -#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) - -#define GPIO16_GPIO PIN_CFG(16, GPIO) -#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) -#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP) -#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) - -#define GPIO17_GPIO PIN_CFG(17, GPIO) -#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) -#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP) -#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) - -#define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_MC0_CMDDIR PIN_CFG_INPUT(18, ALT_A, PULLUP) -#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) -#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) - -#define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC0_DAT0DIR PIN_CFG_INPUT(19, ALT_A, PULLUP) -#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) -#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) - -#define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC0_DAT2DIR PIN_CFG_INPUT(20, ALT_A, PULLUP) -#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) -#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) - -#define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC0_DAT31DIR PIN_CFG_INPUT(21, ALT_A, PULLUP) -#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) -#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) - -#define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC0_FBCLK PIN_CFG_INPUT(22, ALT_A, PULLUP) -#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) -#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) - -#define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC0_CLK PIN_CFG_INPUT(23, ALT_A, PULLUP) -#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) -#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) - -#define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC0_CMD PIN_CFG_INPUT(24, ALT_A, PULLUP) -#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) -#define GPIO24_MS_BS PIN_CFG(24, ALT_C) - -#define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC0_DAT0 PIN_CFG_INPUT(25, ALT_A, PULLUP) -#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) -#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) - -#define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC0_DAT1 PIN_CFG_INPUT(26, ALT_A, PULLUP) -#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) -#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) - -#define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_MC0_DAT2 PIN_CFG_INPUT(27, ALT_A, PULLUP) -#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) -#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) - -#define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_MC0_DAT3 PIN_CFG_INPUT(28, ALT_A, PULLUP) -#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) -#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) - -#define GPIO29_GPIO PIN_CFG(29, GPIO) -#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) -#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) -#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) - -#define GPIO30_GPIO PIN_CFG(30, GPIO) -#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) -#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) -#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) - -#define GPIO31_GPIO PIN_CFG(31, GPIO) -#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) -#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) -#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) - -#define GPIO32_GPIO PIN_CFG(32, GPIO) -#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) -#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) -#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) - -#define GPIO33_GPIO PIN_CFG(33, GPIO) -#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) -#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) -#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) - -#define GPIO34_GPIO PIN_CFG(34, GPIO) -#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) -#define GPIO34_NONE PIN_CFG(34, ALT_B) -#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) - -#define GPIO35_GPIO PIN_CFG(35, GPIO) -#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) -#define GPIO35_NONE PIN_CFG(35, ALT_B) -#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) - -#define GPIO36_GPIO PIN_CFG(36, GPIO) -#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) -#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) -#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) - -#define GPIO64_GPIO PIN_CFG(64, GPIO) -#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) -#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) -#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) - -#define GPIO65_GPIO PIN_CFG(65, GPIO) -#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) -#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) -#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) - -#define GPIO66_GPIO PIN_CFG(66, GPIO) -#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) -#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) -#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) - -#define GPIO67_GPIO PIN_CFG(67, GPIO) -#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) -#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) -#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) - -#define GPIO68_GPIO PIN_CFG(68, GPIO) -#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) -#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) -#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) - -#define GPIO69_GPIO PIN_CFG(69, GPIO) -#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) -#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) -#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) - -#define GPIO70_GPIO PIN_CFG(70, GPIO) -#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) -#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) -#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) - -#define GPIO71_GPIO PIN_CFG(71, GPIO) -#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) -#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) -#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) - -#define GPIO72_GPIO PIN_CFG(72, GPIO) -#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) -#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) -#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) - -#define GPIO73_GPIO PIN_CFG(73, GPIO) -#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) -#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) -#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) - -#define GPIO74_GPIO PIN_CFG(74, GPIO) -#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) -#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) -#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) - -#define GPIO75_GPIO PIN_CFG(75, GPIO) -#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) -#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) -#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) - -#define GPIO76_GPIO PIN_CFG(76, GPIO) -#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) -#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) -#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) - -#define GPIO77_GPIO PIN_CFG(77, GPIO) -#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) -#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) -#define GPIO77_NONE PIN_CFG(77, ALT_C) - -#define GPIO78_GPIO PIN_CFG(78, GPIO) -#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) -#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) -#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) - -#define GPIO79_GPIO PIN_CFG(79, GPIO) -#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) -#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) -#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) - -#define GPIO80_GPIO PIN_CFG(80, GPIO) -#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) -#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) -#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) - -#define GPIO81_GPIO PIN_CFG(81, GPIO) -#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) -#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) -#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) - -#define GPIO82_GPIO PIN_CFG(82, GPIO) -#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) -#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) - -#define GPIO83_GPIO PIN_CFG(83, GPIO) -#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) -#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) - -#define GPIO84_GPIO PIN_CFG(84, GPIO) -#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) -#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) - -#define GPIO85_GPIO PIN_CFG(85, GPIO) -#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) -#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) - -#define GPIO86_GPIO PIN_CFG(86, GPIO) -#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) -#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) -#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) - -#define GPIO87_GPIO PIN_CFG(87, GPIO) -#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) -#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) -#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) - -#define GPIO88_GPIO PIN_CFG(88, GPIO) -#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) -#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) -#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) - -#define GPIO89_GPIO PIN_CFG(89, GPIO) -#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) -#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) -#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) - -#define GPIO90_GPIO PIN_CFG(90, GPIO) -#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) -#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) -#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) - -#define GPIO91_GPIO PIN_CFG(91, GPIO) -#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) -#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) -#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) - -#define GPIO92_GPIO PIN_CFG(92, GPIO) -#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) -#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) -#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) - -#define GPIO93_GPIO PIN_CFG(93, GPIO) -#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) -#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) -#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) - -#define GPIO94_GPIO PIN_CFG(94, GPIO) -#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) -#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) -#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) - -#define GPIO95_GPIO PIN_CFG(95, GPIO) -#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) -#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) -#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) - -#define GPIO96_GPIO PIN_CFG(96, GPIO) -#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) -#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) -#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) - -#define GPIO97_GPIO PIN_CFG(97, GPIO) -#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) -#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) -#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) - -#define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_MC2_CLK PIN_CFG_INPUT(128, ALT_A, PULLUP) -#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) - -#define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_MC2_CMD PIN_CFG_INPUT(129, ALT_A, PULLUP) -#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) - -#define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_MC2_FBCLK PIN_CFG_INPUT(130, ALT_A, PULLUP) -#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) -#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) - -#define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_MC2_DAT0 PIN_CFG_INPUT(131, ALT_A, PULLUP) -#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) - -#define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_MC2_DAT1 PIN_CFG_INPUT(132, ALT_A, PULLUP) -#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) - -#define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_MC2_DAT2 PIN_CFG_INPUT(133, ALT_A, PULLUP) -#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) - -#define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_MC2_DAT3 PIN_CFG_INPUT(134, ALT_A, PULLUP) -#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) - -#define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_MC2_DAT4 PIN_CFG_INPUT(135, ALT_A, PULLUP) -#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) - -#define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_MC2_DAT5 PIN_CFG_INPUT(136, ALT_A, PULLUP) -#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) - -#define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_MC2_DAT6 PIN_CFG_INPUT(137, ALT_A, PULLUP) -#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) - -#define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_MC2_DAT7 PIN_CFG_INPUT(138, ALT_A, PULLUP) -#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) - -#define GPIO139_GPIO PIN_CFG(139, GPIO) -#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) -#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) -#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) - -#define GPIO140_GPIO PIN_CFG(140, GPIO) -#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) -#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) -#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) - -#define GPIO141_GPIO PIN_CFG(141, GPIO) -#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) -#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) -#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) - -#define GPIO142_GPIO PIN_CFG(142, GPIO) -#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) -#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) -#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) - -#define GPIO143_GPIO PIN_CFG(143, GPIO) -#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) - -#define GPIO144_GPIO PIN_CFG(144, GPIO) -#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) - -#define GPIO145_GPIO PIN_CFG(145, GPIO) -#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) - -#define GPIO146_GPIO PIN_CFG(146, GPIO) -#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) - -#define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP) - -#define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP) - -#define GPIO149_GPIO PIN_CFG(149, GPIO) -#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) -#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) -#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) - -#define GPIO150_GPIO PIN_CFG(150, GPIO) -#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) -#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) - -#define GPIO151_GPIO PIN_CFG(151, GPIO) -#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) -#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) -#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) - -#define GPIO152_GPIO PIN_CFG(152, GPIO) -#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) -#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) -#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) - -#define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN) -#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) -#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) - -#define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN) -#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) -#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) - -#define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN) -#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) -#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) - -#define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN) -#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) -#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) - -#define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP) -#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) -#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) - -#define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP) -#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) -#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) - -#define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP) -#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) -#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) - -#define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP) -#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) -#define GPIO160_NONE PIN_CFG(160, ALT_C) - -#define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN) -#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) -#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) - -#define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN) -#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) -#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) - -#define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN) -#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) -#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) - -#define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP) -#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) -#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) - -#define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP) -#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) -#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) - -#define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP) -#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) -#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) - -#define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP) -#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) -#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) - -#define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP) -#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) -#define GPIO168_NONE PIN_CFG(168, ALT_C) - -#define GPIO169_GPIO PIN_CFG(169, GPIO) -#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) -#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) -#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) - -#define GPIO170_GPIO PIN_CFG(170, GPIO) -#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) -#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) -#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) - -#define GPIO171_GPIO PIN_CFG(171, GPIO) -#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) -#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) -#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) - -#define GPIO192_GPIO PIN_CFG(192, GPIO) -#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) - -#define GPIO193_GPIO PIN_CFG(193, GPIO) -#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) - -#define GPIO194_GPIO PIN_CFG(194, GPIO) -#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) - -#define GPIO195_GPIO PIN_CFG(195, GPIO) -#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) - -#define GPIO196_GPIO PIN_CFG(196, GPIO) -#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) - -#define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC4_DAT3 PIN_CFG_INPUT(197, ALT_A, PULLUP) - -#define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC4_DAT2 PIN_CFG_INPUT(198, ALT_A, PULLUP) - -#define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC4_DAT1 PIN_CFG_INPUT(199, ALT_A, PULLUP) - -#define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_MC4_DAT0 PIN_CFG_INPUT(200, ALT_A, PULLUP) - -#define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_MC4_CMD PIN_CFG_INPUT(201, ALT_A, PULLUP) - -#define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_MC4_FBCLK PIN_CFG_INPUT(202, ALT_A, PULLUP) -#define GPIO202_PWL PIN_CFG(202, ALT_B) -#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) - -#define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_MC4_CLK PIN_CFG_INPUT(203, ALT_A, PULLUP) - -#define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_MC4_DAT7 PIN_CFG_INPUT(204, ALT_A, PULLUP) - -#define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_MC4_DAT6 PIN_CFG_INPUT(205, ALT_A, PULLUP) - -#define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_MC4_DAT5 PIN_CFG_INPUT(206, ALT_A, PULLUP) - -#define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_MC4_DAT4 PIN_CFG_INPUT(207, ALT_A, PULLUP) - -#define GPIO208_GPIO PIN_CFG(208, GPIO) -#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) - -#define GPIO209_GPIO PIN_CFG(209, GPIO) -#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) -#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) - -#define GPIO210_GPIO PIN_CFG(210, GPIO) -#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) - -#define GPIO211_GPIO PIN_CFG(211, GPIO) -#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) - -#define GPIO212_GPIO PIN_CFG(212, GPIO) -#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) -#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) - -#define GPIO213_GPIO PIN_CFG(213, GPIO) -#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) -#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) - -#define GPIO214_GPIO PIN_CFG(214, GPIO) -#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) -#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) - -#define GPIO215_GPIO PIN_CFG(215, GPIO) -#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) -#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) -#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) -#define GPIO215_SPI2_TXD PIN_CFG(215, ALT_C) - -#define GPIO216_GPIO PIN_CFG(216, GPIO) -#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) -#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) -#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP) -#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C) - -#define GPIO217_GPIO PIN_CFG(217, GPIO) -#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) -#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) -#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) -#define GPIO217_SPI2_CLK PIN_CFG(217, ALT_C) - -#define GPIO218_GPIO PIN_CFG(218, GPIO) -#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) -#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) -#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP) -#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C) - -#define GPIO219_GPIO PIN_CFG(219, GPIO) -#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) -#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) - -#define GPIO220_GPIO PIN_CFG(220, GPIO) -#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) -#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) -#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) - -#define GPIO221_GPIO PIN_CFG(221, GPIO) -#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) -#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) - -#define GPIO222_GPIO PIN_CFG(222, GPIO) -#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) -#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) - -#define GPIO223_GPIO PIN_CFG(223, GPIO) -#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) -#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) -#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) - -#define GPIO224_GPIO PIN_CFG(224, GPIO) -#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) -#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) -#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) - -#define GPIO225_GPIO PIN_CFG(225, GPIO) -#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) -#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) -#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) - -#define GPIO226_GPIO PIN_CFG(226, GPIO) -#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) -#define GPIO226_PWL PIN_CFG(226, ALT_B) -#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) - -#define GPIO227_GPIO PIN_CFG(227, GPIO) -#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) - -#define GPIO228_GPIO PIN_CFG(228, GPIO) -#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) - -#define GPIO229_GPIO PIN_CFG(229, GPIO) -#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) -#define GPIO229_PWL PIN_CFG(229, ALT_B) -#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP) - -#define GPIO230_GPIO PIN_CFG(230, GPIO) -#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) -#define GPIO230_PWL PIN_CFG(230, ALT_B) -#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP) - -#define GPIO256_GPIO PIN_CFG(256, GPIO) -#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) - -#define GPIO257_GPIO PIN_CFG(257, GPIO) -#define GPIO257_USB_STP PIN_CFG(257, ALT_A) - -#define GPIO258_GPIO PIN_CFG(258, GPIO) -#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) -#define GPIO258_NONE PIN_CFG(258, ALT_B) -#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) - -#define GPIO259_GPIO PIN_CFG(259, GPIO) -#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) - -#define GPIO260_GPIO PIN_CFG(260, GPIO) -#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) - -#define GPIO261_GPIO PIN_CFG(261, GPIO) -#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) - -#define GPIO262_GPIO PIN_CFG(262, GPIO) -#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) - -#define GPIO263_GPIO PIN_CFG(263, GPIO) -#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) - -#define GPIO264_GPIO PIN_CFG(264, GPIO) -#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) - -#define GPIO265_GPIO PIN_CFG(265, GPIO) -#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) - -#define GPIO266_GPIO PIN_CFG(266, GPIO) -#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) - -#define GPIO267_GPIO PIN_CFG(267, GPIO) -#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/platsmp.c b/ANDROID_3.4.5/arch/arm/mach-ux500/platsmp.c deleted file mode 100644 index eff5842f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/platsmp.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2002 ARM Ltd. - * Copyright (C) 2008 STMicroelctronics. - * Copyright (C) 2009 ST-Ericsson. - * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> - * - * This file is based on arm realview platform - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/smp.h> -#include <linux/io.h> - -#include <asm/cacheflush.h> -#include <asm/hardware/gic.h> -#include <asm/smp_plat.h> -#include <asm/smp_scu.h> -#include <mach/hardware.h> -#include <mach/setup.h> - -/* This is called from headsmp.S to wakeup the secondary core */ -extern void u8500_secondary_startup(void); - -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int pen_release = -1; - -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static void __iomem *scu_base_addr(void) -{ - if (cpu_is_u5500()) - return __io_address(U5500_SCU_BASE); - else if (cpu_is_u8500()) - return __io_address(U8500_SCU_BASE); - else - ux500_unknown_soc(); - - return NULL; -} - -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - */ - write_pen_release(cpu_logical_map(cpu)); - - smp_send_reschedule(cpu); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - if (pen_release == -1) - break; - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -static void __init wakeup_secondary(void) -{ - void __iomem *backupram; - - if (cpu_is_u5500()) - backupram = __io_address(U5500_BACKUPRAM0_BASE); - else if (cpu_is_u8500()) - backupram = __io_address(U8500_BACKUPRAM0_BASE); - else - ux500_unknown_soc(); - - /* - * write the address of secondary startup into the backup ram register - * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the - * backup ram register at offset 0x1FF0, which is what boot rom code - * is waiting for. This would wake up the secondary core from WFE - */ -#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 - __raw_writel(virt_to_phys(u8500_secondary_startup), - backupram + UX500_CPU1_JUMPADDR_OFFSET); - -#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 - __raw_writel(0xA1FEED01, - backupram + UX500_CPU1_WAKEMAGIC_OFFSET); - - /* make sure write buffer is drained */ - mb(); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -void __init smp_init_cpus(void) -{ - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - - /* sanity check */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); -} - -void __init platform_smp_prepare_cpus(unsigned int max_cpus) -{ - - scu_enable(scu_base_addr()); - wakeup_secondary(); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/ste-dma40-db5500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/ste-dma40-db5500.h deleted file mode 100644 index cb2110c3..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/ste-dma40-db5500.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - * - * DB5500-SoC-specific configuration for DMA40 - */ - -#ifndef STE_DMA40_DB5500_H -#define STE_DMA40_DB5500_H - -#define DB5500_DMA_NR_DEV 64 - -enum dma_src_dev_type { - DB5500_DMA_DEV0_SPI0_RX = 0, - DB5500_DMA_DEV1_SPI1_RX = 1, - DB5500_DMA_DEV2_SPI2_RX = 2, - DB5500_DMA_DEV3_SPI3_RX = 3, - DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4, - DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5, - DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6, - DB5500_DMA_DEV7_IRDA_RFS = 7, - DB5500_DMA_DEV8_IRDA_FIFO_RX = 8, - DB5500_DMA_DEV9_MSP0_RX = 9, - DB5500_DMA_DEV10_MSP1_RX = 10, - DB5500_DMA_DEV11_MSP2_RX = 11, - DB5500_DMA_DEV12_UART0_RX = 12, - DB5500_DMA_DEV13_UART1_RX = 13, - DB5500_DMA_DEV14_UART2_RX = 14, - DB5500_DMA_DEV15_UART3_RX = 15, - DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16, - DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17, - DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18, - DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19, - DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20, - DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21, - DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22, - DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23, - DB5500_DMA_DEV24_SDMMC0_RX = 24, - DB5500_DMA_DEV25_SDMMC1_RX = 25, - DB5500_DMA_DEV26_SDMMC2_RX = 26, - DB5500_DMA_DEV27_SDMMC3_RX = 27, - DB5500_DMA_DEV28_SDMMC4_RX = 28, - /* 29 - 32 not used */ - DB5500_DMA_DEV33_SDMMC0_RX = 33, - DB5500_DMA_DEV34_SDMMC1_RX = 34, - DB5500_DMA_DEV35_SDMMC2_RX = 35, - DB5500_DMA_DEV36_SDMMC3_RX = 36, - DB5500_DMA_DEV37_SDMMC4_RX = 37, - DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38, - DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39, - DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40, - DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41, - DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42, - DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43, - DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44, - DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45, - /* 46 not used */ - DB5500_DMA_DEV47_MCDE_RX = 47, - DB5500_DMA_DEV48_CRYPTO1_RX = 48, - /* 49, 50 not used */ - DB5500_DMA_DEV49_I2C1_RX = 51, - DB5500_DMA_DEV50_I2C3_RX = 52, - DB5500_DMA_DEV51_I2C2_RX = 53, - /* 54 - 60 not used */ - DB5500_DMA_DEV61_CRYPTO0_RX = 61, - /* 62, 63 not used */ -}; - -enum dma_dest_dev_type { - DB5500_DMA_DEV0_SPI0_TX = 0, - DB5500_DMA_DEV1_SPI1_TX = 1, - DB5500_DMA_DEV2_SPI2_TX = 2, - DB5500_DMA_DEV3_SPI3_TX = 3, - DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4, - DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5, - DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6, - DB5500_DMA_DEV7_IRRC_TX = 7, - DB5500_DMA_DEV8_IRDA_FIFO_TX = 8, - DB5500_DMA_DEV9_MSP0_TX = 9, - DB5500_DMA_DEV10_MSP1_TX = 10, - DB5500_DMA_DEV11_MSP2_TX = 11, - DB5500_DMA_DEV12_UART0_TX = 12, - DB5500_DMA_DEV13_UART1_TX = 13, - DB5500_DMA_DEV14_UART2_TX = 14, - DB5500_DMA_DEV15_UART3_TX = 15, - DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16, - DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17, - DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18, - DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19, - DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20, - DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21, - DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22, - DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23, - DB5500_DMA_DEV24_SDMMC0_TX = 24, - DB5500_DMA_DEV25_SDMMC1_TX = 25, - DB5500_DMA_DEV26_SDMMC2_TX = 26, - DB5500_DMA_DEV27_SDMMC3_TX = 27, - DB5500_DMA_DEV28_SDMMC4_TX = 28, - /* 29 - 31 not used */ - DB5500_DMA_DEV32_FSMC_TX = 32, - DB5500_DMA_DEV33_SDMMC0_TX = 33, - DB5500_DMA_DEV34_SDMMC1_TX = 34, - DB5500_DMA_DEV35_SDMMC2_TX = 35, - DB5500_DMA_DEV36_SDMMC3_TX = 36, - DB5500_DMA_DEV37_SDMMC4_TX = 37, - DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38, - DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39, - DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40, - DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41, - DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42, - DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43, - DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44, - DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45, - /* 46 not used */ - DB5500_DMA_DEV47_STM_TX = 47, - DB5500_DMA_DEV48_CRYPTO1_TX = 48, - DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49, - DB5500_DMA_DEV50_HASH1_TX = 50, - DB5500_DMA_DEV51_I2C1_TX = 51, - DB5500_DMA_DEV52_I2C3_TX = 52, - DB5500_DMA_DEV53_I2C2_TX = 53, - /* 54, 55 not used */ - DB5500_DMA_MEMCPY_TX_1 = 56, - DB5500_DMA_MEMCPY_TX_2 = 57, - DB5500_DMA_MEMCPY_TX_3 = 58, - DB5500_DMA_MEMCPY_TX_4 = 59, - DB5500_DMA_MEMCPY_TX_5 = 60, - DB5500_DMA_DEV61_CRYPTO0_TX = 61, - DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62, - DB5500_DMA_DEV63_HASH0_TX = 63, -}; - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/ste-dma40-db8500.h b/ANDROID_3.4.5/arch/arm/mach-ux500/ste-dma40-db8500.h deleted file mode 100644 index a616419b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/ste-dma40-db8500.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * arch/arm/mach-ux500/ste_dma40_db8500.h - * DB8500-SoC-specific configuration for DMA40 - * - * Copyright (C) ST-Ericsson 2007-2010 - * License terms: GNU General Public License (GPL) version 2 - * Author: Per Friden <per.friden@stericsson.com> - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> - */ -#ifndef STE_DMA40_DB8500_H -#define STE_DMA40_DB8500_H - -#define DB8500_DMA_NR_DEV 64 - -enum dma_src_dev_type { - DB8500_DMA_DEV0_SPI0_RX = 0, - DB8500_DMA_DEV1_SD_MMC0_RX = 1, - DB8500_DMA_DEV2_SD_MMC1_RX = 2, - DB8500_DMA_DEV3_SD_MMC2_RX = 3, - DB8500_DMA_DEV4_I2C1_RX = 4, - DB8500_DMA_DEV5_I2C3_RX = 5, - DB8500_DMA_DEV6_I2C2_RX = 6, - DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */ - DB8500_DMA_DEV8_SSP0_RX = 8, - DB8500_DMA_DEV9_SSP1_RX = 9, - DB8500_DMA_DEV10_MCDE_RX = 10, - DB8500_DMA_DEV11_UART2_RX = 11, - DB8500_DMA_DEV12_UART1_RX = 12, - DB8500_DMA_DEV13_UART0_RX = 13, - DB8500_DMA_DEV14_MSP2_RX = 14, - DB8500_DMA_DEV15_I2C0_RX = 15, - DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16, - DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17, - DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18, - DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19, - DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20, - DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21, - DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22, - DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23, - DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24, - DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25, - DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26, - DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27, - DB8500_DMA_DEV28_SD_MM2_RX = 28, - DB8500_DMA_DEV29_SD_MM0_RX = 29, - DB8500_DMA_DEV30_MSP1_RX = 30, - /* On DB8500v2, MSP3 RX replaces MSP1 RX */ - DB8500_DMA_DEV30_MSP3_RX = 30, - DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31, - DB8500_DMA_DEV32_SD_MM1_RX = 32, - DB8500_DMA_DEV33_SPI2_RX = 33, - DB8500_DMA_DEV34_I2C3_RX2 = 34, - DB8500_DMA_DEV35_SPI1_RX = 35, - DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36, - DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37, - DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38, - DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39, - DB8500_DMA_DEV40_SPI3_RX = 40, - DB8500_DMA_DEV41_SD_MM3_RX = 41, - DB8500_DMA_DEV42_SD_MM4_RX = 42, - DB8500_DMA_DEV43_SD_MM5_RX = 43, - DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44, - DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45, - DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46, - DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47, - DB8500_DMA_DEV48_CAC1_RX = 48, - /* 49, 50 and 51 are not used */ - DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52, - DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53, - DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54, - DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55, - /* 56, 57, 58, 59 and 60 are not used */ - DB8500_DMA_DEV61_CAC0_RX = 61, - /* 62 and 63 are not used */ -}; - -enum dma_dest_dev_type { - DB8500_DMA_DEV0_SPI0_TX = 0, - DB8500_DMA_DEV1_SD_MMC0_TX = 1, - DB8500_DMA_DEV2_SD_MMC1_TX = 2, - DB8500_DMA_DEV3_SD_MMC2_TX = 3, - DB8500_DMA_DEV4_I2C1_TX = 4, - DB8500_DMA_DEV5_I2C3_TX = 5, - DB8500_DMA_DEV6_I2C2_TX = 6, - DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */ - DB8500_DMA_DEV8_SSP0_TX = 8, - DB8500_DMA_DEV9_SSP1_TX = 9, - /* 10 is not used*/ - DB8500_DMA_DEV11_UART2_TX = 11, - DB8500_DMA_DEV12_UART1_TX = 12, - DB8500_DMA_DEV13_UART0_TX = 13, - DB8500_DMA_DEV14_MSP2_TX = 14, - DB8500_DMA_DEV15_I2C0_TX = 15, - DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16, - DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17, - DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18, - DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19, - DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20, - DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21, - DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22, - DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23, - DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24, - DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25, - DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26, - DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27, - DB8500_DMA_DEV28_SD_MM2_TX = 28, - DB8500_DMA_DEV29_SD_MM0_TX = 29, - DB8500_DMA_DEV30_MSP1_TX = 30, - DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31, - DB8500_DMA_DEV32_SD_MM1_TX = 32, - DB8500_DMA_DEV33_SPI2_TX = 33, - DB8500_DMA_DEV34_I2C3_TX2 = 34, - DB8500_DMA_DEV35_SPI1_TX = 35, - DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36, - DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37, - DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38, - DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39, - DB8500_DMA_DEV40_SPI3_TX = 40, - DB8500_DMA_DEV41_SD_MM3_TX = 41, - DB8500_DMA_DEV42_SD_MM4_TX = 42, - DB8500_DMA_DEV43_SD_MM5_TX = 43, - DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44, - DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45, - DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46, - DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47, - DB8500_DMA_DEV48_CAC1_TX = 48, - DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, - DB8500_DMA_DEV50_HAC1_TX = 50, - DB8500_DMA_MEMCPY_TX_0 = 51, - DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52, - DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53, - DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54, - DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55, - DB8500_DMA_MEMCPY_TX_1 = 56, - DB8500_DMA_MEMCPY_TX_2 = 57, - DB8500_DMA_MEMCPY_TX_3 = 58, - DB8500_DMA_MEMCPY_TX_4 = 59, - DB8500_DMA_MEMCPY_TX_5 = 60, - DB8500_DMA_DEV61_CAC0_TX = 61, - DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, - DB8500_DMA_DEV63_HAC0_TX = 63, -}; - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/timer.c b/ANDROID_3.4.5/arch/arm/mach-ux500/timer.c deleted file mode 100644 index d37df98b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/timer.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2011 - * - * License Terms: GNU General Public License v2 - * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson - */ -#include <linux/io.h> -#include <linux/errno.h> -#include <linux/clksrc-dbx500-prcmu.h> -#include <linux/of.h> - -#include <asm/smp_twd.h> - -#include <plat/mtu.h> - -#include <mach/setup.h> -#include <mach/hardware.h> -#include <mach/irqs.h> - -#ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer, - U5500_TWD_BASE, IRQ_LOCALTIMER); -static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, - U8500_TWD_BASE, IRQ_LOCALTIMER); - -static void __init ux500_twd_init(void) -{ - struct twd_local_timer *twd_local_timer; - int err; - - twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer : - &u8500_twd_local_timer; - - if (of_have_populated_dt()) - twd_local_timer_of_register(); - else { - err = twd_local_timer_register(twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); - } -} -#else -#define ux500_twd_init() do { } while(0) -#endif - -static void __init ux500_timer_init(void) -{ - void __iomem *mtu_timer_base; - void __iomem *prcmu_timer_base; - - if (cpu_is_u5500()) { - mtu_timer_base = __io_address(U5500_MTU0_BASE); - prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); - } else if (cpu_is_u8500()) { - mtu_timer_base = __io_address(U8500_MTU0_BASE); - prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); - } else { - ux500_unknown_soc(); - } - - /* - * Here we register the timerblocks active in the system. - * Localtimers (twd) is started when both cpu is up and running. - * MTU register a clocksource, clockevent and sched_clock. - * Since the MTU is located in the VAPE power domain - * it will be cleared in sleep which makes it unsuitable. - * We however need it as a timer tick (clockevent) - * during boot to calibrate delay until twd is started. - * RTC-RTT have problems as timer tick during boot since it is - * depending on delay which is not yet calibrated. RTC-RTT is in the - * always-on powerdomain and is used as clockevent instead of twd when - * sleeping. - * The PRCMU timer 4(3 for DB5500) register a clocksource and - * sched_clock with higher rating then MTU since is always-on. - * - */ - - nmdk_timer_init(mtu_timer_base); - clksrc_dbx500_prcmu_init(prcmu_timer_base); - ux500_twd_init(); -} - -static void ux500_timer_reset(void) -{ - nmdk_clkevt_reset(); - nmdk_clksrc_reset(); -} - -struct sys_timer ux500_timer = { - .init = ux500_timer_init, - .resume = ux500_timer_reset, -}; diff --git a/ANDROID_3.4.5/arch/arm/mach-ux500/usb.c b/ANDROID_3.4.5/arch/arm/mach-ux500/usb.c deleted file mode 100644 index a74af389..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-ux500/usb.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2011 - * - * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ -#include <linux/platform_device.h> -#include <linux/usb/musb.h> -#include <linux/dma-mapping.h> - -#include <plat/ste_dma40.h> -#include <mach/hardware.h> -#include <mach/usb.h> - -#define MUSB_DMA40_RX_CH { \ - .mode = STEDMA40_MODE_LOGICAL, \ - .dir = STEDMA40_PERIPH_TO_MEM, \ - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \ - .src_info.data_width = STEDMA40_WORD_WIDTH, \ - .dst_info.data_width = STEDMA40_WORD_WIDTH, \ - .src_info.psize = STEDMA40_PSIZE_LOG_16, \ - .dst_info.psize = STEDMA40_PSIZE_LOG_16, \ - } - -#define MUSB_DMA40_TX_CH { \ - .mode = STEDMA40_MODE_LOGICAL, \ - .dir = STEDMA40_MEM_TO_PERIPH, \ - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \ - .src_info.data_width = STEDMA40_WORD_WIDTH, \ - .dst_info.data_width = STEDMA40_WORD_WIDTH, \ - .src_info.psize = STEDMA40_PSIZE_LOG_16, \ - .dst_info.psize = STEDMA40_PSIZE_LOG_16, \ - } - -static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS] - = { - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH, - MUSB_DMA40_RX_CH -}; - -static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS] - = { - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, - MUSB_DMA40_TX_CH, -}; - -static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = { - &musb_dma_rx_ch[0], - &musb_dma_rx_ch[1], - &musb_dma_rx_ch[2], - &musb_dma_rx_ch[3], - &musb_dma_rx_ch[4], - &musb_dma_rx_ch[5], - &musb_dma_rx_ch[6], - &musb_dma_rx_ch[7] -}; - -static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = { - &musb_dma_tx_ch[0], - &musb_dma_tx_ch[1], - &musb_dma_tx_ch[2], - &musb_dma_tx_ch[3], - &musb_dma_tx_ch[4], - &musb_dma_tx_ch[5], - &musb_dma_tx_ch[6], - &musb_dma_tx_ch[7] -}; - -static struct ux500_musb_board_data musb_board_data = { - .dma_rx_param_array = ux500_dma_rx_param_array, - .dma_tx_param_array = ux500_dma_tx_param_array, - .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS, - .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS, - .dma_filter = stedma40_filter, -}; - -static u64 ux500_musb_dmamask = DMA_BIT_MASK(32); - -static struct musb_hdrc_config musb_hdrc_config = { - .multipoint = true, - .dyn_fifo = true, - .num_eps = 16, - .ram_bits = 16, -}; - -static struct musb_hdrc_platform_data musb_platform_data = { - .mode = MUSB_OTG, - .config = &musb_hdrc_config, - .board_data = &musb_board_data, -}; - -static struct resource usb_resources[] = { - [0] = { - .name = "usb-mem", - .flags = IORESOURCE_MEM, - }, - - [1] = { - .name = "mc", /* hard-coded in musb */ - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device ux500_musb_device = { - .name = "musb-ux500", - .id = 0, - .dev = { - .platform_data = &musb_platform_data, - .dma_mask = &ux500_musb_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(usb_resources), - .resource = usb_resources, -}; - -static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type) -{ - u32 idx; - - for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++) - musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx]; -} - -static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type) -{ - u32 idx; - - for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++) - musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx]; -} - -void ux500_add_usb(struct device *parent, resource_size_t base, int irq, - int *dma_rx_cfg, int *dma_tx_cfg) -{ - ux500_musb_device.resource[0].start = base; - ux500_musb_device.resource[0].end = base + SZ_64K - 1; - ux500_musb_device.resource[1].start = irq; - ux500_musb_device.resource[1].end = irq; - - ux500_usb_dma_update_rx_ch_config(dma_rx_cfg); - ux500_usb_dma_update_tx_ch_config(dma_tx_cfg); - - ux500_musb_device.dev.parent = parent; - - platform_device_register(&ux500_musb_device); -} |