diff options
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-s3c64xx')
56 files changed, 0 insertions, 9611 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Kconfig b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Kconfig deleted file mode 100644 index 82c09157..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Kconfig +++ /dev/null @@ -1,309 +0,0 @@ -# Copyright 2008 Openmoko, Inc. -# Simtec Electronics, Ben Dooks <ben@simtec.co.uk> -# -# Licensed under GPLv2 - -# temporary until we can eliminate all drivers using it. -config PLAT_S3C64XX - bool - depends on ARCH_S3C64XX - select SAMSUNG_WAKEMASK - select PM_GENERIC_DOMAINS - default y - help - Base platform code for any Samsung S3C64XX device - - -# Configuration options for the S3C6410 CPU - -config CPU_S3C6400 - bool - help - Enable S3C6400 CPU support - -config CPU_S3C6410 - bool - help - Enable S3C6410 CPU support - -config S3C64XX_DMA - bool "S3C64XX DMA" - select S3C_DMA - -config S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_SDHCI_GPIO - bool - help - Internal configuration for default SDHCI setup for S3C6400 and - S3C6410 SoCs. - -config S3C64XX_DEV_ONENAND1 - bool - help - Compile in platform device definition for OneNAND1 controller - -# platform specific device setup - -config S3C64XX_SETUP_I2C0 - bool - default y - help - Common setup code for i2c bus 0. - - Note, currently since i2c0 is always compiled, this setup helper - is always compiled with it. - -config S3C64XX_SETUP_I2C1 - bool - help - Common setup code for i2c bus 1. - -config S3C64XX_SETUP_IDE - bool - help - Common setup code for S3C64XX IDE. - -config S3C64XX_SETUP_FB_24BPP - bool - help - Common setup code for S3C64XX with an 24bpp RGB display helper. - -config S3C64XX_SETUP_KEYPAD - bool - help - Common setup code for S3C64XX KEYPAD GPIO configurations - -config S3C64XX_SETUP_SDHCI_GPIO - bool - help - Common setup code for S3C64XX SDHCI GPIO configurations - -config S3C64XX_SETUP_SPI - bool - help - Common setup code for SPI GPIO configurations - -config S3C64XX_SETUP_USB_PHY - bool - help - Common setup code for USB PHY controller - -# S36400 Macchine support - -config MACH_SMDK6400 - bool "SMDK6400" - select CPU_S3C6400 - select S3C_DEV_HSMMC - select S3C_DEV_NAND - select S3C64XX_SETUP_SDHCI - help - Machine support for the Samsung SMDK6400 - -# S3C6410 machine support - -config MACH_ANW6410 - bool "A&W6410" - select CPU_S3C6410 - select S3C_DEV_FB - select S3C64XX_SETUP_FB_24BPP - help - Machine support for the A&W6410 - -config MACH_MINI6410 - bool "MINI6410" - select CPU_S3C6410 - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C64XX_SETUP_SDHCI - select S3C_DEV_USB_HOST - select S3C_DEV_NAND - select S3C_DEV_FB - select S3C64XX_SETUP_FB_24BPP - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_TS - help - Machine support for the FriendlyARM MINI6410 - -config MACH_REAL6410 - bool "REAL6410" - select CPU_S3C6410 - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C64XX_SETUP_SDHCI - select S3C_DEV_FB - select S3C64XX_SETUP_FB_24BPP - select S3C_DEV_NAND - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_TS - select S3C_DEV_USB_HOST - help - Machine support for the CoreWind REAL6410 - -config MACH_SMDK6410 - bool "SMDK6410" - select CPU_S3C6410 - select SAMSUNG_DEV_ADC - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_I2C1 - select SAMSUNG_DEV_IDE - select S3C_DEV_FB - select S3C_DEV_RTC - select SAMSUNG_DEV_TS - select S3C_DEV_USB_HOST - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - select HAVE_S3C2410_WATCHDOG if WATCHDOG - select S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_I2C1 - select S3C64XX_SETUP_IDE - select S3C64XX_SETUP_FB_24BPP - select S3C64XX_SETUP_KEYPAD - select S3C64XX_SETUP_USB_PHY - help - Machine support for the Samsung SMDK6410 - -# At least some of the SMDK6410s were shipped with the card detect -# for the MMC/SD slots connected to the same input. This means that -# either the boards need to be altered to have channel0 to an alternate -# configuration or that only one slot can be used. - -choice - prompt "SMDK6410 MMC/SD slot setup" - depends on MACH_SMDK6410 - -config SMDK6410_SD_CH0 - bool "Use channel 0 only" - depends on MACH_SMDK6410 - help - Select CON7 (channel 0) as the MMC/SD slot, as - at least some SMDK6410 boards come with the - resistors fitted so that the card detects for - channels 0 and 1 are the same. - -config SMDK6410_SD_CH1 - bool "Use channel 1 only" - depends on MACH_SMDK6410 - help - Select CON6 (channel 1) as the MMC/SD slot, as - at least some SMDK6410 boards come with the - resistors fitted so that the card detects for - channels 0 and 1 are the same. - -endchoice - -config SMDK6410_WM1190_EV1 - bool "Support Wolfson Microelectronics 1190-EV1 PMIC card" - depends on MACH_SMDK6410 - select REGULATOR - select REGULATOR_WM8350 - select SAMSUNG_GPIO_EXTRA64 - select MFD_WM8350_I2C - select MFD_WM8350_CONFIG_MODE_0 - select MFD_WM8350_CONFIG_MODE_3 - select MFD_WM8352_CONFIG_MODE_0 - help - The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC - and audio daughtercard for the Samsung SMDK6410 reference - platform. Enabling this option will build support for this - module into the kernel. The presence of the module will be - detected at runtime so the the resulting kernel can be used - with or without the 1190-EV1 fitted. - -config SMDK6410_WM1192_EV1 - bool "Support Wolfson Microelectronics 1192-EV1 PMIC card" - depends on MACH_SMDK6410 - select REGULATOR - select REGULATOR_WM831X - select SAMSUNG_GPIO_EXTRA64 - select MFD_WM831X - select MFD_WM831X_I2C - help - The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC - daughtercard for the Samsung SMDK6410 reference platform. - Enabling this option will build support for this module into - the kernel. The presence of the daughtercard will be - detected at runtime so the the resulting kernel can be used - with or without the 1192-EV1 fitted. - -config MACH_NCP - bool "NCP" - select CPU_S3C6410 - select S3C_DEV_I2C1 - select S3C_DEV_HSMMC1 - select S3C64XX_SETUP_I2C1 - help - Machine support for the Samsung NCP - -config MACH_HMT - bool "Airgoo HMT" - select CPU_S3C6410 - select S3C_DEV_FB - select S3C_DEV_NAND - select S3C_DEV_USB_HOST - select S3C64XX_SETUP_FB_24BPP - select SAMSUNG_DEV_PWM - help - Machine support for the Airgoo HMT - -config MACH_SMARTQ - bool - select CPU_S3C6410 - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_HSMMC2 - select S3C_DEV_FB - select S3C_DEV_HWMON - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_USB_HOST - select S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_FB_24BPP - select S3C64XX_SETUP_USB_PHY - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_PWM - select SAMSUNG_DEV_TS - help - Shared machine support for SmartQ 5/7 - -config MACH_SMARTQ5 - bool "SmartQ 5" - select MACH_SMARTQ - help - Machine support for the SmartQ 5 - -config MACH_SMARTQ7 - bool "SmartQ 7" - select MACH_SMARTQ - help - Machine support for the SmartQ 7 - -config MACH_WLF_CRAGG_6410 - bool "Wolfson Cragganmore 6410" - select CPU_S3C6410 - select S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_I2C1 - select S3C64XX_SETUP_IDE - select S3C64XX_SETUP_FB_24BPP - select S3C64XX_SETUP_KEYPAD - select S3C64XX_SETUP_SPI - select S3C64XX_SETUP_USB_PHY - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_KEYPAD - select S3C_DEV_USB_HOST - select S3C_DEV_USB_HSOTG - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_HSMMC2 - select S3C_DEV_I2C1 - select S3C_DEV_WDT - select S3C_DEV_RTC - select S3C64XX_DEV_SPI0 - select SAMSUNG_GPIO_EXTRA128 - select I2C - select LEDS_GPIO_REGISTER - help - Machine support for the Wolfson Cragganmore S3C6410 variant. diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Makefile b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Makefile deleted file mode 100644 index f9ce1dc2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -# arch/arm/mach-s3c64xx/Makefile -# -# Copyright 2008 Openmoko, Inc. -# Copyright 2008 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -# Core - -obj-y += common.o clock.o - -# Core support - -obj-$(CONFIG_CPU_S3C6400) += s3c6400.o -obj-$(CONFIG_CPU_S3C6410) += s3c6410.o - -# PM - -obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o - -# DMA support - -obj-$(CONFIG_S3C64XX_DMA) += dma.o - -# Device support - -obj-y += dev-uart.o -obj-y += dev-audio.o -obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o - -# Device setup - -obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o -obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o -obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o -obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o -obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o - -# Machine support - -obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o -obj-$(CONFIG_MACH_HMT) += mach-hmt.o -obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o -obj-$(CONFIG_MACH_NCP) += mach-ncp.o -obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o -obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o -obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o -obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o -obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o -obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o -obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Makefile.boot b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Makefile.boot deleted file mode 100644 index c642333a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y += 0x50008000 -params_phys-y := 0x50000100 diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/clock.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/clock.c deleted file mode 100644 index 52f079a6..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/clock.c +++ /dev/null @@ -1,998 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/clock.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX Base clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <mach/regs-sys.h> -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/cpu-freq.h> -#include <plat/clock.h> -#include <plat/clock-clksrc.h> -#include <plat/pll.h> - -/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call - * ext_xtal_mux for want of an actual name from the manual. -*/ - -static struct clk clk_ext_xtal_mux = { - .name = "ext_xtal", -}; - -#define clk_fin_apll clk_ext_xtal_mux -#define clk_fin_mpll clk_ext_xtal_mux -#define clk_fin_epll clk_ext_xtal_mux - -#define clk_fout_mpll clk_mpll -#define clk_fout_epll clk_epll - -struct clk clk_h2 = { - .name = "hclk2", - .rate = 0, -}; - -struct clk clk_27m = { - .name = "clk_27m", - .rate = 27000000, -}; - -static int clk_48m_ctrl(struct clk *clk, int enable) -{ - unsigned long flags; - u32 val; - - /* can't rely on clock lock, this register has other usages */ - local_irq_save(flags); - - val = __raw_readl(S3C64XX_OTHERS); - if (enable) - val |= S3C64XX_OTHERS_USBMASK; - else - val &= ~S3C64XX_OTHERS_USBMASK; - - __raw_writel(val, S3C64XX_OTHERS); - local_irq_restore(flags); - - return 0; -} - -struct clk clk_48m = { - .name = "clk_48m", - .rate = 48000000, - .enable = clk_48m_ctrl, -}; - -struct clk clk_xusbxti = { - .name = "xusbxti", - .rate = 48000000, -}; - -static int inline s3c64xx_gate(void __iomem *reg, - struct clk *clk, - int enable) -{ - unsigned int ctrlbit = clk->ctrlbit; - u32 con; - - con = __raw_readl(reg); - - if (enable) - con |= ctrlbit; - else - con &= ~ctrlbit; - - __raw_writel(con, reg); - return 0; -} - -static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) -{ - return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); -} - -static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) -{ - return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); -} - -int s3c64xx_sclk_ctrl(struct clk *clk, int enable) -{ - return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); -} - -static struct clk init_clocks_off[] = { - { - .name = "nand", - .parent = &clk_h, - }, { - .name = "rtc", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_RTC, - }, { - .name = "adc", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_TSADC, - }, { - .name = "i2c", -#ifdef CONFIG_S3C_DEV_I2C1 - .devname = "s3c2440-i2c.0", -#else - .devname = "s3c2440-i2c", -#endif - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_IIC, - }, { - .name = "i2c", - .devname = "s3c2440-i2c.1", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, - }, { - .name = "iis", - .devname = "samsung-i2s.0", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_IIS0, - }, { - .name = "iis", - .devname = "samsung-i2s.1", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_IIS1, - }, { -#ifdef CONFIG_CPU_S3C6410 - .name = "iis", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, - }, { -#endif - .name = "keypad", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, - }, { - .name = "spi", - .devname = "s3c64xx-spi.0", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_SPI0, - }, { - .name = "spi", - .devname = "s3c64xx-spi.1", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_SPI1, - }, { - .name = "48m", - .devname = "s3c-sdhci.0", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, - }, { - .name = "48m", - .devname = "s3c-sdhci.1", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, - }, { - .name = "48m", - .devname = "s3c-sdhci.2", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, - }, { - .name = "ac97", - .parent = &clk_p, - .ctrlbit = S3C_CLKCON_PCLK_AC97, - }, { - .name = "cfcon", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_IHOST, - }, { - .name = "dma0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_DMA0, - }, { - .name = "dma1", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_DMA1, - }, { - .name = "3dse", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_3DSE, - }, { - .name = "hclk_secur", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_SECUR, - }, { - .name = "sdma1", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_SDMA1, - }, { - .name = "sdma0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_SDMA0, - }, { - .name = "hclk_jpeg", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_JPEG, - }, { - .name = "camif", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_CAMIF, - }, { - .name = "hclk_scaler", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_SCALER, - }, { - .name = "2d", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_2D, - }, { - .name = "tv", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_TV, - }, { - .name = "post0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_POST0, - }, { - .name = "rot", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_ROT, - }, { - .name = "hclk_mfc", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_MFC, - }, { - .name = "pclk_mfc", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_MFC, - }, { - .name = "dac27", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_DAC27, - }, { - .name = "tv27", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_TV27, - }, { - .name = "scaler27", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SCALER27, - }, { - .name = "sclk_scaler", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SCALER, - }, { - .name = "post0_27", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_POST0_27, - }, { - .name = "secur", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SECUR, - }, { - .name = "sclk_mfc", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_MFC, - }, { - .name = "cam", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_CAM, - }, { - .name = "sclk_jpeg", - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_JPEG, - }, -}; - -static struct clk clk_48m_spi0 = { - .name = "spi_48m", - .devname = "s3c64xx-spi.0", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, -}; - -static struct clk clk_48m_spi1 = { - .name = "spi_48m", - .devname = "s3c64xx-spi.1", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, -}; - -static struct clk init_clocks[] = { - { - .name = "lcd", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_LCD, - }, { - .name = "gpio", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_GPIO, - }, { - .name = "usb-host", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_UHOST, - }, { - .name = "otg", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_USB, - }, { - .name = "timers", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_PWM, - }, { - .name = "uart", - .devname = "s3c6400-uart.0", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_UART0, - }, { - .name = "uart", - .devname = "s3c6400-uart.1", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_UART1, - }, { - .name = "uart", - .devname = "s3c6400-uart.2", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_UART2, - }, { - .name = "uart", - .devname = "s3c6400-uart.3", - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_UART3, - }, { - .name = "watchdog", - .parent = &clk_p, - .ctrlbit = S3C_CLKCON_PCLK_WDT, - }, -}; - -static struct clk clk_hsmmc0 = { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, -}; - -static struct clk clk_hsmmc1 = { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, -}; - -static struct clk clk_hsmmc2 = { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, -}; - -static struct clk clk_fout_apll = { - .name = "fout_apll", -}; - -static struct clk *clk_src_apll_list[] = { - [0] = &clk_fin_apll, - [1] = &clk_fout_apll, -}; - -static struct clksrc_sources clk_src_apll = { - .sources = clk_src_apll_list, - .nr_sources = ARRAY_SIZE(clk_src_apll_list), -}; - -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, - .sources = &clk_src_apll, -}; - -static struct clk *clk_src_epll_list[] = { - [0] = &clk_fin_epll, - [1] = &clk_fout_epll, -}; - -static struct clksrc_sources clk_src_epll = { - .sources = clk_src_epll_list, - .nr_sources = ARRAY_SIZE(clk_src_epll_list), -}; - -static struct clksrc_clk clk_mout_epll = { - .clk = { - .name = "mout_epll", - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, - .sources = &clk_src_epll, -}; - -static struct clk *clk_src_mpll_list[] = { - [0] = &clk_fin_mpll, - [1] = &clk_fout_mpll, -}; - -static struct clksrc_sources clk_src_mpll = { - .sources = clk_src_mpll_list, - .nr_sources = ARRAY_SIZE(clk_src_mpll_list), -}; - -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, - .sources = &clk_src_mpll, -}; - -static unsigned int armclk_mask; - -static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - u32 clkdiv; - - /* divisor mask starts at bit0, so no need to shift */ - clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; - - return rate / (clkdiv + 1); -} - -static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - u32 div; - - if (parent < rate) - return parent; - - div = (parent / rate) - 1; - if (div > armclk_mask) - div = armclk_mask; - - return parent / (div + 1); -} - -static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - u32 div; - u32 val; - - if (rate < parent / (armclk_mask + 1)) - return -EINVAL; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - - val = __raw_readl(S3C_CLK_DIV0); - val &= ~armclk_mask; - val |= (div - 1); - __raw_writel(val, S3C_CLK_DIV0); - - return 0; - -} - -static struct clk clk_arm = { - .name = "armclk", - .parent = &clk_mout_apll.clk, - .ops = &(struct clk_ops) { - .get_rate = s3c64xx_clk_arm_get_rate, - .set_rate = s3c64xx_clk_arm_set_rate, - .round_rate = s3c64xx_clk_arm_round_rate, - }, -}; - -static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) - rate /= 2; - - return rate; -} - -static struct clk_ops clk_dout_ops = { - .get_rate = s3c64xx_clk_doutmpll_get_rate, -}; - -static struct clk clk_dout_mpll = { - .name = "dout_mpll", - .parent = &clk_mout_mpll.clk, - .ops = &clk_dout_ops, -}; - -static struct clk *clkset_spi_mmc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_27m, -}; - -static struct clksrc_sources clkset_spi_mmc = { - .sources = clkset_spi_mmc_list, - .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), -}; - -static struct clk *clkset_irda_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - NULL, - &clk_27m, -}; - -static struct clksrc_sources clkset_irda = { - .sources = clkset_irda_list, - .nr_sources = ARRAY_SIZE(clkset_irda_list), -}; - -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - NULL, - NULL -}; - -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), -}; - -static struct clk *clkset_uhost_list[] = { - &clk_48m, - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, -}; - -static struct clksrc_sources clkset_uhost = { - .sources = clkset_uhost_list, - .nr_sources = ARRAY_SIZE(clkset_uhost_list), -}; - -/* The peripheral clocks are all controlled via clocksource followed - * by an optional divider and gate stage. We currently roll this into - * one clock which hides the intermediate clock from the mux. - * - * Note, the JPEG clock can only be an even divider... - * - * The scaler and LCD clocks depend on the S3C64XX version, and also - * have a common parent divisor so are not included here. - */ - -/* clocks that feed other parts of the clock source tree */ - -static struct clk clk_iis_cd0 = { - .name = "iis_cdclk0", -}; - -static struct clk clk_iis_cd1 = { - .name = "iis_cdclk1", -}; - -static struct clk clk_iisv4_cd = { - .name = "iis_cdclk_v4", -}; - -static struct clk clk_pcm_cd = { - .name = "pcm_cdclk", -}; - -static struct clk *clkset_audio0_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_dout_mpll, - [2] = &clk_fin_epll, - [3] = &clk_iis_cd0, - [4] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio0 = { - .sources = clkset_audio0_list, - .nr_sources = ARRAY_SIZE(clkset_audio0_list), -}; - -static struct clk *clkset_audio1_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_dout_mpll, - [2] = &clk_fin_epll, - [3] = &clk_iis_cd1, - [4] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio1 = { - .sources = clkset_audio1_list, - .nr_sources = ARRAY_SIZE(clkset_audio1_list), -}; - -static struct clk *clkset_audio2_list[] = { - [0] = &clk_mout_epll.clk, - [1] = &clk_dout_mpll, - [2] = &clk_fin_epll, - [3] = &clk_iisv4_cd, - [4] = &clk_pcm_cd, -}; - -static struct clksrc_sources clkset_audio2 = { - .sources = clkset_audio2_list, - .nr_sources = ARRAY_SIZE(clkset_audio2_list), -}; - -static struct clk *clkset_camif_list[] = { - &clk_h2, -}; - -static struct clksrc_sources clkset_camif = { - .sources = clkset_camif_list, - .nr_sources = ARRAY_SIZE(clkset_camif_list), -}; - -static struct clksrc_clk clksrcs[] = { - { - .clk = { - .name = "usb-bus-host", - .ctrlbit = S3C_CLKCON_SCLK_UHOST, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, - .sources = &clkset_uhost, - }, { - .clk = { - .name = "audio-bus", - .devname = "samsung-i2s.0", - .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, - .sources = &clkset_audio0, - }, { - .clk = { - .name = "audio-bus", - .devname = "samsung-i2s.1", - .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, - .sources = &clkset_audio1, - }, { - .clk = { - .name = "audio-bus", - .devname = "samsung-i2s.2", - .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 }, - .sources = &clkset_audio2, - }, { - .clk = { - .name = "irda-bus", - .ctrlbit = S3C_CLKCON_SCLK_IRDA, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, - .sources = &clkset_irda, - }, { - .clk = { - .name = "camera", - .ctrlbit = S3C_CLKCON_SCLK_CAM, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, - .reg_src = { .reg = NULL, .shift = 0, .size = 0 }, - .sources = &clkset_camif, - }, -}; - -/* Where does UCLK0 come from? */ -static struct clksrc_clk clk_sclk_uclk = { - .clk = { - .name = "uclk1", - .ctrlbit = S3C_CLKCON_SCLK_UART, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, - .sources = &clkset_uart, -}; - -static struct clksrc_clk clk_sclk_mmc0 = { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.0", - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_mmc1 = { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.1", - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_mmc2 = { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.2", - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_spi0 = { - .clk = { - .name = "spi-bus", - .devname = "s3c64xx-spi.0", - .ctrlbit = S3C_CLKCON_SCLK_SPI0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, -}; - -static struct clksrc_clk clk_sclk_spi1 = { - .clk = { - .name = "spi-bus", - .devname = "s3c64xx-spi.1", - .ctrlbit = S3C_CLKCON_SCLK_SPI1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, -}; - -/* Clock initialisation code */ - -static struct clksrc_clk *init_parents[] = { - &clk_mout_apll, - &clk_mout_epll, - &clk_mout_mpll, -}; - -static struct clksrc_clk *clksrc_cdev[] = { - &clk_sclk_uclk, - &clk_sclk_mmc0, - &clk_sclk_mmc1, - &clk_sclk_mmc2, - &clk_sclk_spi0, - &clk_sclk_spi1, -}; - -static struct clk *clk_cdev[] = { - &clk_hsmmc0, - &clk_hsmmc1, - &clk_hsmmc2, - &clk_48m_spi0, - &clk_48m_spi1, -}; - -static struct clk_lookup s3c64xx_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), - CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), -}; - -#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - -void __init_or_cpufreq s3c64xx_setup_clocks(void) -{ - struct clk *xtal_clk; - unsigned long xtal; - unsigned long fclk; - unsigned long hclk; - unsigned long hclk2; - unsigned long pclk; - unsigned long epll; - unsigned long apll; - unsigned long mpll; - unsigned int ptr; - u32 clkdiv0; - - printk(KERN_DEBUG "%s: registering clocks\n", __func__); - - clkdiv0 = __raw_readl(S3C_CLK_DIV0); - printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); - - xtal_clk = clk_get(NULL, "xtal"); - BUG_ON(IS_ERR(xtal_clk)); - - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - - /* For now assume the mux always selects the crystal */ - clk_ext_xtal_mux.parent = xtal_clk; - - epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0), - __raw_readl(S3C_EPLL_CON1)); - mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); - apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); - - fclk = mpll; - - printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", - apll, mpll, epll); - - if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL) - /* Synchronous mode */ - hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); - else - /* Asynchronous mode */ - hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); - - hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); - pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); - - printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", - hclk2, hclk, pclk); - - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_apll.rate = apll; - - clk_h2.rate = hclk2; - clk_h.rate = hclk; - clk_p.rate = pclk; - clk_f.rate = fclk; - - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_set_clksrc(&clksrcs[ptr], true); -} - -static struct clk *clks1[] __initdata = { - &clk_ext_xtal_mux, - &clk_iis_cd0, - &clk_iis_cd1, - &clk_iisv4_cd, - &clk_pcm_cd, - &clk_mout_epll.clk, - &clk_mout_mpll.clk, - &clk_dout_mpll, - &clk_arm, -}; - -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_epll, - &clk_27m, - &clk_48m, - &clk_h2, - &clk_xusbxti, -}; - -/** - * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410 - * @xtal: The rate for the clock crystal feeding the PLLs. - * @armclk_divlimit: Divisor mask for ARMCLK. - * - * Register the clocks for the S3C6400 and S3C6410 SoC range, such - * as ARMCLK as well as the necessary parent clocks. - * - * This call does not setup the clocks, which is left to the - * s3c64xx_setup_clocks() call which may be needed by the cpufreq - * or resume code to re-set the clocks if the bootloader has changed - * them. - */ -void __init s3c64xx_register_clocks(unsigned long xtal, - unsigned armclk_divlimit) -{ - unsigned int cnt; - - armclk_mask = armclk_divlimit; - - s3c24xx_register_baseclocks(xtal); - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - - s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); - for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) - s3c_disable_clocks(clk_cdev[cnt], 1); - - s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); - s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); - for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) - s3c_register_clksrc(clksrc_cdev[cnt], 1); - clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup)); - - s3c_pwmclk_init(); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/common.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/common.c deleted file mode 100644 index b3133803..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/common.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Common Codes for S3C64XX machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/dma-mapping.h> -#include <linux/irq.h> -#include <linux/gpio.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/hardware/vic.h> -#include <asm/system_misc.h> - -#include <mach/map.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> - -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/gpio-cfg.h> -#include <plat/irq-uart.h> -#include <plat/irq-vic-timer.h> -#include <plat/regs-irqtype.h> -#include <plat/regs-serial.h> -#include <plat/watchdog-reset.h> - -#include "common.h" - -/* uart registration process */ - -static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); -} - -/* table of supported CPUs */ - -static const char name_s3c6400[] = "S3C6400"; -static const char name_s3c6410[] = "S3C6410"; - -static struct cpu_table cpu_ids[] __initdata = { - { - .idcode = S3C6400_CPU_ID, - .idmask = S3C64XX_CPU_MASK, - .map_io = s3c6400_map_io, - .init_clocks = s3c6400_init_clocks, - .init_uarts = s3c64xx_init_uarts, - .init = s3c6400_init, - .name = name_s3c6400, - }, { - .idcode = S3C6410_CPU_ID, - .idmask = S3C64XX_CPU_MASK, - .map_io = s3c6410_map_io, - .init_clocks = s3c6410_init_clocks, - .init_uarts = s3c64xx_init_uarts, - .init = s3c6410_init, - .name = name_s3c6410, - }, -}; - -/* minimal IO mapping */ - -/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */ -#define UART_OFFS (S3C_PA_UART & 0xfffff) - -static struct map_desc s3c_iodesc[] __initdata = { - { - .virtual = (unsigned long)S3C_VA_SYS, - .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_MEM, - .pfn = __phys_to_pfn(S3C64XX_PA_SROM), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), - .pfn = __phys_to_pfn(S3C_PA_UART), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)VA_VIC0, - .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)VA_VIC1, - .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_TIMER, - .pfn = __phys_to_pfn(S3C_PA_TIMER), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C64XX_VA_GPIO, - .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C64XX_VA_MODEM, - .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_WATCHDOG, - .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_USB_HSPHY, - .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY), - .length = SZ_1K, - .type = MT_DEVICE, - }, -}; - -static struct bus_type s3c64xx_subsys = { - .name = "s3c64xx-core", - .dev_name = "s3c64xx-core", -}; - -static struct device s3c64xx_dev = { - .bus = &s3c64xx_subsys, -}; - -/* read cpu identification code */ - -void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) -{ - /* initialise the io descriptors we need for initialisation */ - iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); - iotable_init(mach_desc, size); - init_consistent_dma_size(SZ_8M); - - /* detect cpu id */ - s3c64xx_init_cpu(); - - s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); -} - -static __init int s3c64xx_dev_init(void) -{ - subsys_system_register(&s3c64xx_subsys, NULL); - return device_register(&s3c64xx_dev); -} -core_initcall(s3c64xx_dev_init); - -/* - * setup the sources the vic should advertise resume - * for, even though it is not doing the wake - * (set_irq_wake needs to be valid) - */ -#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) -#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ - 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ - 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ - 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ - 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) - -void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) -{ - printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); - - /* initialise the pair of VICs */ - vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); - vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); - - /* add the timer sub-irqs */ - s3c_init_vic_timer_irq(5, IRQ_TIMER0); -} - -#define eint_offset(irq) ((irq) - IRQ_EINT(0)) -#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq))) - -static inline void s3c_irq_eint_mask(struct irq_data *data) -{ - u32 mask; - - mask = __raw_readl(S3C64XX_EINT0MASK); - mask |= (u32)data->chip_data; - __raw_writel(mask, S3C64XX_EINT0MASK); -} - -static void s3c_irq_eint_unmask(struct irq_data *data) -{ - u32 mask; - - mask = __raw_readl(S3C64XX_EINT0MASK); - mask &= ~((u32)data->chip_data); - __raw_writel(mask, S3C64XX_EINT0MASK); -} - -static inline void s3c_irq_eint_ack(struct irq_data *data) -{ - __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); -} - -static void s3c_irq_eint_maskack(struct irq_data *data) -{ - /* compiler should in-line these */ - s3c_irq_eint_mask(data); - s3c_irq_eint_ack(data); -} - -static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type) -{ - int offs = eint_offset(data->irq); - int pin, pin_val; - int shift; - u32 ctrl, mask; - u32 newvalue = 0; - void __iomem *reg; - - if (offs > 27) - return -EINVAL; - - if (offs <= 15) - reg = S3C64XX_EINT0CON0; - else - reg = S3C64XX_EINT0CON1; - - switch (type) { - case IRQ_TYPE_NONE: - printk(KERN_WARNING "No edge setting!\n"); - break; - - case IRQ_TYPE_EDGE_RISING: - newvalue = S3C2410_EXTINT_RISEEDGE; - break; - - case IRQ_TYPE_EDGE_FALLING: - newvalue = S3C2410_EXTINT_FALLEDGE; - break; - - case IRQ_TYPE_EDGE_BOTH: - newvalue = S3C2410_EXTINT_BOTHEDGE; - break; - - case IRQ_TYPE_LEVEL_LOW: - newvalue = S3C2410_EXTINT_LOWLEV; - break; - - case IRQ_TYPE_LEVEL_HIGH: - newvalue = S3C2410_EXTINT_HILEV; - break; - - default: - printk(KERN_ERR "No such irq type %d", type); - return -1; - } - - if (offs <= 15) - shift = (offs / 2) * 4; - else - shift = ((offs - 16) / 2) * 4; - mask = 0x7 << shift; - - ctrl = __raw_readl(reg); - ctrl &= ~mask; - ctrl |= newvalue << shift; - __raw_writel(ctrl, reg); - - /* set the GPIO pin appropriately */ - - if (offs < 16) { - pin = S3C64XX_GPN(offs); - pin_val = S3C_GPIO_SFN(2); - } else if (offs < 23) { - pin = S3C64XX_GPL(offs + 8 - 16); - pin_val = S3C_GPIO_SFN(3); - } else { - pin = S3C64XX_GPM(offs - 23); - pin_val = S3C_GPIO_SFN(3); - } - - s3c_gpio_cfgpin(pin, pin_val); - - return 0; -} - -static struct irq_chip s3c_irq_eint = { - .name = "s3c-eint", - .irq_mask = s3c_irq_eint_mask, - .irq_unmask = s3c_irq_eint_unmask, - .irq_mask_ack = s3c_irq_eint_maskack, - .irq_ack = s3c_irq_eint_ack, - .irq_set_type = s3c_irq_eint_set_type, - .irq_set_wake = s3c_irqext_wake, -}; - -/* s3c_irq_demux_eint - * - * This function demuxes the IRQ from the group0 external interrupts, - * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into - * the specific handlers s3c_irq_demux_eintX_Y. - */ -static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) -{ - u32 status = __raw_readl(S3C64XX_EINT0PEND); - u32 mask = __raw_readl(S3C64XX_EINT0MASK); - unsigned int irq; - - status &= ~mask; - status >>= start; - status &= (1 << (end - start + 1)) - 1; - - for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { - if (status & 1) - generic_handle_irq(irq); - - status >>= 1; - } -} - -static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_eint(0, 3); -} - -static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_eint(4, 11); -} - -static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_eint(12, 19); -} - -static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_eint(20, 27); -} - -static int __init s3c64xx_init_irq_eint(void) -{ - int irq; - - for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { - irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); - irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); - set_irq_flags(irq, IRQF_VALID); - } - - irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); - irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); - irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); - irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); - - return 0; -} -arch_initcall(s3c64xx_init_irq_eint); - -void s3c64xx_restart(char mode, const char *cmd) -{ - if (mode != 's') - arch_wdt_reset(); - - /* if all else fails, or mode was for soft, jump to 0 */ - soft_restart(0); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/common.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/common.h deleted file mode 100644 index 7a10be62..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/common.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Common Header for S3C64XX machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H -#define __ARCH_ARM_MACH_S3C64XX_COMMON_H - -void s3c64xx_init_irq(u32 vic0, u32 vic1); -void s3c64xx_init_io(struct map_desc *mach_desc, int size); - -void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit); -void s3c64xx_setup_clocks(void); - -void s3c64xx_restart(char mode, const char *cmd); - -#ifdef CONFIG_CPU_S3C6400 - -extern int s3c6400_init(void); -extern void s3c6400_init_irq(void); -extern void s3c6400_map_io(void); -extern void s3c6400_init_clocks(int xtal); - -#else -#define s3c6400_init_clocks NULL -#define s3c6400_map_io NULL -#define s3c6400_init NULL -#endif - -#ifdef CONFIG_CPU_S3C6410 - -extern int s3c6410_init(void); -extern void s3c6410_init_irq(void); -extern void s3c6410_map_io(void); -extern void s3c6410_init_clocks(int xtal); - -#else -#define s3c6410_init_clocks NULL -#define s3c6410_map_io NULL -#define s3c6410_init NULL -#endif - -#endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/cpuidle.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/cpuidle.c deleted file mode 100644 index 179460f3..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/cpuidle.c +++ /dev/null @@ -1,91 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/cpuidle.c - * - * Copyright (c) 2011 Wolfson Microelectronics, plc - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/cpuidle.h> -#include <linux/io.h> -#include <linux/export.h> -#include <linux/time.h> - -#include <asm/proc-fns.h> - -#include <mach/map.h> - -#include <mach/regs-sys.h> -#include <mach/regs-syscon-power.h> - -static int s3c64xx_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - struct timeval before, after; - unsigned long tmp; - int idle_time; - - local_irq_disable(); - do_gettimeofday(&before); - - /* Setup PWRCFG to enter idle mode */ - tmp = __raw_readl(S3C64XX_PWR_CFG); - tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; - tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE; - __raw_writel(tmp, S3C64XX_PWR_CFG); - - cpu_do_idle(); - - do_gettimeofday(&after); - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - dev->last_residency = idle_time; - return index; -} - -static struct cpuidle_state s3c64xx_cpuidle_set[] = { - [0] = { - .enter = s3c64xx_enter_idle, - .exit_latency = 1, - .target_residency = 1, - .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "IDLE", - .desc = "System active, ARM gated", - }, -}; - -static struct cpuidle_driver s3c64xx_cpuidle_driver = { - .name = "s3c64xx_cpuidle", - .owner = THIS_MODULE, - .state_count = ARRAY_SIZE(s3c64xx_cpuidle_set), -}; - -static struct cpuidle_device s3c64xx_cpuidle_device = { - .state_count = ARRAY_SIZE(s3c64xx_cpuidle_set), -}; - -static int __init s3c64xx_init_cpuidle(void) -{ - int ret; - - memcpy(s3c64xx_cpuidle_driver.states, s3c64xx_cpuidle_set, - sizeof(s3c64xx_cpuidle_set)); - cpuidle_register_driver(&s3c64xx_cpuidle_driver); - - ret = cpuidle_register_device(&s3c64xx_cpuidle_device); - if (ret) { - pr_err("Failed to register cpuidle device: %d\n", ret); - return ret; - } - - return 0; -} -device_initcall(s3c64xx_init_cpuidle); diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dev-audio.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dev-audio.c deleted file mode 100644 index 93470b15..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dev-audio.c +++ /dev/null @@ -1,318 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-audio.c - * - * Copyright 2009 Wolfson Microelectronics - * Mark Brown <broonie@opensource.wolfsonmicro.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> -#include <linux/export.h> - -#include <mach/irqs.h> -#include <mach/map.h> -#include <mach/dma.h> - -#include <plat/devs.h> -#include <plat/audio.h> -#include <plat/gpio-cfg.h> - -static const char *rclksrc[] = { - [0] = "iis", - [1] = "audio-bus", -}; - -static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev) -{ - unsigned int base; - - switch (pdev->id) { - case 0: - base = S3C64XX_GPD(0); - break; - case 1: - base = S3C64XX_GPE(0); - break; - case 2: - s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5)); - return 0; - default: - printk(KERN_DEBUG "Invalid I2S Controller number: %d\n", - pdev->id); - return -EINVAL; - } - - s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3)); - - return 0; -} - -static struct resource s3c64xx_iis0_resource[] = { - [0] = { - .start = S3C64XX_PA_IIS0, - .end = S3C64XX_PA_IIS0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_OUT, - .end = DMACH_I2S0_OUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_IN, - .end = DMACH_I2S0_IN, - .flags = IORESOURCE_DMA, - }, -}; - -static struct s3c_audio_pdata i2sv3_pdata = { - .cfg_gpio = s3c64xx_i2s_cfg_gpio, - .type = { - .i2s = { - .src_clk = rclksrc, - }, - }, -}; - -struct platform_device s3c64xx_device_iis0 = { - .name = "samsung-i2s", - .id = 0, - .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), - .resource = s3c64xx_iis0_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_iis0); - -static struct resource s3c64xx_iis1_resource[] = { - [0] = { - .start = S3C64XX_PA_IIS1, - .end = S3C64XX_PA_IIS1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_OUT, - .end = DMACH_I2S1_OUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_IN, - .end = DMACH_I2S1_IN, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s3c64xx_device_iis1 = { - .name = "samsung-i2s", - .id = 1, - .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), - .resource = s3c64xx_iis1_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_iis1); - -static struct resource s3c64xx_iisv4_resource[] = { - [0] = { - .start = S3C64XX_PA_IISV4, - .end = S3C64XX_PA_IISV4 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_HSI_I2SV40_TX, - .end = DMACH_HSI_I2SV40_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_HSI_I2SV40_RX, - .end = DMACH_HSI_I2SV40_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct s3c_audio_pdata i2sv4_pdata = { - .cfg_gpio = s3c64xx_i2s_cfg_gpio, - .type = { - .i2s = { - .quirks = QUIRK_PRI_6CHAN, - .src_clk = rclksrc, - }, - }, -}; - -struct platform_device s3c64xx_device_iisv4 = { - .name = "samsung-i2s", - .id = 2, - .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), - .resource = s3c64xx_iisv4_resource, - .dev = { - .platform_data = &i2sv4_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_iisv4); - - -/* PCM Controller platform_devices */ - -static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) -{ - unsigned int base; - - switch (pdev->id) { - case 0: - base = S3C64XX_GPD(0); - break; - case 1: - base = S3C64XX_GPE(0); - break; - default: - printk(KERN_DEBUG "Invalid PCM Controller number: %d\n", - pdev->id); - return -EINVAL; - } - - s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2)); - return 0; -} - -static struct resource s3c64xx_pcm0_resource[] = { - [0] = { - .start = S3C64XX_PA_PCM0, - .end = S3C64XX_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct s3c_audio_pdata s3c_pcm0_pdata = { - .cfg_gpio = s3c64xx_pcm_cfg_gpio, -}; - -struct platform_device s3c64xx_device_pcm0 = { - .name = "samsung-pcm", - .id = 0, - .num_resources = ARRAY_SIZE(s3c64xx_pcm0_resource), - .resource = s3c64xx_pcm0_resource, - .dev = { - .platform_data = &s3c_pcm0_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_pcm0); - -static struct resource s3c64xx_pcm1_resource[] = { - [0] = { - .start = S3C64XX_PA_PCM1, - .end = S3C64XX_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct s3c_audio_pdata s3c_pcm1_pdata = { - .cfg_gpio = s3c64xx_pcm_cfg_gpio, -}; - -struct platform_device s3c64xx_device_pcm1 = { - .name = "samsung-pcm", - .id = 1, - .num_resources = ARRAY_SIZE(s3c64xx_pcm1_resource), - .resource = s3c64xx_pcm1_resource, - .dev = { - .platform_data = &s3c_pcm1_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_pcm1); - -/* AC97 Controller platform devices */ - -static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev) -{ - return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4)); -} - -static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev) -{ - return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4)); -} - -static struct resource s3c64xx_ac97_resource[] = { - [0] = { - .start = S3C64XX_PA_AC97, - .end = S3C64XX_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = IRQ_AC97, - .end = IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c_audio_pdata s3c_ac97_pdata; - -static u64 s3c64xx_ac97_dmamask = DMA_BIT_MASK(32); - -struct platform_device s3c64xx_device_ac97 = { - .name = "samsung-ac97", - .id = -1, - .num_resources = ARRAY_SIZE(s3c64xx_ac97_resource), - .resource = s3c64xx_ac97_resource, - .dev = { - .platform_data = &s3c_ac97_pdata, - .dma_mask = &s3c64xx_ac97_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; -EXPORT_SYMBOL(s3c64xx_device_ac97); - -void __init s3c64xx_ac97_setup_gpio(int num) -{ - if (num == S3C64XX_AC97_GPD) - s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpd; - else - s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpe; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dev-uart.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dev-uart.c deleted file mode 100644 index c681b99e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dev-uart.c +++ /dev/null @@ -1,103 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/dev-uart.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Base S3C64XX UART resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/map.h> - -#include <plat/devs.h> - -/* Serial port registrations */ - -/* 64xx uarts are closer together */ - -static struct resource s3c64xx_uart0_resource[] = { - [0] = { - .start = S3C_PA_UART0, - .end = S3C_PA_UART0 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART0, - .end = IRQ_UART0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource s3c64xx_uart1_resource[] = { - [0] = { - .start = S3C_PA_UART1, - .end = S3C_PA_UART1 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART1, - .end = IRQ_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource s3c6xx_uart2_resource[] = { - [0] = { - .start = S3C_PA_UART2, - .end = S3C_PA_UART2 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART2, - .end = IRQ_UART2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource s3c64xx_uart3_resource[] = { - [0] = { - .start = S3C_PA_UART3, - .end = S3C_PA_UART3 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART3, - .end = IRQ_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - - -struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { - [0] = { - .resources = s3c64xx_uart0_resource, - .nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource), - }, - [1] = { - .resources = s3c64xx_uart1_resource, - .nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource), - }, - [2] = { - .resources = s3c6xx_uart2_resource, - .nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource), - }, - [3] = { - .resources = s3c64xx_uart3_resource, - .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), - }, -}; diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dma.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dma.c deleted file mode 100644 index f2a7a172..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/dma.c +++ /dev/null @@ -1,753 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/dma.c - * - * Copyright 2009 Openmoko, Inc. - * Copyright 2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX DMA core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/dmapool.h> -#include <linux/device.h> -#include <linux/errno.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/dma.h> -#include <mach/map.h> -#include <mach/irqs.h> - -#include <mach/regs-sys.h> - -#include <asm/hardware/pl080.h> - -/* dma channel state information */ - -struct s3c64xx_dmac { - struct device dev; - struct clk *clk; - void __iomem *regs; - struct s3c2410_dma_chan *channels; - enum dma_ch chanbase; -}; - -/* pool to provide LLI buffers */ -static struct dma_pool *dma_pool; - -/* Debug configuration and code */ - -static unsigned char debug_show_buffs = 0; - -static void dbg_showchan(struct s3c2410_dma_chan *chan) -{ - pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n", - chan->number, - readl(chan->regs + PL080_CH_SRC_ADDR), - readl(chan->regs + PL080_CH_DST_ADDR), - readl(chan->regs + PL080_CH_LLI), - readl(chan->regs + PL080_CH_CONTROL), - readl(chan->regs + PL080S_CH_CONTROL2), - readl(chan->regs + PL080S_CH_CONFIG)); -} - -static void show_lli(struct pl080s_lli *lli) -{ - pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n", - lli, lli->src_addr, lli->dst_addr, lli->next_lli, - lli->control0, lli->control1); -} - -static void dbg_showbuffs(struct s3c2410_dma_chan *chan) -{ - struct s3c64xx_dma_buff *ptr; - struct s3c64xx_dma_buff *end; - - pr_debug("DMA%d: buffs next %p, curr %p, end %p\n", - chan->number, chan->next, chan->curr, chan->end); - - ptr = chan->next; - end = chan->end; - - if (debug_show_buffs) { - for (; ptr != NULL; ptr = ptr->next) { - pr_debug("DMA%d: %08x ", - chan->number, ptr->lli_dma); - show_lli(ptr->lli); - } - } -} - -/* End of Debug */ - -static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel) -{ - struct s3c2410_dma_chan *chan; - unsigned int start, offs; - - start = 0; - - if (channel >= DMACH_PCM1_TX) - start = 8; - - for (offs = 0; offs < 8; offs++) { - chan = &s3c2410_chans[start + offs]; - if (!chan->in_use) - goto found; - } - - return NULL; - -found: - s3c_dma_chan_map[channel] = chan; - return chan; -} - -int s3c2410_dma_config(enum dma_ch channel, int xferunit) -{ - struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); - - if (chan == NULL) - return -EINVAL; - - switch (xferunit) { - case 1: - chan->hw_width = 0; - break; - case 2: - chan->hw_width = 1; - break; - case 4: - chan->hw_width = 2; - break; - default: - printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit); - return -EINVAL; - } - - return 0; -} -EXPORT_SYMBOL(s3c2410_dma_config); - -static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan, - struct pl080s_lli *lli, - dma_addr_t data, int size) -{ - dma_addr_t src, dst; - u32 control0, control1; - - switch (chan->source) { - case DMA_FROM_DEVICE: - src = chan->dev_addr; - dst = data; - control0 = PL080_CONTROL_SRC_AHB2; - control0 |= PL080_CONTROL_DST_INCR; - break; - - case DMA_TO_DEVICE: - src = data; - dst = chan->dev_addr; - control0 = PL080_CONTROL_DST_AHB2; - control0 |= PL080_CONTROL_SRC_INCR; - break; - default: - BUG(); - } - - /* note, we do not currently setup any of the burst controls */ - - control1 = size >> chan->hw_width; /* size in no of xfers */ - control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */ - control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */ - control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT; - control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT; - - lli->src_addr = src; - lli->dst_addr = dst; - lli->next_lli = 0; - lli->control0 = control0; - lli->control1 = control1; -} - -static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan, - struct pl080s_lli *lli) -{ - void __iomem *regs = chan->regs; - - pr_debug("%s: LLI %p => regs\n", __func__, lli); - show_lli(lli); - - writel(lli->src_addr, regs + PL080_CH_SRC_ADDR); - writel(lli->dst_addr, regs + PL080_CH_DST_ADDR); - writel(lli->next_lli, regs + PL080_CH_LLI); - writel(lli->control0, regs + PL080_CH_CONTROL); - writel(lli->control1, regs + PL080S_CH_CONTROL2); -} - -static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan) -{ - struct s3c64xx_dmac *dmac = chan->dmac; - u32 config; - u32 bit = chan->bit; - - dbg_showchan(chan); - - pr_debug("%s: clearing interrupts\n", __func__); - - /* clear interrupts */ - writel(bit, dmac->regs + PL080_TC_CLEAR); - writel(bit, dmac->regs + PL080_ERR_CLEAR); - - pr_debug("%s: starting channel\n", __func__); - - config = readl(chan->regs + PL080S_CH_CONFIG); - config |= PL080_CONFIG_ENABLE; - config &= ~PL080_CONFIG_HALT; - - pr_debug("%s: writing config %08x\n", __func__, config); - writel(config, chan->regs + PL080S_CH_CONFIG); - - return 0; -} - -static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan) -{ - u32 config; - int timeout; - - pr_debug("%s: stopping channel\n", __func__); - - dbg_showchan(chan); - - config = readl(chan->regs + PL080S_CH_CONFIG); - config |= PL080_CONFIG_HALT; - writel(config, chan->regs + PL080S_CH_CONFIG); - - timeout = 1000; - do { - config = readl(chan->regs + PL080S_CH_CONFIG); - pr_debug("%s: %d - config %08x\n", __func__, timeout, config); - if (config & PL080_CONFIG_ACTIVE) - udelay(10); - else - break; - } while (--timeout > 0); - - if (config & PL080_CONFIG_ACTIVE) { - printk(KERN_ERR "%s: channel still active\n", __func__); - return -EFAULT; - } - - config = readl(chan->regs + PL080S_CH_CONFIG); - config &= ~PL080_CONFIG_ENABLE; - writel(config, chan->regs + PL080S_CH_CONFIG); - - return 0; -} - -static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan, - struct s3c64xx_dma_buff *buf, - enum s3c2410_dma_buffresult result) -{ - if (chan->callback_fn != NULL) - (chan->callback_fn)(chan, buf->pw, 0, result); -} - -static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff) -{ - dma_pool_free(dma_pool, buff->lli, buff->lli_dma); - kfree(buff); -} - -static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan) -{ - struct s3c64xx_dma_buff *buff, *next; - u32 config; - - dbg_showchan(chan); - - pr_debug("%s: flushing channel\n", __func__); - - config = readl(chan->regs + PL080S_CH_CONFIG); - config &= ~PL080_CONFIG_ENABLE; - writel(config, chan->regs + PL080S_CH_CONFIG); - - /* dump all the buffers associated with this channel */ - - for (buff = chan->curr; buff != NULL; buff = next) { - next = buff->next; - pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next); - - s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT); - s3c64xx_dma_freebuff(buff); - } - - chan->curr = chan->next = chan->end = NULL; - - return 0; -} - -int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op) -{ - struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); - - WARN_ON(!chan); - if (!chan) - return -EINVAL; - - switch (op) { - case S3C2410_DMAOP_START: - return s3c64xx_dma_start(chan); - - case S3C2410_DMAOP_STOP: - return s3c64xx_dma_stop(chan); - - case S3C2410_DMAOP_FLUSH: - return s3c64xx_dma_flush(chan); - - /* believe PAUSE/RESUME are no-ops */ - case S3C2410_DMAOP_PAUSE: - case S3C2410_DMAOP_RESUME: - case S3C2410_DMAOP_STARTED: - case S3C2410_DMAOP_TIMEOUT: - return 0; - } - - return -ENOENT; -} -EXPORT_SYMBOL(s3c2410_dma_ctrl); - -/* s3c2410_dma_enque - * - */ - -int s3c2410_dma_enqueue(enum dma_ch channel, void *id, - dma_addr_t data, int size) -{ - struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); - struct s3c64xx_dma_buff *next; - struct s3c64xx_dma_buff *buff; - struct pl080s_lli *lli; - unsigned long flags; - int ret; - - WARN_ON(!chan); - if (!chan) - return -EINVAL; - - buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC); - if (!buff) { - printk(KERN_ERR "%s: no memory for buffer\n", __func__); - return -ENOMEM; - } - - lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma); - if (!lli) { - printk(KERN_ERR "%s: no memory for lli\n", __func__); - ret = -ENOMEM; - goto err_buff; - } - - pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n", - __func__, buff, data, lli, (u32)buff->lli_dma, size); - - buff->lli = lli; - buff->pw = id; - - s3c64xx_dma_fill_lli(chan, lli, data, size); - - local_irq_save(flags); - - if ((next = chan->next) != NULL) { - struct s3c64xx_dma_buff *end = chan->end; - struct pl080s_lli *endlli = end->lli; - - pr_debug("enquing onto channel\n"); - - end->next = buff; - endlli->next_lli = buff->lli_dma; - - if (chan->flags & S3C2410_DMAF_CIRCULAR) { - struct s3c64xx_dma_buff *curr = chan->curr; - lli->next_lli = curr->lli_dma; - } - - if (next == chan->curr) { - writel(buff->lli_dma, chan->regs + PL080_CH_LLI); - chan->next = buff; - } - - show_lli(endlli); - chan->end = buff; - } else { - pr_debug("enquing onto empty channel\n"); - - chan->curr = buff; - chan->next = buff; - chan->end = buff; - - s3c64xx_lli_to_regs(chan, lli); - } - - local_irq_restore(flags); - - show_lli(lli); - - dbg_showchan(chan); - dbg_showbuffs(chan); - return 0; - -err_buff: - kfree(buff); - return ret; -} - -EXPORT_SYMBOL(s3c2410_dma_enqueue); - - -int s3c2410_dma_devconfig(enum dma_ch channel, - enum dma_data_direction source, - unsigned long devaddr) -{ - struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); - u32 peripheral; - u32 config = 0; - - pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n", - __func__, channel, source, devaddr, chan); - - WARN_ON(!chan); - if (!chan) - return -EINVAL; - - peripheral = (chan->peripheral & 0xf); - chan->source = source; - chan->dev_addr = devaddr; - - pr_debug("%s: peripheral %d\n", __func__, peripheral); - - switch (source) { - case DMA_FROM_DEVICE: - config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT; - config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT; - break; - case DMA_TO_DEVICE: - config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT; - config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT; - break; - default: - printk(KERN_ERR "%s: bad source\n", __func__); - return -EINVAL; - } - - /* allow TC and ERR interrupts */ - config |= PL080_CONFIG_TC_IRQ_MASK; - config |= PL080_CONFIG_ERR_IRQ_MASK; - - pr_debug("%s: config %08x\n", __func__, config); - - writel(config, chan->regs + PL080S_CH_CONFIG); - - return 0; -} -EXPORT_SYMBOL(s3c2410_dma_devconfig); - - -int s3c2410_dma_getposition(enum dma_ch channel, - dma_addr_t *src, dma_addr_t *dst) -{ - struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); - - WARN_ON(!chan); - if (!chan) - return -EINVAL; - - if (src != NULL) - *src = readl(chan->regs + PL080_CH_SRC_ADDR); - - if (dst != NULL) - *dst = readl(chan->regs + PL080_CH_DST_ADDR); - - return 0; -} -EXPORT_SYMBOL(s3c2410_dma_getposition); - -/* s3c2410_request_dma - * - * get control of an dma channel -*/ - -int s3c2410_dma_request(enum dma_ch channel, - struct s3c2410_dma_client *client, - void *dev) -{ - struct s3c2410_dma_chan *chan; - unsigned long flags; - - pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", - channel, client->name, dev); - - local_irq_save(flags); - - chan = s3c64xx_dma_map_channel(channel); - if (chan == NULL) { - local_irq_restore(flags); - return -EBUSY; - } - - dbg_showchan(chan); - - chan->client = client; - chan->in_use = 1; - chan->peripheral = channel; - - local_irq_restore(flags); - - /* need to setup */ - - pr_debug("%s: channel initialised, %p\n", __func__, chan); - - return chan->number | DMACH_LOW_LEVEL; -} - -EXPORT_SYMBOL(s3c2410_dma_request); - -/* s3c2410_dma_free - * - * release the given channel back to the system, will stop and flush - * any outstanding transfers, and ensure the channel is ready for the - * next claimant. - * - * Note, although a warning is currently printed if the freeing client - * info is not the same as the registrant's client info, the free is still - * allowed to go through. -*/ - -int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client) -{ - struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); - unsigned long flags; - - if (chan == NULL) - return -EINVAL; - - local_irq_save(flags); - - if (chan->client != client) { - printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", - channel, chan->client, client); - } - - /* sort out stopping and freeing the channel */ - - - chan->client = NULL; - chan->in_use = 0; - - if (!(channel & DMACH_LOW_LEVEL)) - s3c_dma_chan_map[channel] = NULL; - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_free); - -static irqreturn_t s3c64xx_dma_irq(int irq, void *pw) -{ - struct s3c64xx_dmac *dmac = pw; - struct s3c2410_dma_chan *chan; - enum s3c2410_dma_buffresult res; - u32 tcstat, errstat; - u32 bit; - int offs; - - tcstat = readl(dmac->regs + PL080_TC_STATUS); - errstat = readl(dmac->regs + PL080_ERR_STATUS); - - for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) { - struct s3c64xx_dma_buff *buff; - - if (!(errstat & bit) && !(tcstat & bit)) - continue; - - chan = dmac->channels + offs; - res = S3C2410_RES_ERR; - - if (tcstat & bit) { - writel(bit, dmac->regs + PL080_TC_CLEAR); - res = S3C2410_RES_OK; - } - - if (errstat & bit) - writel(bit, dmac->regs + PL080_ERR_CLEAR); - - /* 'next' points to the buffer that is next to the - * currently active buffer. - * For CIRCULAR queues, 'next' will be same as 'curr' - * when 'end' is the active buffer. - */ - buff = chan->curr; - while (buff && buff != chan->next - && buff->next != chan->next) - buff = buff->next; - - if (!buff) - BUG(); - - if (buff == chan->next) - buff = chan->end; - - s3c64xx_dma_bufffdone(chan, buff, res); - - /* Free the node and update curr, if non-circular queue */ - if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) { - chan->curr = buff->next; - s3c64xx_dma_freebuff(buff); - } - - /* Update 'next' */ - buff = chan->next; - if (chan->next == chan->end) { - chan->next = chan->curr; - if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) - chan->end = NULL; - } else { - chan->next = buff->next; - } - } - - return IRQ_HANDLED; -} - -static struct bus_type dma_subsys = { - .name = "s3c64xx-dma", - .dev_name = "s3c64xx-dma", -}; - -static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, - int irq, unsigned int base) -{ - struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno]; - struct s3c64xx_dmac *dmac; - char clkname[16]; - void __iomem *regs; - void __iomem *regptr; - int err, ch; - - dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL); - if (!dmac) { - printk(KERN_ERR "%s: failed to alloc mem\n", __func__); - return -ENOMEM; - } - - dmac->dev.id = chno / 8; - dmac->dev.bus = &dma_subsys; - - err = device_register(&dmac->dev); - if (err) { - printk(KERN_ERR "%s: failed to register device\n", __func__); - goto err_alloc; - } - - regs = ioremap(base, 0x200); - if (!regs) { - printk(KERN_ERR "%s: failed to ioremap()\n", __func__); - err = -ENXIO; - goto err_dev; - } - - snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id); - - dmac->clk = clk_get(NULL, clkname); - if (IS_ERR(dmac->clk)) { - printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname); - err = PTR_ERR(dmac->clk); - goto err_map; - } - - clk_enable(dmac->clk); - - dmac->regs = regs; - dmac->chanbase = chbase; - dmac->channels = chptr; - - err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac); - if (err < 0) { - printk(KERN_ERR "%s: failed to get irq\n", __func__); - goto err_clk; - } - - regptr = regs + PL080_Cx_BASE(0); - - for (ch = 0; ch < 8; ch++, chptr++) { - pr_debug("%s: registering DMA %d (%p)\n", - __func__, chno + ch, regptr); - - chptr->bit = 1 << ch; - chptr->number = chno + ch; - chptr->dmac = dmac; - chptr->regs = regptr; - regptr += PL080_Cx_STRIDE; - } - - /* for the moment, permanently enable the controller */ - writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG); - - printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n", - irq, regs, chno, chno+8); - - return 0; - -err_clk: - clk_disable(dmac->clk); - clk_put(dmac->clk); -err_map: - iounmap(regs); -err_dev: - device_unregister(&dmac->dev); -err_alloc: - kfree(dmac); - return err; -} - -static int __init s3c64xx_dma_init(void) -{ - int ret; - - printk(KERN_INFO "%s: Registering DMA channels\n", __func__); - - dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0); - if (!dma_pool) { - printk(KERN_ERR "%s: failed to create pool\n", __func__); - return -ENOMEM; - } - - ret = subsys_system_register(&dma_subsys, NULL); - if (ret) { - printk(KERN_ERR "%s: failed to create subsys\n", __func__); - return -ENOMEM; - } - - /* Set all DMA configuration to be DMA, not SDMA */ - writel(0xffffff, S3C64XX_SDMA_SEL); - - /* Register standard DMA controllers */ - s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); - s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000); - - return 0; -} - -arch_initcall(s3c64xx_dma_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/crag6410.h deleted file mode 100644 index 4cb2f951..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/crag6410.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Cragganmore 6410 shared definitions - * - * Copyright 2011 Wolfson Microelectronics plc - * Mark Brown <broonie@opensource.wolfsonmicro.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef MACH_CRAG6410_H -#define MACH_CRAG6410_H - -#include <linux/gpio.h> - -#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START -#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) -#define CODEC_IRQ_BASE (IRQ_BOARD_START + 128) - -#define PCA935X_GPIO_BASE GPIO_BOARD_START -#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) -#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32) -#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64) -#define MMGPIO_GPIO_BASE (GPIO_BOARD_START + 96) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/debug-macro.S deleted file mode 100644 index c0c076a9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/debug-macro.S +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-s3c6400/include/mach/debug-macro.S - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* pull in the relevant register and map files. */ - -#include <mach/map.h> -#include <plat/regs-serial.h> - - /* note, for the boot process to work we have to keep the UART - * virtual address aligned to an 1MiB boundary for the L1 - * mapping the head code makes. We keep the UART virtual address - * aligned and add in the offset when we load the value here. - */ - - .macro addruart, rp, rv, tmp - ldr \rp, = S3C_PA_UART - ldr \rv, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) -#if CONFIG_DEBUG_S3C_UART != 0 - add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) - add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) -#endif - .endm - -/* include the reset of the code which will do the work, we're only - * compiling for a single cpu processor type so the default of s3c2440 - * will be fine with us. - */ - -#include <plat/debug-macro.S> diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/dma.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/dma.h deleted file mode 100644 index fe1a98cf..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/dma.h +++ /dev/null @@ -1,131 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/dma.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C6400 - DMA support - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H __FILE__ - -#define S3C_DMA_CHANNELS (16) - -/* see mach-s3c2410/dma.h for notes on dma channel numbers */ - -/* Note, for the S3C64XX architecture we keep the DMACH_ - * defines in the order they are allocated to [S]DMA0/[S]DMA1 - * so that is easy to do DHACH_ -> DMA controller conversion - */ -enum dma_ch { - /* DMA0/SDMA0 */ - DMACH_UART0 = 0, - DMACH_UART0_SRC2, - DMACH_UART1, - DMACH_UART1_SRC2, - DMACH_UART2, - DMACH_UART2_SRC2, - DMACH_UART3, - DMACH_UART3_SRC2, - DMACH_PCM0_TX, - DMACH_PCM0_RX, - DMACH_I2S0_OUT, - DMACH_I2S0_IN, - DMACH_SPI0_TX, - DMACH_SPI0_RX, - DMACH_HSI_I2SV40_TX, - DMACH_HSI_I2SV40_RX, - - /* DMA1/SDMA1 */ - DMACH_PCM1_TX = 16, - DMACH_PCM1_RX, - DMACH_I2S1_OUT, - DMACH_I2S1_IN, - DMACH_SPI1_TX, - DMACH_SPI1_RX, - DMACH_AC97_PCMOUT, - DMACH_AC97_PCMIN, - DMACH_AC97_MICIN, - DMACH_PWM, - DMACH_IRDA, - DMACH_EXTERNAL, - DMACH_RES1, - DMACH_RES2, - DMACH_SECURITY_RX, /* SDMA1 only */ - DMACH_SECURITY_TX, /* SDMA1 only */ - DMACH_MAX /* the end */ -}; - -static inline bool samsung_dma_has_circular(void) -{ - return true; -} - -static inline bool samsung_dma_is_dmadev(void) -{ - return false; -} -#define S3C2410_DMAF_CIRCULAR (1 << 0) - -#include <plat/dma.h> - -#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ - -struct s3c64xx_dma_buff; - -/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor - * @next: Pointer to next buffer in queue or ring. - * @pw: Client provided identifier - * @lli: Pointer to hardware descriptor this buffer is associated with. - * @lli_dma: Hardare address of the descriptor. - */ -struct s3c64xx_dma_buff { - struct s3c64xx_dma_buff *next; - - void *pw; - struct pl080s_lli *lli; - dma_addr_t lli_dma; -}; - -struct s3c64xx_dmac; - -struct s3c2410_dma_chan { - unsigned char number; /* number of this dma channel */ - unsigned char in_use; /* channel allocated */ - unsigned char bit; /* bit for enable/disable/etc */ - unsigned char hw_width; - unsigned char peripheral; - - unsigned int flags; - enum dma_data_direction source; - - - dma_addr_t dev_addr; - - struct s3c2410_dma_client *client; - struct s3c64xx_dmac *dmac; /* pointer to controller */ - - void __iomem *regs; - - /* cdriver callbacks */ - s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ - s3c2410_dma_opfn_t op_fn; /* channel op callback */ - - /* buffer list and information */ - struct s3c64xx_dma_buff *curr; /* current dma buffer */ - struct s3c64xx_dma_buff *next; /* next buffer to load */ - struct s3c64xx_dma_buff *end; /* end of queue */ - - /* note, when channel is running in circular mode, curr is the - * first buffer enqueued, end is the last and curr is where the - * last buffer-done event is set-at. The buffers are not freed - * and the last buffer hardware descriptor points back to the - * first. - */ -}; - -#include <plat/dma-core.h> - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/gpio.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/gpio.h deleted file mode 100644 index 8b540c42..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/gpio.h +++ /dev/null @@ -1,93 +0,0 @@ -/* arch/arm/mach-s3c6400/include/mach/gpio.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C6400 - GPIO lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* GPIO bank sizes */ -#define S3C64XX_GPIO_A_NR (8) -#define S3C64XX_GPIO_B_NR (7) -#define S3C64XX_GPIO_C_NR (8) -#define S3C64XX_GPIO_D_NR (5) -#define S3C64XX_GPIO_E_NR (5) -#define S3C64XX_GPIO_F_NR (16) -#define S3C64XX_GPIO_G_NR (7) -#define S3C64XX_GPIO_H_NR (10) -#define S3C64XX_GPIO_I_NR (16) -#define S3C64XX_GPIO_J_NR (12) -#define S3C64XX_GPIO_K_NR (16) -#define S3C64XX_GPIO_L_NR (15) -#define S3C64XX_GPIO_M_NR (6) -#define S3C64XX_GPIO_N_NR (16) -#define S3C64XX_GPIO_O_NR (16) -#define S3C64XX_GPIO_P_NR (15) -#define S3C64XX_GPIO_Q_NR (9) - -/* GPIO bank numbes */ - -/* CONFIG_S3C_GPIO_SPACE allows the user to select extra - * space for debugging purposes so that any accidental - * change from one gpio bank to another can be caught. -*/ - -#define S3C64XX_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) - -enum s3c_gpio_number { - S3C64XX_GPIO_A_START = 0, - S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), - S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), - S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), - S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), - S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), - S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), - S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), - S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), - S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), - S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), - S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), - S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), - S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), - S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), - S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), - S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), -}; - -/* S3C64XX GPIO number definitions. */ - -#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) -#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) -#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) -#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) -#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) -#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) -#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) -#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) -#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) -#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) -#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) -#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) -#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) -#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) -#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) -#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) -#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) - -/* the end of the S3C64XX specific gpios */ -#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) -#define S3C_GPIO_END S3C64XX_GPIO_END - -/* define the number of gpios we need to the one after the GPQ() range */ -#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) - -#define BOARD_NR_GPIOS (16 + CONFIG_SAMSUNG_GPIO_EXTRA) - -#define ARCH_NR_GPIOS (GPIO_BOARD_START + BOARD_NR_GPIOS) diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/hardware.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/hardware.h deleted file mode 100644 index 862d033e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/hardware.h +++ /dev/null @@ -1,16 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C6400 - Hardware support - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H __FILE__ - -/* currently nothing here, placeholder */ - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/irqs.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/irqs.h deleted file mode 100644 index 96d60e0d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ /dev/null @@ -1,193 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - IRQ support - */ - -#ifndef __ASM_MACH_S3C64XX_IRQS_H -#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - * - * note, since we're using the VICs, our start must be a - * mulitple of 32 to allow the common code to work - */ - -#define S3C_IRQ_OFFSET (32) - -#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) - -#define IRQ_VIC0_BASE S3C_IRQ(0) -#define IRQ_VIC1_BASE S3C_IRQ(32) - -/* VIC based IRQs */ - -#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) -#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) - -/* VIC0 */ - -#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) -#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) -#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) -#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) -#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) -#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) -#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) -#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) -#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) -#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) -#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) -#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) -#define IRQ_2D S3C64XX_IRQ_VIC0(11) -#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) -#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) -#define IRQ_BATF S3C64XX_IRQ_VIC0(14) -#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) -#define IRQ_MFC S3C64XX_IRQ_VIC0(16) -#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) -#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) -#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) -#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) -#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) -#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) -#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) -#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) -#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) -#define IRQ_WDT S3C64XX_IRQ_VIC0(26) -#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) -#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) -#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) -#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) -#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) - -/* VIC1 */ - -#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) -#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) -#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) -#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) -#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) -#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) -#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) -#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) -#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) -#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) -#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) -#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) -#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) -#define IRQ_NFC S3C64XX_IRQ_VIC1(13) -#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) -#define IRQ_USBH S3C64XX_IRQ_VIC1(15) -#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) -#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) -#define IRQ_IIC S3C64XX_IRQ_VIC1(18) -#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) -#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) -#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) -#define IRQ_MSM S3C64XX_IRQ_VIC1(22) -#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) -#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) -#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) -#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ -#define IRQ_OTG S3C64XX_IRQ_VIC1(26) -#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) -#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) -#define IRQ_SEC S3C64XX_IRQ_VIC1(29) -#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) -#define IRQ_TC IRQ_PENDN -#define IRQ_ADC S3C64XX_IRQ_VIC1(31) - -#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) - -#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) -#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) -#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) -#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) -#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) - -/* compatibility for device defines */ - -#define IRQ_IIC1 IRQ_S3C6410_IIC1 - -/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series - * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE - * which we place after the pair of VICs. */ - -#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) - -#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) -#define IRQ_EINT(x) S3C_EINT(x) -#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) - -/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) - * that they are sourced from the GPIO pins but with a different scheme for - * priority and source indication. - * - * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO - * interrupts, but for historical reasons they are kept apart from these - * next interrupts. - * - * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the - * machine specific support files. - */ - -#define IRQ_EINT_GROUP1_NR (15) -#define IRQ_EINT_GROUP2_NR (8) -#define IRQ_EINT_GROUP3_NR (5) -#define IRQ_EINT_GROUP4_NR (14) -#define IRQ_EINT_GROUP5_NR (7) -#define IRQ_EINT_GROUP6_NR (10) -#define IRQ_EINT_GROUP7_NR (16) -#define IRQ_EINT_GROUP8_NR (15) -#define IRQ_EINT_GROUP9_NR (9) - -#define IRQ_EINT_GROUP_BASE S3C_EINT(28) -#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) -#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) -#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) -#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) -#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) -#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) -#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) -#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) -#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) - -#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) - -/* Define a group of interrupts for board-specific use (eg, for MFD - * interrupt controllers). */ -#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) - -#ifdef CONFIG_MACH_WLF_CRAGG_6410 -#define IRQ_BOARD_NR 160 -#elif defined(CONFIG_SMDK6410_WM1190_EV1) -#define IRQ_BOARD_NR 64 -#elif defined(CONFIG_SMDK6410_WM1192_EV1) -#define IRQ_BOARD_NR 64 -#else -#define IRQ_BOARD_NR 16 -#endif - -#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) - -/* Set the default NR_IRQS */ - -#define NR_IRQS (IRQ_BOARD_END + 1) - -/* Compatibility */ - -#define IRQ_ONENAND IRQ_ONENAND0 -#define IRQ_I2S0 IRQ_S3C6410_IIS - -#endif /* __ASM_MACH_S3C64XX_IRQS_H */ - diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/map.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/map.h deleted file mode 100644 index 8e2097bb..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/map.h +++ /dev/null @@ -1,125 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/map.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C64XX - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H __FILE__ - -#include <plat/map-base.h> -#include <plat/map-s3c.h> - -/* - * Post-mux Chip Select Regions Xm0CSn_ - * These may be used by SROM, NAND or CF depending on settings - */ - -#define S3C64XX_PA_XM0CSN0 (0x10000000) -#define S3C64XX_PA_XM0CSN1 (0x18000000) -#define S3C64XX_PA_XM0CSN2 (0x20000000) -#define S3C64XX_PA_XM0CSN3 (0x28000000) -#define S3C64XX_PA_XM0CSN4 (0x30000000) -#define S3C64XX_PA_XM0CSN5 (0x38000000) - -/* HSMMC units */ -#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) -#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) -#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) -#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) - -#define S3C_PA_UART (0x7F005000) -#define S3C_PA_UART0 (S3C_PA_UART + 0x00) -#define S3C_PA_UART1 (S3C_PA_UART + 0x400) -#define S3C_PA_UART2 (S3C_PA_UART + 0x800) -#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) -#define S3C_UART_OFFSET (0x400) - -/* See notes on UART VA mapping in debug-macro.S */ -#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) - -#define S3C_VA_UART0 S3C_VA_UARTx(0) -#define S3C_VA_UART1 S3C_VA_UARTx(1) -#define S3C_VA_UART2 S3C_VA_UARTx(2) -#define S3C_VA_UART3 S3C_VA_UARTx(3) - -#define S3C64XX_PA_SROM (0x70000000) - -#define S3C64XX_PA_ONENAND0 (0x70100000) -#define S3C64XX_PA_ONENAND0_BUF (0x20000000) -#define S3C64XX_SZ_ONENAND0_BUF (SZ_64M) - -/* NAND and OneNAND1 controllers occupy the same register region - (depending on SoC POP version) */ -#define S3C64XX_PA_ONENAND1 (0x70200000) -#define S3C64XX_PA_ONENAND1_BUF (0x28000000) -#define S3C64XX_SZ_ONENAND1_BUF (SZ_64M) - -#define S3C64XX_PA_NAND (0x70200000) -#define S3C64XX_PA_FB (0x77100000) -#define S3C64XX_PA_USB_HSOTG (0x7C000000) -#define S3C64XX_PA_WATCHDOG (0x7E004000) -#define S3C64XX_PA_RTC (0x7E005000) -#define S3C64XX_PA_KEYPAD (0x7E00A000) -#define S3C64XX_PA_ADC (0x7E00B000) -#define S3C64XX_PA_SYSCON (0x7E00F000) -#define S3C64XX_PA_AC97 (0x7F001000) -#define S3C64XX_PA_IIS0 (0x7F002000) -#define S3C64XX_PA_IIS1 (0x7F003000) -#define S3C64XX_PA_TIMER (0x7F006000) -#define S3C64XX_PA_IIC0 (0x7F004000) -#define S3C64XX_PA_SPI0 (0x7F00B000) -#define S3C64XX_PA_SPI1 (0x7F00C000) -#define S3C64XX_PA_PCM0 (0x7F009000) -#define S3C64XX_PA_PCM1 (0x7F00A000) -#define S3C64XX_PA_IISV4 (0x7F00D000) -#define S3C64XX_PA_IIC1 (0x7F00F000) - -#define S3C64XX_PA_GPIO (0x7F008000) -#define S3C64XX_SZ_GPIO SZ_4K - -#define S3C64XX_PA_SDRAM (0x50000000) - -#define S3C64XX_PA_CFCON (0x70300000) - -#define S3C64XX_PA_VIC0 (0x71200000) -#define S3C64XX_PA_VIC1 (0x71300000) - -#define S3C64XX_PA_MODEM (0x74108000) - -#define S3C64XX_PA_USBHOST (0x74300000) - -#define S3C64XX_PA_USB_HSPHY (0x7C100000) - -/* compatibiltiy defines. */ -#define S3C_PA_TIMER S3C64XX_PA_TIMER -#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 -#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 -#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 -#define S3C_PA_IIC S3C64XX_PA_IIC0 -#define S3C_PA_IIC1 S3C64XX_PA_IIC1 -#define S3C_PA_NAND S3C64XX_PA_NAND -#define S3C_PA_ONENAND S3C64XX_PA_ONENAND0 -#define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF -#define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF -#define S3C_PA_FB S3C64XX_PA_FB -#define S3C_PA_USBHOST S3C64XX_PA_USBHOST -#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG -#define S3C_PA_RTC S3C64XX_PA_RTC -#define S3C_PA_WDT S3C64XX_PA_WATCHDOG -#define S3C_PA_SPI0 S3C64XX_PA_SPI0 -#define S3C_PA_SPI1 S3C64XX_PA_SPI1 - -#define SAMSUNG_PA_ADC S3C64XX_PA_ADC -#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON -#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD - -#endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/pm-core.h deleted file mode 100644 index fcf3dcab..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ /dev/null @@ -1,115 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <mach/regs-gpio.h> - -static inline void s3c_pm_debug_init_uart(void) -{ - u32 tmp = __raw_readl(S3C_PCLK_GATE); - - /* As a note, since the S3C64XX UARTs generally have multiple - * clock sources, we simply enable PCLK at the moment and hope - * that the resume settings for the UART are suitable for the - * use with PCLK. - */ - - tmp |= S3C_CLKCON_PCLK_UART0; - tmp |= S3C_CLKCON_PCLK_UART1; - tmp |= S3C_CLKCON_PCLK_UART2; - tmp |= S3C_CLKCON_PCLK_UART3; - - __raw_writel(tmp, S3C_PCLK_GATE); - udelay(10); -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - /* VIC should have already been taken care of */ - - /* clear any pending EINT0 interrupts */ - __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ -} - -static inline void s3c_pm_arch_show_resume_irqs(void) -{ -} - -/* make these defines, we currently do not have any need to change - * the IRQ wake controls depending on the CPU we are running on */ - -#define s3c_irqwake_eintallow ((1 << 28) - 1) -#define s3c_irqwake_intallow (~0) - -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ - u32 ucon = __raw_readl(regs + S3C2410_UCON); - u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; - u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; - u32 new_ucon; - u32 delta; - - /* S3C64XX UART blocks only support level interrupts, so ensure that - * when we restore unused UART blocks we force the level interrupt - * settigs. */ - save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; - - /* We have a constraint on changing the clock type of the UART - * between UCLKx and PCLK, so ensure that when we restore UCON - * that the CLK field is correctly modified if the bootloader - * has changed anything. - */ - if (ucon_clk != save_clk) { - new_ucon = save->ucon; - delta = ucon_clk ^ save_clk; - - /* change from UCLKx => wrong PCLK, - * either UCLK can be tested for by a bit-test - * with UCLK0 */ - if (ucon_clk & S3C6400_UCON_UCLK0 && - !(save_clk & S3C6400_UCON_UCLK0) && - delta & S3C6400_UCON_PCLK2) { - new_ucon &= ~S3C6400_UCON_UCLK0; - } else if (delta == S3C6400_UCON_PCLK2) { - /* as an precaution, don't change from - * PCLK2 => PCLK or vice-versa */ - new_ucon ^= S3C6400_UCON_PCLK2; - } - - S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", - ucon, new_ucon, save->ucon); - save->ucon = new_ucon; - } -} - -static inline void s3c_pm_restored_gpios(void) -{ - /* ensure sleep mode has been cleared from the system */ - - __raw_writel(0, S3C64XX_SLPEN); -} - -static inline void samsung_pm_saved_gpios(void) -{ - /* turn on the sleep mode and keep it there, as it seems that during - * suspend the xCON registers get re-set and thus you can end up with - * problems between going to sleep and resuming. - */ - - __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-clock.h deleted file mode 100644 index 05332b99..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ /dev/null @@ -1,162 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_CLOCK_H -#define __PLAT_REGS_CLOCK_H __FILE__ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_APLL_LOCK S3C_CLKREG(0x00) -#define S3C_MPLL_LOCK S3C_CLKREG(0x04) -#define S3C_EPLL_LOCK S3C_CLKREG(0x08) -#define S3C_APLL_CON S3C_CLKREG(0x0C) -#define S3C_MPLL_CON S3C_CLKREG(0x10) -#define S3C_EPLL_CON0 S3C_CLKREG(0x14) -#define S3C_EPLL_CON1 S3C_CLKREG(0x18) -#define S3C_CLK_SRC S3C_CLKREG(0x1C) -#define S3C_CLK_DIV0 S3C_CLKREG(0x20) -#define S3C_CLK_DIV1 S3C_CLKREG(0x24) -#define S3C_CLK_DIV2 S3C_CLKREG(0x28) -#define S3C_CLK_OUT S3C_CLKREG(0x2C) -#define S3C_HCLK_GATE S3C_CLKREG(0x30) -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C_SCLK_GATE S3C_CLKREG(0x38) -#define S3C_MEM0_GATE S3C_CLKREG(0x3C) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) - -/* CLKDIV0 */ -#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) -#define S3C6400_CLKDIV0_PCLK_SHIFT (12) -#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) -#define S3C6400_CLKDIV0_HCLK2_SHIFT (9) -#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) -#define S3C6400_CLKDIV0_HCLK_SHIFT (8) -#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) -#define S3C6400_CLKDIV0_MPLL_SHIFT (4) - -#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) -#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) -#define S3C6400_CLKDIV0_ARM_SHIFT (0) - -/* HCLK GATE Registers */ -#define S3C_CLKCON_HCLK_3DSE (1<<31) -#define S3C_CLKCON_HCLK_UHOST (1<<29) -#define S3C_CLKCON_HCLK_SECUR (1<<28) -#define S3C_CLKCON_HCLK_SDMA1 (1<<27) -#define S3C_CLKCON_HCLK_SDMA0 (1<<26) -#define S3C_CLKCON_HCLK_IROM (1<<25) -#define S3C_CLKCON_HCLK_DDR1 (1<<24) -#define S3C_CLKCON_HCLK_DDR0 (1<<23) -#define S3C_CLKCON_HCLK_MEM1 (1<<22) -#define S3C_CLKCON_HCLK_MEM0 (1<<21) -#define S3C_CLKCON_HCLK_USB (1<<20) -#define S3C_CLKCON_HCLK_HSMMC2 (1<<19) -#define S3C_CLKCON_HCLK_HSMMC1 (1<<18) -#define S3C_CLKCON_HCLK_HSMMC0 (1<<17) -#define S3C_CLKCON_HCLK_MDP (1<<16) -#define S3C_CLKCON_HCLK_DHOST (1<<15) -#define S3C_CLKCON_HCLK_IHOST (1<<14) -#define S3C_CLKCON_HCLK_DMA1 (1<<13) -#define S3C_CLKCON_HCLK_DMA0 (1<<12) -#define S3C_CLKCON_HCLK_JPEG (1<<11) -#define S3C_CLKCON_HCLK_CAMIF (1<<10) -#define S3C_CLKCON_HCLK_SCALER (1<<9) -#define S3C_CLKCON_HCLK_2D (1<<8) -#define S3C_CLKCON_HCLK_TV (1<<7) -#define S3C_CLKCON_HCLK_POST0 (1<<5) -#define S3C_CLKCON_HCLK_ROT (1<<4) -#define S3C_CLKCON_HCLK_LCD (1<<3) -#define S3C_CLKCON_HCLK_TZIC (1<<2) -#define S3C_CLKCON_HCLK_INTC (1<<1) -#define S3C_CLKCON_HCLK_MFC (1<<0) - -/* PCLK GATE Registers */ -#define S3C6410_CLKCON_PCLK_I2C1 (1<<27) -#define S3C6410_CLKCON_PCLK_IIS2 (1<<26) -#define S3C_CLKCON_PCLK_SKEY (1<<24) -#define S3C_CLKCON_PCLK_CHIPID (1<<23) -#define S3C_CLKCON_PCLK_SPI1 (1<<22) -#define S3C_CLKCON_PCLK_SPI0 (1<<21) -#define S3C_CLKCON_PCLK_HSIRX (1<<20) -#define S3C_CLKCON_PCLK_HSITX (1<<19) -#define S3C_CLKCON_PCLK_GPIO (1<<18) -#define S3C_CLKCON_PCLK_IIC (1<<17) -#define S3C_CLKCON_PCLK_IIS1 (1<<16) -#define S3C_CLKCON_PCLK_IIS0 (1<<15) -#define S3C_CLKCON_PCLK_AC97 (1<<14) -#define S3C_CLKCON_PCLK_TZPC (1<<13) -#define S3C_CLKCON_PCLK_TSADC (1<<12) -#define S3C_CLKCON_PCLK_KEYPAD (1<<11) -#define S3C_CLKCON_PCLK_IRDA (1<<10) -#define S3C_CLKCON_PCLK_PCM1 (1<<9) -#define S3C_CLKCON_PCLK_PCM0 (1<<8) -#define S3C_CLKCON_PCLK_PWM (1<<7) -#define S3C_CLKCON_PCLK_RTC (1<<6) -#define S3C_CLKCON_PCLK_WDT (1<<5) -#define S3C_CLKCON_PCLK_UART3 (1<<4) -#define S3C_CLKCON_PCLK_UART2 (1<<3) -#define S3C_CLKCON_PCLK_UART1 (1<<2) -#define S3C_CLKCON_PCLK_UART0 (1<<1) -#define S3C_CLKCON_PCLK_MFC (1<<0) - -/* SCLK GATE Registers */ -#define S3C_CLKCON_SCLK_UHOST (1<<30) -#define S3C_CLKCON_SCLK_MMC2_48 (1<<29) -#define S3C_CLKCON_SCLK_MMC1_48 (1<<28) -#define S3C_CLKCON_SCLK_MMC0_48 (1<<27) -#define S3C_CLKCON_SCLK_MMC2 (1<<26) -#define S3C_CLKCON_SCLK_MMC1 (1<<25) -#define S3C_CLKCON_SCLK_MMC0 (1<<24) -#define S3C_CLKCON_SCLK_SPI1_48 (1<<23) -#define S3C_CLKCON_SCLK_SPI0_48 (1<<22) -#define S3C_CLKCON_SCLK_SPI1 (1<<21) -#define S3C_CLKCON_SCLK_SPI0 (1<<20) -#define S3C_CLKCON_SCLK_DAC27 (1<<19) -#define S3C_CLKCON_SCLK_TV27 (1<<18) -#define S3C_CLKCON_SCLK_SCALER27 (1<<17) -#define S3C_CLKCON_SCLK_SCALER (1<<16) -#define S3C_CLKCON_SCLK_LCD27 (1<<15) -#define S3C_CLKCON_SCLK_LCD (1<<14) -#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) -#define S3C6410_CLKCON_FIMC (1<<13) -#define S3C_CLKCON_SCLK_POST0_27 (1<<12) -#define S3C6400_CLKCON_SCLK_POST1 (1<<11) -#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) -#define S3C_CLKCON_SCLK_POST0 (1<<10) -#define S3C_CLKCON_SCLK_AUDIO1 (1<<9) -#define S3C_CLKCON_SCLK_AUDIO0 (1<<8) -#define S3C_CLKCON_SCLK_SECUR (1<<7) -#define S3C_CLKCON_SCLK_IRDA (1<<6) -#define S3C_CLKCON_SCLK_UART (1<<5) -#define S3C_CLKCON_SCLK_ONENAND (1<<4) -#define S3C_CLKCON_SCLK_MFC (1<<3) -#define S3C_CLKCON_SCLK_CAM (1<<2) -#define S3C_CLKCON_SCLK_JPEG (1<<1) - -/* CLKSRC */ - -#define S3C6400_CLKSRC_APLL_MOUT (1 << 0) -#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) -#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) -#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) -#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) -#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) -#define S3C6400_CLKSRC_MFC (1 << 4) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h deleted file mode 100644 index 82342f6f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h +++ /dev/null @@ -1,25 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - GPIO memory port register definitions - */ - -#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H -#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ - -#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) -#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) - -#define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0) -#define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4) -#define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8) - -#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) -#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4) - -#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */ - diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h deleted file mode 100644 index 81f7f6e6..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h +++ /dev/null @@ -1,187 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - GPIO register definitions - */ - -#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H -#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ - -/* Base addresses for each of the banks */ - -#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) - -#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) -#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) -#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) -#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) -#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) -#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) -#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) -#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) -#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) -#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) -#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) -#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) -#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) -#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) -#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) -#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) -#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) - -/* SPCON */ - -#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) - -#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) -#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) - -#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) -#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) - -#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) -#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) - -#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) -#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) - -#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) -#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) - -#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) - -#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) - -#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) - -#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) -#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) -#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) -#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) -#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) - -#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) -#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) -#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) -#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) -#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) - -#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) -#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) -#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) -#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) -#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) - -#define S3C64XX_SPCON_USBH_DMPD (1 << 7) -#define S3C64XX_SPCON_USBH_DPPD (1 << 6) -#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) -#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) -#define S3C64XX_SPCON_USBH_SUSPND (1 << 3) - -#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) -#define S3C64XX_SPCON_LCD_SEL_SHIFT (0) -#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) -#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) -#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) - - -/* External interrupt registers */ - -#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) -#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) -#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) -#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) -#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) - -#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) -#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) -#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) -#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) -#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) - -#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) -#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) -#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) -#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) -#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) - -#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) -#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) -#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) -#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) -#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) - -#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) -#define S3C64XX_PRIORITY_ARB(x) (1 << (x)) - -#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) -#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) - -#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) -#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) -#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) -#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) -#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) -#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) - -#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) -#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) - -/* GPIO sleep configuration */ - -#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) - -#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) -#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) - -#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) -#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) -#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) -#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) - -#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) -#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) -#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) -#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) - - -#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) - -#define S3C64XX_SLPEN_USE_xSLP (1 << 0) -#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) - -#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ - diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-irq.h deleted file mode 100644 index bcce68a0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-irq.h +++ /dev/null @@ -1,20 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C64XX - IRQ register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_IRQ_H -#define __ASM_ARCH_REGS_IRQ_H __FILE__ - -#include <asm/hardware/vic.h> - -#endif /* __ASM_ARCH_6400_REGS_IRQ_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-modem.h deleted file mode 100644 index 49f7759d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-modem.h +++ /dev/null @@ -1,31 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C64XX - modem block registers - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C64XX_REGS_MODEM_H -#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__ - -#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) - -#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0) -#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4) -#define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8) -#define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC) -#define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10) -#define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14) -#define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18) - -#define MIFPCON_INT2M_LEVEL (1 << 4) -#define MIFPCON_LCD_BYPASS (1 << 3) - -#endif /* __PLAT_S3C64XX_REGS_MODEM_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-srom.h deleted file mode 100644 index 756731b3..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-srom.h +++ /dev/null @@ -1,59 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h - * - * Copyright 2009 Andy Green <andy@warmcat.com> - * - * S3C64XX SROM definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_SROM_H -#define __PLAT_REGS_SROM_H __FILE__ - -#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) - -#define S3C64XX_SROM_BW S3C64XX_SROMREG(0) -#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) -#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) -#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) -#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) -#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) -#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) - -/* - * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 - */ - -#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 -#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 -#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 -#define S3C64XX_SROM_BW__CS_MASK 0xf - -#define S3C64XX_SROM_BW__NCS0__SHIFT 0 -#define S3C64XX_SROM_BW__NCS1__SHIFT 4 -#define S3C64XX_SROM_BW__NCS2__SHIFT 8 -#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc -#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 - -/* - * applies to same to BCS0 - BCS4 - */ - -#define S3C64XX_SROM_BCX__PMC__SHIFT 0 -#define S3C64XX_SROM_BCX__PMC__MASK 3 -#define S3C64XX_SROM_BCX__TACP__SHIFT 4 -#define S3C64XX_SROM_BCX__TACP__MASK 0xf -#define S3C64XX_SROM_BCX__TCAH__SHIFT 8 -#define S3C64XX_SROM_BCX__TCAH__MASK 0xf -#define S3C64XX_SROM_BCX__TCOH__SHIFT 12 -#define S3C64XX_SROM_BCX__TCOH__MASK 0xf -#define S3C64XX_SROM_BCX__TACC__SHIFT 16 -#define S3C64XX_SROM_BCX__TACC__MASK 0x1f -#define S3C64XX_SROM_BCX__TCOS__SHIFT 24 -#define S3C64XX_SROM_BCX__TCOS__MASK 0xf -#define S3C64XX_SROM_BCX__TACS__SHIFT 28 -#define S3C64XX_SROM_BCX__TACS__MASK 0xf - -#endif /* _PLAT_REGS_SROM_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-sys.h deleted file mode 100644 index b91e0209..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-sys.h +++ /dev/null @@ -1,31 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX system register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_SYS_H -#define __PLAT_REGS_SYS_H __FILE__ - -#define S3C_SYSREG(x) (S3C_VA_SYS + (x)) - -#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100) -#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) -#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) - -#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110) - -#define S3C64XX_OTHERS S3C_SYSREG(0x900) - -#define S3C64XX_OTHERS_USBMASK (1 << 16) -#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6) - -#endif /* _PLAT_REGS_SYS_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h deleted file mode 100644 index 270d96ac..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h +++ /dev/null @@ -1,116 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C64XX - syscon power and sleep control registers - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H -#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__ - -#define S3C64XX_PWR_CFG S3C_SYSREG(0x804) - -#define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17) -#define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16) -#define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15) -#define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14) -#define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13) -#define S3C64XX_PWRCFG_TS_DISABLE (1 << 12) -#define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11) -#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10) -#define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9) -#define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8) -#define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7) - -#define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5) -#define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5) -#define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5) -#define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5) -#define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5) -#define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5) - -#define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3) -#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3) -#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3) -#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3) -#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3) - -#define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2) -#define S3C64XX_PWRCFG_OSC27_EN (1 << 0) - -#define S3C64XX_EINT_MASK S3C_SYSREG(0x808) - -#define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810) - -#define S3C64XX_NORMALCFG_IROM_ON (1 << 30) -#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16) -#define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15) -#define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14) -#define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13) -#define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12) -#define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10) -#define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9) - -#define S3C64XX_STOP_CFG S3C_SYSREG(0x814) - -#define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29) -#define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20) -#define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17) -#define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8) -#define S3C64XX_STOPCFG_OSC_EN (1 << 0) - -#define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818) - -#define S3C64XX_SLEEPCFG_OSC_EN (1 << 0) - -#define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c) - -#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6) -#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5) -#define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4) -#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3) -#define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2) -#define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1) -#define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0) - -#define S3C64XX_OSC_STABLE S3C_SYSREG(0x824) -#define S3C64XX_PWR_STABLE S3C_SYSREG(0x828) - -#define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908) - -#define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11) -#define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10) -#define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9) -#define S3C64XX_WAKEUPSTAT_HSI (1 << 8) -#define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6) -#define S3C64XX_WAKEUPSTAT_MSM (1 << 5) -#define S3C64XX_WAKEUPSTAT_KEY (1 << 4) -#define S3C64XX_WAKEUPSTAT_TS (1 << 3) -#define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2) -#define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1) -#define S3C64XX_WAKEUPSTAT_EINT (1 << 0) - -#define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c) - -#define S3C64XX_BLKPWRSTAT_G (1 << 7) -#define S3C64XX_BLKPWRSTAT_ETM (1 << 6) -#define S3C64XX_BLKPWRSTAT_S (1 << 5) -#define S3C64XX_BLKPWRSTAT_F (1 << 4) -#define S3C64XX_BLKPWRSTAT_P (1 << 3) -#define S3C64XX_BLKPWRSTAT_I (1 << 2) -#define S3C64XX_BLKPWRSTAT_V (1 << 1) -#define S3C64XX_BLKPWRSTAT_TOP (1 << 0) - -#define S3C64XX_INFORM0 S3C_SYSREG(0xA00) -#define S3C64XX_INFORM1 S3C_SYSREG(0xA04) -#define S3C64XX_INFORM2 S3C_SYSREG(0xA08) -#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C) - -#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h deleted file mode 100644 index 9d0c43b4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h +++ /dev/null @@ -1,18 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h - * - * Copyright (C) 2009 Samsung Electronics Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __S3C64XX_PLAT_SPI_CLKS_H -#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__ - -#define S3C64XX_SPI_SRCCLK_PCLK 0 -#define S3C64XX_SPI_SRCCLK_SPIBUS 1 -#define S3C64XX_SPI_SRCCLK_48M 2 - -#endif /* __S3C64XX_PLAT_SPI_CLKS_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/tick.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/tick.h deleted file mode 100644 index ebe18a94..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/tick.h +++ /dev/null @@ -1,29 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/tick.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C64XX - Timer tick support definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TICK_H -#define __ASM_ARCH_TICK_H __FILE__ - -/* note, the timer interrutps turn up in 2 places, the vic and then - * the timer block. We take the VIC as the base at the moment. - */ -static inline u32 s3c24xx_ostimer_pending(void) -{ - u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); - return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); -} - -#define TICK_MAX (0xffffffff) - -#endif /* __ASM_ARCH_6400_TICK_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/timex.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/timex.h deleted file mode 100644 index fb2e8cd4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/timex.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c64xx/include/mach/timex.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C6400 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - -#define CLOCK_TICK_RATE 12000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/uncompress.h deleted file mode 100644 index c6a82a20..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/include/mach/uncompress.h +++ /dev/null @@ -1,28 +0,0 @@ -/* arch/arm/mach-s3c6400/include/mach/uncompress.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C6400 - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/map.h> -#include <plat/uncompress.h> - -static void arch_detect_cpu(void) -{ - /* we do not need to do any cpu detection here at the moment. */ - fifo_mask = S3C2440_UFSTAT_TXMASK; - fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/irq-pm.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/irq-pm.c deleted file mode 100644 index 0c7e1d96..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/irq-pm.c +++ /dev/null @@ -1,111 +0,0 @@ -/* arch/arm/plat-s3c64xx/irq-pm.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Interrupt handling Power Management - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/syscore_ops.h> -#include <linux/interrupt.h> -#include <linux/serial_core.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <mach/map.h> - -#include <plat/regs-serial.h> -#include <plat/regs-timer.h> -#include <mach/regs-gpio.h> -#include <plat/cpu.h> -#include <plat/pm.h> - -/* We handled all the IRQ types in this code, to save having to make several - * small files to handle each different type separately. Having the EINT_GRP - * code here shouldn't be as much bloat as the IRQ table space needed when - * they are enabled. The added benefit is we ensure that these registers are - * in the same state as we suspended. - */ - -static struct sleep_save irq_save[] = { - SAVE_ITEM(S3C64XX_PRIORITY), - SAVE_ITEM(S3C64XX_EINT0CON0), - SAVE_ITEM(S3C64XX_EINT0CON1), - SAVE_ITEM(S3C64XX_EINT0FLTCON0), - SAVE_ITEM(S3C64XX_EINT0FLTCON1), - SAVE_ITEM(S3C64XX_EINT0FLTCON2), - SAVE_ITEM(S3C64XX_EINT0FLTCON3), - SAVE_ITEM(S3C64XX_EINT0MASK), - SAVE_ITEM(S3C64XX_TINT_CSTAT), -}; - -static struct irq_grp_save { - u32 fltcon; - u32 con; - u32 mask; -} eint_grp_save[5]; - -static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; - -static int s3c64xx_irq_pm_suspend(void) -{ - struct irq_grp_save *grp = eint_grp_save; - int i; - - S3C_PMDBG("%s: suspending IRQs\n", __func__); - - s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); - - for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) - irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); - - for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { - grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); - grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); - grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); - } - - return 0; -} - -static void s3c64xx_irq_pm_resume(void) -{ - struct irq_grp_save *grp = eint_grp_save; - int i; - - S3C_PMDBG("%s: resuming IRQs\n", __func__); - - s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); - - for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) - __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); - - for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { - __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4)); - __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); - __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); - } - - S3C_PMDBG("%s: IRQ configuration restored\n", __func__); -} - -static struct syscore_ops s3c64xx_irq_syscore_ops = { - .suspend = s3c64xx_irq_pm_suspend, - .resume = s3c64xx_irq_pm_resume, -}; - -static __init int s3c64xx_syscore_init(void) -{ - register_syscore_ops(&s3c64xx_irq_syscore_ops); - - return 0; -} - -core_initcall(s3c64xx_syscore_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-anw6410.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-anw6410.c deleted file mode 100644 index b86f2779..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-anw6410.c +++ /dev/null @@ -1,246 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/mach-anw6410.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * Copyright 2009 Kwangwoo Lee - * Kwangwoo Lee <kwangwoo.lee@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/dm9000.h> - -#include <video/platform_lcd.h> - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <plat/iic.h> -#include <plat/fb.h> -#include <plat/regs-fb-v4.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <mach/regs-gpio.h> -#include <mach/regs-modem.h> - -#include "common.h" - -/* DM9000 */ -#define ANW6410_PA_DM9000 (0x18000000) - -/* A hardware buffer to control external devices is mapped at 0x30000000. - * It can not be read. So current status must be kept in anw6410_extdev_status. - */ -#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000) -#define ANW6410_PA_EXTDEV (0x30000000) - -#define ANW6410_EN_DM9000 (1<<11) -#define ANW6410_EN_LCD (1<<14) - -static __u32 anw6410_extdev_status; - -static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, -}; - -/* framebuffer and LCD setup. */ -static void __init anw6410_lcd_mode_set(void) -{ - u32 tmp; - - /* set the LCD type */ - tmp = __raw_readl(S3C64XX_SPCON); - tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; - tmp |= S3C64XX_SPCON_LCD_SEL_RGB; - __raw_writel(tmp, S3C64XX_SPCON); - - /* remove the LCD bypass */ - tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); - tmp &= ~MIFPCON_LCD_BYPASS; - __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); -} - -/* GPF1 = LCD panel power - * GPF4 = LCD backlight control - */ -static void anw6410_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) { - anw6410_extdev_status |= (ANW6410_EN_LCD << 16); - __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV); - - gpio_direction_output(S3C64XX_GPF(1), 1); - gpio_direction_output(S3C64XX_GPF(4), 1); - } else { - anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16); - __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV); - - gpio_direction_output(S3C64XX_GPF(1), 0); - gpio_direction_output(S3C64XX_GPF(4), 0); - } -} - -static struct plat_lcd_data anw6410_lcd_power_data = { - .set_power = anw6410_lcd_power_set, -}; - -static struct platform_device anw6410_lcd_powerdev = { - .name = "platform-lcd", - .dev.parent = &s3c_device_fb.dev, - .dev.platform_data = &anw6410_lcd_power_data, -}; - -static struct s3c_fb_pd_win anw6410_fb_win0 = { - /* this is to ensure we use win0 */ - .win_mode = { - .left_margin = 8, - .right_margin = 13, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .max_bpp = 32, - .default_bpp = 16, -}; - -/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ -static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &anw6410_fb_win0, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -}; - -/* DM9000AEP 10/100 ethernet controller */ -static void __init anw6410_dm9000_enable(void) -{ - anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16); - __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV); -} - -static struct resource anw6410_dm9000_resource[] = { - [0] = { - .start = ANW6410_PA_DM9000, - .end = ANW6410_PA_DM9000 + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = ANW6410_PA_DM9000 + 4, - .end = ANW6410_PA_DM9000 + 4 + 500, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_EINT(15), - .end = IRQ_EINT(15), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, - }, -}; - -static struct dm9000_plat_data anw6410_dm9000_pdata = { - .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), - /* dev_addr can be set to provide hwaddr. */ -}; - -static struct platform_device anw6410_device_eth = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(anw6410_dm9000_resource), - .resource = anw6410_dm9000_resource, - .dev = { - .platform_data = &anw6410_dm9000_pdata, - }, -}; - -static struct map_desc anw6410_iodesc[] __initdata = { - { - .virtual = (unsigned long)ANW6410_VA_EXTDEV, - .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV), - .length = SZ_64K, - .type = MT_DEVICE, - }, -}; - -static struct platform_device *anw6410_devices[] __initdata = { - &s3c_device_fb, - &anw6410_lcd_powerdev, - &anw6410_device_eth, -}; - -static void __init anw6410_map_io(void) -{ - s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); - - anw6410_lcd_mode_set(); -} - -static void __init anw6410_machine_init(void) -{ - s3c_fb_set_platdata(&anw6410_lcd_pdata); - - gpio_request(S3C64XX_GPF(1), "panel power"); - gpio_request(S3C64XX_GPF(4), "LCD backlight"); - - anw6410_dm9000_enable(); - - platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices)); -} - -MACHINE_START(ANW6410, "A&W6410") - /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */ - .atag_offset = 0x100, - - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = anw6410_map_io, - .init_machine = anw6410_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-crag6410-module.c deleted file mode 100644 index 0ace108c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ /dev/null @@ -1,272 +0,0 @@ -/* Speyside modules for Cragganmore - board data probing - * - * Copyright 2011 Wolfson Microelectronics plc - * Mark Brown <broonie@opensource.wolfsonmicro.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/export.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/spi/spi.h> - -#include <linux/mfd/wm831x/irq.h> -#include <linux/mfd/wm831x/gpio.h> -#include <linux/mfd/wm8994/pdata.h> - -#include <linux/regulator/machine.h> - -#include <sound/wm5100.h> -#include <sound/wm8996.h> -#include <sound/wm8962.h> -#include <sound/wm9081.h> - -#include <plat/s3c64xx-spi.h> - -#include <mach/crag6410.h> - -static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = { - .set_level = gpio_set_value, - .line = S3C64XX_GPC(3), -}; - -static struct spi_board_info wm1253_devs[] = { - [0] = { - .modalias = "wm0010", - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - .controller_data = &wm0010_spi_csinfo, - }, -}; - -static struct wm5100_pdata wm5100_pdata = { - .ldo_ena = S3C64XX_GPN(7), - .irq_flags = IRQF_TRIGGER_HIGH, - .gpio_base = CODEC_GPIO_BASE, - - .in_mode = { - WM5100_IN_DIFF, - WM5100_IN_DIFF, - WM5100_IN_DIFF, - WM5100_IN_SE, - }, - - .hp_pol = CODEC_GPIO_BASE + 3, - .jack_modes = { - { WM5100_MICDET_MICBIAS3, 0, 0 }, - { WM5100_MICDET_MICBIAS2, 1, 1 }, - }, - - .gpio_defaults = { - 0, - 0, - 0, - 0, - 0x2, /* IRQ: CMOS output */ - 0x3, /* CLKOUT: CMOS output */ - }, -}; - -static struct wm8996_retune_mobile_config wm8996_retune[] = { - { - .name = "Sub LPF", - .rate = 48000, - .regs = { - 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, - 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, - 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 - }, - }, - { - .name = "Sub HPF", - .rate = 48000, - .regs = { - 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, - 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, - 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 - }, - }, -}; - -static struct wm8996_pdata wm8996_pdata __initdata = { - .ldo_ena = S3C64XX_GPN(7), - .gpio_base = CODEC_GPIO_BASE, - .micdet_def = 1, - .inl_mode = WM8996_DIFFERRENTIAL_1, - .inr_mode = WM8996_DIFFERRENTIAL_1, - - .irq_flags = IRQF_TRIGGER_RISING, - - .gpio_default = { - 0x8001, /* GPIO1 == ADCLRCLK1 */ - 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */ - 0x0141, /* GPIO3 == HP_SEL */ - 0x0002, /* GPIO4 == IRQ */ - 0x020e, /* GPIO5 == CLKOUT */ - }, - - .retune_mobile_cfgs = wm8996_retune, - .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune), -}; - -static struct wm8962_pdata wm8962_pdata __initdata = { - .gpio_init = { - 0, - WM8962_GPIO_FN_OPCLK, - WM8962_GPIO_FN_DMICCLK, - 0, - 0x8000 | WM8962_GPIO_FN_DMICDAT, - WM8962_GPIO_FN_IRQ, /* Open drain mode */ - }, - .in4_dc_measure = true, -}; - -static struct wm9081_pdata wm9081_pdata __initdata = { - .irq_high = false, - .irq_cmos = false, -}; - -static const struct i2c_board_info wm1254_devs[] = { - { I2C_BOARD_INFO("wm8996", 0x1a), - .platform_data = &wm8996_pdata, - .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, - }, - { I2C_BOARD_INFO("wm9081", 0x6c), - .platform_data = &wm9081_pdata, }, -}; - -static const struct i2c_board_info wm1255_devs[] = { - { I2C_BOARD_INFO("wm5100", 0x1a), - .platform_data = &wm5100_pdata, - .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, - }, - { I2C_BOARD_INFO("wm9081", 0x6c), - .platform_data = &wm9081_pdata, }, -}; - -static const struct i2c_board_info wm1259_devs[] = { - { I2C_BOARD_INFO("wm8962", 0x1a), - .platform_data = &wm8962_pdata, - .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, - }, -}; - -static struct regulator_init_data wm8994_ldo1 = { - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data wm8994_ldo2 = { - .supply_regulator = "WALLVDD", -}; - -static struct wm8994_pdata wm8994_pdata = { - .gpio_base = CODEC_GPIO_BASE, - .gpio_defaults = { - 0x3, /* IRQ out, active high, CMOS */ - }, - .irq_base = CODEC_IRQ_BASE, - .ldo = { - { .init_data = &wm8994_ldo1, }, - { .init_data = &wm8994_ldo2, }, - }, -}; - -static const struct i2c_board_info wm1277_devs[] = { - { I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */ - .platform_data = &wm8994_pdata, - .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, - }, -}; - -static __devinitdata const struct { - u8 id; - const char *name; - const struct i2c_board_info *i2c_devs; - int num_i2c_devs; - const struct spi_board_info *spi_devs; - int num_spi_devs; -} gf_mods[] = { - { .id = 0x01, .name = "1250-EV1 Springbank" }, - { .id = 0x02, .name = "1251-EV1 Jura" }, - { .id = 0x03, .name = "1252-EV1 Glenlivet" }, - { .id = 0x11, .name = "6249-EV2 Glenfarclas", }, - { .id = 0x14, .name = "6271-EV1 Lochnagar" }, - { .id = 0x15, .name = "XXXX-EV1 Bells" }, - { .id = 0x21, .name = "1275-EV1 Mortlach" }, - { .id = 0x25, .name = "1274-EV1 Glencadam" }, - { .id = 0x31, .name = "1253-EV1 Tomatin", - .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) }, - { .id = 0x32, .name = "XXXX-EV1 Caol Illa" }, - { .id = 0x33, .name = "XXXX-EV1 Oban" }, - { .id = 0x39, .name = "1254-EV1 Dallas Dhu", - .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) }, - { .id = 0x3a, .name = "1259-EV1 Tobermory", - .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) }, - { .id = 0x3b, .name = "1255-EV1 Kilchoman", - .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) }, - { .id = 0x3c, .name = "1273-EV1 Longmorn" }, - { .id = 0x3d, .name = "1277-EV1 Littlemill", - .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) }, -}; - -static __devinit int wlf_gf_module_probe(struct i2c_client *i2c, - const struct i2c_device_id *i2c_id) -{ - int ret, i, j, id, rev; - - ret = i2c_smbus_read_byte_data(i2c, 0); - if (ret < 0) { - dev_err(&i2c->dev, "Failed to read ID: %d\n", ret); - return ret; - } - - id = (ret & 0xfe) >> 2; - rev = ret & 0x3; - for (i = 0; i < ARRAY_SIZE(gf_mods); i++) - if (id == gf_mods[i].id) - break; - - if (i < ARRAY_SIZE(gf_mods)) { - dev_info(&i2c->dev, "%s revision %d\n", - gf_mods[i].name, rev + 1); - - for (j = 0; j < gf_mods[i].num_i2c_devs; j++) { - if (!i2c_new_device(i2c->adapter, - &(gf_mods[i].i2c_devs[j]))) - dev_err(&i2c->dev, - "Failed to register dev: %d\n", ret); - } - - spi_register_board_info(gf_mods[i].spi_devs, - gf_mods[i].num_spi_devs); - } else { - dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n", - id, rev + 1); - } - - return 0; -} - -static const struct i2c_device_id wlf_gf_module_id[] = { - { "wlf-gf-module", 0 }, - { } -}; - -static struct i2c_driver wlf_gf_module_driver = { - .driver = { - .name = "wlf-gf-module", - .owner = THIS_MODULE, - }, - .probe = wlf_gf_module_probe, - .id_table = wlf_gf_module_id, -}; - -static int __init wlf_gf_module_register(void) -{ - return i2c_add_driver(&wlf_gf_module_driver); -} -module_init(wlf_gf_module_register); diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-crag6410.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-crag6410.c deleted file mode 100644 index e20bf583..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-crag6410.c +++ /dev/null @@ -1,816 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c - * - * Copyright 2011 Wolfson Microelectronics plc - * Mark Brown <broonie@opensource.wolfsonmicro.com> - * - * Copyright 2011 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/fb.h> -#include <linux/io.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/delay.h> -#include <linux/mmc/host.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/pwm_backlight.h> -#include <linux/dm9000.h> -#include <linux/gpio_keys.h> -#include <linux/basic_mmio_gpio.h> -#include <linux/spi/spi.h> - -#include <linux/i2c/pca953x.h> - -#include <video/platform_lcd.h> - -#include <linux/mfd/wm831x/core.h> -#include <linux/mfd/wm831x/pdata.h> -#include <linux/mfd/wm831x/irq.h> -#include <linux/mfd/wm831x/gpio.h> - -#include <sound/wm1250-ev1.h> - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <mach/regs-sys.h> -#include <mach/regs-gpio.h> -#include <mach/regs-modem.h> -#include <mach/crag6410.h> - -#include <mach/regs-gpio-memport.h> - -#include <plat/regs-serial.h> -#include <plat/regs-fb-v4.h> -#include <plat/fb.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> -#include <plat/udc-hs.h> - -#include <plat/keypad.h> -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/adc.h> -#include <plat/iic.h> -#include <plat/pm.h> - -#include "common.h" - -/* serial port setup */ - -#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -static struct platform_pwm_backlight_data crag6410_backlight_data = { - .pwm_id = 0, - .max_brightness = 1000, - .dft_brightness = 600, - .pwm_period_ns = 100000, /* about 1kHz */ -}; - -static struct platform_device crag6410_backlight_device = { - .name = "pwm-backlight", - .id = -1, - .dev = { - .parent = &s3c_device_timer[0].dev, - .platform_data = &crag6410_backlight_data, - }, -}; - -static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) -{ - pr_debug("%s: setting power %d\n", __func__, power); - - if (power) { - gpio_set_value(S3C64XX_GPB(0), 1); - msleep(1); - s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2)); - } else { - gpio_direction_output(S3C64XX_GPF(14), 0); - gpio_set_value(S3C64XX_GPB(0), 0); - } -} - -static struct platform_device crag6410_lcd_powerdev = { - .name = "platform-lcd", - .id = -1, - .dev.parent = &s3c_device_fb.dev, - .dev.platform_data = &(struct plat_lcd_data) { - .set_power = crag6410_lcd_power_set, - }, -}; - -/* 640x480 URT */ -static struct s3c_fb_pd_win crag6410_fb_win0 = { - /* this is to ensure we use win0 */ - .win_mode = { - .left_margin = 150, - .right_margin = 80, - .upper_margin = 40, - .lower_margin = 5, - .hsync_len = 40, - .vsync_len = 5, - .xres = 640, - .yres = 480, - }, - .max_bpp = 32, - .default_bpp = 16, - .virtual_y = 480 * 2, - .virtual_x = 640, -}; - -/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ -static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &crag6410_fb_win0, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -}; - -/* 2x6 keypad */ - -static uint32_t crag6410_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(0, 0, KEY_VOLUMEUP), - KEY(0, 1, KEY_HOME), - KEY(0, 2, KEY_VOLUMEDOWN), - KEY(0, 3, KEY_HELP), - KEY(0, 4, KEY_MENU), - KEY(0, 5, KEY_MEDIA), - KEY(1, 0, 232), - KEY(1, 1, KEY_DOWN), - KEY(1, 2, KEY_LEFT), - KEY(1, 3, KEY_UP), - KEY(1, 4, KEY_RIGHT), - KEY(1, 5, KEY_CAMERA), -}; - -static struct matrix_keymap_data crag6410_keymap_data __initdata = { - .keymap = crag6410_keymap, - .keymap_size = ARRAY_SIZE(crag6410_keymap), -}; - -static struct samsung_keypad_platdata crag6410_keypad_data __initdata = { - .keymap_data = &crag6410_keymap_data, - .rows = 2, - .cols = 6, -}; - -static struct gpio_keys_button crag6410_gpio_keys[] = { - [0] = { - .code = KEY_SUSPEND, - .gpio = S3C64XX_GPL(10), /* EINT 18 */ - .type = EV_KEY, - .wakeup = 1, - .active_low = 1, - }, - [1] = { - .code = SW_FRONT_PROXIMITY, - .gpio = S3C64XX_GPN(11), /* EINT 11 */ - .type = EV_SW, - }, -}; - -static struct gpio_keys_platform_data crag6410_gpio_keydata = { - .buttons = crag6410_gpio_keys, - .nbuttons = ARRAY_SIZE(crag6410_gpio_keys), -}; - -static struct platform_device crag6410_gpio_keydev = { - .name = "gpio-keys", - .id = 0, - .dev.platform_data = &crag6410_gpio_keydata, -}; - -static struct resource crag6410_dm9k_resource[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN5, - .end = S3C64XX_PA_XM0CSN5 + 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C64XX_PA_XM0CSN5 + (1 << 8), - .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = S3C_EINT(17), - .end = S3C_EINT(17), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct dm9000_plat_data mini6410_dm9k_pdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device crag6410_dm9k_device = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(crag6410_dm9k_resource), - .resource = crag6410_dm9k_resource, - .dev.platform_data = &mini6410_dm9k_pdata, -}; - -static struct resource crag6410_mmgpio_resource[] = { - [0] = { - .name = "dat", - .start = S3C64XX_PA_XM0CSN4 + 1, - .end = S3C64XX_PA_XM0CSN4 + 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device crag6410_mmgpio = { - .name = "basic-mmio-gpio", - .id = -1, - .resource = crag6410_mmgpio_resource, - .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource), - .dev.platform_data = &(struct bgpio_pdata) { - .base = MMGPIO_GPIO_BASE, - }, -}; - -static struct platform_device speyside_device = { - .name = "speyside", - .id = -1, -}; - -static struct platform_device lowland_device = { - .name = "lowland", - .id = -1, -}; - -static struct platform_device tobermory_device = { - .name = "tobermory", - .id = -1, -}; - -static struct platform_device littlemill_device = { - .name = "littlemill", - .id = -1, -}; - -static struct regulator_consumer_supply wallvdd_consumers[] = { - REGULATOR_SUPPLY("SPKVDD", "1-001a"), - REGULATOR_SUPPLY("SPKVDD1", "1-001a"), - REGULATOR_SUPPLY("SPKVDD2", "1-001a"), - REGULATOR_SUPPLY("SPKVDDL", "1-001a"), - REGULATOR_SUPPLY("SPKVDDR", "1-001a"), -}; - -static struct regulator_init_data wallvdd_data = { - .constraints = { - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers), - .consumer_supplies = wallvdd_consumers, -}; - -static struct fixed_voltage_config wallvdd_pdata = { - .supply_name = "WALLVDD", - .microvolts = 5000000, - .init_data = &wallvdd_data, - .gpio = -EINVAL, -}; - -static struct platform_device wallvdd_device = { - .name = "reg-fixed-voltage", - .id = -1, - .dev = { - .platform_data = &wallvdd_pdata, - }, -}; - -static struct platform_device *crag6410_devices[] __initdata = { - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_i2c0, - &s3c_device_i2c1, - &s3c_device_fb, - &s3c_device_ohci, - &s3c_device_usb_hsotg, - &s3c_device_timer[0], - &s3c64xx_device_iis0, - &s3c64xx_device_iis1, - &samsung_asoc_dma, - &samsung_device_keypad, - &crag6410_gpio_keydev, - &crag6410_dm9k_device, - &s3c64xx_device_spi0, - &crag6410_mmgpio, - &crag6410_lcd_powerdev, - &crag6410_backlight_device, - &speyside_device, - &tobermory_device, - &littlemill_device, - &lowland_device, - &wallvdd_device, -}; - -static struct pca953x_platform_data crag6410_pca_data = { - .gpio_base = PCA935X_GPIO_BASE, - .irq_base = -1, -}; - -/* VDDARM is controlled by DVS1 connected to GPK(0) */ -static struct wm831x_buckv_pdata vddarm_pdata = { - .dvs_control_src = 1, - .dvs_gpio = S3C64XX_GPK(0), -}; - -static struct regulator_consumer_supply vddarm_consumers[] __initdata = { - REGULATOR_SUPPLY("vddarm", NULL), -}; - -static struct regulator_init_data vddarm __initdata = { - .constraints = { - .name = "VDDARM", - .min_uV = 1000000, - .max_uV = 1300000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers), - .consumer_supplies = vddarm_consumers, - .supply_regulator = "WALLVDD", - .driver_data = &vddarm_pdata, -}; - -static struct regulator_consumer_supply vddint_consumers[] __initdata = { - REGULATOR_SUPPLY("vddint", NULL), -}; - -static struct regulator_init_data vddint __initdata = { - .constraints = { - .name = "VDDINT", - .min_uV = 1000000, - .max_uV = 1200000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(vddint_consumers), - .consumer_supplies = vddint_consumers, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddmem __initdata = { - .constraints = { - .name = "VDDMEM", - .always_on = 1, - }, -}; - -static struct regulator_init_data vddsys __initdata = { - .constraints = { - .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS", - .always_on = 1, - }, -}; - -static struct regulator_consumer_supply vddmmc_consumers[] __initdata = { - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"), - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), -}; - -static struct regulator_init_data vddmmc __initdata = { - .constraints = { - .name = "VDDMMC,UH", - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers), - .consumer_supplies = vddmmc_consumers, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddotgi __initdata = { - .constraints = { - .name = "VDDOTGi", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddotg __initdata = { - .constraints = { - .name = "VDDOTG", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddhi __initdata = { - .constraints = { - .name = "VDDHI", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddadc __initdata = { - .constraints = { - .name = "VDDADC,VDDDAC", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddmem0 __initdata = { - .constraints = { - .name = "VDDMEM0", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddpll __initdata = { - .constraints = { - .name = "VDDPLL", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddlcd __initdata = { - .constraints = { - .name = "VDDLCD", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct regulator_init_data vddalive __initdata = { - .constraints = { - .name = "VDDALIVE", - .always_on = 1, - }, - .supply_regulator = "WALLVDD", -}; - -static struct wm831x_backup_pdata banff_backup_pdata __initdata = { - .charger_enable = 1, - .vlim = 2500, /* mV */ - .ilim = 200, /* uA */ -}; - -static struct wm831x_status_pdata banff_red_led __initdata = { - .name = "banff:red:", - .default_src = WM831X_STATUS_MANUAL, -}; - -static struct wm831x_status_pdata banff_green_led __initdata = { - .name = "banff:green:", - .default_src = WM831X_STATUS_MANUAL, -}; - -static struct wm831x_touch_pdata touch_pdata __initdata = { - .data_irq = S3C_EINT(26), - .pd_irq = S3C_EINT(27), -}; - -static struct wm831x_pdata crag_pmic_pdata __initdata = { - .wm831x_num = 1, - .irq_base = BANFF_PMIC_IRQ_BASE, - .gpio_base = BANFF_PMIC_GPIO_BASE, - .soft_shutdown = true, - - .backup = &banff_backup_pdata, - - .gpio_defaults = { - /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */ - [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8, - /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/ - [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6, - /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/ - [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7, - }, - - .dcdc = { - &vddarm, /* DCDC1 */ - &vddint, /* DCDC2 */ - &vddmem, /* DCDC3 */ - }, - - .ldo = { - &vddsys, /* LDO1 */ - &vddmmc, /* LDO2 */ - NULL, /* LDO3 */ - &vddotgi, /* LDO4 */ - &vddotg, /* LDO5 */ - &vddhi, /* LDO6 */ - &vddadc, /* LDO7 */ - &vddmem0, /* LDO8 */ - &vddpll, /* LDO9 */ - &vddlcd, /* LDO10 */ - &vddalive, /* LDO11 */ - }, - - .status = { - &banff_green_led, - &banff_red_led, - }, - - .touch = &touch_pdata, -}; - -static struct i2c_board_info i2c_devs0[] __initdata = { - { I2C_BOARD_INFO("24c08", 0x50), }, - { I2C_BOARD_INFO("tca6408", 0x20), - .platform_data = &crag6410_pca_data, - }, - { I2C_BOARD_INFO("wm8312", 0x34), - .platform_data = &crag_pmic_pdata, - .irq = S3C_EINT(23), - }, -}; - -static struct s3c2410_platform_i2c i2c0_pdata = { - .frequency = 400000, -}; - -static struct regulator_consumer_supply pvdd_1v2_consumers[] __initdata = { - REGULATOR_SUPPLY("DCVDD", "spi0.0"), - REGULATOR_SUPPLY("AVDD", "spi0.0"), -}; - -static struct regulator_init_data pvdd_1v2 __initdata = { - .constraints = { - .name = "PVDD_1V2", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - - .consumer_supplies = pvdd_1v2_consumers, - .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers), -}; - -static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = { - REGULATOR_SUPPLY("LDOVDD", "1-001a"), - REGULATOR_SUPPLY("PLLVDD", "1-001a"), - REGULATOR_SUPPLY("DBVDD", "1-001a"), - REGULATOR_SUPPLY("DBVDD1", "1-001a"), - REGULATOR_SUPPLY("DBVDD2", "1-001a"), - REGULATOR_SUPPLY("DBVDD3", "1-001a"), - REGULATOR_SUPPLY("CPVDD", "1-001a"), - REGULATOR_SUPPLY("AVDD2", "1-001a"), - REGULATOR_SUPPLY("DCVDD", "1-001a"), - REGULATOR_SUPPLY("AVDD", "1-001a"), - REGULATOR_SUPPLY("DBVDD", "spi0.0"), -}; - -static struct regulator_init_data pvdd_1v8 __initdata = { - .constraints = { - .name = "PVDD_1V8", - .always_on = 1, - }, - - .consumer_supplies = pvdd_1v8_consumers, - .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers), -}; - -static struct regulator_consumer_supply pvdd_3v3_consumers[] __initdata = { - REGULATOR_SUPPLY("MICVDD", "1-001a"), - REGULATOR_SUPPLY("AVDD1", "1-001a"), -}; - -static struct regulator_init_data pvdd_3v3 __initdata = { - .constraints = { - .name = "PVDD_3V3", - .always_on = 1, - }, - - .consumer_supplies = pvdd_3v3_consumers, - .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers), -}; - -static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = { - .wm831x_num = 2, - .irq_base = GLENFARCLAS_PMIC_IRQ_BASE, - .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE, - .soft_shutdown = true, - - .gpio_defaults = { - /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */ - [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA, - [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA, - [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA, - }, - - .dcdc = { - &pvdd_1v2, /* DCDC1 */ - &pvdd_1v8, /* DCDC2 */ - &pvdd_3v3, /* DCDC3 */ - }, - - .disable_touch = true, -}; - -static struct wm1250_ev1_pdata wm1250_ev1_pdata = { - .gpios = { - [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12), - [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12), - [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13), - [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14), - [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8), - }, -}; - -static struct i2c_board_info i2c_devs1[] __initdata = { - { I2C_BOARD_INFO("wm8311", 0x34), - .irq = S3C_EINT(0), - .platform_data = &glenfarclas_pmic_pdata }, - - { I2C_BOARD_INFO("wlf-gf-module", 0x24) }, - { I2C_BOARD_INFO("wlf-gf-module", 0x25) }, - { I2C_BOARD_INFO("wlf-gf-module", 0x26) }, - - { I2C_BOARD_INFO("wm1250-ev1", 0x27), - .platform_data = &wm1250_ev1_pdata }, -}; - -static struct s3c2410_platform_i2c i2c1_pdata = { - .frequency = 400000, - .bus_num = 1, -}; - -static void __init crag6410_map_io(void) -{ - s3c64xx_init_io(NULL, 0); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); - - /* LCD type and Bypass set by bootloader */ -} - -static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = { - .max_width = 4, - .cd_type = S3C_SDHCI_CD_PERMANENT, - .host_caps = MMC_CAP_POWER_OFF_CARD, -}; - -static void crag6410_cfg_sdhci0(struct platform_device *dev, int width) -{ - /* Set all the necessary GPG pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); - - /* force card-detected for prototype 0 */ - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN); -} - -static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = { - .max_width = 4, - .cd_type = S3C_SDHCI_CD_INTERNAL, - .cfg_gpio = crag6410_cfg_sdhci0, - .host_caps = MMC_CAP_POWER_OFF_CARD, -}; - -static const struct gpio_led gpio_leds[] = { - { - .name = "d13:green:", - .gpio = MMGPIO_GPIO_BASE + 0, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d14:green:", - .gpio = MMGPIO_GPIO_BASE + 1, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d15:green:", - .gpio = MMGPIO_GPIO_BASE + 2, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d16:green:", - .gpio = MMGPIO_GPIO_BASE + 3, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d17:green:", - .gpio = MMGPIO_GPIO_BASE + 4, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d18:green:", - .gpio = MMGPIO_GPIO_BASE + 5, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d19:green:", - .gpio = MMGPIO_GPIO_BASE + 6, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "d20:green:", - .gpio = MMGPIO_GPIO_BASE + 7, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, -}; - -static const struct gpio_led_platform_data gpio_leds_pdata = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct s3c_hsotg_plat crag6410_hsotg_pdata; - -static void __init crag6410_machine_init(void) -{ - /* Open drain IRQs need pullups */ - s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP); - - gpio_request(S3C64XX_GPB(0), "LCD power"); - gpio_direction_output(S3C64XX_GPB(0), 0); - - gpio_request(S3C64XX_GPF(14), "LCD PWM"); - gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */ - - gpio_request(S3C64XX_GPB(1), "SD power"); - gpio_direction_output(S3C64XX_GPB(1), 0); - - gpio_request(S3C64XX_GPF(10), "nRESETSEL"); - gpio_direction_output(S3C64XX_GPF(10), 1); - - s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata); - s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata); - - s3c_i2c0_set_platdata(&i2c0_pdata); - s3c_i2c1_set_platdata(&i2c1_pdata); - s3c_fb_set_platdata(&crag6410_lcd_pdata); - s3c_hsotg_set_platdata(&crag6410_hsotg_pdata); - - i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); - i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); - - samsung_keypad_set_platdata(&crag6410_keypad_data); - s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1); - - platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); - - gpio_led_register_device(-1, &gpio_leds_pdata); - - regulator_has_full_constraints(); - - s3c64xx_pm_init(); -} - -MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") - /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */ - .atag_offset = 0x100, - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = crag6410_map_io, - .init_machine = crag6410_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-hmt.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-hmt.c deleted file mode 100644 index 521e07b8..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-hmt.c +++ /dev/null @@ -1,277 +0,0 @@ -/* mach-hmt.c - Platform code for Airgoo HMT - * - * Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/leds.h> -#include <linux/pwm_backlight.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <asm/hardware/vic.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <plat/iic.h> -#include <plat/fb.h> -#include <plat/nand.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/regs-fb-v4.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -static int hmt_bl_init(struct device *dev) -{ - int ret; - - ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable"); - if (!ret) - ret = gpio_direction_output(S3C64XX_GPB(4), 0); - - return ret; -} - -static int hmt_bl_notify(struct device *dev, int brightness) -{ - /* - * translate from CIELUV/CIELAB L*->brightness, E.G. from - * perceived luminance to light output. Assumes range 0..25600 - */ - if (brightness < 0x800) { - /* Y = Yn * L / 903.3 */ - brightness = (100*256 * brightness + 231245/2) / 231245; - } else { - /* Y = Yn * ((L + 16) / 116 )^3 */ - int t = (brightness*4 + 16*1024 + 58)/116; - brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000); - } - - gpio_set_value(S3C64XX_GPB(4), brightness); - - return brightness; -} - -static void hmt_bl_exit(struct device *dev) -{ - gpio_free(S3C64XX_GPB(4)); -} - -static struct platform_pwm_backlight_data hmt_backlight_data = { - .pwm_id = 1, - .max_brightness = 100 * 256, - .dft_brightness = 40 * 256, - .pwm_period_ns = 1000000000 / (100 * 256 * 20), - .init = hmt_bl_init, - .notify = hmt_bl_notify, - .exit = hmt_bl_exit, - -}; - -static struct platform_device hmt_backlight_device = { - .name = "pwm-backlight", - .dev = { - .parent = &s3c_device_timer[1].dev, - .platform_data = &hmt_backlight_data, - }, -}; - -static struct s3c_fb_pd_win hmt_fb_win0 = { - .win_mode = { - .left_margin = 8, - .right_margin = 13, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .max_bpp = 32, - .default_bpp = 16, -}; - -/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ -static struct s3c_fb_platdata hmt_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &hmt_fb_win0, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -}; - -static struct mtd_partition hmt_nand_part[] = { - [0] = { - .name = "uboot", - .size = SZ_512K, - .offset = 0, - }, - [1] = { - .name = "uboot-env1", - .size = SZ_256K, - .offset = SZ_512K, - }, - [2] = { - .name = "uboot-env2", - .size = SZ_256K, - .offset = SZ_512K + SZ_256K, - }, - [3] = { - .name = "kernel", - .size = SZ_2M, - .offset = SZ_1M, - }, - [4] = { - .name = "rootfs", - .size = MTDPART_SIZ_FULL, - .offset = SZ_1M + SZ_2M, - }, -}; - -static struct s3c2410_nand_set hmt_nand_sets[] = { - [0] = { - .name = "nand", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(hmt_nand_part), - .partitions = hmt_nand_part, - }, -}; - -static struct s3c2410_platform_nand hmt_nand_info = { - .tacls = 25, - .twrph0 = 55, - .twrph1 = 40, - .nr_sets = ARRAY_SIZE(hmt_nand_sets), - .sets = hmt_nand_sets, -}; - -static struct gpio_led hmt_leds[] = { - { /* left function keys */ - .name = "left:blue", - .gpio = S3C64XX_GPO(12), - .default_trigger = "default-on", - }, - { /* right function keys - red */ - .name = "right:red", - .gpio = S3C64XX_GPO(13), - }, - { /* right function keys - green */ - .name = "right:green", - .gpio = S3C64XX_GPO(14), - }, - { /* right function keys - blue */ - .name = "right:blue", - .gpio = S3C64XX_GPO(15), - .default_trigger = "default-on", - }, -}; - -static struct gpio_led_platform_data hmt_led_data = { - .num_leds = ARRAY_SIZE(hmt_leds), - .leds = hmt_leds, -}; - -static struct platform_device hmt_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &hmt_led_data, -}; - -static struct map_desc hmt_iodesc[] = {}; - -static struct platform_device *hmt_devices[] __initdata = { - &s3c_device_i2c0, - &s3c_device_nand, - &s3c_device_fb, - &s3c_device_ohci, - &s3c_device_timer[1], - &hmt_backlight_device, - &hmt_leds_device, -}; - -static void __init hmt_map_io(void) -{ - s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); -} - -static void __init hmt_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - s3c_fb_set_platdata(&hmt_lcd_pdata); - s3c_nand_set_platdata(&hmt_nand_info); - - gpio_request(S3C64XX_GPC(7), "usb power"); - gpio_direction_output(S3C64XX_GPC(7), 0); - gpio_request(S3C64XX_GPM(0), "usb power"); - gpio_direction_output(S3C64XX_GPM(0), 1); - gpio_request(S3C64XX_GPK(7), "usb power"); - gpio_direction_output(S3C64XX_GPK(7), 1); - gpio_request(S3C64XX_GPF(13), "usb power"); - gpio_direction_output(S3C64XX_GPF(13), 1); - - platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices)); -} - -MACHINE_START(HMT, "Airgoo-HMT") - /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */ - .atag_offset = 0x100, - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = hmt_map_io, - .init_machine = hmt_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-mini6410.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-mini6410.c deleted file mode 100644 index c34c2ab2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-mini6410.c +++ /dev/null @@ -1,355 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c - * - * Copyright 2010 Darius Augulis <augulis.darius@gmail.com> - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/dm9000.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/serial_core.h> -#include <linux/types.h> - -#include <asm/hardware/vic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/regs-modem.h> -#include <mach/regs-srom.h> - -#include <plat/adc.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/nand.h> -#include <plat/regs-serial.h> -#include <plat/ts.h> -#include <plat/regs-fb-v4.h> - -#include <video/platform_lcd.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -/* DM9000AEP 10/100 ethernet controller */ - -static struct resource mini6410_dm9k_resource[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN1, - .end = S3C64XX_PA_XM0CSN1 + 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C64XX_PA_XM0CSN1 + 4, - .end = S3C64XX_PA_XM0CSN1 + 5, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = S3C_EINT(7), - .end = S3C_EINT(7), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - } -}; - -static struct dm9000_plat_data mini6410_dm9k_pdata = { - .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), -}; - -static struct platform_device mini6410_device_eth = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(mini6410_dm9k_resource), - .resource = mini6410_dm9k_resource, - .dev = { - .platform_data = &mini6410_dm9k_pdata, - }, -}; - -static struct mtd_partition mini6410_nand_part[] = { - [0] = { - .name = "uboot", - .size = SZ_1M, - .offset = 0, - }, - [1] = { - .name = "kernel", - .size = SZ_2M, - .offset = SZ_1M, - }, - [2] = { - .name = "rootfs", - .size = MTDPART_SIZ_FULL, - .offset = SZ_1M + SZ_2M, - }, -}; - -static struct s3c2410_nand_set mini6410_nand_sets[] = { - [0] = { - .name = "nand", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(mini6410_nand_part), - .partitions = mini6410_nand_part, - }, -}; - -static struct s3c2410_platform_nand mini6410_nand_info = { - .tacls = 25, - .twrph0 = 55, - .twrph1 = 40, - .nr_sets = ARRAY_SIZE(mini6410_nand_sets), - .sets = mini6410_nand_sets, -}; - -static struct s3c_fb_pd_win mini6410_fb_win[] = { - { - .win_mode = { /* 4.3" 480x272 */ - .left_margin = 3, - .right_margin = 2, - .upper_margin = 1, - .lower_margin = 1, - .hsync_len = 40, - .vsync_len = 1, - .xres = 480, - .yres = 272, - }, - .max_bpp = 32, - .default_bpp = 16, - }, { - .win_mode = { /* 7.0" 800x480 */ - .left_margin = 8, - .right_margin = 13, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .max_bpp = 32, - .default_bpp = 16, - }, -}; - -static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &mini6410_fb_win[0], - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -}; - -static void mini6410_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(S3C64XX_GPE(0), 1); - else - gpio_direction_output(S3C64XX_GPE(0), 0); -} - -static struct plat_lcd_data mini6410_lcd_power_data = { - .set_power = mini6410_lcd_power_set, -}; - -static struct platform_device mini6410_lcd_powerdev = { - .name = "platform-lcd", - .dev.parent = &s3c_device_fb.dev, - .dev.platform_data = &mini6410_lcd_power_data, -}; - -static struct platform_device *mini6410_devices[] __initdata = { - &mini6410_device_eth, - &s3c_device_hsmmc0, - &s3c_device_hsmmc1, - &s3c_device_ohci, - &s3c_device_nand, - &s3c_device_fb, - &mini6410_lcd_powerdev, - &s3c_device_adc, - &s3c_device_ts, -}; - -static void __init mini6410_map_io(void) -{ - u32 tmp; - - s3c64xx_init_io(NULL, 0); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs)); - - /* set the LCD type */ - tmp = __raw_readl(S3C64XX_SPCON); - tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; - tmp |= S3C64XX_SPCON_LCD_SEL_RGB; - __raw_writel(tmp, S3C64XX_SPCON); - - /* remove the LCD bypass */ - tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); - tmp &= ~MIFPCON_LCD_BYPASS; - __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); -} - -/* - * mini6410_features string - * - * 0-9 LCD configuration - * - */ -static char mini6410_features_str[12] __initdata = "0"; - -static int __init mini6410_features_setup(char *str) -{ - if (str) - strlcpy(mini6410_features_str, str, - sizeof(mini6410_features_str)); - return 1; -} - -__setup("mini6410=", mini6410_features_setup); - -#define FEATURE_SCREEN (1 << 0) - -struct mini6410_features_t { - int done; - int lcd_index; -}; - -static void mini6410_parse_features( - struct mini6410_features_t *features, - const char *features_str) -{ - const char *fp = features_str; - - features->done = 0; - features->lcd_index = 0; - - while (*fp) { - char f = *fp++; - - switch (f) { - case '0'...'9': /* tft screen */ - if (features->done & FEATURE_SCREEN) { - printk(KERN_INFO "MINI6410: '%c' ignored, " - "screen type already set\n", f); - } else { - int li = f - '0'; - if (li >= ARRAY_SIZE(mini6410_fb_win)) - printk(KERN_INFO "MINI6410: '%c' out " - "of range LCD mode\n", f); - else { - features->lcd_index = li; - } - } - features->done |= FEATURE_SCREEN; - break; - } - } -} - -static void __init mini6410_machine_init(void) -{ - u32 cs1; - struct mini6410_features_t features = { 0 }; - - printk(KERN_INFO "MINI6410: Option string mini6410=%s\n", - mini6410_features_str); - - /* Parse the feature string */ - mini6410_parse_features(&features, mini6410_features_str); - - mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index]; - - printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n", - mini6410_lcd_pdata.win[0]->win_mode.xres, - mini6410_lcd_pdata.win[0]->win_mode.yres); - - s3c_nand_set_platdata(&mini6410_nand_info); - s3c_fb_set_platdata(&mini6410_lcd_pdata); - s3c24xx_ts_set_platdata(NULL); - - /* configure nCS1 width to 16 bits */ - - cs1 = __raw_readl(S3C64XX_SROM_BW) & - ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | - (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << - S3C64XX_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S3C64XX_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - - __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | - (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | - (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | - (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | - (13 << S3C64XX_SROM_BCX__TACC__SHIFT) | - (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | - (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); - - gpio_request(S3C64XX_GPF(15), "LCD power"); - gpio_request(S3C64XX_GPE(0), "LCD power"); - - platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices)); -} - -MACHINE_START(MINI6410, "MINI6410") - /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ - .atag_offset = 0x100, - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = mini6410_map_io, - .init_machine = mini6410_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-ncp.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-ncp.c deleted file mode 100644 index 0efa2ba7..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-ncp.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * linux/arch/arm/mach-s3c64xx/mach-ncp.c - * - * Copyright (C) 2008-2009 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/delay.h> - -#include <video/platform_lcd.h> - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <plat/iic.h> -#include <plat/fb.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/regs-fb-v4.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = { - /* REVISIT: NCP uses only serial 1, 2 */ - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -static struct platform_device *ncp_devices[] __initdata = { - &s3c_device_hsmmc1, - &s3c_device_i2c0, -}; - -static struct map_desc ncp_iodesc[] __initdata = {}; - -static void __init ncp_map_io(void) -{ - s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs)); -} - -static void __init ncp_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - - platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices)); -} - -MACHINE_START(NCP, "NCP") - /* Maintainer: Samsung Electronics */ - .atag_offset = 0x100, - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = ncp_map_io, - .init_machine = ncp_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-real6410.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-real6410.c deleted file mode 100644 index be2a9a22..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-real6410.c +++ /dev/null @@ -1,336 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/mach-real6410.c - * - * Copyright 2010 Darius Augulis <augulis.darius@gmail.com> - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/dm9000.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/types.h> - -#include <asm/hardware/vic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/regs-modem.h> -#include <mach/regs-srom.h> - -#include <plat/adc.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/nand.h> -#include <plat/regs-serial.h> -#include <plat/ts.h> -#include <plat/regs-fb-v4.h> - -#include <video/platform_lcd.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -/* DM9000AEP 10/100 ethernet controller */ - -static struct resource real6410_dm9k_resource[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN1, - .end = S3C64XX_PA_XM0CSN1 + 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C64XX_PA_XM0CSN1 + 4, - .end = S3C64XX_PA_XM0CSN1 + 5, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = S3C_EINT(7), - .end = S3C_EINT(7), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - } -}; - -static struct dm9000_plat_data real6410_dm9k_pdata = { - .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), -}; - -static struct platform_device real6410_device_eth = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(real6410_dm9k_resource), - .resource = real6410_dm9k_resource, - .dev = { - .platform_data = &real6410_dm9k_pdata, - }, -}; - -static struct s3c_fb_pd_win real6410_fb_win[] = { - { - .win_mode = { /* 4.3" 480x272 */ - .left_margin = 3, - .right_margin = 2, - .upper_margin = 1, - .lower_margin = 1, - .hsync_len = 40, - .vsync_len = 1, - .xres = 480, - .yres = 272, - }, - .max_bpp = 32, - .default_bpp = 16, - }, { - .win_mode = { /* 7.0" 800x480 */ - .left_margin = 8, - .right_margin = 13, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .max_bpp = 32, - .default_bpp = 16, - }, -}; - -static struct s3c_fb_platdata real6410_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &real6410_fb_win[0], - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -}; - -static struct mtd_partition real6410_nand_part[] = { - [0] = { - .name = "uboot", - .size = SZ_1M, - .offset = 0, - }, - [1] = { - .name = "kernel", - .size = SZ_2M, - .offset = SZ_1M, - }, - [2] = { - .name = "rootfs", - .size = MTDPART_SIZ_FULL, - .offset = SZ_1M + SZ_2M, - }, -}; - -static struct s3c2410_nand_set real6410_nand_sets[] = { - [0] = { - .name = "nand", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(real6410_nand_part), - .partitions = real6410_nand_part, - }, -}; - -static struct s3c2410_platform_nand real6410_nand_info = { - .tacls = 25, - .twrph0 = 55, - .twrph1 = 40, - .nr_sets = ARRAY_SIZE(real6410_nand_sets), - .sets = real6410_nand_sets, -}; - -static struct platform_device *real6410_devices[] __initdata = { - &real6410_device_eth, - &s3c_device_hsmmc0, - &s3c_device_hsmmc1, - &s3c_device_fb, - &s3c_device_nand, - &s3c_device_adc, - &s3c_device_ts, - &s3c_device_ohci, -}; - -static void __init real6410_map_io(void) -{ - u32 tmp; - - s3c64xx_init_io(NULL, 0); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs)); - - /* set the LCD type */ - tmp = __raw_readl(S3C64XX_SPCON); - tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; - tmp |= S3C64XX_SPCON_LCD_SEL_RGB; - __raw_writel(tmp, S3C64XX_SPCON); - - /* remove the LCD bypass */ - tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); - tmp &= ~MIFPCON_LCD_BYPASS; - __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); -} - -/* - * real6410_features string - * - * 0-9 LCD configuration - * - */ -static char real6410_features_str[12] __initdata = "0"; - -static int __init real6410_features_setup(char *str) -{ - if (str) - strlcpy(real6410_features_str, str, - sizeof(real6410_features_str)); - return 1; -} - -__setup("real6410=", real6410_features_setup); - -#define FEATURE_SCREEN (1 << 0) - -struct real6410_features_t { - int done; - int lcd_index; -}; - -static void real6410_parse_features( - struct real6410_features_t *features, - const char *features_str) -{ - const char *fp = features_str; - - features->done = 0; - features->lcd_index = 0; - - while (*fp) { - char f = *fp++; - - switch (f) { - case '0'...'9': /* tft screen */ - if (features->done & FEATURE_SCREEN) { - printk(KERN_INFO "REAL6410: '%c' ignored, " - "screen type already set\n", f); - } else { - int li = f - '0'; - if (li >= ARRAY_SIZE(real6410_fb_win)) - printk(KERN_INFO "REAL6410: '%c' out " - "of range LCD mode\n", f); - else { - features->lcd_index = li; - } - } - features->done |= FEATURE_SCREEN; - break; - } - } -} - -static void __init real6410_machine_init(void) -{ - u32 cs1; - struct real6410_features_t features = { 0 }; - - printk(KERN_INFO "REAL6410: Option string real6410=%s\n", - real6410_features_str); - - /* Parse the feature string */ - real6410_parse_features(&features, real6410_features_str); - - real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index]; - - printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n", - real6410_lcd_pdata.win[0]->win_mode.xres, - real6410_lcd_pdata.win[0]->win_mode.yres); - - s3c_fb_set_platdata(&real6410_lcd_pdata); - s3c_nand_set_platdata(&real6410_nand_info); - s3c24xx_ts_set_platdata(NULL); - - /* configure nCS1 width to 16 bits */ - - cs1 = __raw_readl(S3C64XX_SROM_BW) & - ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | - (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << - S3C64XX_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S3C64XX_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - - __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | - (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | - (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | - (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | - (13 << S3C64XX_SROM_BCX__TACC__SHIFT) | - (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | - (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); - - gpio_request(S3C64XX_GPF(15), "LCD power"); - - platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices)); -} - -MACHINE_START(REAL6410, "REAL6410") - /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ - .atag_offset = 0x100, - - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = real6410_map_io, - .init_machine = real6410_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq.c deleted file mode 100644 index ce745e19..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * linux/arch/arm/mach-s3c64xx/mach-smartq.c - * - * Copyright (C) 2010 Maurus Cuelenaere - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/pwm_backlight.h> -#include <linux/serial_core.h> -#include <linux/spi/spi_gpio.h> -#include <linux/usb/gpio_vbus.h> - -#include <asm/mach-types.h> -#include <asm/mach/map.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/regs-modem.h> - -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/iic.h> -#include <plat/gpio-cfg.h> -#include <plat/hwmon.h> -#include <plat/regs-serial.h> -#include <plat/udc-hs.h> -#include <plat/usb-control.h> -#include <plat/sdhci.h> -#include <plat/ts.h> - -#include <video/platform_lcd.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) - -static struct s3c2410_uartcfg smartq_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -static void smartq_usb_host_powercontrol(int port, int to) -{ - pr_debug("%s(%d, %d)\n", __func__, port, to); - - if (port == 0) { - gpio_set_value(S3C64XX_GPL(0), to); - gpio_set_value(S3C64XX_GPL(1), to); - } -} - -static irqreturn_t smartq_usb_host_ocirq(int irq, void *pw) -{ - struct s3c2410_hcd_info *info = pw; - - if (gpio_get_value(S3C64XX_GPL(10)) == 0) { - pr_debug("%s: over-current irq (oc detected)\n", __func__); - s3c2410_usb_report_oc(info, 3); - } else { - pr_debug("%s: over-current irq (oc cleared)\n", __func__); - s3c2410_usb_report_oc(info, 0); - } - - return IRQ_HANDLED; -} - -static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on) -{ - int ret; - - /* This isn't present on a SmartQ 5 board */ - if (machine_is_smartq5()) - return; - - if (on) { - ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)), - smartq_usb_host_ocirq, IRQF_DISABLED | - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "USB host overcurrent", info); - if (ret != 0) - pr_err("failed to request usb oc irq: %d\n", ret); - } else { - free_irq(gpio_to_irq(S3C64XX_GPL(10)), info); - } -} - -static struct s3c2410_hcd_info smartq_usb_host_info = { - .port[0] = { - .flags = S3C_HCDFLG_USED - }, - .port[1] = { - .flags = 0 - }, - - .power_control = smartq_usb_host_powercontrol, - .enable_oc = smartq_usb_host_enableoc, -}; - -static struct gpio_vbus_mach_info smartq_usb_otg_vbus_pdata = { - .gpio_vbus = S3C64XX_GPL(9), - .gpio_pullup = -1, - .gpio_vbus_inverted = true, -}; - -static struct platform_device smartq_usb_otg_vbus_dev = { - .name = "gpio-vbus", - .dev.platform_data = &smartq_usb_otg_vbus_pdata, -}; - -static int smartq_bl_init(struct device *dev) -{ - s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2)); - - return 0; -} - -static struct platform_pwm_backlight_data smartq_backlight_data = { - .pwm_id = 1, - .max_brightness = 1000, - .dft_brightness = 600, - .pwm_period_ns = 1000000000 / (1000 * 20), - .init = smartq_bl_init, -}; - -static struct platform_device smartq_backlight_device = { - .name = "pwm-backlight", - .dev = { - .parent = &s3c_device_timer[1].dev, - .platform_data = &smartq_backlight_data, - }, -}; - -static struct s3c2410_ts_mach_info smartq_touchscreen_pdata __initdata = { - .delay = 65535, - .presc = 99, - .oversampling_shift = 4, -}; - -static struct s3c_sdhci_platdata smartq_internal_hsmmc_pdata = { - .max_width = 4, - .cd_type = S3C_SDHCI_CD_PERMANENT, -}; - -static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = { - /* Battery voltage (?-4.2V) */ - .in[0] = &(struct s3c_hwmon_chcfg) { - .name = "smartq:battery-voltage", - .mult = 3300, - .div = 2048, - }, - /* Reference voltage (1.2V) */ - .in[1] = &(struct s3c_hwmon_chcfg) { - .name = "smartq:reference-voltage", - .mult = 3300, - .div = 4096, - }, -}; - -static struct s3c_hsotg_plat smartq_hsotg_pdata; - -static int __init smartq_lcd_setup_gpio(void) -{ - int ret; - - ret = gpio_request(S3C64XX_GPM(3), "LCD power"); - if (ret < 0) - return ret; - - /* turn power off */ - gpio_direction_output(S3C64XX_GPM(3), 0); - - return 0; -} - -/* GPM0 -> CS */ -static struct spi_gpio_platform_data smartq_lcd_control = { - .sck = S3C64XX_GPM(1), - .mosi = S3C64XX_GPM(2), - .miso = S3C64XX_GPM(2), -}; - -static struct platform_device smartq_lcd_control_device = { - .name = "spi-gpio", - .id = 1, - .dev.platform_data = &smartq_lcd_control, -}; - -static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) -{ - gpio_direction_output(S3C64XX_GPM(3), power); -} - -static struct plat_lcd_data smartq_lcd_power_data = { - .set_power = smartq_lcd_power_set, -}; - -static struct platform_device smartq_lcd_power_device = { - .name = "platform-lcd", - .dev.parent = &s3c_device_fb.dev, - .dev.platform_data = &smartq_lcd_power_data, -}; - -static struct i2c_board_info smartq_i2c_devs[] __initdata = { - { I2C_BOARD_INFO("wm8987", 0x1a), }, -}; - -static struct platform_device *smartq_devices[] __initdata = { - &s3c_device_hsmmc1, /* Init iNAND first, ... */ - &s3c_device_hsmmc0, /* ... then the external SD card */ - &s3c_device_hsmmc2, - &s3c_device_adc, - &s3c_device_fb, - &s3c_device_hwmon, - &s3c_device_i2c0, - &s3c_device_ohci, - &s3c_device_rtc, - &s3c_device_timer[1], - &s3c_device_ts, - &s3c_device_usb_hsotg, - &s3c64xx_device_iis0, - &smartq_backlight_device, - &smartq_lcd_control_device, - &smartq_lcd_power_device, - &smartq_usb_otg_vbus_dev, -}; - -static void __init smartq_lcd_mode_set(void) -{ - u32 tmp; - - /* set the LCD type */ - tmp = __raw_readl(S3C64XX_SPCON); - tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; - tmp |= S3C64XX_SPCON_LCD_SEL_RGB; - __raw_writel(tmp, S3C64XX_SPCON); - - /* remove the LCD bypass */ - tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); - tmp &= ~MIFPCON_LCD_BYPASS; - __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); -} - -static void smartq_power_off(void) -{ - gpio_direction_output(S3C64XX_GPK(15), 1); -} - -static int __init smartq_power_off_init(void) -{ - int ret; - - ret = gpio_request(S3C64XX_GPK(15), "Power control"); - if (ret < 0) { - pr_err("%s: failed to get GPK15\n", __func__); - return ret; - } - - /* leave power on */ - gpio_direction_output(S3C64XX_GPK(15), 0); - - pm_power_off = smartq_power_off; - - return ret; -} - -static int __init smartq_usb_host_init(void) -{ - int ret; - - ret = gpio_request(S3C64XX_GPL(0), "USB power control"); - if (ret < 0) { - pr_err("%s: failed to get GPL0\n", __func__); - return ret; - } - - ret = gpio_request(S3C64XX_GPL(1), "USB host power control"); - if (ret < 0) { - pr_err("%s: failed to get GPL1\n", __func__); - goto err; - } - - if (!machine_is_smartq5()) { - /* This isn't present on a SmartQ 5 board */ - ret = gpio_request(S3C64XX_GPL(10), "USB host overcurrent"); - if (ret < 0) { - pr_err("%s: failed to get GPL10\n", __func__); - goto err2; - } - } - - /* turn power off */ - gpio_direction_output(S3C64XX_GPL(0), 0); - gpio_direction_output(S3C64XX_GPL(1), 0); - if (!machine_is_smartq5()) - gpio_direction_input(S3C64XX_GPL(10)); - - s3c_device_ohci.dev.platform_data = &smartq_usb_host_info; - - return 0; - -err2: - gpio_free(S3C64XX_GPL(1)); -err: - gpio_free(S3C64XX_GPL(0)); - return ret; -} - -static int __init smartq_usb_otg_init(void) -{ - clk_xusbxti.rate = 12000000; - - return 0; -} - -static int __init smartq_wifi_init(void) -{ - int ret; - - ret = gpio_request(S3C64XX_GPK(1), "wifi control"); - if (ret < 0) { - pr_err("%s: failed to get GPK1\n", __func__); - return ret; - } - - ret = gpio_request(S3C64XX_GPK(2), "wifi reset"); - if (ret < 0) { - pr_err("%s: failed to get GPK2\n", __func__); - gpio_free(S3C64XX_GPK(1)); - return ret; - } - - /* turn power on */ - gpio_direction_output(S3C64XX_GPK(1), 1); - - /* reset device */ - gpio_direction_output(S3C64XX_GPK(2), 0); - mdelay(100); - gpio_set_value(S3C64XX_GPK(2), 1); - gpio_direction_input(S3C64XX_GPK(2)); - - return 0; -} - -static struct map_desc smartq_iodesc[] __initdata = {}; -void __init smartq_map_io(void) -{ - s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); - - smartq_lcd_mode_set(); -} - -void __init smartq_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - s3c_hsotg_set_platdata(&smartq_hsotg_pdata); - s3c_hwmon_set_platdata(&smartq_hwmon_pdata); - s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata); - s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata); - s3c24xx_ts_set_platdata(&smartq_touchscreen_pdata); - - i2c_register_board_info(0, smartq_i2c_devs, - ARRAY_SIZE(smartq_i2c_devs)); - - WARN_ON(smartq_lcd_setup_gpio()); - WARN_ON(smartq_power_off_init()); - WARN_ON(smartq_usb_host_init()); - WARN_ON(smartq_usb_otg_init()); - WARN_ON(smartq_wifi_init()); - - platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq.h b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq.h deleted file mode 100644 index 8e8b693d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/arch/arm/mach-s3c64xx/mach-smartq.h - * - * Copyright (C) 2010 Maurus Cuelenaere - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __MACH_SMARTQ_H -#define __MACH_SMARTQ_H __FILE__ - -#include <linux/init.h> - -extern void __init smartq_map_io(void); -extern void __init smartq_machine_init(void); - -#endif /* __MACH_SMARTQ_H */ diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq5.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq5.c deleted file mode 100644 index 3f42431d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq5.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * linux/arch/arm/mach-s3c64xx/mach-smartq5.c - * - * Copyright (C) 2010 Maurus Cuelenaere - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/init.h> -#include <linux/input.h> -#include <linux/leds.h> -#include <linux/platform_device.h> - -#include <asm/hardware/vic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <plat/regs-fb-v4.h> - -#include "common.h" -#include "mach-smartq.h" - -static struct gpio_led smartq5_leds[] = { - { - .name = "smartq5:green", - .active_low = 1, - .gpio = S3C64XX_GPN(8), - }, - { - .name = "smartq5:red", - .active_low = 1, - .gpio = S3C64XX_GPN(9), - }, -}; - -static struct gpio_led_platform_data smartq5_led_data = { - .num_leds = ARRAY_SIZE(smartq5_leds), - .leds = smartq5_leds, -}; - -static struct platform_device smartq5_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &smartq5_led_data, -}; - -/* Labels according to the SmartQ manual */ -static struct gpio_keys_button smartq5_buttons[] = { - { - .gpio = S3C64XX_GPL(14), - .code = KEY_POWER, - .desc = "Power", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(2), - .code = KEY_KPMINUS, - .desc = "Minus", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(12), - .code = KEY_KPPLUS, - .desc = "Plus", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(15), - .code = KEY_ENTER, - .desc = "Move", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, -}; - -static struct gpio_keys_platform_data smartq5_buttons_data = { - .buttons = smartq5_buttons, - .nbuttons = ARRAY_SIZE(smartq5_buttons), -}; - -static struct platform_device smartq5_buttons_device = { - .name = "gpio-keys", - .id = 0, - .num_resources = 0, - .dev = { - .platform_data = &smartq5_buttons_data, - } -}; - -static struct s3c_fb_pd_win smartq5_fb_win0 = { - .win_mode = { - .left_margin = 216, - .right_margin = 40, - .upper_margin = 35, - .lower_margin = 10, - .hsync_len = 1, - .vsync_len = 1, - .xres = 800, - .yres = 480, - .refresh = 80, - }, - .max_bpp = 32, - .default_bpp = 16, -}; - -static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &smartq5_fb_win0, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | - VIDCON1_INV_VDEN, -}; - -static struct platform_device *smartq5_devices[] __initdata = { - &smartq5_leds_device, - &smartq5_buttons_device, -}; - -static void __init smartq5_machine_init(void) -{ - s3c_fb_set_platdata(&smartq5_lcd_pdata); - - smartq_machine_init(); - - platform_add_devices(smartq5_devices, ARRAY_SIZE(smartq5_devices)); -} - -MACHINE_START(SMARTQ5, "SmartQ 5") - /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ - .atag_offset = 0x100, - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = smartq_map_io, - .init_machine = smartq5_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq7.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq7.c deleted file mode 100644 index e5c09b6d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smartq7.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * linux/arch/arm/mach-s3c64xx/mach-smartq7.c - * - * Copyright (C) 2010 Maurus Cuelenaere - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/init.h> -#include <linux/input.h> -#include <linux/leds.h> -#include <linux/platform_device.h> - -#include <asm/hardware/vic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <plat/regs-fb-v4.h> - -#include "common.h" -#include "mach-smartq.h" - -static struct gpio_led smartq7_leds[] = { - { - .name = "smartq7:red", - .active_low = 1, - .gpio = S3C64XX_GPN(8), - }, - { - .name = "smartq7:green", - .active_low = 1, - .gpio = S3C64XX_GPN(9), - }, -}; - -static struct gpio_led_platform_data smartq7_led_data = { - .num_leds = ARRAY_SIZE(smartq7_leds), - .leds = smartq7_leds, -}; - -static struct platform_device smartq7_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &smartq7_led_data, -}; - -/* Labels according to the SmartQ manual */ -static struct gpio_keys_button smartq7_buttons[] = { - { - .gpio = S3C64XX_GPL(14), - .code = KEY_POWER, - .desc = "Power", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(2), - .code = KEY_FN, - .desc = "Function", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(3), - .code = KEY_KPMINUS, - .desc = "Minus", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(4), - .code = KEY_KPPLUS, - .desc = "Plus", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(12), - .code = KEY_ENTER, - .desc = "Enter", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, - { - .gpio = S3C64XX_GPN(15), - .code = KEY_ESC, - .desc = "Cancel", - .active_low = 1, - .debounce_interval = 5, - .type = EV_KEY, - }, -}; - -static struct gpio_keys_platform_data smartq7_buttons_data = { - .buttons = smartq7_buttons, - .nbuttons = ARRAY_SIZE(smartq7_buttons), -}; - -static struct platform_device smartq7_buttons_device = { - .name = "gpio-keys", - .id = 0, - .num_resources = 0, - .dev = { - .platform_data = &smartq7_buttons_data, - } -}; - -static struct s3c_fb_pd_win smartq7_fb_win0 = { - .win_mode = { - .left_margin = 3, - .right_margin = 5, - .upper_margin = 1, - .lower_margin = 20, - .hsync_len = 10, - .vsync_len = 3, - .xres = 800, - .yres = 480, - .refresh = 80, - }, - .max_bpp = 32, - .default_bpp = 16, -}; - -static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &smartq7_fb_win0, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | - VIDCON1_INV_VCLK, -}; - -static struct platform_device *smartq7_devices[] __initdata = { - &smartq7_leds_device, - &smartq7_buttons_device, -}; - -static void __init smartq7_machine_init(void) -{ - s3c_fb_set_platdata(&smartq7_lcd_pdata); - - smartq_machine_init(); - - platform_add_devices(smartq7_devices, ARRAY_SIZE(smartq7_devices)); -} - -MACHINE_START(SMARTQ7, "SmartQ 7") - /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ - .atag_offset = 0x100, - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = smartq_map_io, - .init_machine = smartq7_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smdk6400.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smdk6400.c deleted file mode 100644 index 5f096534..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ /dev/null @@ -1,98 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/mach-smdk6400.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/io.h> - -#include <asm/mach-types.h> - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <plat/regs-serial.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/iic.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, -}; - -static struct map_desc smdk6400_iodesc[] = {}; - -static void __init smdk6400_map_io(void) -{ - s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); -} - -static struct platform_device *smdk6400_devices[] __initdata = { - &s3c_device_hsmmc1, - &s3c_device_i2c0, -}; - -static struct i2c_board_info i2c_devs[] __initdata = { - { I2C_BOARD_INFO("wm8753", 0x1A), }, - { I2C_BOARD_INFO("24c08", 0x50), }, -}; - -static void __init smdk6400_machine_init(void) -{ - i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs)); - platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices)); -} - -MACHINE_START(SMDK6400, "SMDK6400") - /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ - .atag_offset = 0x100, - - .init_irq = s3c6400_init_irq, - .handle_irq = vic_handle_irq, - .map_io = smdk6400_map_io, - .init_machine = smdk6400_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smdk6410.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smdk6410.c deleted file mode 100644 index d55bc96d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ /dev/null @@ -1,714 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/input.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/leds.h> -#include <linux/fb.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/smsc911x.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/pwm_backlight.h> - -#ifdef CONFIG_SMDK6410_WM1190_EV1 -#include <linux/mfd/wm8350/core.h> -#include <linux/mfd/wm8350/pmic.h> -#endif - -#ifdef CONFIG_SMDK6410_WM1192_EV1 -#include <linux/mfd/wm831x/core.h> -#include <linux/mfd/wm831x/pdata.h> -#endif - -#include <video/platform_lcd.h> - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <mach/regs-modem.h> -#include <mach/regs-gpio.h> -#include <mach/regs-sys.h> -#include <mach/regs-srom.h> -#include <plat/ata.h> -#include <plat/iic.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/adc.h> -#include <plat/ts.h> -#include <plat/keypad.h> -#include <plat/backlight.h> -#include <plat/regs-fb-v4.h> -#include <plat/udc-hs.h> - -#include "common.h" - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, -}; - -/* framebuffer and LCD setup. */ - -/* GPF15 = LCD backlight control - * GPF13 => Panel power - * GPN5 = LCD nRESET signal - * PWM_TOUT1 => backlight brightness - */ - -static void smdk6410_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) { - gpio_direction_output(S3C64XX_GPF(13), 1); - - /* fire nRESET on power up */ - gpio_direction_output(S3C64XX_GPN(5), 0); - msleep(10); - gpio_direction_output(S3C64XX_GPN(5), 1); - msleep(1); - } else { - gpio_direction_output(S3C64XX_GPF(13), 0); - } -} - -static struct plat_lcd_data smdk6410_lcd_power_data = { - .set_power = smdk6410_lcd_power_set, -}; - -static struct platform_device smdk6410_lcd_powerdev = { - .name = "platform-lcd", - .dev.parent = &s3c_device_fb.dev, - .dev.platform_data = &smdk6410_lcd_power_data, -}; - -static struct s3c_fb_pd_win smdk6410_fb_win0 = { - /* this is to ensure we use win0 */ - .win_mode = { - .left_margin = 8, - .right_margin = 13, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .max_bpp = 32, - .default_bpp = 16, - .virtual_y = 480 * 2, - .virtual_x = 800, -}; - -/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ -static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { - .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, - .win[0] = &smdk6410_fb_win0, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -}; - -/* - * Configuring Ethernet on SMDK6410 - * - * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6. - * The constant address below corresponds to nCS1 - * - * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet" - * 2) CFG6 needs to be switched to "LAN9115" side - */ - -static struct resource smdk6410_smsc911x_resources[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN1, - .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C_EINT(10), - .end = S3C_EINT(10), - .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW, - }, -}; - -static struct smsc911x_platform_config smdk6410_smsc911x_pdata = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - - -static struct platform_device smdk6410_smsc911x = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources), - .resource = &smdk6410_smsc911x_resources[0], - .dev = { - .platform_data = &smdk6410_smsc911x_pdata, - }, -}; - -#ifdef CONFIG_REGULATOR -static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = { - REGULATOR_SUPPLY("PVDD", "0-001b"), - REGULATOR_SUPPLY("AVDD", "0-001b"), -}; - -static struct regulator_init_data smdk6410_b_pwr_5v_data = { - .constraints = { - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers), - .consumer_supplies = smdk6410_b_pwr_5v_consumers, -}; - -static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = { - .supply_name = "B_PWR_5V", - .microvolts = 5000000, - .init_data = &smdk6410_b_pwr_5v_data, - .gpio = -EINVAL, -}; - -static struct platform_device smdk6410_b_pwr_5v = { - .name = "reg-fixed-voltage", - .id = -1, - .dev = { - .platform_data = &smdk6410_b_pwr_5v_pdata, - }, -}; -#endif - -static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = { - .setup_gpio = s3c64xx_ide_setup_gpio, -}; - -static uint32_t smdk6410_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), - KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), - KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), - KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) -}; - -static struct matrix_keymap_data smdk6410_keymap_data __initdata = { - .keymap = smdk6410_keymap, - .keymap_size = ARRAY_SIZE(smdk6410_keymap), -}; - -static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = { - .keymap_data = &smdk6410_keymap_data, - .rows = 2, - .cols = 8, -}; - -static struct map_desc smdk6410_iodesc[] = {}; - -static struct platform_device *smdk6410_devices[] __initdata = { -#ifdef CONFIG_SMDK6410_SD_CH0 - &s3c_device_hsmmc0, -#endif -#ifdef CONFIG_SMDK6410_SD_CH1 - &s3c_device_hsmmc1, -#endif - &s3c_device_i2c0, - &s3c_device_i2c1, - &s3c_device_fb, - &s3c_device_ohci, - &s3c_device_usb_hsotg, - &samsung_asoc_dma, - &s3c64xx_device_iisv4, - &samsung_device_keypad, - -#ifdef CONFIG_REGULATOR - &smdk6410_b_pwr_5v, -#endif - &smdk6410_lcd_powerdev, - - &smdk6410_smsc911x, - &s3c_device_adc, - &s3c_device_cfcon, - &s3c_device_rtc, - &s3c_device_ts, - &s3c_device_wdt, -}; - -#ifdef CONFIG_REGULATOR -/* ARM core */ -static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = { - REGULATOR_SUPPLY("vddarm", NULL), -}; - -/* VDDARM, BUCK1 on J5 */ -static struct regulator_init_data smdk6410_vddarm = { - .constraints = { - .name = "PVDD_ARM", - .min_uV = 1000000, - .max_uV = 1300000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers), - .consumer_supplies = smdk6410_vddarm_consumers, -}; - -/* VDD_INT, BUCK2 on J5 */ -static struct regulator_init_data smdk6410_vddint = { - .constraints = { - .name = "PVDD_INT", - .min_uV = 1000000, - .max_uV = 1200000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, -}; - -/* VDD_HI, LDO3 on J5 */ -static struct regulator_init_data smdk6410_vddhi = { - .constraints = { - .name = "PVDD_HI", - .always_on = 1, - }, -}; - -/* VDD_PLL, LDO2 on J5 */ -static struct regulator_init_data smdk6410_vddpll = { - .constraints = { - .name = "PVDD_PLL", - .always_on = 1, - }, -}; - -/* VDD_UH_MMC, LDO5 on J5 */ -static struct regulator_init_data smdk6410_vdduh_mmc = { - .constraints = { - .name = "PVDD_UH+PVDD_MMC", - .always_on = 1, - }, -}; - -/* VCCM3BT, LDO8 on J5 */ -static struct regulator_init_data smdk6410_vccmc3bt = { - .constraints = { - .name = "PVCCM3BT", - .always_on = 1, - }, -}; - -/* VCCM2MTV, LDO11 on J5 */ -static struct regulator_init_data smdk6410_vccm2mtv = { - .constraints = { - .name = "PVCCM2MTV", - .always_on = 1, - }, -}; - -/* VDD_LCD, LDO12 on J5 */ -static struct regulator_init_data smdk6410_vddlcd = { - .constraints = { - .name = "PVDD_LCD", - .always_on = 1, - }, -}; - -/* VDD_OTGI, LDO9 on J5 */ -static struct regulator_init_data smdk6410_vddotgi = { - .constraints = { - .name = "PVDD_OTGI", - .always_on = 1, - }, -}; - -/* VDD_OTG, LDO14 on J5 */ -static struct regulator_init_data smdk6410_vddotg = { - .constraints = { - .name = "PVDD_OTG", - .always_on = 1, - }, -}; - -/* VDD_ALIVE, LDO15 on J5 */ -static struct regulator_init_data smdk6410_vddalive = { - .constraints = { - .name = "PVDD_ALIVE", - .always_on = 1, - }, -}; - -/* VDD_AUDIO, VLDO_AUDIO on J5 */ -static struct regulator_init_data smdk6410_vddaudio = { - .constraints = { - .name = "PVDD_AUDIO", - .always_on = 1, - }, -}; -#endif - -#ifdef CONFIG_SMDK6410_WM1190_EV1 -/* S3C64xx internal logic & PLL */ -static struct regulator_init_data wm8350_dcdc1_data = { - .constraints = { - .name = "PVDD_INT+PVDD_PLL", - .min_uV = 1200000, - .max_uV = 1200000, - .always_on = 1, - .apply_uV = 1, - }, -}; - -/* Memory */ -static struct regulator_init_data wm8350_dcdc3_data = { - .constraints = { - .name = "PVDD_MEM", - .min_uV = 1800000, - .max_uV = 1800000, - .always_on = 1, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - }, -}; - -/* USB, EXT, PCM, ADC/DAC, USB, MMC */ -static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { - REGULATOR_SUPPLY("DVDD", "0-001b"), -}; - -static struct regulator_init_data wm8350_dcdc4_data = { - .constraints = { - .name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV", - .min_uV = 3000000, - .max_uV = 3000000, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers), - .consumer_supplies = wm8350_dcdc4_consumers, -}; - -/* OTGi/1190-EV1 HPVDD & AVDD */ -static struct regulator_init_data wm8350_ldo4_data = { - .constraints = { - .name = "PVDD_OTGI+HPVDD+AVDD", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - }, -}; - -static struct { - int regulator; - struct regulator_init_data *initdata; -} wm1190_regulators[] = { - { WM8350_DCDC_1, &wm8350_dcdc1_data }, - { WM8350_DCDC_3, &wm8350_dcdc3_data }, - { WM8350_DCDC_4, &wm8350_dcdc4_data }, - { WM8350_DCDC_6, &smdk6410_vddarm }, - { WM8350_LDO_1, &smdk6410_vddalive }, - { WM8350_LDO_2, &smdk6410_vddotg }, - { WM8350_LDO_3, &smdk6410_vddlcd }, - { WM8350_LDO_4, &wm8350_ldo4_data }, -}; - -static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) -{ - int i; - - /* Configure the IRQ line */ - s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP); - - /* Instantiate the regulators */ - for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++) - wm8350_register_regulator(wm8350, - wm1190_regulators[i].regulator, - wm1190_regulators[i].initdata); - - return 0; -} - -static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { - .init = smdk6410_wm8350_init, - .irq_high = 1, - .irq_base = IRQ_BOARD_START, -}; -#endif - -#ifdef CONFIG_SMDK6410_WM1192_EV1 -static struct gpio_led wm1192_pmic_leds[] = { - { - .name = "PMIC:red:power", - .gpio = GPIO_BOARD_START + 3, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, -}; - -static struct gpio_led_platform_data wm1192_pmic_led = { - .num_leds = ARRAY_SIZE(wm1192_pmic_leds), - .leds = wm1192_pmic_leds, -}; - -static struct platform_device wm1192_pmic_led_dev = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &wm1192_pmic_led, - }, -}; - -static int wm1192_pre_init(struct wm831x *wm831x) -{ - int ret; - - /* Configure the IRQ line */ - s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP); - - ret = platform_device_register(&wm1192_pmic_led_dev); - if (ret != 0) - dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret); - - return 0; -} - -static struct wm831x_backlight_pdata wm1192_backlight_pdata = { - .isink = 1, - .max_uA = 27554, -}; - -static struct regulator_init_data wm1192_dcdc3 = { - .constraints = { - .name = "PVDD_MEM+PVDD_GPS", - .always_on = 1, - }, -}; - -static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { - REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */ -}; - -static struct regulator_init_data wm1192_ldo1 = { - .constraints = { - .name = "PVDD_LCD+PVDD_EXT", - .always_on = 1, - }, - .consumer_supplies = wm1192_ldo1_consumers, - .num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers), -}; - -static struct wm831x_status_pdata wm1192_led7_pdata = { - .name = "LED7:green:", -}; - -static struct wm831x_status_pdata wm1192_led8_pdata = { - .name = "LED8:green:", -}; - -static struct wm831x_pdata smdk6410_wm1192_pdata = { - .pre_init = wm1192_pre_init, - .irq_base = IRQ_BOARD_START, - - .backlight = &wm1192_backlight_pdata, - .dcdc = { - &smdk6410_vddarm, /* DCDC1 */ - &smdk6410_vddint, /* DCDC2 */ - &wm1192_dcdc3, - }, - .gpio_base = GPIO_BOARD_START, - .ldo = { - &wm1192_ldo1, /* LDO1 */ - &smdk6410_vdduh_mmc, /* LDO2 */ - NULL, /* LDO3 NC */ - &smdk6410_vddotgi, /* LDO4 */ - &smdk6410_vddotg, /* LDO5 */ - &smdk6410_vddhi, /* LDO6 */ - &smdk6410_vddaudio, /* LDO7 */ - &smdk6410_vccm2mtv, /* LDO8 */ - &smdk6410_vddpll, /* LDO9 */ - &smdk6410_vccmc3bt, /* LDO10 */ - &smdk6410_vddalive, /* LDO11 */ - }, - .status = { - &wm1192_led7_pdata, - &wm1192_led8_pdata, - }, -}; -#endif - -static struct i2c_board_info i2c_devs0[] __initdata = { - { I2C_BOARD_INFO("24c08", 0x50), }, - { I2C_BOARD_INFO("wm8580", 0x1b), }, - -#ifdef CONFIG_SMDK6410_WM1192_EV1 - { I2C_BOARD_INFO("wm8312", 0x34), - .platform_data = &smdk6410_wm1192_pdata, - .irq = S3C_EINT(12), - }, -#endif - -#ifdef CONFIG_SMDK6410_WM1190_EV1 - { I2C_BOARD_INFO("wm8350", 0x1a), - .platform_data = &smdk6410_wm8350_pdata, - .irq = S3C_EINT(12), - }, -#endif -}; - -static struct i2c_board_info i2c_devs1[] __initdata = { - { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ -}; - -/* LCD Backlight data */ -static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = { - .no = S3C64XX_GPF(15), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdk6410_bl_data = { - .pwm_id = 1, -}; - -static struct s3c_hsotg_plat smdk6410_hsotg_pdata; - -static void __init smdk6410_map_io(void) -{ - u32 tmp; - - s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); - - /* set the LCD type */ - - tmp = __raw_readl(S3C64XX_SPCON); - tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; - tmp |= S3C64XX_SPCON_LCD_SEL_RGB; - __raw_writel(tmp, S3C64XX_SPCON); - - /* remove the lcd bypass */ - tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); - tmp &= ~MIFPCON_LCD_BYPASS; - __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); -} - -static void __init smdk6410_machine_init(void) -{ - u32 cs1; - - s3c_i2c0_set_platdata(NULL); - s3c_i2c1_set_platdata(NULL); - s3c_fb_set_platdata(&smdk6410_lcd_pdata); - s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata); - - samsung_keypad_set_platdata(&smdk6410_keypad_data); - - s3c24xx_ts_set_platdata(NULL); - - /* configure nCS1 width to 16 bits */ - - cs1 = __raw_readl(S3C64XX_SROM_BW) & - ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | - (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << - S3C64XX_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S3C64XX_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - - __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | - (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | - (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | - (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | - (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) | - (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | - (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); - - gpio_request(S3C64XX_GPN(5), "LCD power"); - gpio_request(S3C64XX_GPF(13), "LCD power"); - - i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); - i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); - - s3c_ide_set_platdata(&smdk6410_ide_pdata); - - samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data); - - platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); -} - -MACHINE_START(SMDK6410, "SMDK6410") - /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ - .atag_offset = 0x100, - - .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, - .map_io = smdk6410_map_io, - .init_machine = smdk6410_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c64xx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/pm.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/pm.c deleted file mode 100644 index 7d3e81b9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/pm.c +++ /dev/null @@ -1,374 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/pm.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX CPU PM support. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/suspend.h> -#include <linux/serial_core.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/pm_domain.h> - -#include <mach/map.h> -#include <mach/irqs.h> - -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/wakeup-mask.h> - -#include <mach/regs-sys.h> -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> -#include <mach/regs-syscon-power.h> -#include <mach/regs-gpio-memport.h> -#include <mach/regs-modem.h> - -struct s3c64xx_pm_domain { - char *const name; - u32 ena; - u32 pwr_stat; - struct generic_pm_domain pd; -}; - -static int s3c64xx_pd_off(struct generic_pm_domain *domain) -{ - struct s3c64xx_pm_domain *pd; - u32 val; - - pd = container_of(domain, struct s3c64xx_pm_domain, pd); - - val = __raw_readl(S3C64XX_NORMAL_CFG); - val &= ~(pd->ena); - __raw_writel(val, S3C64XX_NORMAL_CFG); - - return 0; -} - -static int s3c64xx_pd_on(struct generic_pm_domain *domain) -{ - struct s3c64xx_pm_domain *pd; - u32 val; - long retry = 1000000L; - - pd = container_of(domain, struct s3c64xx_pm_domain, pd); - - val = __raw_readl(S3C64XX_NORMAL_CFG); - val |= pd->ena; - __raw_writel(val, S3C64XX_NORMAL_CFG); - - /* Not all domains provide power status readback */ - if (pd->pwr_stat) { - do { - cpu_relax(); - if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat) - break; - } while (retry--); - - if (!retry) { - pr_err("Failed to start domain %s\n", pd->name); - return -EBUSY; - } - } - - return 0; -} - -static struct s3c64xx_pm_domain s3c64xx_pm_irom = { - .name = "IROM", - .ena = S3C64XX_NORMALCFG_IROM_ON, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_etm = { - .name = "ETM", - .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON, - .pwr_stat = S3C64XX_BLKPWRSTAT_ETM, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_s = { - .name = "S", - .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON, - .pwr_stat = S3C64XX_BLKPWRSTAT_S, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_f = { - .name = "F", - .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON, - .pwr_stat = S3C64XX_BLKPWRSTAT_F, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_p = { - .name = "P", - .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON, - .pwr_stat = S3C64XX_BLKPWRSTAT_P, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_i = { - .name = "I", - .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON, - .pwr_stat = S3C64XX_BLKPWRSTAT_I, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_g = { - .name = "G", - .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain s3c64xx_pm_v = { - .name = "V", - .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON, - .pwr_stat = S3C64XX_BLKPWRSTAT_V, - .pd = { - .power_off = s3c64xx_pd_off, - .power_on = s3c64xx_pd_on, - }, -}; - -static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = { - &s3c64xx_pm_irom, -}; - -static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = { - &s3c64xx_pm_etm, - &s3c64xx_pm_g, - &s3c64xx_pm_v, - &s3c64xx_pm_i, - &s3c64xx_pm_p, - &s3c64xx_pm_s, - &s3c64xx_pm_f, -}; - -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK -void s3c_pm_debug_smdkled(u32 set, u32 clear) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i < 4; i++) { - if (clear & (1 << i)) - gpio_set_value(S3C64XX_GPN(12 + i), 0); - if (set & (1 << i)) - gpio_set_value(S3C64XX_GPN(12 + i), 1); - } - local_irq_restore(flags); -} -#endif - -static struct sleep_save core_save[] = { - SAVE_ITEM(S3C_APLL_LOCK), - SAVE_ITEM(S3C_MPLL_LOCK), - SAVE_ITEM(S3C_EPLL_LOCK), - SAVE_ITEM(S3C_CLK_SRC), - SAVE_ITEM(S3C_CLK_DIV0), - SAVE_ITEM(S3C_CLK_DIV1), - SAVE_ITEM(S3C_CLK_DIV2), - SAVE_ITEM(S3C_CLK_OUT), - SAVE_ITEM(S3C_HCLK_GATE), - SAVE_ITEM(S3C_PCLK_GATE), - SAVE_ITEM(S3C_SCLK_GATE), - SAVE_ITEM(S3C_MEM0_GATE), - - SAVE_ITEM(S3C_EPLL_CON1), - SAVE_ITEM(S3C_EPLL_CON0), - - SAVE_ITEM(S3C64XX_MEM0DRVCON), - SAVE_ITEM(S3C64XX_MEM1DRVCON), - -#ifndef CONFIG_CPU_FREQ - SAVE_ITEM(S3C_APLL_CON), - SAVE_ITEM(S3C_MPLL_CON), -#endif -}; - -static struct sleep_save misc_save[] = { - SAVE_ITEM(S3C64XX_AHB_CON0), - SAVE_ITEM(S3C64XX_AHB_CON1), - SAVE_ITEM(S3C64XX_AHB_CON2), - - SAVE_ITEM(S3C64XX_SPCON), - - SAVE_ITEM(S3C64XX_MEM0CONSTOP), - SAVE_ITEM(S3C64XX_MEM1CONSTOP), - SAVE_ITEM(S3C64XX_MEM0CONSLP0), - SAVE_ITEM(S3C64XX_MEM0CONSLP1), - SAVE_ITEM(S3C64XX_MEM1CONSLP), - - SAVE_ITEM(S3C64XX_SDMA_SEL), - SAVE_ITEM(S3C64XX_MODEM_MIFPCON), - - SAVE_ITEM(S3C64XX_NORMAL_CFG), -}; - -void s3c_pm_configure_extint(void) -{ - __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); -} - -void s3c_pm_restore_core(void) -{ - __raw_writel(0, S3C64XX_EINT_MASK); - - s3c_pm_debug_smdkled(1 << 2, 0); - - s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); - s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); -} - -void s3c_pm_save_core(void) -{ - s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); - s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); -} - -/* since both s3c6400 and s3c6410 share the same sleep pm calls, we - * put the per-cpu code in here until any new cpu comes along and changes - * this. - */ - -static int s3c64xx_cpu_suspend(unsigned long arg) -{ - unsigned long tmp; - - /* set our standby method to sleep */ - - tmp = __raw_readl(S3C64XX_PWR_CFG); - tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; - tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; - __raw_writel(tmp, S3C64XX_PWR_CFG); - - /* clear any old wakeup */ - - __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), - S3C64XX_WAKEUP_STAT); - - /* set the LED state to 0110 over sleep */ - s3c_pm_debug_smdkled(3 << 1, 0xf); - - /* issue the standby signal into the pm unit. Note, we - * issue a write-buffer drain just in case */ - - tmp = 0; - - asm("b 1f\n\t" - ".align 5\n\t" - "1:\n\t" - "mcr p15, 0, %0, c7, c10, 5\n\t" - "mcr p15, 0, %0, c7, c10, 4\n\t" - "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); - - /* we should never get past here */ - - panic("sleep resumed to originator?"); -} - -/* mapping of interrupts to parts of the wakeup mask */ -static struct samsung_wakeup_mask wake_irqs[] = { - { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, }, - { .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, }, - { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, }, - { .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, }, - { .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, }, - { .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, }, - { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE}, - { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, - { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE }, - { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, -}; - -static void s3c64xx_pm_prepare(void) -{ - samsung_sync_wakemask(S3C64XX_PWR_CFG, - wake_irqs, ARRAY_SIZE(wake_irqs)); - - /* store address of resume. */ - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); - - /* ensure previous wakeup state is cleared before sleeping */ - __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); -} - -int __init s3c64xx_pm_init(void) -{ - int i; - - s3c_pm_init(); - - for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++) - pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd, - &pm_domain_always_on_gov, false); - - for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) - pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); - - if (dev_get_platdata(&s3c_device_fb.dev)) - pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev); - - return 0; -} - -static __init int s3c64xx_pm_initcall(void) -{ - pm_cpu_prep = s3c64xx_pm_prepare; - pm_cpu_sleep = s3c64xx_cpu_suspend; - pm_uart_udivslot = 1; - -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK - gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); - gpio_request(S3C64XX_GPN(13), "DEBUG_LED1"); - gpio_request(S3C64XX_GPN(14), "DEBUG_LED2"); - gpio_request(S3C64XX_GPN(15), "DEBUG_LED3"); - gpio_direction_output(S3C64XX_GPN(12), 0); - gpio_direction_output(S3C64XX_GPN(13), 0); - gpio_direction_output(S3C64XX_GPN(14), 0); - gpio_direction_output(S3C64XX_GPN(15), 0); -#endif - - return 0; -} -arch_initcall(s3c64xx_pm_initcall); - -static __init int s3c64xx_pm_late_initcall(void) -{ - pm_genpd_poweroff_unused(); - - return 0; -} -late_initcall(s3c64xx_pm_late_initcall); diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/s3c6400.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/s3c6400.c deleted file mode 100644 index 4869714c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/s3c6400.c +++ /dev/null @@ -1,95 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/cpu.c - * - * Copyright 2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/device.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <plat/cpu-freq.h> -#include <plat/regs-serial.h> -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/clock.h> -#include <plat/sdhci.h> -#include <plat/iic-core.h> -#include <plat/onenand-core.h> - -#include "common.h" - -void __init s3c6400_map_io(void) -{ - /* setup SDHCI */ - - s3c6400_default_sdhci0(); - s3c6400_default_sdhci1(); - s3c6400_default_sdhci2(); - - /* the i2c devices are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); - - s3c_device_nand.name = "s3c6400-nand"; - - s3c_onenand_setname("s3c6400-onenand"); - s3c64xx_onenand1_setname("s3c6400-onenand"); -} - -void __init s3c6400_init_clocks(int xtal) -{ - s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK); - s3c64xx_setup_clocks(); -} - -void __init s3c6400_init_irq(void) -{ - /* VIC0 does not have IRQS 5..7, - * VIC1 is fully populated. */ - s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); -} - -static struct bus_type s3c6400_subsys = { - .name = "s3c6400-core", - .dev_name = "s3c6400-core", -}; - -static struct device s3c6400_dev = { - .bus = &s3c6400_subsys, -}; - -static int __init s3c6400_core_init(void) -{ - return subsys_system_register(&s3c6400_subsys, NULL); -} - -core_initcall(s3c6400_core_init); - -int __init s3c6400_init(void) -{ - printk("S3C6400: Initialising architecture\n"); - - return device_register(&s3c6400_dev); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/s3c6410.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/s3c6410.c deleted file mode 100644 index 31c29fdf..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/s3c6410.c +++ /dev/null @@ -1,99 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/s3c6410.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/device.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <plat/cpu-freq.h> -#include <plat/regs-serial.h> -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/clock.h> -#include <plat/sdhci.h> -#include <plat/ata-core.h> -#include <plat/adc-core.h> -#include <plat/iic-core.h> -#include <plat/onenand-core.h> - -#include "common.h" - -void __init s3c6410_map_io(void) -{ - /* initialise device information early */ - s3c6410_default_sdhci0(); - s3c6410_default_sdhci1(); - s3c6410_default_sdhci2(); - - /* the i2c devices are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); - s3c_i2c1_setname("s3c2440-i2c"); - - s3c_adc_setname("s3c64xx-adc"); - s3c_device_nand.name = "s3c6400-nand"; - s3c_onenand_setname("s3c6410-onenand"); - s3c64xx_onenand1_setname("s3c6410-onenand"); - s3c_cfcon_setname("s3c64xx-pata"); -} - -void __init s3c6410_init_clocks(int xtal) -{ - printk(KERN_DEBUG "%s: initialising clocks\n", __func__); - s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK); - s3c64xx_setup_clocks(); -} - -void __init s3c6410_init_irq(void) -{ - /* VIC0 is missing IRQ7, VIC1 is fully populated. */ - s3c64xx_init_irq(~0 & ~(1 << 7), ~0); -} - -struct bus_type s3c6410_subsys = { - .name = "s3c6410-core", - .dev_name = "s3c6410-core", -}; - -static struct device s3c6410_dev = { - .bus = &s3c6410_subsys, -}; - -static int __init s3c6410_core_init(void) -{ - return subsys_system_register(&s3c6410_subsys, NULL); -} - -core_initcall(s3c6410_core_init); - -int __init s3c6410_init(void) -{ - printk("S3C6410: Initialising architecture\n"); - - return device_register(&s3c6410_dev); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-fb-24bpp.c deleted file mode 100644 index 2cf80026..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-fb-24bpp.c +++ /dev/null @@ -1,27 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Base S3C64XX setup information for 24bpp LCD framebuffer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/fb.h> -#include <linux/gpio.h> - -#include <plat/fb.h> -#include <plat/gpio-cfg.h> - -void s3c64xx_fb_gpio_setup_24bpp(void) -{ - s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-i2c0.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-i2c0.c deleted file mode 100644 index 241af94a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-i2c0.c +++ /dev/null @@ -1,28 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Base S3C64XX I2C bus 0 gpio configuration - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/gpio.h> - -struct platform_device; /* don't need the contents */ - -#include <plat/iic.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c0_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S3C64XX_GPB(5), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-i2c1.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-i2c1.c deleted file mode 100644 index 3d13a961..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-i2c1.c +++ /dev/null @@ -1,28 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Base S3C64XX I2C bus 1 gpio configuration - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/gpio.h> - -struct platform_device; /* don't need the contents */ - -#include <plat/iic.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c1_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S3C64XX_GPB(2), 2, - S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-ide.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-ide.c deleted file mode 100644 index 41b42560..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-ide.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-ide.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S3C64XX setup information for IDE - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/io.h> - -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <plat/gpio-cfg.h> -#include <plat/ata.h> - -void s3c64xx_ide_setup_gpio(void) -{ - u32 reg; - - reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); - - /* Independent CF interface, CF chip select configuration */ - writel(reg | MEM_SYS_CFG_INDEP_CF | - MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG); - - s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4)); - - /* Set XhiDATA[15:0] pins as CF Data[15:0] */ - s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5)); - - /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */ - s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6)); - - /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ - s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1)); - s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-keypad.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-keypad.c deleted file mode 100644 index 1d4d0ee9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-keypad.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-keypad.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * GPIO configuration for S3C64XX KeyPad device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/keypad.h> - -void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) -{ - /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3)); - - /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c deleted file mode 100644 index 6eac071a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c +++ /dev/null @@ -1,57 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <plat/gpio-cfg.h> -#include <plat/sdhci.h> - -void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); - } -} - -void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPH pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2)); - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); - } -} - -void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) -{ - /* Set all the necessary GPH pins to special-function 3 */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3)); - - /* Set all the necessary GPC pins to special-function 3 */ - s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-spi.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-spi.c deleted file mode 100644 index d9592ad7..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-spi.c +++ /dev/null @@ -1,45 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-spi.c - * - * Copyright (C) 2011 Samsung Electronics Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gpio.h> -#include <linux/platform_device.h> - -#include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> - -#ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - return 0; -} -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - return 0; -} -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-usb-phy.c b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-usb-phy.c deleted file mode 100644 index f6757e02..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/setup-usb-phy.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <mach/map.h> -#include <mach/regs-sys.h> -#include <plat/cpu.h> -#include <plat/regs-usb-hsotg-phy.h> -#include <plat/usb-phy.h> - -static int s3c_usb_otgphy_init(struct platform_device *pdev) -{ - struct clk *xusbxti; - u32 phyclk; - - writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); - - /* set clock frequency for PLL */ - phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; - - xusbxti = clk_get(&pdev->dev, "xusbxti"); - if (xusbxti && !IS_ERR(xusbxti)) { - switch (clk_get_rate(xusbxti)) { - case 12 * MHZ: - phyclk |= S3C_PHYCLK_CLKSEL_12M; - break; - case 24 * MHZ: - phyclk |= S3C_PHYCLK_CLKSEL_24M; - break; - default: - case 48 * MHZ: - /* default reference clock */ - break; - } - clk_put(xusbxti); - } - - /* TODO: select external clock/oscillator */ - writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); - - /* set to normal OTG PHY */ - writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); - mdelay(1); - - /* reset OTG PHY and Link */ - writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, - S3C_RSTCON); - udelay(20); /* at-least 10uS */ - writel(0, S3C_RSTCON); - - return 0; -} - -static int s3c_usb_otgphy_exit(struct platform_device *pdev) -{ - writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | - S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR); - - writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); - - return 0; -} - -int s5p_usb_phy_init(struct platform_device *pdev, int type) -{ - if (type == S5P_USB_PHY_DEVICE) - return s3c_usb_otgphy_init(pdev); - - return -EINVAL; -} - -int s5p_usb_phy_exit(struct platform_device *pdev, int type) -{ - if (type == S5P_USB_PHY_DEVICE) - return s3c_usb_otgphy_exit(pdev); - - return -EINVAL; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/sleep.S b/ANDROID_3.4.5/arch/arm/mach-s3c64xx/sleep.S deleted file mode 100644 index 34313f9c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-s3c64xx/sleep.S +++ /dev/null @@ -1,72 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/sleep.S - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX CPU sleep code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <mach/map.h> - -#undef S3C64XX_VA_GPIO -#define S3C64XX_VA_GPIO (0x0) - -#include <mach/regs-gpio.h> - -#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) - - .text - - /* Sleep magic, the word before the resume entry point so that the - * bootloader can check for a resumeable image. */ - - .word 0x2bedf00d - - /* s3c_cpu_reusme - * - * This is the entry point, stored by whatever method the bootloader - * requires to get the kernel runnign again. This code expects to be - * entered with no caches live and the MMU disabled. It will then - * restore the MMU and other basic CP registers saved and restart - * the kernel C code to finish the resume code. - */ - -ENTRY(s3c_cpu_resume) - msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE - ldr r2, =LL_UART /* for debug */ - -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK - -#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) -#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) - -#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) -#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) - - /* Initialise the GPIO state if we are debugging via the SMDK LEDs, - * as the uboot version supplied resets these to inputs during the - * resume checks. - */ - - ldr r3, =S3C64XX_PA_GPIO - ldr r0, [ r3, #S3C64XX_GPNCON ] - bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ - S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) - orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ - S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) - str r0, [ r3, #S3C64XX_GPNCON ] - - ldr r0, [ r3, #S3C64XX_GPNDAT ] - bic r0, r0, #0xf << 12 @ GPN12..15 - orr r0, r0, #1 << 15 @ GPN15 - str r0, [ r3, #S3C64XX_GPNDAT ] -#endif - b cpu_resume |