diff options
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-imx')
114 files changed, 0 insertions, 30334 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/Kconfig b/ANDROID_3.4.5/arch/arm/mach-imx/Kconfig deleted file mode 100644 index 7561eca1..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/Kconfig +++ /dev/null @@ -1,850 +0,0 @@ -config HAVE_IMX_GPC - bool - -config HAVE_IMX_MMDC - bool - -config HAVE_IMX_SRC - bool - -config ARCH_MX1 - bool - -config MACH_MX21 - bool - -config ARCH_MX25 - bool - -config MACH_MX27 - bool - -config ARCH_MX5 - bool - -config ARCH_MX50 - bool - -config ARCH_MX51 - bool - -config ARCH_MX53 - bool - -config SOC_IMX1 - bool - select ARCH_MX1 - select CPU_ARM920T - select IMX_HAVE_IOMUX_V1 - select MXC_AVIC - -config SOC_IMX21 - bool - select MACH_MX21 - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 - select MXC_AVIC - -config SOC_IMX25 - bool - select ARCH_MX25 - select CPU_ARM926T - select ARCH_MXC_IOMUX_V3 - select MXC_AVIC - -config SOC_IMX27 - bool - select MACH_MX27 - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 - select MXC_AVIC - -config SOC_IMX31 - bool - select CPU_V6 - select IMX_HAVE_PLATFORM_MXC_RNGA - select MXC_AVIC - select SMP_ON_UP if SMP - -config SOC_IMX35 - bool - select CPU_V6 - select ARCH_MXC_IOMUX_V3 - select HAVE_EPIT - select MXC_AVIC - select SMP_ON_UP if SMP - -config SOC_IMX5 - select CPU_V7 - select MXC_TZIC - select ARCH_MXC_IOMUX_V3 - select ARCH_HAS_CPUFREQ - select ARCH_MX5 - bool - -config SOC_IMX50 - bool - select SOC_IMX5 - select ARCH_MX50 - -config SOC_IMX51 - bool - select SOC_IMX5 - select ARCH_MX5 - select ARCH_MX51 - -config SOC_IMX53 - bool - select SOC_IMX5 - select ARCH_MX5 - select ARCH_MX53 - -if ARCH_IMX_V4_V5 - -comment "MX1 platforms:" -config MACH_MXLADS - bool - -config ARCH_MX1ADS - bool "MX1ADS platform" - select MACH_MXLADS - select SOC_IMX1 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - help - Say Y here if you are using Motorola MX1ADS/MXLADS boards - -config MACH_SCB9328 - bool "Synertronixx scb9328" - select IMX_HAVE_PLATFORM_IMX_UART - help - Say Y here if you are using a Synertronixx scb9328 board - -config MACH_APF9328 - bool "APF9328" - select SOC_IMX1 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - help - Say Yes here if you are using the Armadeus APF9328 development board - -comment "MX21 platforms:" - -config MACH_MX21ADS - bool "MX21ADS platform" - select SOC_IMX21 - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - help - Include support for MX21ADS platform. This includes specific - configurations for the board and its peripherals. - -comment "MX25 platforms:" - -config MACH_MX25_3DS - bool "Support MX25PDK (3DS) Platform" - select SOC_IMX25 - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - -config MACH_EUKREA_CPUIMX25SD - bool "Support Eukrea CPUIMX25 Platform" - select SOC_IMX25 - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX25SD - default MACH_EUKREA_MBIMXSD25_BASEBOARD - -config MACH_EUKREA_MBIMXSD25_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_SSI - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -comment "MX27 platforms:" - -config MACH_MX27ADS - bool "MX27ADS platform" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - help - Include support for MX27ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCM038 - bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for phyCORE-i.MX27 (aka pcm038) platform. This - includes specific configurations for the module and its peripherals. - -choice - prompt "Baseboard" - depends on MACH_PCM038 - default MACH_PCM970_BASEBOARD - -config MACH_PCM970_BASEBOARD - bool "PHYTEC PCM970 development board" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_MXC_MMC - help - This adds board specific devices that can be found on Phytec's - PCM970 evaluation board. - -endchoice - -config MACH_CPUIMX27 - bool "Eukrea CPUIMX27 module" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select MXC_ULPI if USB_ULPI - help - Include support for Eukrea CPUIMX27 platform. This includes - specific configurations for the module and its peripherals. - -config MACH_EUKREA_CPUIMX27_USESDHC2 - bool "CPUIMX27 integrates SDHC2 module" - depends on MACH_CPUIMX27 - select IMX_HAVE_PLATFORM_MXC_MMC - help - This adds support for the internal SDHC2 used on CPUIMX27 - for wifi or eMMC. - -config MACH_EUKREA_CPUIMX27_USEUART4 - bool "CPUIMX27 integrates UART4 module" - depends on MACH_CPUIMX27 - help - This adds support for the internal UART4 used on CPUIMX27 - for bluetooth. - -choice - prompt "Baseboard" - depends on MACH_CPUIMX27 - default MACH_EUKREA_MBIMX27_BASEBOARD - -config MACH_EUKREA_MBIMX27_BASEBOARD - bool "Eukrea MBIMX27 development board" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMX27 evaluation board. - -endchoice - -config MACH_MX27_3DS - bool "MX27PDK platform" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MX2_CAMERA - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select MXC_ULPI if USB_ULPI - help - Include support for MX27PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_IMX27_VISSTRIM_M10 - bool "Vista Silicon i.MX27 Visstrim_m10" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MX2_CAMERA - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select LEDS_GPIO_REGISTER - help - Include support for Visstrim_m10 platform and its different variants. - This includes specific configurations for the board and its - peripherals. - -config MACH_IMX27LITE - bool "LogicPD MX27 LITEKIT platform" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX_SSI - help - Include support for MX27 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCA100 - bool "Phytec phyCARD-s (pca100)" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for phyCARD-s (aka pca100) platform. This - includes specific configurations for the module and its peripherals. - -config MACH_MXT_TD60 - bool "Maxtrack i-MXT TD60" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - help - Include support for i-MXT (aka td60) platform. This - includes specific configurations for the module and its peripherals. - -config MACH_IMX27IPCAM - bool "IMX27 IPCAM platform" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - help - Include support for IMX27 IPCAM platform. This includes specific - configurations for the board and its peripherals. - -config MACH_IMX27_DT - bool "Support i.MX27 platforms from device tree" - select SOC_IMX27 - select USE_OF - help - Include support for Freescale i.MX27 based platforms - using the device tree for discovery - -endif - -if ARCH_IMX_V6_V7 - -comment "MX31 platforms:" - -config MACH_MX31ADS - bool "Support MX31ADS platforms" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - default y - help - Include support for MX31ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31ADS_WM1133_EV1 - bool "Support Wolfson Microelectronics 1133-EV1 module" - depends on MACH_MX31ADS - depends on MFD_WM8350_I2C - depends on REGULATOR_WM8350 - select MFD_WM8350_CONFIG_MODE_0 - select MFD_WM8352_CONFIG_MODE_0 - help - Include support for the Wolfson Microelectronics 1133-EV1 PMU - and audio module for the MX31ADS platform. - -config MACH_MX31LILLY - bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for mx31 based LILLY1131 modules. This includes - specific configurations for the board and its peripherals. - -config MACH_MX31LITE - bool "Support MX31 LITEKIT (LogicPD)" - select SOC_IMX31 - select MXC_ULPI if USB_ULPI - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_RTC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - Include support for MX31 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCM037 - bool "Support Phytec pcm037 (i.MX31) platforms" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select MXC_ULPI if USB_ULPI - help - Include support for Phytec pcm037 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_PCM037_EET - bool "Support pcm037 EET board extensions" - depends on MACH_PCM037 - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_SPI_IMX - help - Add support for PCM037 EET baseboard extensions. If you are using the - OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel - command-line parameter. - -config MACH_MX31_3DS - bool "Support MX31PDK (3DS)" - select SOC_IMX31 - select MXC_DEBUG_BOARD - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for MX31PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31_3DS_MXC_NAND_USE_BBT - bool "Make the MXC NAND driver use the in flash Bad Block Table" - depends on MACH_MX31_3DS - depends on MTD_NAND_MXC - help - Enable this if you want that the MXC NAND driver uses the in flash - Bad Block Table to know what blocks are bad instead of scanning the - entire flash looking for bad block markers. - -config MACH_MX31MOBOARD - bool "Support mx31moboard platforms (EPFL Mobots group)" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - select MXC_ULPI if USB_ULPI - help - Include support for mx31moboard platform. This includes specific - configurations for the board and its peripherals. - -config MACH_QONG - bool "Support Dave/DENX QongEVB-LITE platform" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX2_WDT - help - Include support for Dave/DENX QongEVB-LITE platform. This includes - specific configurations for the board and its peripherals. - -config MACH_ARMADILLO5X0 - bool "Support Atmark Armadillo-500 Development Base Board" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select MXC_ULPI if USB_ULPI - help - Include support for Atmark Armadillo-500 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_KZM_ARM11_01 - bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - help - Include support for KZM-ARM11-01. This includes specific - configurations for the board and its peripherals. - -config MACH_BUG - bool "Support Buglabs BUGBase platform" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - default y - help - Include support for BUGBase 1.3 platform. This includes specific - configurations for the board and its peripherals. - -comment "MX35 platforms:" - -config MACH_PCM043 - bool "Support Phytec pcm043 (i.MX35) platforms" - select SOC_IMX35 - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI - help - Include support for Phytec pcm043 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_MX35_3DS - bool "Support MX35PDK platform" - select SOC_IMX35 - select MXC_DEBUG_BOARD - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for MX35PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_EUKREA_CPUIMX35SD - bool "Support Eukrea CPUIMX35 Platform" - select SOC_IMX35 - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI - help - Include support for Eukrea CPUIMX35 platform. This includes - specific configurations for the board and its peripherals. - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX35SD - default MACH_EUKREA_MBIMXSD35_BASEBOARD - -config MACH_EUKREA_MBIMXSD35_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IPU_CORE - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -config MACH_VPR200 - bool "Support VPR200 platform" - select SOC_IMX35 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for VPR200 platform. This includes specific - configurations for the board and its peripherals. - -comment "i.MX5 platforms:" - -config MACH_MX50_RDP - bool "Support MX50 reference design platform" - depends on BROKEN - select SOC_IMX50 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - help - Include support for MX50 reference design platform (RDP) board. This - includes specific configurations for the board and its peripherals. - -comment "i.MX51 machines:" - -config MACH_IMX51_DT - bool "Support i.MX51 platforms from device tree" - select SOC_IMX51 - select USE_OF - select MACH_MX51_BABBAGE - help - Include support for Freescale i.MX51 based platforms - using the device tree for discovery - -config MACH_MX51_BABBAGE - bool "Support MX51 BABBAGE platforms" - select SOC_IMX51 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - help - Include support for MX51 Babbage platform, also known as MX51EVK in - u-boot. This includes specific configurations for the board and its - peripherals. - -config MACH_MX51_3DS - bool "Support MX51PDK (3DS)" - select SOC_IMX51 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - help - Include support for MX51PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. - -config MACH_EUKREA_CPUIMX51 - bool "Support Eukrea CPUIMX51 module" - select SOC_IMX51 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - help - Include support for Eukrea CPUIMX51 platform. This includes - specific configurations for the module and its peripherals. - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX51 - default MACH_EUKREA_MBIMX51_BASEBOARD - -config MACH_EUKREA_MBIMX51_BASEBOARD - prompt "Eukrea MBIMX51 development board" - bool - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMX51 evaluation board. - -endchoice - -config MACH_EUKREA_CPUIMX51SD - bool "Support Eukrea CPUIMX51SD module" - select SOC_IMX51 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - help - Include support for Eukrea CPUIMX51SD platform. This includes - specific configurations for the module and its peripherals. - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX51SD - default MACH_EUKREA_MBIMXSD51_BASEBOARD - -config MACH_EUKREA_MBIMXSD51_BASEBOARD - prompt "Eukrea MBIMXSD development board" - bool - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -config MX51_EFIKA_COMMON - bool - select SOC_IMX51 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_PATA_IMX - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - -config MACH_MX51_EFIKAMX - bool "Support MX51 Genesi Efika MX nettop" - select LEDS_GPIO_REGISTER - select MX51_EFIKA_COMMON - help - Include support for Genesi Efika MX nettop. This includes specific - configurations for the board and its peripherals. - -config MACH_MX51_EFIKASB - bool "Support MX51 Genesi Efika Smartbook" - select LEDS_GPIO_REGISTER - select MX51_EFIKA_COMMON - help - Include support for Genesi Efika Smartbook. This includes specific - configurations for the board and its peripherals. - -comment "i.MX53 machines:" - -config MACH_IMX53_DT - bool "Support i.MX53 platforms from device tree" - select SOC_IMX53 - select USE_OF - select MACH_MX53_ARD - select MACH_MX53_EVK - select MACH_MX53_LOCO - select MACH_MX53_SMD - help - Include support for Freescale i.MX53 based platforms - using the device tree for discovery - -config MACH_MX53_EVK - bool "Support MX53 EVK platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - Include support for MX53 EVK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX53_SMD - bool "Support MX53 SMD platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for MX53 SMD platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX53_LOCO - bool "Support MX53 LOCO platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_GPIO_KEYS - select LEDS_GPIO_REGISTER - help - Include support for MX53 LOCO platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX53_ARD - bool "Support MX53 ARD platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_GPIO_KEYS - help - Include support for MX53 ARD platform. This includes specific - configurations for the board and its peripherals. - -comment "i.MX6 family:" - -config SOC_IMX6Q - bool "i.MX6 Quad support" - select ARM_CPU_SUSPEND if PM - select ARM_GIC - select CPU_V7 - select HAVE_ARM_SCU - select HAVE_IMX_GPC - select HAVE_IMX_MMDC - select HAVE_IMX_SRC - select HAVE_SMP - select USE_OF - - help - This enables support for Freescale i.MX6 Quad processor. - -endif diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/Makefile b/ANDROID_3.4.5/arch/arm/mach-imx/Makefile deleted file mode 100644 index ab939c50..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/Makefile +++ /dev/null @@ -1,96 +0,0 @@ -obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o -obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o - -obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o - -obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o -obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o - -obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o -obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o - -obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o - -# Support for CMOS sensor interface -obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o - -# i.MX1 based machines -obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o -obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o - -# i.MX21 based machines -obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o - -# i.MX25 based machines -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o - -# i.MX27 based machines -obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o -obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o -obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o -obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o -obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o -obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o -obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o -obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o -obj-$(CONFIG_MACH_PCA100) += mach-pca100.o -obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o -obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o -obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o - -# i.MX31 based machines -obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o -obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o -obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o -obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ - mx31moboard-marxbot.o mx31moboard-smartbot.o -obj-$(CONFIG_MACH_QONG) += mach-qong.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o -obj-$(CONFIG_MACH_BUG) += mach-bug.o - -# i.MX35 based machines -obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o -obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o - -obj-$(CONFIG_DEBUG_LL) += lluart.o -obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o -obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o -obj-$(CONFIG_HAVE_IMX_SRC) += src.o -obj-$(CONFIG_CPU_V7) += head-v7.o -AFLAGS_head-v7.o :=-Wa,-march=armv7-a -obj-$(CONFIG_SMP) += platsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o - -ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o -endif - -# i.MX5 based machines -obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o -obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o -obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o -obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o -obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o -obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o -obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o -obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o -obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o -obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o -obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o - -obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o -obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/Makefile.boot b/ANDROID_3.4.5/arch/arm/mach-imx/Makefile.boot deleted file mode 100644 index 3851d8a2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/Makefile.boot +++ /dev/null @@ -1,45 +0,0 @@ -zreladdr-$(CONFIG_SOC_IMX1) += 0x08008000 -params_phys-$(CONFIG_SOC_IMX1) := 0x08000100 -initrd_phys-$(CONFIG_SOC_IMX1) := 0x08800000 - -zreladdr-$(CONFIG_SOC_IMX21) += 0xC0008000 -params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100 -initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000 - -zreladdr-$(CONFIG_SOC_IMX25) += 0x80008000 -params_phys-$(CONFIG_SOC_IMX25) := 0x80000100 -initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000 - -zreladdr-$(CONFIG_SOC_IMX27) += 0xA0008000 -params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100 -initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000 - -zreladdr-$(CONFIG_SOC_IMX31) += 0x80008000 -params_phys-$(CONFIG_SOC_IMX31) := 0x80000100 -initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000 - -zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000 -params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 -initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 - -zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000 -params_phys-$(CONFIG_SOC_IMX50) := 0x70000100 -initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000 - -zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 -params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 -initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 - -zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000 -params_phys-$(CONFIG_SOC_IMX53) := 0x70000100 -initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000 - -zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 -params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 -initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 - -dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb -dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ - imx53-qsb.dtb imx53-smd.dtb -dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ - imx6q-sabrelite.dtb diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx1.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx1.c deleted file mode 100644 index 4aabeb24..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx1.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/math64.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <mach/clock.h> -#include <mach/hardware.h> -#include <mach/common.h> - -#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) - -/* CCM register addresses */ -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_PCDR IO_ADDR_CCM(0x20) - -#define CCM_CSCR_CLKO_OFFSET 29 -#define CCM_CSCR_CLKO_MASK (0x7 << 29) -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << 26) -#define CCM_CSCR_OSC_EN_SHIFT 17 -#define CCM_CSCR_SYSTEM_SEL (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xf << 10) -#define CCM_CSCR_PRESC (1 << 15) - -#define CCM_PCDR_PCLK3_OFFSET 16 -#define CCM_PCDR_PCLK3_MASK (0x7f << 16) -#define CCM_PCDR_PCLK2_OFFSET 4 -#define CCM_PCDR_PCLK2_MASK (0xf << 4) -#define CCM_PCDR_PCLK1_OFFSET 0 -#define CCM_PCDR_PCLK1_MASK 0xf - -#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) - -/* SCM register addresses */ -#define SCM_GCCR IO_ADDR_SCM(0xc) - -#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 -#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 -#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 -#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 - -static int _clk_enable(struct clk *clk) -{ - unsigned int reg; - - reg = __raw_readl(clk->enable_reg); - reg |= 1 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void _clk_disable(struct clk *clk) -{ - unsigned int reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(1 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size, - struct clk *parent) -{ - int i; - - for (i = 0; i < size; i++) - if (parent == clk_arr[i]) - return i; - - return -EINVAL; -} - -static unsigned long -_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit) -{ - int div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (parent_rate % rate) - div++; - - if (div > limit) - div = limit; - - return parent_rate / div; -} - -static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) -{ - return clk->parent->round_rate(clk->parent, rate); -} - -static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) -{ - return clk->parent->set_rate(clk->parent, rate); -} - -static unsigned long clk16m_get_rate(struct clk *clk) -{ - return 16000000; -} - -static struct clk clk16m = { - .get_rate = clk16m_get_rate, - .enable = _clk_enable, - .enable_reg = CCM_CSCR, - .enable_shift = CCM_CSCR_OSC_EN_SHIFT, - .disable = _clk_disable, -}; - -/* in Hz */ -static unsigned long clk32_rate; - -static unsigned long clk32_get_rate(struct clk *clk) -{ - return clk32_rate; -} - -static struct clk clk32 = { - .get_rate = clk32_get_rate, -}; - -static unsigned long clk32_premult_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) * 512; -} - -static struct clk clk32_premult = { - .parent = &clk32, - .get_rate = clk32_premult_get_rate, -}; - -static const struct clk *prem_clk_clocks[] = { - &clk32_premult, - &clk16m, -}; - -static int prem_clk_set_parent(struct clk *clk, struct clk *parent) -{ - int i; - unsigned int reg = __raw_readl(CCM_CSCR); - - i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks), - parent); - - switch (i) { - case 0: - reg &= ~CCM_CSCR_SYSTEM_SEL; - break; - case 1: - reg |= CCM_CSCR_SYSTEM_SEL; - break; - default: - return i; - } - - __raw_writel(reg, CCM_CSCR); - - return 0; -} - -static struct clk prem_clk = { - .set_parent = prem_clk_set_parent, -}; - -static unsigned long system_clk_get_rate(struct clk *clk) -{ - return mxc_decode_pll(__raw_readl(CCM_SPCTL0), - clk_get_rate(clk->parent)); -} - -static struct clk system_clk = { - .parent = &prem_clk, - .get_rate = system_clk_get_rate, -}; - -static unsigned long mcu_clk_get_rate(struct clk *clk) -{ - return mxc_decode_pll(__raw_readl(CCM_MPCTL0), - clk_get_rate(clk->parent)); -} - -static struct clk mcu_clk = { - .parent = &clk32_premult, - .get_rate = mcu_clk_get_rate, -}; - -static unsigned long fclk_get_rate(struct clk *clk) -{ - unsigned long fclk = clk_get_rate(clk->parent); - - if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC) - fclk /= 2; - - return fclk; -} - -static struct clk fclk = { - .parent = &mcu_clk, - .get_rate = fclk_get_rate, -}; - -/* - * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA ) - */ -static unsigned long hclk_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) & - CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1); -} - -static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate) -{ - return _clk_simple_round_rate(clk, rate, 16); -} - -static int hclk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int div; - unsigned int reg; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 16 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - div--; - - reg = __raw_readl(CCM_CSCR); - reg &= ~CCM_CSCR_BCLK_MASK; - reg |= div << CCM_CSCR_BCLK_OFFSET; - __raw_writel(reg, CCM_CSCR); - - return 0; -} - -static struct clk hclk = { - .parent = &system_clk, - .get_rate = hclk_get_rate, - .round_rate = hclk_round_rate, - .set_rate = hclk_set_rate, -}; - -static unsigned long clk48m_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) & - CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1); -} - -static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate) -{ - return _clk_simple_round_rate(clk, rate, 8); -} - -static int clk48m_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int div; - unsigned int reg; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 8 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - div--; - - reg = __raw_readl(CCM_CSCR); - reg &= ~CCM_CSCR_USB_MASK; - reg |= div << CCM_CSCR_USB_OFFSET; - __raw_writel(reg, CCM_CSCR); - - return 0; -} - -static struct clk clk48m = { - .parent = &system_clk, - .get_rate = clk48m_get_rate, - .round_rate = clk48m_round_rate, - .set_rate = clk48m_set_rate, -}; - -/* - * get peripheral clock 1 ( UART[12], Timer[12], PWM ) - */ -static unsigned long perclk1_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & - CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1); -} - -static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate) -{ - return _clk_simple_round_rate(clk, rate, 16); -} - -static int perclk1_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int div; - unsigned int reg; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 16 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - div--; - - reg = __raw_readl(CCM_PCDR); - reg &= ~CCM_PCDR_PCLK1_MASK; - reg |= div << CCM_PCDR_PCLK1_OFFSET; - __raw_writel(reg, CCM_PCDR); - - return 0; -} - -/* - * get peripheral clock 2 ( LCD, SD, SPI[12] ) - */ -static unsigned long perclk2_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & - CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1); -} - -static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate) -{ - return _clk_simple_round_rate(clk, rate, 16); -} - -static int perclk2_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int div; - unsigned int reg; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 16 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - div--; - - reg = __raw_readl(CCM_PCDR); - reg &= ~CCM_PCDR_PCLK2_MASK; - reg |= div << CCM_PCDR_PCLK2_OFFSET; - __raw_writel(reg, CCM_PCDR); - - return 0; -} - -/* - * get peripheral clock 3 ( SSI ) - */ -static unsigned long perclk3_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & - CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1); -} - -static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate) -{ - return _clk_simple_round_rate(clk, rate, 128); -} - -static int perclk3_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int div; - unsigned int reg; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 128 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - div--; - - reg = __raw_readl(CCM_PCDR); - reg &= ~CCM_PCDR_PCLK3_MASK; - reg |= div << CCM_PCDR_PCLK3_OFFSET; - __raw_writel(reg, CCM_PCDR); - - return 0; -} - -static struct clk perclk[] = { - { - .id = 0, - .parent = &system_clk, - .get_rate = perclk1_get_rate, - .round_rate = perclk1_round_rate, - .set_rate = perclk1_set_rate, - }, { - .id = 1, - .parent = &system_clk, - .get_rate = perclk2_get_rate, - .round_rate = perclk2_round_rate, - .set_rate = perclk2_set_rate, - }, { - .id = 2, - .parent = &system_clk, - .get_rate = perclk3_get_rate, - .round_rate = perclk3_round_rate, - .set_rate = perclk3_set_rate, - } -}; - -static const struct clk *clko_clocks[] = { - &perclk[0], - &hclk, - &clk48m, - &clk16m, - &prem_clk, - &fclk, -}; - -static int clko_set_parent(struct clk *clk, struct clk *parent) -{ - int i; - unsigned int reg; - - i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent); - if (i < 0) - return i; - - reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK; - reg |= i << CCM_CSCR_CLKO_OFFSET; - __raw_writel(reg, CCM_CSCR); - - if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) { - clk->set_rate = _clk_parent_set_rate; - clk->round_rate = _clk_parent_round_rate; - } else { - clk->set_rate = NULL; - clk->round_rate = NULL; - } - - return 0; -} - -static struct clk clko_clk = { - .set_parent = clko_set_parent, -}; - -static struct clk dma_clk = { - .parent = &hclk, - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, - .enable = _clk_enable, - .enable_reg = SCM_GCCR, - .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET, - .disable = _clk_disable, -}; - -static struct clk csi_clk = { - .parent = &hclk, - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, - .enable = _clk_enable, - .enable_reg = SCM_GCCR, - .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET, - .disable = _clk_disable, -}; - -static struct clk mma_clk = { - .parent = &hclk, - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, - .enable = _clk_enable, - .enable_reg = SCM_GCCR, - .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET, - .disable = _clk_disable, -}; - -static struct clk usbd_clk = { - .parent = &clk48m, - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, - .enable = _clk_enable, - .enable_reg = SCM_GCCR, - .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET, - .disable = _clk_disable, -}; - -static struct clk gpt_clk = { - .parent = &perclk[0], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk uart_clk = { - .parent = &perclk[0], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk i2c_clk = { - .parent = &hclk, - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk spi_clk = { - .parent = &perclk[1], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk sdhc_clk = { - .parent = &perclk[1], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk lcdc_clk = { - .parent = &perclk[1], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk mshc_clk = { - .parent = &hclk, - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk ssi_clk = { - .parent = &perclk[2], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, -}; - -static struct clk rtc_clk = { - .parent = &clk32, -}; - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, -static struct clk_lookup lookups[] __initdata = { - _REGISTER_CLOCK(NULL, "dma", dma_clk) - _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk) - _REGISTER_CLOCK(NULL, "mma", mma_clk) - _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk) - _REGISTER_CLOCK(NULL, "gpt", gpt_clk) - _REGISTER_CLOCK("imx1-uart.0", NULL, uart_clk) - _REGISTER_CLOCK("imx1-uart.1", NULL, uart_clk) - _REGISTER_CLOCK("imx1-uart.2", NULL, uart_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) - _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk) - _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk) - _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) - _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK(NULL, "mshc", mshc_clk) - _REGISTER_CLOCK(NULL, "ssi", ssi_clk) - _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk) -}; - -int __init mx1_clocks_init(unsigned long fref) -{ - unsigned int reg; - - /* disable clocks we are able to */ - __raw_writel(0, SCM_GCCR); - - clk32_rate = fref; - reg = __raw_readl(CCM_CSCR); - - /* detect clock reference for system PLL */ - if (reg & CCM_CSCR_SYSTEM_SEL) { - prem_clk.parent = &clk16m; - } else { - /* ensure that oscillator is disabled */ - reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT); - __raw_writel(reg, CCM_CSCR); - prem_clk.parent = &clk32_premult; - } - - /* detect reference for CLKO */ - reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET; - clko_clk.parent = (struct clk *)clko_clocks[reg]; - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - clk_enable(&hclk); - clk_enable(&fclk); - - mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), - MX1_TIM1_INT); - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx21.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx21.c deleted file mode 100644 index ee15d8c9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx21.c +++ /dev/null @@ -1,1239 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/clkdev.h> - -#include <mach/clock.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <asm/div64.h> - -#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) - -/* Register offsets */ -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_MPCTL1 IO_ADDR_CCM(0x8) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_SPCTL1 IO_ADDR_CCM(0x10) -#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) -#define CCM_PCDR0 IO_ADDR_CCM(0x18) -#define CCM_PCDR1 IO_ADDR_CCM(0x1c) -#define CCM_PCCR0 IO_ADDR_CCM(0x20) -#define CCM_PCCR1 IO_ADDR_CCM(0x24) -#define CCM_CCSR IO_ADDR_CCM(0x28) -#define CCM_PMCTL IO_ADDR_CCM(0x2c) -#define CCM_PMCOUNT IO_ADDR_CCM(0x30) -#define CCM_WKGDCTL IO_ADDR_CCM(0x34) - -#define CCM_CSCR_PRESC_OFFSET 29 -#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) - -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) -#define CCM_CSCR_SD_OFFSET 24 -#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) -#define CCM_CSCR_SPLLRES (1 << 22) -#define CCM_CSCR_MPLLRES (1 << 21) -#define CCM_CSCR_SSI2_OFFSET 20 -#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) -#define CCM_CSCR_SSI1_OFFSET 19 -#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) -#define CCM_CSCR_FIR_OFFSET 18 -#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) -#define CCM_CSCR_SP (1 << 17) -#define CCM_CSCR_MCU (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) -#define CCM_CSCR_IPDIV_OFFSET 9 -#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) - -#define CCM_CSCR_OSC26MDIV (1 << 4) -#define CCM_CSCR_OSC26M (1 << 3) -#define CCM_CSCR_FPM (1 << 2) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN 1 - -#define CCM_MPCTL0_CPLM (1 << 31) -#define CCM_MPCTL0_PD_OFFSET 26 -#define CCM_MPCTL0_PD_MASK (0xf << 26) -#define CCM_MPCTL0_MFD_OFFSET 16 -#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) -#define CCM_MPCTL0_MFI_OFFSET 10 -#define CCM_MPCTL0_MFI_MASK (0xf << 10) -#define CCM_MPCTL0_MFN_OFFSET 0 -#define CCM_MPCTL0_MFN_MASK 0x3ff - -#define CCM_MPCTL1_LF (1 << 15) -#define CCM_MPCTL1_BRMO (1 << 6) - -#define CCM_SPCTL0_CPLM (1 << 31) -#define CCM_SPCTL0_PD_OFFSET 26 -#define CCM_SPCTL0_PD_MASK (0xf << 26) -#define CCM_SPCTL0_MFD_OFFSET 16 -#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) -#define CCM_SPCTL0_MFI_OFFSET 10 -#define CCM_SPCTL0_MFI_MASK (0xf << 10) -#define CCM_SPCTL0_MFN_OFFSET 0 -#define CCM_SPCTL0_MFN_MASK 0x3ff - -#define CCM_SPCTL1_LF (1 << 15) -#define CCM_SPCTL1_BRMO (1 << 6) - -#define CCM_OSC26MCTL_PEAK_OFFSET 16 -#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) -#define CCM_OSC26MCTL_AGC_OFFSET 8 -#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) -#define CCM_OSC26MCTL_ANATEST_OFFSET 0 -#define CCM_OSC26MCTL_ANATEST_MASK 0x3f - -#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 -#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) -#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 -#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) -#define CCM_PCDR0_NFCDIV_OFFSET 12 -#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) -#define CCM_PCDR0_48MDIV_OFFSET 5 -#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) -#define CCM_PCDR0_FIRIDIV_OFFSET 0 -#define CCM_PCDR0_FIRIDIV_MASK 0x1f -#define CCM_PCDR1_PERDIV4_OFFSET 24 -#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) -#define CCM_PCDR1_PERDIV3_OFFSET 16 -#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) -#define CCM_PCDR1_PERDIV2_OFFSET 8 -#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) -#define CCM_PCDR1_PERDIV1_OFFSET 0 -#define CCM_PCDR1_PERDIV1_MASK 0x3f - -#define CCM_PCCR_HCLK_CSI_OFFSET 31 -#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_DMA_OFFSET 30 -#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_BROM_OFFSET 28 -#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_EMMA_OFFSET 27 -#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_LCDC_OFFSET 26 -#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_SLCDC_OFFSET 25 -#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_USBOTG_OFFSET 24 -#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_BMI_OFFSET 23 -#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) -#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 -#define CCM_PCCR_PERCLK4_OFFSET 22 -#define CCM_PCCR_PERCLK4_REG CCM_PCCR0 -#define CCM_PCCR_SLCDC_OFFSET 21 -#define CCM_PCCR_SLCDC_REG CCM_PCCR0 -#define CCM_PCCR_FIRI_BAUD_OFFSET 20 -#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) -#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_NFC_OFFSET 19 -#define CCM_PCCR_NFC_REG CCM_PCCR0 -#define CCM_PCCR_LCDC_OFFSET 18 -#define CCM_PCCR_LCDC_REG CCM_PCCR0 -#define CCM_PCCR_SSI1_BAUD_OFFSET 17 -#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_SSI2_BAUD_OFFSET 16 -#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_EMMA_OFFSET 15 -#define CCM_PCCR_EMMA_REG CCM_PCCR0 -#define CCM_PCCR_USBOTG_OFFSET 14 -#define CCM_PCCR_USBOTG_REG CCM_PCCR0 -#define CCM_PCCR_DMA_OFFSET 13 -#define CCM_PCCR_DMA_REG CCM_PCCR0 -#define CCM_PCCR_I2C1_OFFSET 12 -#define CCM_PCCR_I2C1_REG CCM_PCCR0 -#define CCM_PCCR_GPIO_OFFSET 11 -#define CCM_PCCR_GPIO_REG CCM_PCCR0 -#define CCM_PCCR_SDHC2_OFFSET 10 -#define CCM_PCCR_SDHC2_REG CCM_PCCR0 -#define CCM_PCCR_SDHC1_OFFSET 9 -#define CCM_PCCR_SDHC1_REG CCM_PCCR0 -#define CCM_PCCR_FIRI_OFFSET 8 -#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) -#define CCM_PCCR_FIRI_REG CCM_PCCR0 -#define CCM_PCCR_SSI2_IPG_OFFSET 7 -#define CCM_PCCR_SSI2_REG CCM_PCCR0 -#define CCM_PCCR_SSI1_IPG_OFFSET 6 -#define CCM_PCCR_SSI1_REG CCM_PCCR0 -#define CCM_PCCR_CSPI2_OFFSET 5 -#define CCM_PCCR_CSPI2_REG CCM_PCCR0 -#define CCM_PCCR_CSPI1_OFFSET 4 -#define CCM_PCCR_CSPI1_REG CCM_PCCR0 -#define CCM_PCCR_UART4_OFFSET 3 -#define CCM_PCCR_UART4_REG CCM_PCCR0 -#define CCM_PCCR_UART3_OFFSET 2 -#define CCM_PCCR_UART3_REG CCM_PCCR0 -#define CCM_PCCR_UART2_OFFSET 1 -#define CCM_PCCR_UART2_REG CCM_PCCR0 -#define CCM_PCCR_UART1_OFFSET 0 -#define CCM_PCCR_UART1_REG CCM_PCCR0 - -#define CCM_PCCR_OWIRE_OFFSET 31 -#define CCM_PCCR_OWIRE_REG CCM_PCCR1 -#define CCM_PCCR_KPP_OFFSET 30 -#define CCM_PCCR_KPP_REG CCM_PCCR1 -#define CCM_PCCR_RTC_OFFSET 29 -#define CCM_PCCR_RTC_REG CCM_PCCR1 -#define CCM_PCCR_PWM_OFFSET 28 -#define CCM_PCCR_PWM_REG CCM_PCCR1 -#define CCM_PCCR_GPT3_OFFSET 27 -#define CCM_PCCR_GPT3_REG CCM_PCCR1 -#define CCM_PCCR_GPT2_OFFSET 26 -#define CCM_PCCR_GPT2_REG CCM_PCCR1 -#define CCM_PCCR_GPT1_OFFSET 25 -#define CCM_PCCR_GPT1_REG CCM_PCCR1 -#define CCM_PCCR_WDT_OFFSET 24 -#define CCM_PCCR_WDT_REG CCM_PCCR1 -#define CCM_PCCR_CSPI3_OFFSET 23 -#define CCM_PCCR_CSPI3_REG CCM_PCCR1 - -#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) -#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) -#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) -#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) -#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) -#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) -#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) -#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) -#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) -#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) -#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) -#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) -#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) -#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) -#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) -#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) -#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) -#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) -#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) -#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) -#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) -#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) -#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) -#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) -#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) -#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) -#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) -#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) -#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) -#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) -#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) -#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) -#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) -#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) -#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) -#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) -#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) - -#define CCM_CCSR_32KSR (1 << 15) - -#define CCM_CCSR_CLKMODE1 (1 << 9) -#define CCM_CCSR_CLKMODE0 (1 << 8) - -#define CCM_CCSR_CLKOSEL_OFFSET 0 -#define CCM_CCSR_CLKOSEL_MASK 0x1f - -#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ -#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ - -static int _clk_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= 1 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - return 0; -} - -static void _clk_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(1 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -static unsigned long _clk_generic_round_rate(struct clk *clk, - unsigned long rate, - u32 max_divisor) -{ - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (parent_rate % rate) - div++; - - if (div > max_divisor) - div = max_divisor; - - return parent_rate / div; -} - -static int _clk_spll_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(CCM_CSCR); - reg |= CCM_CSCR_SPEN; - __raw_writel(reg, CCM_CSCR); - - while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) - ; - return 0; -} - -static void _clk_spll_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(CCM_CSCR); - reg &= ~CCM_CSCR_SPEN; - __raw_writel(reg, CCM_CSCR); -} - - -#define CSCR() (__raw_readl(CCM_CSCR)) -#define PCDR0() (__raw_readl(CCM_PCDR0)) -#define PCDR1() (__raw_readl(CCM_PCDR1)) - -static unsigned long _clk_perclkx_round_rate(struct clk *clk, - unsigned long rate) -{ - return _clk_generic_round_rate(clk, rate, 64); -} - -static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->id < 0 || clk->id > 3) - return -EINVAL; - - div = parent_rate / rate; - if (div > 64 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - div--; - - reg = - __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << - (clk->id << 3)); - reg |= div << (clk->id << 3); - __raw_writel(reg, CCM_PCDR1); - - return 0; -} - -static unsigned long _clk_usb_recalc(struct clk *clk) -{ - unsigned long usb_pdf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; - - return parent_rate / (usb_pdf + 1U); -} - -static unsigned long _clk_usb_round_rate(struct clk *clk, - unsigned long rate) -{ - return _clk_generic_round_rate(clk, rate, 8); -} - -static int _clk_usb_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div > 8 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - div--; - - reg = CSCR() & ~CCM_CSCR_USB_MASK; - reg |= div << CCM_CSCR_USB_OFFSET; - __raw_writel(reg, CCM_CSCR); - - return 0; -} - -static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf) -{ - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ - - return 2UL * parent_rate / pdf; -} - -static unsigned long _clk_ssi1_recalc(struct clk *clk) -{ - return _clk_ssix_recalc(clk, - (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) - >> CCM_PCDR0_SSI1BAUDDIV_OFFSET); -} - -static unsigned long _clk_ssi2_recalc(struct clk *clk) -{ - return _clk_ssix_recalc(clk, - (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> - CCM_PCDR0_SSI2BAUDDIV_OFFSET); -} - -static unsigned long _clk_nfc_recalc(struct clk *clk) -{ - unsigned long nfc_pdf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK) - >> CCM_PCDR0_NFCDIV_OFFSET; - - return parent_rate / (nfc_pdf + 1); -} - -static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) -{ - return clk->parent->round_rate(clk->parent, rate); -} - -static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) -{ - return clk->parent->set_rate(clk->parent, rate); -} - -static unsigned long external_high_reference; /* in Hz */ - -static unsigned long get_high_reference_clock_rate(struct clk *clk) -{ - return external_high_reference; -} - -/* - * the high frequency external clock reference - * Default case is 26MHz. - */ -static struct clk ckih_clk = { - .get_rate = get_high_reference_clock_rate, -}; - -static unsigned long external_low_reference; /* in Hz */ - -static unsigned long get_low_reference_clock_rate(struct clk *clk) -{ - return external_low_reference; -} - -/* - * the low frequency external clock reference - * Default case is 32.768kHz. - */ -static struct clk ckil_clk = { - .get_rate = get_low_reference_clock_rate, -}; - - -static unsigned long _clk_fpm_recalc(struct clk *clk) -{ - return clk_get_rate(clk->parent) * 512; -} - -/* Output of frequency pre multiplier */ -static struct clk fpm_clk = { - .parent = &ckil_clk, - .get_rate = _clk_fpm_recalc, -}; - -static unsigned long get_mpll_clk(struct clk *clk) -{ - uint32_t reg; - unsigned long ref_clk; - unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; - unsigned long long temp; - - ref_clk = clk_get_rate(clk->parent); - - reg = __raw_readl(CCM_MPCTL0); - pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; - mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; - mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; - mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; - - mfi = (mfi <= 5) ? 5 : mfi; - temp = 2LL * ref_clk * mfn; - do_div(temp, mfd + 1); - temp = 2LL * ref_clk * mfi + temp; - do_div(temp, pdf + 1); - - return (unsigned long)temp; -} - -static struct clk mpll_clk = { - .parent = &ckih_clk, - .get_rate = get_mpll_clk, -}; - -static unsigned long _clk_fclk_get_rate(struct clk *clk) -{ - unsigned long parent_rate; - u32 div; - - div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; - parent_rate = clk_get_rate(clk->parent); - - return parent_rate / (div+1); -} - -static struct clk fclk_clk = { - .parent = &mpll_clk, - .get_rate = _clk_fclk_get_rate -}; - -static unsigned long get_spll_clk(struct clk *clk) -{ - uint32_t reg; - unsigned long ref_clk; - unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; - unsigned long long temp; - - ref_clk = clk_get_rate(clk->parent); - - reg = __raw_readl(CCM_SPCTL0); - pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; - mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; - mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; - mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; - - mfi = (mfi <= 5) ? 5 : mfi; - temp = 2LL * ref_clk * mfn; - do_div(temp, mfd + 1); - temp = 2LL * ref_clk * mfi + temp; - do_div(temp, pdf + 1); - - return (unsigned long)temp; -} - -static struct clk spll_clk = { - .parent = &ckih_clk, - .get_rate = get_spll_clk, - .enable = _clk_spll_enable, - .disable = _clk_spll_disable, -}; - -static unsigned long get_hclk_clk(struct clk *clk) -{ - unsigned long rate; - unsigned long bclk_pdf; - - bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) - >> CCM_CSCR_BCLK_OFFSET; - - rate = clk_get_rate(clk->parent); - return rate / (bclk_pdf + 1); -} - -static struct clk hclk_clk = { - .parent = &fclk_clk, - .get_rate = get_hclk_clk, -}; - -static unsigned long get_ipg_clk(struct clk *clk) -{ - unsigned long rate; - unsigned long ipg_pdf; - - ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; - - rate = clk_get_rate(clk->parent); - return rate / (ipg_pdf + 1); -} - -static struct clk ipg_clk = { - .parent = &hclk_clk, - .get_rate = get_ipg_clk, -}; - -static unsigned long _clk_perclkx_recalc(struct clk *clk) -{ - unsigned long perclk_pdf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->id < 0 || clk->id > 3) - return 0; - - perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; - - return parent_rate / (perclk_pdf + 1); -} - -static struct clk per_clk[] = { - { - .id = 0, - .parent = &mpll_clk, - .get_rate = _clk_perclkx_recalc, - }, { - .id = 1, - .parent = &mpll_clk, - .get_rate = _clk_perclkx_recalc, - }, { - .id = 2, - .parent = &mpll_clk, - .round_rate = _clk_perclkx_round_rate, - .set_rate = _clk_perclkx_set_rate, - .get_rate = _clk_perclkx_recalc, - /* Enable/Disable done via lcd_clkc[1] */ - }, { - .id = 3, - .parent = &mpll_clk, - .round_rate = _clk_perclkx_round_rate, - .set_rate = _clk_perclkx_set_rate, - .get_rate = _clk_perclkx_recalc, - /* Enable/Disable done via csi_clk[1] */ - }, -}; - -static struct clk uart_ipg_clk[]; - -static struct clk uart_clk[] = { - { - .id = 0, - .parent = &per_clk[0], - .secondary = &uart_ipg_clk[0], - }, { - .id = 1, - .parent = &per_clk[0], - .secondary = &uart_ipg_clk[1], - }, { - .id = 2, - .parent = &per_clk[0], - .secondary = &uart_ipg_clk[2], - }, { - .id = 3, - .parent = &per_clk[0], - .secondary = &uart_ipg_clk[3], - }, -}; - -static struct clk uart_ipg_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_UART1_REG, - .enable_shift = CCM_PCCR_UART1_OFFSET, - .disable = _clk_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_UART2_REG, - .enable_shift = CCM_PCCR_UART2_OFFSET, - .disable = _clk_disable, - }, { - .id = 2, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_UART3_REG, - .enable_shift = CCM_PCCR_UART3_OFFSET, - .disable = _clk_disable, - }, { - .id = 3, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_UART4_REG, - .enable_shift = CCM_PCCR_UART4_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk gpt_ipg_clk[]; - -static struct clk gpt_clk[] = { - { - .id = 0, - .parent = &per_clk[0], - .secondary = &gpt_ipg_clk[0], - }, { - .id = 1, - .parent = &per_clk[0], - .secondary = &gpt_ipg_clk[1], - }, { - .id = 2, - .parent = &per_clk[0], - .secondary = &gpt_ipg_clk[2], - }, -}; - -static struct clk gpt_ipg_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_GPT1_REG, - .enable_shift = CCM_PCCR_GPT1_OFFSET, - .disable = _clk_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_GPT2_REG, - .enable_shift = CCM_PCCR_GPT2_OFFSET, - .disable = _clk_disable, - }, { - .id = 2, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_GPT3_REG, - .enable_shift = CCM_PCCR_GPT3_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk pwm_clk[] = { - { - .parent = &per_clk[0], - .secondary = &pwm_clk[1], - }, { - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_PWM_REG, - .enable_shift = CCM_PCCR_PWM_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk sdhc_ipg_clk[]; - -static struct clk sdhc_clk[] = { - { - .id = 0, - .parent = &per_clk[1], - .secondary = &sdhc_ipg_clk[0], - }, { - .id = 1, - .parent = &per_clk[1], - .secondary = &sdhc_ipg_clk[1], - }, -}; - -static struct clk sdhc_ipg_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SDHC1_REG, - .enable_shift = CCM_PCCR_SDHC1_OFFSET, - .disable = _clk_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SDHC2_REG, - .enable_shift = CCM_PCCR_SDHC2_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk cspi_ipg_clk[]; - -static struct clk cspi_clk[] = { - { - .id = 0, - .parent = &per_clk[1], - .secondary = &cspi_ipg_clk[0], - }, { - .id = 1, - .parent = &per_clk[1], - .secondary = &cspi_ipg_clk[1], - }, { - .id = 2, - .parent = &per_clk[1], - .secondary = &cspi_ipg_clk[2], - }, -}; - -static struct clk cspi_ipg_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_CSPI1_REG, - .enable_shift = CCM_PCCR_CSPI1_OFFSET, - .disable = _clk_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_CSPI2_REG, - .enable_shift = CCM_PCCR_CSPI2_OFFSET, - .disable = _clk_disable, - }, { - .id = 3, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_CSPI3_REG, - .enable_shift = CCM_PCCR_CSPI3_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk lcdc_clk[] = { - { - .parent = &per_clk[2], - .secondary = &lcdc_clk[1], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, - }, { - .parent = &ipg_clk, - .secondary = &lcdc_clk[2], - .enable = _clk_enable, - .enable_reg = CCM_PCCR_LCDC_REG, - .enable_shift = CCM_PCCR_LCDC_OFFSET, - .disable = _clk_disable, - }, { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_LCDC_REG, - .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk csi_clk[] = { - { - .parent = &per_clk[3], - .secondary = &csi_clk[1], - .round_rate = _clk_parent_round_rate, - .set_rate = _clk_parent_set_rate, - }, { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_CSI_REG, - .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk usb_clk[] = { - { - .parent = &spll_clk, - .secondary = &usb_clk[1], - .get_rate = _clk_usb_recalc, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_USBOTG_REG, - .enable_shift = CCM_PCCR_USBOTG_OFFSET, - .disable = _clk_disable, - .round_rate = _clk_usb_round_rate, - .set_rate = _clk_usb_set_rate, - }, { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_USBOTG_REG, - .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET, - .disable = _clk_disable, - } -}; - -static struct clk ssi_ipg_clk[]; - -static struct clk ssi_clk[] = { - { - .id = 0, - .parent = &mpll_clk, - .secondary = &ssi_ipg_clk[0], - .get_rate = _clk_ssi1_recalc, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SSI1_BAUD_REG, - .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET, - .disable = _clk_disable, - }, { - .id = 1, - .parent = &mpll_clk, - .secondary = &ssi_ipg_clk[1], - .get_rate = _clk_ssi2_recalc, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SSI2_BAUD_REG, - .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk ssi_ipg_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SSI1_REG, - .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET, - .disable = _clk_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SSI2_REG, - .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET, - .disable = _clk_disable, - }, -}; - - -static struct clk nfc_clk = { - .parent = &fclk_clk, - .get_rate = _clk_nfc_recalc, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_NFC_REG, - .enable_shift = CCM_PCCR_NFC_OFFSET, - .disable = _clk_disable, -}; - -static struct clk dma_clk[] = { - { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_DMA_REG, - .enable_shift = CCM_PCCR_DMA_OFFSET, - .disable = _clk_disable, - .secondary = &dma_clk[1], - }, { - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_DMA_REG, - .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET, - .disable = _clk_disable, - }, -}; - -static struct clk brom_clk = { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_BROM_REG, - .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET, - .disable = _clk_disable, -}; - -static struct clk emma_clk[] = { - { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_EMMA_REG, - .enable_shift = CCM_PCCR_EMMA_OFFSET, - .disable = _clk_disable, - .secondary = &emma_clk[1], - }, { - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_EMMA_REG, - .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET, - .disable = _clk_disable, - } -}; - -static struct clk slcdc_clk[] = { - { - .parent = &hclk_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_SLCDC_REG, - .enable_shift = CCM_PCCR_SLCDC_OFFSET, - .disable = _clk_disable, - .secondary = &slcdc_clk[1], - }, { - .enable = _clk_enable, - .enable_reg = CCM_PCCR_HCLK_SLCDC_REG, - .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET, - .disable = _clk_disable, - } -}; - -static struct clk wdog_clk = { - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_WDT_REG, - .enable_shift = CCM_PCCR_WDT_OFFSET, - .disable = _clk_disable, -}; - -static struct clk gpio_clk = { - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_GPIO_REG, - .enable_shift = CCM_PCCR_GPIO_OFFSET, - .disable = _clk_disable, -}; - -static struct clk i2c_clk = { - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_I2C1_REG, - .enable_shift = CCM_PCCR_I2C1_OFFSET, - .disable = _clk_disable, -}; - -static struct clk kpp_clk = { - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_KPP_REG, - .enable_shift = CCM_PCCR_KPP_OFFSET, - .disable = _clk_disable, -}; - -static struct clk owire_clk = { - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_OWIRE_REG, - .enable_shift = CCM_PCCR_OWIRE_OFFSET, - .disable = _clk_disable, -}; - -static struct clk rtc_clk = { - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = CCM_PCCR_RTC_REG, - .enable_shift = CCM_PCCR_RTC_OFFSET, - .disable = _clk_disable, -}; - -static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) -{ - return _clk_generic_round_rate(clk, rate, 8); -} - -static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 8 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - div--; - - reg = __raw_readl(CCM_PCDR0); - - if (clk->parent == &usb_clk[0]) { - reg &= ~CCM_PCDR0_48MDIV_MASK; - reg |= div << CCM_PCDR0_48MDIV_OFFSET; - } - __raw_writel(reg, CCM_PCDR0); - - return 0; -} - -static unsigned long _clk_clko_recalc(struct clk *clk) -{ - u32 div = 0; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->parent == &usb_clk[0]) /* 48M */ - div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK - >> CCM_PCDR0_48MDIV_OFFSET; - div++; - - return parent_rate / div; -} - -static struct clk clko_clk; - -static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; - - if (parent == &ckil_clk) - reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &fpm_clk) - reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &ckih_clk) - reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == mpll_clk.parent) - reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == spll_clk.parent) - reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &mpll_clk) - reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &spll_clk) - reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &fclk_clk) - reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &hclk_clk) - reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &ipg_clk) - reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &per_clk[0]) - reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &per_clk[1]) - reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &per_clk[2]) - reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &per_clk[3]) - reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &ssi_clk[0]) - reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &ssi_clk[1]) - reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &nfc_clk) - reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &usb_clk[0]) - reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET; - else if (parent == &clko_clk) - reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; - else - return -EINVAL; - - __raw_writel(reg, CCM_CCSR); - - return 0; -} - -static struct clk clko_clk = { - .get_rate = _clk_clko_recalc, - .set_rate = _clk_clko_set_rate, - .round_rate = _clk_clko_round_rate, - .set_parent = _clk_clko_set_parent, -}; - - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, -static struct clk_lookup lookups[] = { -/* It's unlikely that any driver wants one of them directly: - _REGISTER_CLOCK(NULL, "ckih", ckih_clk) - _REGISTER_CLOCK(NULL, "ckil", ckil_clk) - _REGISTER_CLOCK(NULL, "fpm", fpm_clk) - _REGISTER_CLOCK(NULL, "mpll", mpll_clk) - _REGISTER_CLOCK(NULL, "spll", spll_clk) - _REGISTER_CLOCK(NULL, "fclk", fclk_clk) - _REGISTER_CLOCK(NULL, "hclk", hclk_clk) - _REGISTER_CLOCK(NULL, "ipg", ipg_clk) -*/ - _REGISTER_CLOCK(NULL, "perclk1", per_clk[0]) - _REGISTER_CLOCK(NULL, "perclk2", per_clk[1]) - _REGISTER_CLOCK(NULL, "perclk3", per_clk[2]) - _REGISTER_CLOCK(NULL, "perclk4", per_clk[3]) - _REGISTER_CLOCK(NULL, "clko", clko_clk) - _REGISTER_CLOCK("imx21-uart.0", NULL, uart_clk[0]) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart_clk[1]) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart_clk[2]) - _REGISTER_CLOCK("imx21-uart.3", NULL, uart_clk[3]) - _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0]) - _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1]) - _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2]) - _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) - _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) - _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) - _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0]) - _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1]) - _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2]) - _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) - _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) - _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0]) - _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0]) - _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1]) - _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) - _REGISTER_CLOCK(NULL, "dma", dma_clk[0]) - _REGISTER_CLOCK(NULL, "brom", brom_clk) - _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) - _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) - _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) - _REGISTER_CLOCK(NULL, "gpio", gpio_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) - _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) - _REGISTER_CLOCK(NULL, "owire", owire_clk) - _REGISTER_CLOCK(NULL, "rtc", rtc_clk) -}; - -/* - * must be called very early to get information about the - * available clock rate when the timer framework starts - */ -int __init mx21_clocks_init(unsigned long lref, unsigned long href) -{ - u32 cscr; - - external_low_reference = lref; - external_high_reference = href; - - /* detect clock reference for both system PLL */ - cscr = CSCR(); - if (cscr & CCM_CSCR_MCU) - mpll_clk.parent = &ckih_clk; - else - mpll_clk.parent = &fpm_clk; - - if (cscr & CCM_CSCR_SP) - spll_clk.parent = &ckih_clk; - else - spll_clk.parent = &fpm_clk; - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - /* Turn off all clock gates */ - __raw_writel(0, CCM_PCCR0); - __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1); - - /* This turns of the serial PLL as well */ - spll_clk.disable(&spll_clk); - - /* This will propagate to all children and init all the clock rates. */ - clk_enable(&per_clk[0]); - clk_enable(&gpio_clk); - -#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) - clk_enable(&uart_clk[0]); -#endif - - mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), - MX21_INT_GPT1); - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx25.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx25.c deleted file mode 100644 index b0fec74c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx25.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (C) 2009 by Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <mach/clock.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/mx25.h> - -#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR) - -#define CCM_MPCTL 0x00 -#define CCM_UPCTL 0x04 -#define CCM_CCTL 0x08 -#define CCM_CGCR0 0x0C -#define CCM_CGCR1 0x10 -#define CCM_CGCR2 0x14 -#define CCM_PCDR0 0x18 -#define CCM_PCDR1 0x1C -#define CCM_PCDR2 0x20 -#define CCM_PCDR3 0x24 -#define CCM_RCSR 0x28 -#define CCM_CRDR 0x2C -#define CCM_DCVR0 0x30 -#define CCM_DCVR1 0x34 -#define CCM_DCVR2 0x38 -#define CCM_DCVR3 0x3c -#define CCM_LTR0 0x40 -#define CCM_LTR1 0x44 -#define CCM_LTR2 0x48 -#define CCM_LTR3 0x4c - -static unsigned long get_rate_mpll(void) -{ - ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL); - - return mxc_decode_pll(mpctl, 24000000); -} - -static unsigned long get_rate_upll(void) -{ - ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL); - - return mxc_decode_pll(mpctl, 24000000); -} - -unsigned long get_rate_arm(struct clk *clk) -{ - unsigned long cctl = readl(CRM_BASE + CCM_CCTL); - unsigned long rate = get_rate_mpll(); - - if (cctl & (1 << 14)) - rate = (rate * 3) >> 2; - - return rate / ((cctl >> 30) + 1); -} - -static unsigned long get_rate_ahb(struct clk *clk) -{ - unsigned long cctl = readl(CRM_BASE + CCM_CCTL); - - return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1); -} - -static unsigned long get_rate_ipg(struct clk *clk) -{ - return get_rate_ahb(NULL) >> 1; -} - -static unsigned long get_rate_per(int per) -{ - unsigned long ofs = (per & 0x3) * 8; - unsigned long reg = per & ~0x3; - unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f; - unsigned long fref; - - if (readl(CRM_BASE + 0x64) & (1 << per)) - fref = get_rate_upll(); - else - fref = get_rate_ahb(NULL); - - return fref / (val + 1); -} - -static unsigned long get_rate_uart(struct clk *clk) -{ - return get_rate_per(15); -} - -static unsigned long get_rate_ssi2(struct clk *clk) -{ - return get_rate_per(14); -} - -static unsigned long get_rate_ssi1(struct clk *clk) -{ - return get_rate_per(13); -} - -static unsigned long get_rate_i2c(struct clk *clk) -{ - return get_rate_per(6); -} - -static unsigned long get_rate_nfc(struct clk *clk) -{ - return get_rate_per(8); -} - -static unsigned long get_rate_gpt(struct clk *clk) -{ - return get_rate_per(5); -} - -static unsigned long get_rate_lcdc(struct clk *clk) -{ - return get_rate_per(7); -} - -static unsigned long get_rate_esdhc1(struct clk *clk) -{ - return get_rate_per(3); -} - -static unsigned long get_rate_esdhc2(struct clk *clk) -{ - return get_rate_per(4); -} - -static unsigned long get_rate_csi(struct clk *clk) -{ - return get_rate_per(0); -} - -static unsigned long get_rate_otg(struct clk *clk) -{ - unsigned long cctl = readl(CRM_BASE + CCM_CCTL); - unsigned long rate = get_rate_upll(); - - return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1); -} - -static int clk_cgcr_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= 1 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void clk_cgcr_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(1 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = CRM_BASE + er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .set_rate = sr, \ - .enable = clk_cgcr_enable, \ - .disable = clk_cgcr_disable, \ - .secondary = s, \ - } - -/* - * Note: the following IPG clock gating bits are wrongly marked "Reserved" in - * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is - * taken from the Freescale released BSP. - * - * bit reg offset clock - * - * 0 CGCR1 0 AUDMUX - * 12 CGCR1 12 ESAI - * 16 CGCR1 16 GPIO1 - * 17 CGCR1 17 GPIO2 - * 18 CGCR1 18 GPIO3 - * 23 CGCR1 23 I2C1 - * 24 CGCR1 24 I2C2 - * 25 CGCR1 25 I2C3 - * 27 CGCR1 27 IOMUXC - * 28 CGCR1 28 KPP - * 30 CGCR1 30 OWIRE - * 36 CGCR2 4 RTIC - * 51 CGCR2 19 WDOG - */ - -DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); -DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); -DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1, NULL, NULL); -DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL, - &esdhc1_ahb_clk); -DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL); -DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL, - &esdhc2_ahb_clk); -DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL, NULL, NULL); -DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); -DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); -DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); -DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); -DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); -DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); -DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); -DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); -DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk); -DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk); -DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL); -DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL); -DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); -DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); -DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); -DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); -DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); -DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2, 6, get_rate_ipg, NULL, &sdma_ahb_clk); -DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL, - &esdhc1_per_clk); -DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL, - &esdhc2_per_clk); -DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); -DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); -DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); -DEFINE_CLOCK(iim_clk, 0, CCM_CGCR1, 26, NULL, NULL, NULL); - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - /* i.mx25 has the i.mx21 type uart */ - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk) - _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) - _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) - _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) - /* i.mx25 has the i.mx35 type cspi */ - _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk) - _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk) - _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) - _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) - _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) - _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) - _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) - _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) - _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk) - _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) - _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk) - _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) - _REGISTER_CLOCK(NULL, "audmux", audmux_clk) - _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) - _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) - /* i.mx25 has the i.mx35 type sdma */ - _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) - _REGISTER_CLOCK(NULL, "iim", iim_clk) -}; - -int __init mx25_clocks_init(void) -{ - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - /* Turn off all clocks except the ones we need to survive, namely: - * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM, - * SCC - */ - __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); - __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); - __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); -#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) - clk_enable(&uart1_clk); -#endif - - /* Clock source for lcdc and csi is upll */ - __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), - CRM_BASE + 0x64); - - /* Clock source for gpt is ahb_div */ - __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64); - - clk_enable(&iim_clk); - imx_print_silicon_rev("i.MX25", mx25_revision()); - clk_disable(&iim_clk); - - mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx27.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx27.c deleted file mode 100644 index 98e04f5a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx27.c +++ /dev/null @@ -1,785 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/clkdev.h> -#include <linux/of.h> - -#include <asm/div64.h> - -#include <mach/clock.h> -#include <mach/common.h> -#include <mach/hardware.h> - -#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) - -/* Register offsets */ -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_MPCTL1 IO_ADDR_CCM(0x8) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_SPCTL1 IO_ADDR_CCM(0x10) -#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) -#define CCM_PCDR0 IO_ADDR_CCM(0x18) -#define CCM_PCDR1 IO_ADDR_CCM(0x1c) -#define CCM_PCCR0 IO_ADDR_CCM(0x20) -#define CCM_PCCR1 IO_ADDR_CCM(0x24) -#define CCM_CCSR IO_ADDR_CCM(0x28) -#define CCM_PMCTL IO_ADDR_CCM(0x2c) -#define CCM_PMCOUNT IO_ADDR_CCM(0x30) -#define CCM_WKGDCTL IO_ADDR_CCM(0x34) - -#define CCM_CSCR_UPDATE_DIS (1 << 31) -#define CCM_CSCR_SSI2 (1 << 23) -#define CCM_CSCR_SSI1 (1 << 22) -#define CCM_CSCR_VPU (1 << 21) -#define CCM_CSCR_MSHC (1 << 20) -#define CCM_CSCR_SPLLRES (1 << 19) -#define CCM_CSCR_MPLLRES (1 << 18) -#define CCM_CSCR_SP (1 << 17) -#define CCM_CSCR_MCU (1 << 16) -#define CCM_CSCR_OSC26MDIV (1 << 4) -#define CCM_CSCR_OSC26M (1 << 3) -#define CCM_CSCR_FPM (1 << 2) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN (1 << 0) - -/* i.MX27 TO 2+ */ -#define CCM_CSCR_ARM_SRC (1 << 15) - -#define CCM_SPCTL1_LF (1 << 15) -#define CCM_SPCTL1_BRMO (1 << 6) - -static struct clk mpll_main1_clk, mpll_main2_clk; - -static int clk_pccr_enable(struct clk *clk) -{ - unsigned long reg; - - if (!clk->enable_reg) - return 0; - - reg = __raw_readl(clk->enable_reg); - reg |= 1 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void clk_pccr_disable(struct clk *clk) -{ - unsigned long reg; - - if (!clk->enable_reg) - return; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(1 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -static int clk_spll_enable(struct clk *clk) -{ - unsigned long reg; - - reg = __raw_readl(CCM_CSCR); - reg |= CCM_CSCR_SPEN; - __raw_writel(reg, CCM_CSCR); - - while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF)); - - return 0; -} - -static void clk_spll_disable(struct clk *clk) -{ - unsigned long reg; - - reg = __raw_readl(CCM_CSCR); - reg &= ~CCM_CSCR_SPEN; - __raw_writel(reg, CCM_CSCR); -} - -static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) -{ - int cscr = __raw_readl(CCM_CSCR); - - if (clk->parent == parent) - return 0; - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { - if (parent == &mpll_main1_clk) { - cscr |= CCM_CSCR_ARM_SRC; - } else { - if (parent == &mpll_main2_clk) - cscr &= ~CCM_CSCR_ARM_SRC; - else - return -EINVAL; - } - __raw_writel(cscr, CCM_CSCR); - clk->parent = parent; - return 0; - } - return -ENODEV; -} - -static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate) -{ - int div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (parent_rate % rate) - div++; - - if (div > 4) - div = 4; - - return parent_rate / div; -} - -static int set_rate_cpu(struct clk *clk, unsigned long rate) -{ - unsigned int div; - uint32_t reg; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - if (div > 4 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - div--; - - reg = __raw_readl(CCM_CSCR); - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { - reg &= ~(3 << 12); - reg |= div << 12; - reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); - __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR); - } else { - printk(KERN_ERR "Can't set CPU frequency!\n"); - } - - return 0; -} - -static unsigned long round_rate_per(struct clk *clk, unsigned long rate) -{ - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (parent_rate % rate) - div++; - - if (div > 64) - div = 64; - - return parent_rate / div; -} - -static int set_rate_per(struct clk *clk, unsigned long rate) -{ - u32 reg; - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->id < 0 || clk->id > 3) - return -EINVAL; - - div = parent_rate / rate; - if (div > 64 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - div--; - - reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3)); - reg |= div << (clk->id << 3); - __raw_writel(reg, CCM_PCDR1); - - return 0; -} - -static unsigned long get_rate_usb(struct clk *clk) -{ - unsigned long usb_pdf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7; - - return parent_rate / (usb_pdf + 1U); -} - -static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) -{ - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - pdf += 4; /* MX27 TO2+ */ - else - pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ - - return 2UL * parent_rate / pdf; -} - -static unsigned long get_rate_ssi1(struct clk *clk) -{ - return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f); -} - -static unsigned long get_rate_ssi2(struct clk *clk) -{ - return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f); -} - -static unsigned long get_rate_nfc(struct clk *clk) -{ - unsigned long nfc_pdf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; - else - nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; - - return parent_rate / (nfc_pdf + 1); -} - -static unsigned long get_rate_vpu(struct clk *clk) -{ - unsigned long vpu_pdf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { - vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; - vpu_pdf += 4; - } else { - vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf; - vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; - } - - return 2UL * parent_rate / vpu_pdf; -} - -static unsigned long round_rate_parent(struct clk *clk, unsigned long rate) -{ - return clk->parent->round_rate(clk->parent, rate); -} - -static unsigned long get_rate_parent(struct clk *clk) -{ - return clk_get_rate(clk->parent); -} - -static int set_rate_parent(struct clk *clk, unsigned long rate) -{ - return clk->parent->set_rate(clk->parent, rate); -} - -/* in Hz */ -static unsigned long external_high_reference = 26000000; - -static unsigned long get_rate_high_reference(struct clk *clk) -{ - return external_high_reference; -} - -/* in Hz */ -static unsigned long external_low_reference = 32768; - -static unsigned long get_rate_low_reference(struct clk *clk) -{ - return external_low_reference; -} - -static unsigned long get_rate_fpm(struct clk *clk) -{ - return clk_get_rate(clk->parent) * 1024; -} - -static unsigned long get_rate_mpll(struct clk *clk) -{ - return mxc_decode_pll(__raw_readl(CCM_MPCTL0), - clk_get_rate(clk->parent)); -} - -static unsigned long get_rate_mpll_main(struct clk *clk) -{ - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - /* i.MX27 TO2: - * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 - * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 - */ - if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1) - return 2UL * parent_rate / 3UL; - - return parent_rate; -} - -static unsigned long get_rate_spll(struct clk *clk) -{ - uint32_t reg; - unsigned long rate; - - rate = clk_get_rate(clk->parent); - - reg = __raw_readl(CCM_SPCTL0); - - /* On TO2 we have to write the value back. Otherwise we - * read 0 from this register the next time. - */ - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - __raw_writel(reg, CCM_SPCTL0); - - return mxc_decode_pll(reg, rate); -} - -static unsigned long get_rate_cpu(struct clk *clk) -{ - u32 div; - unsigned long rate; - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; - else - div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; - - rate = clk_get_rate(clk->parent); - return rate / (div + 1); -} - -static unsigned long get_rate_ahb(struct clk *clk) -{ - unsigned long rate, bclk_pdf; - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; - else - bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; - - rate = clk_get_rate(clk->parent); - return rate / (bclk_pdf + 1); -} - -static unsigned long get_rate_ipg(struct clk *clk) -{ - unsigned long rate, ipg_pdf; - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - return clk_get_rate(clk->parent); - else - ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; - - rate = clk_get_rate(clk->parent); - return rate / (ipg_pdf + 1); -} - -static unsigned long get_rate_per(struct clk *clk) -{ - unsigned long perclk_pdf, parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->id < 0 || clk->id > 3) - return 0; - - perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f; - - return parent_rate / (perclk_pdf + 1); -} - -/* - * the high frequency external clock reference - * Default case is 26MHz. Could be changed at runtime - * with a call to change_external_high_reference() - */ -static struct clk ckih_clk = { - .get_rate = get_rate_high_reference, -}; - -static struct clk mpll_clk = { - .parent = &ckih_clk, - .get_rate = get_rate_mpll, -}; - -/* For i.MX27 TO2, it is the MPLL path 1 of ARM core - * It provides the clock source whose rate is same as MPLL - */ -static struct clk mpll_main1_clk = { - .id = 0, - .parent = &mpll_clk, - .get_rate = get_rate_mpll_main, -}; - -/* For i.MX27 TO2, it is the MPLL path 2 of ARM core - * It provides the clock source whose rate is same MPLL * 2 / 3 - */ -static struct clk mpll_main2_clk = { - .id = 1, - .parent = &mpll_clk, - .get_rate = get_rate_mpll_main, -}; - -static struct clk ahb_clk = { - .parent = &mpll_main2_clk, - .get_rate = get_rate_ahb, -}; - -static struct clk ipg_clk = { - .parent = &ahb_clk, - .get_rate = get_rate_ipg, -}; - -static struct clk cpu_clk = { - .parent = &mpll_main2_clk, - .set_parent = clk_cpu_set_parent, - .round_rate = round_rate_cpu, - .get_rate = get_rate_cpu, - .set_rate = set_rate_cpu, -}; - -static struct clk spll_clk = { - .parent = &ckih_clk, - .get_rate = get_rate_spll, - .enable = clk_spll_enable, - .disable = clk_spll_disable, -}; - -/* - * the low frequency external clock reference - * Default case is 32.768kHz. - */ -static struct clk ckil_clk = { - .get_rate = get_rate_low_reference, -}; - -/* Output of frequency pre multiplier */ -static struct clk fpm_clk = { - .parent = &ckil_clk, - .get_rate = get_rate_fpm, -}; - -#define PCCR0 CCM_PCCR0 -#define PCCR1 CCM_PCCR1 - -#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .enable = clk_pccr_enable, \ - .disable = clk_pccr_disable, \ - .secondary = s, \ - .parent = p, \ - } - -#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = get_rate_##getsetround, \ - .set_rate = set_rate_##getsetround, \ - .round_rate = round_rate_##getsetround, \ - .enable = clk_pccr_enable, \ - .disable = clk_pccr_disable, \ - .secondary = s, \ - .parent = p, \ - } - -/* Forward declaration to keep the following list in order */ -static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1, - dma_clk1, lcdc_clk2, vpu_clk1; - -/* All clocks we can gate through PCCRx in the order of PCCRx bits */ -DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk); -DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk); -DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk); -DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk); -DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk); -DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk); -DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk); -DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk); - -DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk); -DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk); -DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk); -DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk); -DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk); -DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk); -DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk); -DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk); -DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk); -DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(pata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); -DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); - -/* Clocks we cannot directly gate, but drivers need their rates */ -DEFINE_CLOCK(cspi1_clk, 0, NULL, 0, NULL, &cspi1_clk1, &per2_clk); -DEFINE_CLOCK(cspi2_clk, 1, NULL, 0, NULL, &cspi2_clk1, &per2_clk); -DEFINE_CLOCK(cspi3_clk, 2, NULL, 0, NULL, &cspi13_clk1, &per2_clk); -DEFINE_CLOCK(sdhc1_clk, 0, NULL, 0, NULL, &sdhc1_clk1, &per2_clk); -DEFINE_CLOCK(sdhc2_clk, 1, NULL, 0, NULL, &sdhc2_clk1, &per2_clk); -DEFINE_CLOCK(sdhc3_clk, 2, NULL, 0, NULL, &sdhc3_clk1, &per2_clk); -DEFINE_CLOCK(pwm_clk, 0, NULL, 0, NULL, &pwm_clk1, &per1_clk); -DEFINE_CLOCK(gpt1_clk, 0, NULL, 0, NULL, &gpt1_clk1, &per1_clk); -DEFINE_CLOCK(gpt2_clk, 1, NULL, 0, NULL, &gpt2_clk1, &per1_clk); -DEFINE_CLOCK(gpt3_clk, 2, NULL, 0, NULL, &gpt3_clk1, &per1_clk); -DEFINE_CLOCK(gpt4_clk, 3, NULL, 0, NULL, &gpt4_clk1, &per1_clk); -DEFINE_CLOCK(gpt5_clk, 4, NULL, 0, NULL, &gpt5_clk1, &per1_clk); -DEFINE_CLOCK(gpt6_clk, 5, NULL, 0, NULL, &gpt6_clk1, &per1_clk); -DEFINE_CLOCK(uart1_clk, 0, NULL, 0, NULL, &uart1_clk1, &per1_clk); -DEFINE_CLOCK(uart2_clk, 1, NULL, 0, NULL, &uart2_clk1, &per1_clk); -DEFINE_CLOCK(uart3_clk, 2, NULL, 0, NULL, &uart3_clk1, &per1_clk); -DEFINE_CLOCK(uart4_clk, 3, NULL, 0, NULL, &uart4_clk1, &per1_clk); -DEFINE_CLOCK(uart5_clk, 4, NULL, 0, NULL, &uart5_clk1, &per1_clk); -DEFINE_CLOCK(uart6_clk, 5, NULL, 0, NULL, &uart6_clk1, &per1_clk); -DEFINE_CLOCK1(lcdc_clk, 0, NULL, 0, parent, &lcdc_clk1, &per3_clk); -DEFINE_CLOCK1(csi_clk, 0, NULL, 0, parent, &csi_clk1, &per4_clk); - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - /* i.mx27 has the i.mx21 type uart */ - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk) - _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk) - _REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk) - _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk) - _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk) - _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk) - _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk) - _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk) - _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk) - _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk) - _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) - _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) - _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) - _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk) - _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) - _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1) - _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1) - _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk) - _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) - _REGISTER_CLOCK(NULL, "vpu", vpu_clk) - _REGISTER_CLOCK(NULL, "dma", dma_clk) - _REGISTER_CLOCK(NULL, "rtic", rtic_clk) - _REGISTER_CLOCK(NULL, "brom", brom_clk) - _REGISTER_CLOCK(NULL, "emma", emma_clk) - _REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk) - _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk) - _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk) - _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) - _REGISTER_CLOCK("pata_imx", NULL, pata_clk) - _REGISTER_CLOCK(NULL, "mstick", mstick_clk) - _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) - _REGISTER_CLOCK(NULL, "gpio", gpio_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) - _REGISTER_CLOCK(NULL, "iim", iim_clk) - _REGISTER_CLOCK(NULL, "kpp", kpp_clk) - _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) - _REGISTER_CLOCK(NULL, "rtc", rtc_clk) - _REGISTER_CLOCK(NULL, "scc", scc_clk) -}; - -/* Adjust the clock path for TO2 and later */ -static void __init to2_adjust_clocks(void) -{ - unsigned long cscr = __raw_readl(CCM_CSCR); - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { - if (cscr & CCM_CSCR_ARM_SRC) - cpu_clk.parent = &mpll_main1_clk; - - if (!(cscr & CCM_CSCR_SSI2)) - ssi1_clk.parent = &spll_clk; - - if (!(cscr & CCM_CSCR_SSI1)) - ssi1_clk.parent = &spll_clk; - - if (!(cscr & CCM_CSCR_VPU)) - vpu_clk.parent = &spll_clk; - } else { - cpu_clk.parent = &mpll_clk; - cpu_clk.set_parent = NULL; - cpu_clk.round_rate = NULL; - cpu_clk.set_rate = NULL; - ahb_clk.parent = &mpll_clk; - - per1_clk.parent = &mpll_clk; - per2_clk.parent = &mpll_clk; - per3_clk.parent = &mpll_clk; - per4_clk.parent = &mpll_clk; - - ssi1_clk.parent = &mpll_clk; - ssi2_clk.parent = &mpll_clk; - - vpu_clk.parent = &mpll_clk; - } -} - -/* - * must be called very early to get information about the - * available clock rate when the timer framework starts - */ -int __init mx27_clocks_init(unsigned long fref) -{ - u32 cscr = __raw_readl(CCM_CSCR); - - external_high_reference = fref; - - /* detect clock reference for both system PLLs */ - if (cscr & CCM_CSCR_MCU) - mpll_clk.parent = &ckih_clk; - else - mpll_clk.parent = &fpm_clk; - - if (cscr & CCM_CSCR_SP) - spll_clk.parent = &ckih_clk; - else - spll_clk.parent = &fpm_clk; - - to2_adjust_clocks(); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - /* Turn off all clocks we do not need */ - __raw_writel(0, CCM_PCCR0); - __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1); - - spll_clk.disable(&spll_clk); - - /* enable basic clocks */ - clk_enable(&per1_clk); - clk_enable(&gpio_clk); - clk_enable(&emi_clk); - clk_enable(&iim_clk); - imx_print_silicon_rev("i.MX27", mx27_revision()); - clk_disable(&iim_clk); - -#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) - clk_enable(&uart1_clk); -#endif - - mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), - MX27_INT_GPT1); - - return 0; -} - -#ifdef CONFIG_OF -int __init mx27_clocks_init_dt(void) -{ - struct device_node *np; - u32 fref = 26000000; /* default */ - - for_each_compatible_node(np, NULL, "fixed-clock") { - if (!of_device_is_compatible(np, "fsl,imx-osc26m")) - continue; - - if (!of_property_read_u32(np, "clock-frequency", &fref)) - break; - } - - return mx27_clocks_init(fref); -} -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx31.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx31.c deleted file mode 100644 index 3a943cd4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx31.c +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <asm/div64.h> - -#include <mach/clock.h> -#include <mach/hardware.h> -#include <mach/mx31.h> -#include <mach/common.h> - -#include "crmregs-imx3.h" - -#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ - -static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) -{ - u32 min_pre, temp_pre, old_err, err; - - if (div >= 512) { - *pre = 8; - *post = 64; - } else if (div >= 64) { - min_pre = (div - 1) / 64 + 1; - old_err = 8; - for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { - err = div % temp_pre; - if (err == 0) { - *pre = temp_pre; - break; - } - err = temp_pre - err; - if (err < old_err) { - old_err = err; - *pre = temp_pre; - } - } - *post = (div + *pre - 1) / *pre; - } else if (div <= 8) { - *pre = div; - *post = 1; - } else { - *pre = 1; - *post = div; - } -} - -static struct clk mcu_pll_clk; -static struct clk serial_pll_clk; -static struct clk ipg_clk; -static struct clk ckih_clk; - -static int cgr_enable(struct clk *clk) -{ - u32 reg; - - if (!clk->enable_reg) - return 0; - - reg = __raw_readl(clk->enable_reg); - reg |= 3 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void cgr_disable(struct clk *clk) -{ - u32 reg; - - if (!clk->enable_reg) - return; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(3 << clk->enable_shift); - - /* special case for EMI clock */ - if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8) - reg |= (1 << clk->enable_shift); - - __raw_writel(reg, clk->enable_reg); -} - -static unsigned long pll_ref_get_rate(void) -{ - unsigned long ccmr; - unsigned int prcs; - - ccmr = __raw_readl(MXC_CCM_CCMR); - prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET; - if (prcs == 0x1) - return CKIL_CLK_FREQ * 1024; - else - return clk_get_rate(&ckih_clk); -} - -static unsigned long usb_pll_get_rate(struct clk *clk) -{ - unsigned long reg; - - reg = __raw_readl(MXC_CCM_UPCTL); - - return mxc_decode_pll(reg, pll_ref_get_rate()); -} - -static unsigned long serial_pll_get_rate(struct clk *clk) -{ - unsigned long reg; - - reg = __raw_readl(MXC_CCM_SRPCTL); - - return mxc_decode_pll(reg, pll_ref_get_rate()); -} - -static unsigned long mcu_pll_get_rate(struct clk *clk) -{ - unsigned long reg, ccmr; - - ccmr = __raw_readl(MXC_CCM_CCMR); - - if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS)) - return clk_get_rate(&ckih_clk); - - reg = __raw_readl(MXC_CCM_MPCTL); - - return mxc_decode_pll(reg, pll_ref_get_rate()); -} - -static int usb_pll_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CCMR); - reg |= MXC_CCM_CCMR_UPE; - __raw_writel(reg, MXC_CCM_CCMR); - - /* No lock bit on MX31, so using max time from spec */ - udelay(80); - - return 0; -} - -static void usb_pll_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CCMR); - reg &= ~MXC_CCM_CCMR_UPE; - __raw_writel(reg, MXC_CCM_CCMR); -} - -static int serial_pll_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CCMR); - reg |= MXC_CCM_CCMR_SPE; - __raw_writel(reg, MXC_CCM_CCMR); - - /* No lock bit on MX31, so using max time from spec */ - udelay(80); - - return 0; -} - -static void serial_pll_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CCMR); - reg &= ~MXC_CCM_CCMR_SPE; - __raw_writel(reg, MXC_CCM_CCMR); -} - -#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off) -#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) -#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) - -static unsigned long mcu_main_get_rate(struct clk *clk) -{ - u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); - - if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL) - return clk_get_rate(&serial_pll_clk); - else - return clk_get_rate(&mcu_pll_clk); -} - -static unsigned long ahb_get_rate(struct clk *clk) -{ - unsigned long max_pdf; - - max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK, - MXC_CCM_PDR0_MAX_PODF_OFFSET); - return clk_get_rate(clk->parent) / (max_pdf + 1); -} - -static unsigned long ipg_get_rate(struct clk *clk) -{ - unsigned long ipg_pdf; - - ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK, - MXC_CCM_PDR0_IPG_PODF_OFFSET); - return clk_get_rate(clk->parent) / (ipg_pdf + 1); -} - -static unsigned long nfc_get_rate(struct clk *clk) -{ - unsigned long nfc_pdf; - - nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK, - MXC_CCM_PDR0_NFC_PODF_OFFSET); - return clk_get_rate(clk->parent) / (nfc_pdf + 1); -} - -static unsigned long hsp_get_rate(struct clk *clk) -{ - unsigned long hsp_pdf; - - hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK, - MXC_CCM_PDR0_HSP_PODF_OFFSET); - return clk_get_rate(clk->parent) / (hsp_pdf + 1); -} - -static unsigned long usb_get_rate(struct clk *clk) -{ - unsigned long usb_pdf, usb_prepdf; - - usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK, - MXC_CCM_PDR1_USB_PODF_OFFSET); - usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK, - MXC_CCM_PDR1_USB_PRDF_OFFSET); - return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); -} - -static unsigned long csi_get_rate(struct clk *clk) -{ - u32 reg, pre, post; - - reg = __raw_readl(MXC_CCM_PDR0); - pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >> - MXC_CCM_PDR0_CSI_PRDF_OFFSET; - pre++; - post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >> - MXC_CCM_PDR0_CSI_PODF_OFFSET; - post++; - return clk_get_rate(clk->parent) / (pre * post); -} - -static unsigned long csi_round_rate(struct clk *clk, unsigned long rate) -{ - u32 pre, post, parent = clk_get_rate(clk->parent); - u32 div = parent / rate; - - if (parent % rate) - div++; - - __calc_pre_post_dividers(div, &pre, &post); - - return parent / (pre * post); -} - -static int csi_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); - - div = parent / rate; - - if ((parent / div) != rate) - return -EINVAL; - - __calc_pre_post_dividers(div, &pre, &post); - - /* Set CSI clock divider */ - reg = __raw_readl(MXC_CCM_PDR0) & - ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK); - reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET; - reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET; - __raw_writel(reg, MXC_CCM_PDR0); - - return 0; -} - -static unsigned long ssi1_get_rate(struct clk *clk) -{ - unsigned long ssi1_pdf, ssi1_prepdf; - - ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK, - MXC_CCM_PDR1_SSI1_PODF_OFFSET); - ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK, - MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET); - return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); -} - -static unsigned long ssi2_get_rate(struct clk *clk) -{ - unsigned long ssi2_pdf, ssi2_prepdf; - - ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK, - MXC_CCM_PDR1_SSI2_PODF_OFFSET); - ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK, - MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET); - return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); -} - -static unsigned long firi_get_rate(struct clk *clk) -{ - unsigned long firi_pdf, firi_prepdf; - - firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK, - MXC_CCM_PDR1_FIRI_PODF_OFFSET); - firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK, - MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET); - return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); -} - -static unsigned long firi_round_rate(struct clk *clk, unsigned long rate) -{ - u32 pre, post; - u32 parent = clk_get_rate(clk->parent); - u32 div = parent / rate; - - if (parent % rate) - div++; - - __calc_pre_post_dividers(div, &pre, &post); - - return parent / (pre * post); - -} - -static int firi_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); - - div = parent / rate; - - if ((parent / div) != rate) - return -EINVAL; - - __calc_pre_post_dividers(div, &pre, &post); - - /* Set FIRI clock divider */ - reg = __raw_readl(MXC_CCM_PDR1) & - ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK); - reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET; - reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_PDR1); - - return 0; -} - -static unsigned long mbx_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 2; -} - -static unsigned long mstick1_get_rate(struct clk *clk) -{ - unsigned long msti_pdf; - - msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK, - MXC_CCM_PDR2_MST1_PDF_OFFSET); - return clk_get_rate(clk->parent) / (msti_pdf + 1); -} - -static unsigned long mstick2_get_rate(struct clk *clk) -{ - unsigned long msti_pdf; - - msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK, - MXC_CCM_PDR2_MST2_PDF_OFFSET); - return clk_get_rate(clk->parent) / (msti_pdf + 1); -} - -static unsigned long ckih_rate; - -static unsigned long clk_ckih_get_rate(struct clk *clk) -{ - return ckih_rate; -} - -static unsigned long clk_ckil_get_rate(struct clk *clk) -{ - return CKIL_CLK_FREQ; -} - -static struct clk ckih_clk = { - .get_rate = clk_ckih_get_rate, -}; - -static struct clk mcu_pll_clk = { - .parent = &ckih_clk, - .get_rate = mcu_pll_get_rate, -}; - -static struct clk mcu_main_clk = { - .parent = &mcu_pll_clk, - .get_rate = mcu_main_get_rate, -}; - -static struct clk serial_pll_clk = { - .parent = &ckih_clk, - .get_rate = serial_pll_get_rate, - .enable = serial_pll_enable, - .disable = serial_pll_disable, -}; - -static struct clk usb_pll_clk = { - .parent = &ckih_clk, - .get_rate = usb_pll_get_rate, - .enable = usb_pll_enable, - .disable = usb_pll_disable, -}; - -static struct clk ahb_clk = { - .parent = &mcu_main_clk, - .get_rate = ahb_get_rate, -}; - -#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .enable = cgr_enable, \ - .disable = cgr_disable, \ - .secondary = s, \ - .parent = p, \ - } - -#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = getsetround##_get_rate, \ - .set_rate = getsetround##_set_rate, \ - .round_rate = getsetround##_round_rate, \ - .enable = cgr_enable, \ - .disable = cgr_disable, \ - .secondary = s, \ - .parent = p, \ - } - -DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL); - -DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk); -DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk); - -DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk); -DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk); -DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk); -DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk); -DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk); -DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk); -DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk); -DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk); - -DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk); -DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk); -DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk); -DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk); - -DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk); -DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk); -DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) - _REGISTER_CLOCK(NULL, "gpt", gpt_clk) - _REGISTER_CLOCK(NULL, "pwm", pwm_clk) - _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) - _REGISTER_CLOCK(NULL, "rtc", rtc_clk) - _REGISTER_CLOCK(NULL, "epit", epit1_clk) - _REGISTER_CLOCK(NULL, "epit", epit2_clk) - _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) - _REGISTER_CLOCK("ipu-core", NULL, ipu_clk) - _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) - _REGISTER_CLOCK(NULL, "kpp", kpp_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1) - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2) - _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1) - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2) - _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1) - _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2) - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1) - _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2) - _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk) - /* i.mx31 has the i.mx21 type uart */ - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk) - _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) - _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) - _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) - _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) - _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK(NULL, "firi", firi_clk) - _REGISTER_CLOCK("pata_imx", NULL, pata_clk) - _REGISTER_CLOCK(NULL, "rtic", rtic_clk) - _REGISTER_CLOCK(NULL, "rng", rng_clk) - _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1) - _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2) - _REGISTER_CLOCK(NULL, "mstick", mstick1_clk) - _REGISTER_CLOCK(NULL, "mstick", mstick2_clk) - _REGISTER_CLOCK(NULL, "scc", scc_clk) - _REGISTER_CLOCK(NULL, "iim", iim_clk) - _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk) - _REGISTER_CLOCK(NULL, "mbx", mbx_clk) -}; - -int __init mx31_clocks_init(unsigned long fref) -{ - u32 reg; - - ckih_rate = fref; - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - /* change the csi_clk parent if necessary */ - reg = __raw_readl(MXC_CCM_CCMR); - if (!(reg & MXC_CCM_CCMR_CSCS)) - if (clk_set_parent(&csi_clk, &usb_pll_clk)) - pr_err("%s: error changing csi_clk parent\n", __func__); - - - /* Turn off all possible clocks */ - __raw_writel((3 << 4), MXC_CCM_CGR0); - __raw_writel(0, MXC_CCM_CGR1); - __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| - 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for - MX32, but still required to be set */ - MXC_CCM_CGR2); - - /* - * Before turning off usb_pll make sure ipg_per_clk is generated - * by ipg_clk and not usb_pll. - */ - __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR); - - usb_pll_disable(&usb_pll_clk); - - pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); - - clk_enable(&gpt_clk); - clk_enable(&emi_clk); - clk_enable(&iim_clk); - mx31_revision(); - clk_disable(&iim_clk); - - clk_enable(&serial_pll_clk); - - if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { - reg = __raw_readl(MXC_CCM_PMCR1); - /* No PLL restart on DVFS switch; enable auto EMI handshake */ - reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; - __raw_writel(reg, MXC_CCM_PMCR1); - } - - mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), - MX31_INT_GPT); - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx35.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx35.c deleted file mode 100644 index e56c1a83..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx35.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright (C) 2009 by Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <mach/clock.h> -#include <mach/hardware.h> -#include <mach/common.h> - -#include "crmregs-imx3.h" - -#ifdef HAVE_SET_RATE_SUPPORT -static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost) -{ - u32 min_pre, temp_pre, old_err, err; - - min_pre = (div - 1) / maxpost + 1; - old_err = 8; - - for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { - if (div > (temp_pre * maxpost)) - break; - - if (div < (temp_pre * temp_pre)) - continue; - - err = div % temp_pre; - - if (err == 0) { - *pre = temp_pre; - break; - } - - err = temp_pre - err; - - if (err < old_err) { - old_err = err; - *pre = temp_pre; - } - } - - *post = (div + *pre - 1) / *pre; -} - -/* get the best values for a 3-bit divider combined with a 6-bit divider */ -static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post) -{ - if (div >= 512) { - *pre = 8; - *post = 64; - } else if (div >= 64) { - calc_dividers(div, pre, post, 64); - } else if (div <= 8) { - *pre = div; - *post = 1; - } else { - *pre = 1; - *post = div; - } -} - -/* get the best values for two cascaded 3-bit dividers */ -static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post) -{ - if (div >= 64) { - *pre = *post = 8; - } else if (div > 8) { - calc_dividers(div, pre, post, 8); - } else { - *pre = 1; - *post = div; - } -} -#endif - -static unsigned long get_rate_mpll(void) -{ - ulong mpctl = __raw_readl(MX35_CCM_MPCTL); - - return mxc_decode_pll(mpctl, 24000000); -} - -static unsigned long get_rate_ppll(void) -{ - ulong ppctl = __raw_readl(MX35_CCM_PPCTL); - - return mxc_decode_pll(ppctl, 24000000); -} - -struct arm_ahb_div { - unsigned char arm, ahb, sel; -}; - -static struct arm_ahb_div clk_consumer[] = { - { .arm = 1, .ahb = 4, .sel = 0}, - { .arm = 1, .ahb = 3, .sel = 1}, - { .arm = 2, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 1, .sel = 0}, - { .arm = 1, .ahb = 5, .sel = 0}, - { .arm = 1, .ahb = 8, .sel = 0}, - { .arm = 1, .ahb = 6, .sel = 1}, - { .arm = 2, .ahb = 4, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, -}; - -static unsigned long get_rate_arm(void) -{ - unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0); - struct arm_ahb_div *aad; - unsigned long fref = get_rate_mpll(); - - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 3 / 4; - - return fref / aad->arm; -} - -static unsigned long get_rate_ahb(struct clk *clk) -{ - unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0); - struct arm_ahb_div *aad; - unsigned long fref = get_rate_arm(); - - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - - return fref / aad->ahb; -} - -static unsigned long get_rate_ipg(struct clk *clk) -{ - return get_rate_ahb(NULL) >> 1; -} - -static unsigned long get_rate_uart(struct clk *clk) -{ - unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3); - unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4); - unsigned long div = ((pdr4 >> 10) & 0x3f) + 1; - - if (pdr3 & (1 << 14)) - return get_rate_arm() / div; - else - return get_rate_ppll() / div; -} - -static unsigned long get_rate_sdhc(struct clk *clk) -{ - unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3); - unsigned long div, rate; - - if (pdr3 & (1 << 6)) - rate = get_rate_arm(); - else - rate = get_rate_ppll(); - - switch (clk->id) { - default: - case 0: - div = pdr3 & 0x3f; - break; - case 1: - div = (pdr3 >> 8) & 0x3f; - break; - case 2: - div = (pdr3 >> 16) & 0x3f; - break; - } - - return rate / (div + 1); -} - -static unsigned long get_rate_mshc(struct clk *clk) -{ - unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1); - unsigned long div1, div2, rate; - - if (pdr1 & (1 << 7)) - rate = get_rate_arm(); - else - rate = get_rate_ppll(); - - div1 = (pdr1 >> 29) & 0x7; - div2 = (pdr1 >> 22) & 0x3f; - - return rate / ((div1 + 1) * (div2 + 1)); -} - -static unsigned long get_rate_ssi(struct clk *clk) -{ - unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2); - unsigned long div1, div2, rate; - - if (pdr2 & (1 << 6)) - rate = get_rate_arm(); - else - rate = get_rate_ppll(); - - switch (clk->id) { - default: - case 0: - div1 = pdr2 & 0x3f; - div2 = (pdr2 >> 24) & 0x7; - break; - case 1: - div1 = (pdr2 >> 8) & 0x3f; - div2 = (pdr2 >> 27) & 0x7; - break; - } - - return rate / ((div1 + 1) * (div2 + 1)); -} - -static unsigned long get_rate_csi(struct clk *clk) -{ - unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2); - unsigned long rate; - - if (pdr2 & (1 << 7)) - rate = get_rate_arm(); - else - rate = get_rate_ppll(); - - return rate / (((pdr2 >> 16) & 0x3f) + 1); -} - -static unsigned long get_rate_otg(struct clk *clk) -{ - unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4); - unsigned long rate; - - if (pdr4 & (1 << 9)) - rate = get_rate_arm(); - else - rate = get_rate_ppll(); - - return rate / (((pdr4 >> 22) & 0x3f) + 1); -} - -static unsigned long get_rate_ipg_per(struct clk *clk) -{ - unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0); - unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4); - unsigned long div; - - if (pdr0 & (1 << 26)) { - div = (pdr4 >> 16) & 0x3f; - return get_rate_arm() / (div + 1); - } else { - div = (pdr0 >> 12) & 0x7; - return get_rate_ahb(NULL) / (div + 1); - } -} - -static unsigned long get_rate_hsp(struct clk *clk) -{ - unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03; - unsigned long fref = get_rate_mpll(); - - if (fref > 400 * 1000 * 1000) { - switch (hsp_podf) { - case 0: - return fref >> 2; - case 1: - return fref >> 3; - case 2: - return fref / 3; - } - } else { - switch (hsp_podf) { - case 0: - case 2: - return fref / 3; - case 1: - return fref / 6; - } - } - - return 0; -} - -static int clk_cgr_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= 3 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void clk_cgr_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(3 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -#define DEFINE_CLOCK(name, i, er, es, gr, sr) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .set_rate = sr, \ - .enable = clk_cgr_enable, \ - .disable = clk_cgr_disable, \ - } - -DEFINE_CLOCK(asrc_clk, 0, MX35_CCM_CGR0, 0, NULL, NULL); -DEFINE_CLOCK(pata_clk, 0, MX35_CCM_CGR0, 2, get_rate_ipg, NULL); -/* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0, 4, NULL, NULL); */ -DEFINE_CLOCK(can1_clk, 0, MX35_CCM_CGR0, 6, get_rate_ipg, NULL); -DEFINE_CLOCK(can2_clk, 1, MX35_CCM_CGR0, 8, get_rate_ipg, NULL); -DEFINE_CLOCK(cspi1_clk, 0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL); -DEFINE_CLOCK(cspi2_clk, 1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL); -DEFINE_CLOCK(ect_clk, 0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL); -DEFINE_CLOCK(edio_clk, 0, MX35_CCM_CGR0, 16, NULL, NULL); -DEFINE_CLOCK(emi_clk, 0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL); -DEFINE_CLOCK(epit1_clk, 0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL); -DEFINE_CLOCK(epit2_clk, 1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL); -DEFINE_CLOCK(esai_clk, 0, MX35_CCM_CGR0, 24, NULL, NULL); -DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL); -DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL); -DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL); - -DEFINE_CLOCK(fec_clk, 0, MX35_CCM_CGR1, 0, get_rate_ipg, NULL); -DEFINE_CLOCK(gpio1_clk, 0, MX35_CCM_CGR1, 2, NULL, NULL); -DEFINE_CLOCK(gpio2_clk, 1, MX35_CCM_CGR1, 4, NULL, NULL); -DEFINE_CLOCK(gpio3_clk, 2, MX35_CCM_CGR1, 6, NULL, NULL); -DEFINE_CLOCK(gpt_clk, 0, MX35_CCM_CGR1, 8, get_rate_ipg, NULL); -DEFINE_CLOCK(i2c1_clk, 0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL); -DEFINE_CLOCK(i2c2_clk, 1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL); -DEFINE_CLOCK(i2c3_clk, 2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL); -DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL); -DEFINE_CLOCK(ipu_clk, 0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL); -DEFINE_CLOCK(kpp_clk, 0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL); -DEFINE_CLOCK(mlb_clk, 0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL); -DEFINE_CLOCK(mshc_clk, 0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL); -DEFINE_CLOCK(owire_clk, 0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL); -DEFINE_CLOCK(pwm_clk, 0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL); -DEFINE_CLOCK(rngc_clk, 0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL); - -DEFINE_CLOCK(rtc_clk, 0, MX35_CCM_CGR2, 0, get_rate_ipg, NULL); -DEFINE_CLOCK(rtic_clk, 0, MX35_CCM_CGR2, 2, get_rate_ahb, NULL); -DEFINE_CLOCK(scc_clk, 0, MX35_CCM_CGR2, 4, get_rate_ipg, NULL); -DEFINE_CLOCK(sdma_clk, 0, MX35_CCM_CGR2, 6, NULL, NULL); -DEFINE_CLOCK(spba_clk, 0, MX35_CCM_CGR2, 8, get_rate_ipg, NULL); -DEFINE_CLOCK(spdif_clk, 0, MX35_CCM_CGR2, 10, NULL, NULL); -DEFINE_CLOCK(ssi1_clk, 0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL); -DEFINE_CLOCK(ssi2_clk, 1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL); -DEFINE_CLOCK(uart1_clk, 0, MX35_CCM_CGR2, 16, get_rate_uart, NULL); -DEFINE_CLOCK(uart2_clk, 1, MX35_CCM_CGR2, 18, get_rate_uart, NULL); -DEFINE_CLOCK(uart3_clk, 2, MX35_CCM_CGR2, 20, get_rate_uart, NULL); -DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL); -DEFINE_CLOCK(wdog_clk, 0, MX35_CCM_CGR2, 24, NULL, NULL); -DEFINE_CLOCK(max_clk, 0, MX35_CCM_CGR2, 26, NULL, NULL); -DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL); - -DEFINE_CLOCK(csi_clk, 0, MX35_CCM_CGR3, 0, get_rate_csi, NULL); -DEFINE_CLOCK(iim_clk, 0, MX35_CCM_CGR3, 2, NULL, NULL); -DEFINE_CLOCK(gpu2d_clk, 0, MX35_CCM_CGR3, 4, NULL, NULL); - -DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL); - -static int clk_dummy_enable(struct clk *clk) -{ - return 0; -} - -static void clk_dummy_disable(struct clk *clk) -{ -} - -static unsigned long get_rate_nfc(struct clk *clk) -{ - unsigned long div1; - - div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1; - - return get_rate_ahb(NULL) / div1; -} - -/* NAND Controller: It seems it can't be disabled */ -static struct clk nfc_clk = { - .id = 0, - .enable_reg = 0, - .enable_shift = 0, - .get_rate = get_rate_nfc, - .set_rate = NULL, /* set_rate_nfc, */ - .enable = clk_dummy_enable, - .disable = clk_dummy_disable -}; - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK(NULL, "asrc", asrc_clk) - _REGISTER_CLOCK("pata_imx", NULL, pata_clk) - _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) - _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) - _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) - _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk) - _REGISTER_CLOCK(NULL, "ect", ect_clk) - _REGISTER_CLOCK(NULL, "edio", edio_clk) - _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk) - _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk) - _REGISTER_CLOCK(NULL, "esai", esai_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx35.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx35.1", NULL, esdhc2_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx35.2", NULL, esdhc3_clk) - /* i.mx35 has the i.mx27 type fec */ - _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk) - _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) - _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) - _REGISTER_CLOCK(NULL, "gpio", gpio3_clk) - _REGISTER_CLOCK("gpt.0", NULL, gpt_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) - _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) - _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk) - _REGISTER_CLOCK("ipu-core", NULL, ipu_clk) - _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) - _REGISTER_CLOCK(NULL, "kpp", kpp_clk) - _REGISTER_CLOCK(NULL, "mlb", mlb_clk) - _REGISTER_CLOCK(NULL, "mshc", mshc_clk) - _REGISTER_CLOCK("mxc_w1", NULL, owire_clk) - _REGISTER_CLOCK(NULL, "pwm", pwm_clk) - _REGISTER_CLOCK(NULL, "rngc", rngc_clk) - _REGISTER_CLOCK(NULL, "rtc", rtc_clk) - _REGISTER_CLOCK(NULL, "rtic", rtic_clk) - _REGISTER_CLOCK(NULL, "scc", scc_clk) - _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) - _REGISTER_CLOCK(NULL, "spba", spba_clk) - _REGISTER_CLOCK(NULL, "spdif", spdif_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - /* i.mx35 has the i.mx21 type uart */ - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) - _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) - _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) - _REGISTER_CLOCK(NULL, "max", max_clk) - _REGISTER_CLOCK(NULL, "audmux", audmux_clk) - _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk) - _REGISTER_CLOCK(NULL, "iim", iim_clk) - _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) - _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) -}; - -int __init mx35_clocks_init() -{ - unsigned int cgr2 = 3 << 26; - -#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) - cgr2 |= 3 << 16; -#endif - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - /* Turn off all clocks except the ones we need to survive, namely: - * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart - */ - __raw_writel((3 << 18), MX35_CCM_CGR0); - __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), - MX35_CCM_CGR1); - __raw_writel(cgr2, MX35_CCM_CGR2); - __raw_writel(0, MX35_CCM_CGR3); - - clk_enable(&iim_clk); - imx_print_silicon_rev("i.MX35", mx35_revision()); - clk_disable(&iim_clk); - - /* - * Check if we came up in internal boot mode. If yes, we need some - * extra clocks turned on, otherwise the MX35 boot ROM code will - * hang after a watchdog reset. - */ - if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) { - /* Additionally turn on UART1, SCC, and IIM clocks */ - clk_enable(&iim_clk); - clk_enable(&uart1_clk); - clk_enable(&scc_clk); - } - -#ifdef CONFIG_MXC_USE_EPIT - epit_timer_init(&epit1_clk, - MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); -#else - mxc_timer_init(&gpt_clk, - MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); -#endif - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx6q.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx6q.c deleted file mode 100644 index 111c328f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-imx6q.c +++ /dev/null @@ -1,2111 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/types.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <asm/div64.h> -#include <asm/mach/map.h> -#include <mach/clock.h> -#include <mach/common.h> -#include <mach/hardware.h> - -#define PLL_BASE IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR) -#define PLL1_SYS (PLL_BASE + 0x000) -#define PLL2_BUS (PLL_BASE + 0x030) -#define PLL3_USB_OTG (PLL_BASE + 0x010) -#define PLL4_AUDIO (PLL_BASE + 0x070) -#define PLL5_VIDEO (PLL_BASE + 0x0a0) -#define PLL6_MLB (PLL_BASE + 0x0d0) -#define PLL7_USB_HOST (PLL_BASE + 0x020) -#define PLL8_ENET (PLL_BASE + 0x0e0) -#define PFD_480 (PLL_BASE + 0x0f0) -#define PFD_528 (PLL_BASE + 0x100) -#define PLL_NUM_OFFSET 0x010 -#define PLL_DENOM_OFFSET 0x020 - -#define PFD0 7 -#define PFD1 15 -#define PFD2 23 -#define PFD3 31 -#define PFD_FRAC_MASK 0x3f - -#define BM_PLL_BYPASS (0x1 << 16) -#define BM_PLL_ENABLE (0x1 << 13) -#define BM_PLL_POWER_DOWN (0x1 << 12) -#define BM_PLL_LOCK (0x1 << 31) -#define BP_PLL_SYS_DIV_SELECT 0 -#define BM_PLL_SYS_DIV_SELECT (0x7f << 0) -#define BP_PLL_BUS_DIV_SELECT 0 -#define BM_PLL_BUS_DIV_SELECT (0x1 << 0) -#define BP_PLL_USB_DIV_SELECT 0 -#define BM_PLL_USB_DIV_SELECT (0x3 << 0) -#define BP_PLL_AV_DIV_SELECT 0 -#define BM_PLL_AV_DIV_SELECT (0x7f << 0) -#define BP_PLL_ENET_DIV_SELECT 0 -#define BM_PLL_ENET_DIV_SELECT (0x3 << 0) -#define BM_PLL_ENET_EN_PCIE (0x1 << 19) -#define BM_PLL_ENET_EN_SATA (0x1 << 20) - -#define CCM_BASE IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR) -#define CCR (CCM_BASE + 0x00) -#define CCDR (CCM_BASE + 0x04) -#define CSR (CCM_BASE + 0x08) -#define CCSR (CCM_BASE + 0x0c) -#define CACRR (CCM_BASE + 0x10) -#define CBCDR (CCM_BASE + 0x14) -#define CBCMR (CCM_BASE + 0x18) -#define CSCMR1 (CCM_BASE + 0x1c) -#define CSCMR2 (CCM_BASE + 0x20) -#define CSCDR1 (CCM_BASE + 0x24) -#define CS1CDR (CCM_BASE + 0x28) -#define CS2CDR (CCM_BASE + 0x2c) -#define CDCDR (CCM_BASE + 0x30) -#define CHSCCDR (CCM_BASE + 0x34) -#define CSCDR2 (CCM_BASE + 0x38) -#define CSCDR3 (CCM_BASE + 0x3c) -#define CSCDR4 (CCM_BASE + 0x40) -#define CWDR (CCM_BASE + 0x44) -#define CDHIPR (CCM_BASE + 0x48) -#define CDCR (CCM_BASE + 0x4c) -#define CTOR (CCM_BASE + 0x50) -#define CLPCR (CCM_BASE + 0x54) -#define CISR (CCM_BASE + 0x58) -#define CIMR (CCM_BASE + 0x5c) -#define CCOSR (CCM_BASE + 0x60) -#define CGPR (CCM_BASE + 0x64) -#define CCGR0 (CCM_BASE + 0x68) -#define CCGR1 (CCM_BASE + 0x6c) -#define CCGR2 (CCM_BASE + 0x70) -#define CCGR3 (CCM_BASE + 0x74) -#define CCGR4 (CCM_BASE + 0x78) -#define CCGR5 (CCM_BASE + 0x7c) -#define CCGR6 (CCM_BASE + 0x80) -#define CCGR7 (CCM_BASE + 0x84) -#define CMEOR (CCM_BASE + 0x88) - -#define CG0 0 -#define CG1 2 -#define CG2 4 -#define CG3 6 -#define CG4 8 -#define CG5 10 -#define CG6 12 -#define CG7 14 -#define CG8 16 -#define CG9 18 -#define CG10 20 -#define CG11 22 -#define CG12 24 -#define CG13 26 -#define CG14 28 -#define CG15 30 - -#define BM_CCSR_PLL1_SW_SEL (0x1 << 2) -#define BM_CCSR_STEP_SEL (0x1 << 8) - -#define BP_CACRR_ARM_PODF 0 -#define BM_CACRR_ARM_PODF (0x7 << 0) - -#define BP_CBCDR_PERIPH2_CLK2_PODF 0 -#define BM_CBCDR_PERIPH2_CLK2_PODF (0x7 << 0) -#define BP_CBCDR_MMDC_CH1_AXI_PODF 3 -#define BM_CBCDR_MMDC_CH1_AXI_PODF (0x7 << 3) -#define BP_CBCDR_AXI_SEL 6 -#define BM_CBCDR_AXI_SEL (0x3 << 6) -#define BP_CBCDR_IPG_PODF 8 -#define BM_CBCDR_IPG_PODF (0x3 << 8) -#define BP_CBCDR_AHB_PODF 10 -#define BM_CBCDR_AHB_PODF (0x7 << 10) -#define BP_CBCDR_AXI_PODF 16 -#define BM_CBCDR_AXI_PODF (0x7 << 16) -#define BP_CBCDR_MMDC_CH0_AXI_PODF 19 -#define BM_CBCDR_MMDC_CH0_AXI_PODF (0x7 << 19) -#define BP_CBCDR_PERIPH_CLK_SEL 25 -#define BM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define BP_CBCDR_PERIPH2_CLK_SEL 26 -#define BM_CBCDR_PERIPH2_CLK_SEL (0x1 << 26) -#define BP_CBCDR_PERIPH_CLK2_PODF 27 -#define BM_CBCDR_PERIPH_CLK2_PODF (0x7 << 27) - -#define BP_CBCMR_GPU2D_AXI_SEL 0 -#define BM_CBCMR_GPU2D_AXI_SEL (0x1 << 0) -#define BP_CBCMR_GPU3D_AXI_SEL 1 -#define BM_CBCMR_GPU3D_AXI_SEL (0x1 << 1) -#define BP_CBCMR_GPU3D_CORE_SEL 4 -#define BM_CBCMR_GPU3D_CORE_SEL (0x3 << 4) -#define BP_CBCMR_GPU3D_SHADER_SEL 8 -#define BM_CBCMR_GPU3D_SHADER_SEL (0x3 << 8) -#define BP_CBCMR_PCIE_AXI_SEL 10 -#define BM_CBCMR_PCIE_AXI_SEL (0x1 << 10) -#define BP_CBCMR_VDO_AXI_SEL 11 -#define BM_CBCMR_VDO_AXI_SEL (0x1 << 11) -#define BP_CBCMR_PERIPH_CLK2_SEL 12 -#define BM_CBCMR_PERIPH_CLK2_SEL (0x3 << 12) -#define BP_CBCMR_VPU_AXI_SEL 14 -#define BM_CBCMR_VPU_AXI_SEL (0x3 << 14) -#define BP_CBCMR_GPU2D_CORE_SEL 16 -#define BM_CBCMR_GPU2D_CORE_SEL (0x3 << 16) -#define BP_CBCMR_PRE_PERIPH_CLK_SEL 18 -#define BM_CBCMR_PRE_PERIPH_CLK_SEL (0x3 << 18) -#define BP_CBCMR_PERIPH2_CLK2_SEL 20 -#define BM_CBCMR_PERIPH2_CLK2_SEL (0x1 << 20) -#define BP_CBCMR_PRE_PERIPH2_CLK_SEL 21 -#define BM_CBCMR_PRE_PERIPH2_CLK_SEL (0x3 << 21) -#define BP_CBCMR_GPU2D_CORE_PODF 23 -#define BM_CBCMR_GPU2D_CORE_PODF (0x7 << 23) -#define BP_CBCMR_GPU3D_CORE_PODF 26 -#define BM_CBCMR_GPU3D_CORE_PODF (0x7 << 26) -#define BP_CBCMR_GPU3D_SHADER_PODF 29 -#define BM_CBCMR_GPU3D_SHADER_PODF (0x7 << 29) - -#define BP_CSCMR1_PERCLK_PODF 0 -#define BM_CSCMR1_PERCLK_PODF (0x3f << 0) -#define BP_CSCMR1_SSI1_SEL 10 -#define BM_CSCMR1_SSI1_SEL (0x3 << 10) -#define BP_CSCMR1_SSI2_SEL 12 -#define BM_CSCMR1_SSI2_SEL (0x3 << 12) -#define BP_CSCMR1_SSI3_SEL 14 -#define BM_CSCMR1_SSI3_SEL (0x3 << 14) -#define BP_CSCMR1_USDHC1_SEL 16 -#define BM_CSCMR1_USDHC1_SEL (0x1 << 16) -#define BP_CSCMR1_USDHC2_SEL 17 -#define BM_CSCMR1_USDHC2_SEL (0x1 << 17) -#define BP_CSCMR1_USDHC3_SEL 18 -#define BM_CSCMR1_USDHC3_SEL (0x1 << 18) -#define BP_CSCMR1_USDHC4_SEL 19 -#define BM_CSCMR1_USDHC4_SEL (0x1 << 19) -#define BP_CSCMR1_EMI_PODF 20 -#define BM_CSCMR1_EMI_PODF (0x7 << 20) -#define BP_CSCMR1_EMI_SLOW_PODF 23 -#define BM_CSCMR1_EMI_SLOW_PODF (0x7 << 23) -#define BP_CSCMR1_EMI_SEL 27 -#define BM_CSCMR1_EMI_SEL (0x3 << 27) -#define BP_CSCMR1_EMI_SLOW_SEL 29 -#define BM_CSCMR1_EMI_SLOW_SEL (0x3 << 29) - -#define BP_CSCMR2_CAN_PODF 2 -#define BM_CSCMR2_CAN_PODF (0x3f << 2) -#define BM_CSCMR2_LDB_DI0_IPU_DIV (0x1 << 10) -#define BM_CSCMR2_LDB_DI1_IPU_DIV (0x1 << 11) -#define BP_CSCMR2_ESAI_SEL 19 -#define BM_CSCMR2_ESAI_SEL (0x3 << 19) - -#define BP_CSCDR1_UART_PODF 0 -#define BM_CSCDR1_UART_PODF (0x3f << 0) -#define BP_CSCDR1_USDHC1_PODF 11 -#define BM_CSCDR1_USDHC1_PODF (0x7 << 11) -#define BP_CSCDR1_USDHC2_PODF 16 -#define BM_CSCDR1_USDHC2_PODF (0x7 << 16) -#define BP_CSCDR1_USDHC3_PODF 19 -#define BM_CSCDR1_USDHC3_PODF (0x7 << 19) -#define BP_CSCDR1_USDHC4_PODF 22 -#define BM_CSCDR1_USDHC4_PODF (0x7 << 22) -#define BP_CSCDR1_VPU_AXI_PODF 25 -#define BM_CSCDR1_VPU_AXI_PODF (0x7 << 25) - -#define BP_CS1CDR_SSI1_PODF 0 -#define BM_CS1CDR_SSI1_PODF (0x3f << 0) -#define BP_CS1CDR_SSI1_PRED 6 -#define BM_CS1CDR_SSI1_PRED (0x7 << 6) -#define BP_CS1CDR_ESAI_PRED 9 -#define BM_CS1CDR_ESAI_PRED (0x7 << 9) -#define BP_CS1CDR_SSI3_PODF 16 -#define BM_CS1CDR_SSI3_PODF (0x3f << 16) -#define BP_CS1CDR_SSI3_PRED 22 -#define BM_CS1CDR_SSI3_PRED (0x7 << 22) -#define BP_CS1CDR_ESAI_PODF 25 -#define BM_CS1CDR_ESAI_PODF (0x7 << 25) - -#define BP_CS2CDR_SSI2_PODF 0 -#define BM_CS2CDR_SSI2_PODF (0x3f << 0) -#define BP_CS2CDR_SSI2_PRED 6 -#define BM_CS2CDR_SSI2_PRED (0x7 << 6) -#define BP_CS2CDR_LDB_DI0_SEL 9 -#define BM_CS2CDR_LDB_DI0_SEL (0x7 << 9) -#define BP_CS2CDR_LDB_DI1_SEL 12 -#define BM_CS2CDR_LDB_DI1_SEL (0x7 << 12) -#define BP_CS2CDR_ENFC_SEL 16 -#define BM_CS2CDR_ENFC_SEL (0x3 << 16) -#define BP_CS2CDR_ENFC_PRED 18 -#define BM_CS2CDR_ENFC_PRED (0x7 << 18) -#define BP_CS2CDR_ENFC_PODF 21 -#define BM_CS2CDR_ENFC_PODF (0x3f << 21) - -#define BP_CDCDR_ASRC_SERIAL_SEL 7 -#define BM_CDCDR_ASRC_SERIAL_SEL (0x3 << 7) -#define BP_CDCDR_ASRC_SERIAL_PODF 9 -#define BM_CDCDR_ASRC_SERIAL_PODF (0x7 << 9) -#define BP_CDCDR_ASRC_SERIAL_PRED 12 -#define BM_CDCDR_ASRC_SERIAL_PRED (0x7 << 12) -#define BP_CDCDR_SPDIF_SEL 20 -#define BM_CDCDR_SPDIF_SEL (0x3 << 20) -#define BP_CDCDR_SPDIF_PODF 22 -#define BM_CDCDR_SPDIF_PODF (0x7 << 22) -#define BP_CDCDR_SPDIF_PRED 25 -#define BM_CDCDR_SPDIF_PRED (0x7 << 25) -#define BP_CDCDR_HSI_TX_PODF 29 -#define BM_CDCDR_HSI_TX_PODF (0x7 << 29) -#define BP_CDCDR_HSI_TX_SEL 28 -#define BM_CDCDR_HSI_TX_SEL (0x1 << 28) - -#define BP_CHSCCDR_IPU1_DI0_SEL 0 -#define BM_CHSCCDR_IPU1_DI0_SEL (0x7 << 0) -#define BP_CHSCCDR_IPU1_DI0_PRE_PODF 3 -#define BM_CHSCCDR_IPU1_DI0_PRE_PODF (0x7 << 3) -#define BP_CHSCCDR_IPU1_DI0_PRE_SEL 6 -#define BM_CHSCCDR_IPU1_DI0_PRE_SEL (0x7 << 6) -#define BP_CHSCCDR_IPU1_DI1_SEL 9 -#define BM_CHSCCDR_IPU1_DI1_SEL (0x7 << 9) -#define BP_CHSCCDR_IPU1_DI1_PRE_PODF 12 -#define BM_CHSCCDR_IPU1_DI1_PRE_PODF (0x7 << 12) -#define BP_CHSCCDR_IPU1_DI1_PRE_SEL 15 -#define BM_CHSCCDR_IPU1_DI1_PRE_SEL (0x7 << 15) - -#define BP_CSCDR2_IPU2_DI0_SEL 0 -#define BM_CSCDR2_IPU2_DI0_SEL (0x7) -#define BP_CSCDR2_IPU2_DI0_PRE_PODF 3 -#define BM_CSCDR2_IPU2_DI0_PRE_PODF (0x7 << 3) -#define BP_CSCDR2_IPU2_DI0_PRE_SEL 6 -#define BM_CSCDR2_IPU2_DI0_PRE_SEL (0x7 << 6) -#define BP_CSCDR2_IPU2_DI1_SEL 9 -#define BM_CSCDR2_IPU2_DI1_SEL (0x7 << 9) -#define BP_CSCDR2_IPU2_DI1_PRE_PODF 12 -#define BM_CSCDR2_IPU2_DI1_PRE_PODF (0x7 << 12) -#define BP_CSCDR2_IPU2_DI1_PRE_SEL 15 -#define BM_CSCDR2_IPU2_DI1_PRE_SEL (0x7 << 15) -#define BP_CSCDR2_ECSPI_CLK_PODF 19 -#define BM_CSCDR2_ECSPI_CLK_PODF (0x3f << 19) - -#define BP_CSCDR3_IPU1_HSP_SEL 9 -#define BM_CSCDR3_IPU1_HSP_SEL (0x3 << 9) -#define BP_CSCDR3_IPU1_HSP_PODF 11 -#define BM_CSCDR3_IPU1_HSP_PODF (0x7 << 11) -#define BP_CSCDR3_IPU2_HSP_SEL 14 -#define BM_CSCDR3_IPU2_HSP_SEL (0x3 << 14) -#define BP_CSCDR3_IPU2_HSP_PODF 16 -#define BM_CSCDR3_IPU2_HSP_PODF (0x7 << 16) - -#define BM_CDHIPR_AXI_PODF_BUSY (0x1 << 0) -#define BM_CDHIPR_AHB_PODF_BUSY (0x1 << 1) -#define BM_CDHIPR_MMDC_CH1_PODF_BUSY (0x1 << 2) -#define BM_CDHIPR_PERIPH2_SEL_BUSY (0x1 << 3) -#define BM_CDHIPR_MMDC_CH0_PODF_BUSY (0x1 << 4) -#define BM_CDHIPR_PERIPH_SEL_BUSY (0x1 << 5) -#define BM_CDHIPR_ARM_PODF_BUSY (0x1 << 16) - -#define BP_CLPCR_LPM 0 -#define BM_CLPCR_LPM (0x3 << 0) -#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) -#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define BM_CLPCR_SBYOS (0x1 << 6) -#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define BM_CLPCR_VSTBY (0x1 << 8) -#define BP_CLPCR_STBY_COUNT 9 -#define BM_CLPCR_STBY_COUNT (0x3 << 9) -#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) -#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) -#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) -#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) -#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) -#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) -#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) -#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) -#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) -#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) - -#define BP_CCOSR_CKO1_EN 7 -#define BP_CCOSR_CKO1_PODF 4 -#define BM_CCOSR_CKO1_PODF (0x7 << 4) -#define BP_CCOSR_CKO1_SEL 0 -#define BM_CCOSR_CKO1_SEL (0xf << 0) - -#define FREQ_480M 480000000 -#define FREQ_528M 528000000 -#define FREQ_594M 594000000 -#define FREQ_650M 650000000 -#define FREQ_1300M 1300000000 - -static struct clk pll1_sys; -static struct clk pll2_bus; -static struct clk pll3_usb_otg; -static struct clk pll4_audio; -static struct clk pll5_video; -static struct clk pll6_mlb; -static struct clk pll7_usb_host; -static struct clk pll8_enet; -static struct clk apbh_dma_clk; -static struct clk arm_clk; -static struct clk ipg_clk; -static struct clk ahb_clk; -static struct clk axi_clk; -static struct clk mmdc_ch0_axi_clk; -static struct clk mmdc_ch1_axi_clk; -static struct clk periph_clk; -static struct clk periph_pre_clk; -static struct clk periph_clk2_clk; -static struct clk periph2_clk; -static struct clk periph2_pre_clk; -static struct clk periph2_clk2_clk; -static struct clk gpu2d_core_clk; -static struct clk gpu3d_core_clk; -static struct clk gpu3d_shader_clk; -static struct clk ipg_perclk; -static struct clk emi_clk; -static struct clk emi_slow_clk; -static struct clk can1_clk; -static struct clk uart_clk; -static struct clk usdhc1_clk; -static struct clk usdhc2_clk; -static struct clk usdhc3_clk; -static struct clk usdhc4_clk; -static struct clk vpu_clk; -static struct clk hsi_tx_clk; -static struct clk ipu1_di0_pre_clk; -static struct clk ipu1_di1_pre_clk; -static struct clk ipu2_di0_pre_clk; -static struct clk ipu2_di1_pre_clk; -static struct clk ipu1_clk; -static struct clk ipu2_clk; -static struct clk ssi1_clk; -static struct clk ssi3_clk; -static struct clk esai_clk; -static struct clk ssi2_clk; -static struct clk spdif_clk; -static struct clk asrc_serial_clk; -static struct clk gpu2d_axi_clk; -static struct clk gpu3d_axi_clk; -static struct clk pcie_clk; -static struct clk vdo_axi_clk; -static struct clk ldb_di0_clk; -static struct clk ldb_di1_clk; -static struct clk ipu1_di0_clk; -static struct clk ipu1_di1_clk; -static struct clk ipu2_di0_clk; -static struct clk ipu2_di1_clk; -static struct clk enfc_clk; -static struct clk cko1_clk; -static struct clk dummy_clk = {}; - -static unsigned long external_high_reference; -static unsigned long external_low_reference; -static unsigned long oscillator_reference; - -static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) -{ - return oscillator_reference; -} - -static unsigned long get_high_reference_clock_rate(struct clk *clk) -{ - return external_high_reference; -} - -static unsigned long get_low_reference_clock_rate(struct clk *clk) -{ - return external_low_reference; -} - -static struct clk ckil_clk = { - .get_rate = get_low_reference_clock_rate, -}; - -static struct clk ckih_clk = { - .get_rate = get_high_reference_clock_rate, -}; - -static struct clk osc_clk = { - .get_rate = get_oscillator_reference_clock_rate, -}; - -static inline void __iomem *pll_get_reg_addr(struct clk *pll) -{ - if (pll == &pll1_sys) - return PLL1_SYS; - else if (pll == &pll2_bus) - return PLL2_BUS; - else if (pll == &pll3_usb_otg) - return PLL3_USB_OTG; - else if (pll == &pll4_audio) - return PLL4_AUDIO; - else if (pll == &pll5_video) - return PLL5_VIDEO; - else if (pll == &pll6_mlb) - return PLL6_MLB; - else if (pll == &pll7_usb_host) - return PLL7_USB_HOST; - else if (pll == &pll8_enet) - return PLL8_ENET; - else - BUG(); - - return NULL; -} - -static int pll_enable(struct clk *clk) -{ - int timeout = 0x100000; - void __iomem *reg; - u32 val; - - reg = pll_get_reg_addr(clk); - val = readl_relaxed(reg); - val &= ~BM_PLL_BYPASS; - val &= ~BM_PLL_POWER_DOWN; - /* 480MHz PLLs have the opposite definition for power bit */ - if (clk == &pll3_usb_otg || clk == &pll7_usb_host) - val |= BM_PLL_POWER_DOWN; - writel_relaxed(val, reg); - - /* Wait for PLL to lock */ - while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout) - cpu_relax(); - - if (unlikely(!timeout)) - return -EBUSY; - - /* Enable the PLL output now */ - val = readl_relaxed(reg); - val |= BM_PLL_ENABLE; - writel_relaxed(val, reg); - - return 0; -} - -static void pll_disable(struct clk *clk) -{ - void __iomem *reg; - u32 val; - - reg = pll_get_reg_addr(clk); - val = readl_relaxed(reg); - val &= ~BM_PLL_ENABLE; - val |= BM_PLL_BYPASS; - val |= BM_PLL_POWER_DOWN; - if (clk == &pll3_usb_otg || clk == &pll7_usb_host) - val &= ~BM_PLL_POWER_DOWN; - writel_relaxed(val, reg); -} - -static unsigned long pll1_sys_get_rate(struct clk *clk) -{ - u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >> - BP_PLL_SYS_DIV_SELECT; - - return clk_get_rate(clk->parent) * div / 2; -} - -static int pll1_sys_set_rate(struct clk *clk, unsigned long rate) -{ - u32 val, div; - - if (rate < FREQ_650M || rate > FREQ_1300M) - return -EINVAL; - - div = rate * 2 / clk_get_rate(clk->parent); - val = readl_relaxed(PLL1_SYS); - val &= ~BM_PLL_SYS_DIV_SELECT; - val |= div << BP_PLL_SYS_DIV_SELECT; - writel_relaxed(val, PLL1_SYS); - - return 0; -} - -static unsigned long pll8_enet_get_rate(struct clk *clk) -{ - u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >> - BP_PLL_ENET_DIV_SELECT; - - switch (div) { - case 0: - return 25000000; - case 1: - return 50000000; - case 2: - return 100000000; - case 3: - return 125000000; - } - - return 0; -} - -static int pll8_enet_set_rate(struct clk *clk, unsigned long rate) -{ - u32 val, div; - - switch (rate) { - case 25000000: - div = 0; - break; - case 50000000: - div = 1; - break; - case 100000000: - div = 2; - break; - case 125000000: - div = 3; - break; - default: - return -EINVAL; - } - - val = readl_relaxed(PLL8_ENET); - val &= ~BM_PLL_ENET_DIV_SELECT; - val |= div << BP_PLL_ENET_DIV_SELECT; - writel_relaxed(val, PLL8_ENET); - - return 0; -} - -static unsigned long pll_av_get_rate(struct clk *clk) -{ - void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO; - unsigned long parent_rate = clk_get_rate(clk->parent); - u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET); - u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET); - u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >> - BP_PLL_AV_DIV_SELECT; - - return (parent_rate * div) + ((parent_rate / mfd) * mfn); -} - -static int pll_av_set_rate(struct clk *clk, unsigned long rate) -{ - void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO; - unsigned int parent_rate = clk_get_rate(clk->parent); - u32 val, div; - u32 mfn, mfd = 1000000; - s64 temp64; - - if (rate < FREQ_650M || rate > FREQ_1300M) - return -EINVAL; - - div = rate / parent_rate; - temp64 = (u64) (rate - div * parent_rate); - temp64 *= mfd; - do_div(temp64, parent_rate); - mfn = temp64; - - val = readl_relaxed(reg); - val &= ~BM_PLL_AV_DIV_SELECT; - val |= div << BP_PLL_AV_DIV_SELECT; - writel_relaxed(val, reg); - writel_relaxed(mfn, reg + PLL_NUM_OFFSET); - writel_relaxed(mfd, reg + PLL_DENOM_OFFSET); - - return 0; -} - -static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm) -{ - void __iomem *reg; - - if (clk == &pll2_bus) { - reg = PLL2_BUS; - *bp = BP_PLL_BUS_DIV_SELECT; - *bm = BM_PLL_BUS_DIV_SELECT; - } else if (clk == &pll3_usb_otg) { - reg = PLL3_USB_OTG; - *bp = BP_PLL_USB_DIV_SELECT; - *bm = BM_PLL_USB_DIV_SELECT; - } else if (clk == &pll7_usb_host) { - reg = PLL7_USB_HOST; - *bp = BP_PLL_USB_DIV_SELECT; - *bm = BM_PLL_USB_DIV_SELECT; - } else { - BUG(); - } - - return reg; -} - -static unsigned long pll_get_rate(struct clk *clk) -{ - void __iomem *reg; - u32 div, bp, bm; - - reg = pll_get_div_reg_bit(clk, &bp, &bm); - div = (readl_relaxed(reg) & bm) >> bp; - - return (div == 1) ? clk_get_rate(clk->parent) * 22 : - clk_get_rate(clk->parent) * 20; -} - -static int pll_set_rate(struct clk *clk, unsigned long rate) -{ - void __iomem *reg; - u32 val, div, bp, bm; - - if (rate == FREQ_528M) - div = 1; - else if (rate == FREQ_480M) - div = 0; - else - return -EINVAL; - - reg = pll_get_div_reg_bit(clk, &bp, &bm); - val = readl_relaxed(reg); - val &= ~bm; - val |= div << bp; - writel_relaxed(val, reg); - - return 0; -} - -#define pll2_bus_get_rate pll_get_rate -#define pll2_bus_set_rate pll_set_rate -#define pll3_usb_otg_get_rate pll_get_rate -#define pll3_usb_otg_set_rate pll_set_rate -#define pll7_usb_host_get_rate pll_get_rate -#define pll7_usb_host_set_rate pll_set_rate -#define pll4_audio_get_rate pll_av_get_rate -#define pll4_audio_set_rate pll_av_set_rate -#define pll5_video_get_rate pll_av_get_rate -#define pll5_video_set_rate pll_av_set_rate -#define pll6_mlb_get_rate NULL -#define pll6_mlb_set_rate NULL - -#define DEF_PLL(name) \ - static struct clk name = { \ - .enable = pll_enable, \ - .disable = pll_disable, \ - .get_rate = name##_get_rate, \ - .set_rate = name##_set_rate, \ - .parent = &osc_clk, \ - } - -DEF_PLL(pll1_sys); -DEF_PLL(pll2_bus); -DEF_PLL(pll3_usb_otg); -DEF_PLL(pll4_audio); -DEF_PLL(pll5_video); -DEF_PLL(pll6_mlb); -DEF_PLL(pll7_usb_host); -DEF_PLL(pll8_enet); - -static unsigned long pfd_get_rate(struct clk *clk) -{ - u64 tmp = (u64) clk_get_rate(clk->parent) * 18; - u32 frac, bp_frac; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - - bp_frac = clk->enable_shift - 7; - frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK; - do_div(tmp, frac); - - return tmp; -} - -static int pfd_set_rate(struct clk *clk, unsigned long rate) -{ - u32 val, frac, bp_frac; - u64 tmp = (u64) clk_get_rate(clk->parent) * 18; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - - /* - * Round up the divider so that we don't set a rate - * higher than what is requested - */ - tmp += rate / 2; - do_div(tmp, rate); - frac = tmp; - frac = (frac < 12) ? 12 : frac; - frac = (frac > 35) ? 35 : frac; - - /* - * The frac field always starts from 7 bits lower - * position of enable bit - */ - bp_frac = clk->enable_shift - 7; - val = readl_relaxed(clk->enable_reg); - val &= ~(PFD_FRAC_MASK << bp_frac); - val |= frac << bp_frac; - writel_relaxed(val, clk->enable_reg); - - tmp = (u64) clk_get_rate(clk->parent) * 18; - do_div(tmp, frac); - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); - - return 0; -} - -static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) -{ - u32 frac; - u64 tmp; - - tmp = (u64) clk_get_rate(clk->parent) * 18; - tmp += rate / 2; - do_div(tmp, rate); - frac = tmp; - frac = (frac < 12) ? 12 : frac; - frac = (frac > 35) ? 35 : frac; - tmp = (u64) clk_get_rate(clk->parent) * 18; - do_div(tmp, frac); - - return tmp; -} - -static int pfd_enable(struct clk *clk) -{ - u32 val; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - - val = readl_relaxed(clk->enable_reg); - val &= ~(1 << clk->enable_shift); - writel_relaxed(val, clk->enable_reg); - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); - - return 0; -} - -static void pfd_disable(struct clk *clk) -{ - u32 val; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - - val = readl_relaxed(clk->enable_reg); - val |= 1 << clk->enable_shift; - writel_relaxed(val, clk->enable_reg); - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); -} - -#define DEF_PFD(name, er, es, p) \ - static struct clk name = { \ - .enable_reg = er, \ - .enable_shift = es, \ - .enable = pfd_enable, \ - .disable = pfd_disable, \ - .get_rate = pfd_get_rate, \ - .set_rate = pfd_set_rate, \ - .round_rate = pfd_round_rate, \ - .parent = p, \ - } - -DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus); -DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus); -DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus); -DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg); -DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg); -DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); -DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); - -static unsigned long twd_clk_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 2; -} - -static struct clk twd_clk = { - .parent = &arm_clk, - .get_rate = twd_clk_get_rate, -}; - -static unsigned long pll2_200m_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 2; -} - -static struct clk pll2_200m = { - .parent = &pll2_pfd_400m, - .get_rate = pll2_200m_get_rate, -}; - -static unsigned long pll3_120m_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 4; -} - -static struct clk pll3_120m = { - .parent = &pll3_usb_otg, - .get_rate = pll3_120m_get_rate, -}; - -static unsigned long pll3_80m_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 6; -} - -static struct clk pll3_80m = { - .parent = &pll3_usb_otg, - .get_rate = pll3_80m_get_rate, -}; - -static unsigned long pll3_60m_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 8; -} - -static struct clk pll3_60m = { - .parent = &pll3_usb_otg, - .get_rate = pll3_60m_get_rate, -}; - -static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 val = readl_relaxed(CCSR); - - if (parent == &pll1_sys) { - val &= ~BM_CCSR_PLL1_SW_SEL; - val &= ~BM_CCSR_STEP_SEL; - } else if (parent == &osc_clk) { - val |= BM_CCSR_PLL1_SW_SEL; - val &= ~BM_CCSR_STEP_SEL; - } else if (parent == &pll2_pfd_400m) { - val |= BM_CCSR_PLL1_SW_SEL; - val |= BM_CCSR_STEP_SEL; - } else { - return -EINVAL; - } - - writel_relaxed(val, CCSR); - - return 0; -} - -static struct clk pll1_sw_clk = { - .parent = &pll1_sys, - .set_parent = pll1_sw_clk_set_parent, -}; - -static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf) -{ - u32 min_pred, temp_pred, old_err, err; - - if (div >= 512) { - *pred = 8; - *podf = 64; - } else if (div >= 8) { - min_pred = (div - 1) / 64 + 1; - old_err = 8; - for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) { - err = div % temp_pred; - if (err == 0) { - *pred = temp_pred; - break; - } - err = temp_pred - err; - if (err < old_err) { - old_err = err; - *pred = temp_pred; - } - } - *podf = (div + *pred - 1) / *pred; - } else if (div < 8) { - *pred = div; - *podf = 1; - } -} - -static int _clk_enable(struct clk *clk) -{ - u32 reg; - reg = readl_relaxed(clk->enable_reg); - reg |= 0x3 << clk->enable_shift; - writel_relaxed(reg, clk->enable_reg); - - return 0; -} - -static void _clk_disable(struct clk *clk) -{ - u32 reg; - reg = readl_relaxed(clk->enable_reg); - reg &= ~(0x3 << clk->enable_shift); - writel_relaxed(reg, clk->enable_reg); -} - -static int _clk_enable_1b(struct clk *clk) -{ - u32 reg; - reg = readl_relaxed(clk->enable_reg); - reg |= 0x1 << clk->enable_shift; - writel_relaxed(reg, clk->enable_reg); - - return 0; -} - -static void _clk_disable_1b(struct clk *clk) -{ - u32 reg; - reg = readl_relaxed(clk->enable_reg); - reg &= ~(0x1 << clk->enable_shift); - writel_relaxed(reg, clk->enable_reg); -} - -struct divider { - struct clk *clk; - void __iomem *reg; - u32 bp_pred; - u32 bm_pred; - u32 bp_podf; - u32 bm_podf; -}; - -#define DEF_CLK_DIV1(d, c, r, b) \ - static struct divider d = { \ - .clk = c, \ - .reg = r, \ - .bp_podf = BP_##r##_##b##_PODF, \ - .bm_podf = BM_##r##_##b##_PODF, \ - } - -DEF_CLK_DIV1(arm_div, &arm_clk, CACRR, ARM); -DEF_CLK_DIV1(ipg_div, &ipg_clk, CBCDR, IPG); -DEF_CLK_DIV1(ahb_div, &ahb_clk, CBCDR, AHB); -DEF_CLK_DIV1(axi_div, &axi_clk, CBCDR, AXI); -DEF_CLK_DIV1(mmdc_ch0_axi_div, &mmdc_ch0_axi_clk, CBCDR, MMDC_CH0_AXI); -DEF_CLK_DIV1(mmdc_ch1_axi_div, &mmdc_ch1_axi_clk, CBCDR, MMDC_CH1_AXI); -DEF_CLK_DIV1(periph_clk2_div, &periph_clk2_clk, CBCDR, PERIPH_CLK2); -DEF_CLK_DIV1(periph2_clk2_div, &periph2_clk2_clk, CBCDR, PERIPH2_CLK2); -DEF_CLK_DIV1(gpu2d_core_div, &gpu2d_core_clk, CBCMR, GPU2D_CORE); -DEF_CLK_DIV1(gpu3d_core_div, &gpu3d_core_clk, CBCMR, GPU3D_CORE); -DEF_CLK_DIV1(gpu3d_shader_div, &gpu3d_shader_clk, CBCMR, GPU3D_SHADER); -DEF_CLK_DIV1(ipg_perclk_div, &ipg_perclk, CSCMR1, PERCLK); -DEF_CLK_DIV1(emi_div, &emi_clk, CSCMR1, EMI); -DEF_CLK_DIV1(emi_slow_div, &emi_slow_clk, CSCMR1, EMI_SLOW); -DEF_CLK_DIV1(can_div, &can1_clk, CSCMR2, CAN); -DEF_CLK_DIV1(uart_div, &uart_clk, CSCDR1, UART); -DEF_CLK_DIV1(usdhc1_div, &usdhc1_clk, CSCDR1, USDHC1); -DEF_CLK_DIV1(usdhc2_div, &usdhc2_clk, CSCDR1, USDHC2); -DEF_CLK_DIV1(usdhc3_div, &usdhc3_clk, CSCDR1, USDHC3); -DEF_CLK_DIV1(usdhc4_div, &usdhc4_clk, CSCDR1, USDHC4); -DEF_CLK_DIV1(vpu_div, &vpu_clk, CSCDR1, VPU_AXI); -DEF_CLK_DIV1(hsi_tx_div, &hsi_tx_clk, CDCDR, HSI_TX); -DEF_CLK_DIV1(ipu1_di0_pre_div, &ipu1_di0_pre_clk, CHSCCDR, IPU1_DI0_PRE); -DEF_CLK_DIV1(ipu1_di1_pre_div, &ipu1_di1_pre_clk, CHSCCDR, IPU1_DI1_PRE); -DEF_CLK_DIV1(ipu2_di0_pre_div, &ipu2_di0_pre_clk, CSCDR2, IPU2_DI0_PRE); -DEF_CLK_DIV1(ipu2_di1_pre_div, &ipu2_di1_pre_clk, CSCDR2, IPU2_DI1_PRE); -DEF_CLK_DIV1(ipu1_div, &ipu1_clk, CSCDR3, IPU1_HSP); -DEF_CLK_DIV1(ipu2_div, &ipu2_clk, CSCDR3, IPU2_HSP); -DEF_CLK_DIV1(cko1_div, &cko1_clk, CCOSR, CKO1); - -#define DEF_CLK_DIV2(d, c, r, b) \ - static struct divider d = { \ - .clk = c, \ - .reg = r, \ - .bp_pred = BP_##r##_##b##_PRED, \ - .bm_pred = BM_##r##_##b##_PRED, \ - .bp_podf = BP_##r##_##b##_PODF, \ - .bm_podf = BM_##r##_##b##_PODF, \ - } - -DEF_CLK_DIV2(ssi1_div, &ssi1_clk, CS1CDR, SSI1); -DEF_CLK_DIV2(ssi3_div, &ssi3_clk, CS1CDR, SSI3); -DEF_CLK_DIV2(esai_div, &esai_clk, CS1CDR, ESAI); -DEF_CLK_DIV2(ssi2_div, &ssi2_clk, CS2CDR, SSI2); -DEF_CLK_DIV2(enfc_div, &enfc_clk, CS2CDR, ENFC); -DEF_CLK_DIV2(spdif_div, &spdif_clk, CDCDR, SPDIF); -DEF_CLK_DIV2(asrc_serial_div, &asrc_serial_clk, CDCDR, ASRC_SERIAL); - -static struct divider *dividers[] = { - &arm_div, - &ipg_div, - &ahb_div, - &axi_div, - &mmdc_ch0_axi_div, - &mmdc_ch1_axi_div, - &periph_clk2_div, - &periph2_clk2_div, - &gpu2d_core_div, - &gpu3d_core_div, - &gpu3d_shader_div, - &ipg_perclk_div, - &emi_div, - &emi_slow_div, - &can_div, - &uart_div, - &usdhc1_div, - &usdhc2_div, - &usdhc3_div, - &usdhc4_div, - &vpu_div, - &hsi_tx_div, - &ipu1_di0_pre_div, - &ipu1_di1_pre_div, - &ipu2_di0_pre_div, - &ipu2_di1_pre_div, - &ipu1_div, - &ipu2_div, - &ssi1_div, - &ssi3_div, - &esai_div, - &ssi2_div, - &enfc_div, - &spdif_div, - &asrc_serial_div, - &cko1_div, -}; - -static unsigned long ldb_di_clk_get_rate(struct clk *clk) -{ - u32 val = readl_relaxed(CSCMR2); - - val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV : - BM_CSCMR2_LDB_DI1_IPU_DIV; - if (val) - return clk_get_rate(clk->parent) / 7; - else - return clk_get_rate(clk->parent) * 2 / 7; -} - -static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - u32 val = readl_relaxed(CSCMR2); - - if (rate * 7 <= parent_rate + parent_rate / 20) - val |= BM_CSCMR2_LDB_DI0_IPU_DIV; - else - val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV; - - writel_relaxed(val, CSCMR2); - - return 0; -} - -static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - - if (rate * 7 <= parent_rate + parent_rate / 20) - return parent_rate / 7; - else - return 2 * parent_rate / 7; -} - -static unsigned long _clk_get_rate(struct clk *clk) -{ - struct divider *d; - u32 val, pred, podf; - int i, num; - - if (clk == &ldb_di0_clk || clk == &ldb_di1_clk) - return ldb_di_clk_get_rate(clk); - - num = ARRAY_SIZE(dividers); - for (i = 0; i < num; i++) - if (dividers[i]->clk == clk) { - d = dividers[i]; - break; - } - if (i == num) - return clk_get_rate(clk->parent); - - val = readl_relaxed(d->reg); - pred = ((val & d->bm_pred) >> d->bp_pred) + 1; - podf = ((val & d->bm_podf) >> d->bp_podf) + 1; - - return clk_get_rate(clk->parent) / (pred * podf); -} - -static int clk_busy_wait(struct clk *clk) -{ - int timeout = 0x100000; - u32 bm; - - if (clk == &axi_clk) - bm = BM_CDHIPR_AXI_PODF_BUSY; - else if (clk == &ahb_clk) - bm = BM_CDHIPR_AHB_PODF_BUSY; - else if (clk == &mmdc_ch0_axi_clk) - bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY; - else if (clk == &periph_clk) - bm = BM_CDHIPR_PERIPH_SEL_BUSY; - else if (clk == &arm_clk) - bm = BM_CDHIPR_ARM_PODF_BUSY; - else - return -EINVAL; - - while ((readl_relaxed(CDHIPR) & bm) && --timeout) - cpu_relax(); - - if (unlikely(!timeout)) - return -EBUSY; - - return 0; -} - -static int _clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - struct divider *d; - u32 val, div, max_div, pred = 0, podf; - int i, num; - - if (clk == &ldb_di0_clk || clk == &ldb_di1_clk) - return ldb_di_clk_set_rate(clk, rate); - - num = ARRAY_SIZE(dividers); - for (i = 0; i < num; i++) - if (dividers[i]->clk == clk) { - d = dividers[i]; - break; - } - if (i == num) - return -EINVAL; - - max_div = ((d->bm_pred >> d->bp_pred) + 1) * - ((d->bm_podf >> d->bp_podf) + 1); - - div = parent_rate / rate; - if (div == 0) - div++; - - if ((parent_rate / div != rate) || div > max_div) - return -EINVAL; - - if (d->bm_pred) { - calc_pred_podf_dividers(div, &pred, &podf); - } else { - pred = 1; - podf = div; - } - - val = readl_relaxed(d->reg); - val &= ~(d->bm_pred | d->bm_podf); - val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf; - writel_relaxed(val, d->reg); - - if (clk == &axi_clk || clk == &ahb_clk || - clk == &mmdc_ch0_axi_clk || clk == &arm_clk) - return clk_busy_wait(clk); - - return 0; -} - -static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - u32 div = parent_rate / rate; - u32 div_max, pred = 0, podf; - struct divider *d; - int i, num; - - if (clk == &ldb_di0_clk || clk == &ldb_di1_clk) - return ldb_di_clk_round_rate(clk, rate); - - num = ARRAY_SIZE(dividers); - for (i = 0; i < num; i++) - if (dividers[i]->clk == clk) { - d = dividers[i]; - break; - } - if (i == num) - return -EINVAL; - - if (div == 0 || parent_rate % rate) - div++; - - if (d->bm_pred) { - calc_pred_podf_dividers(div, &pred, &podf); - div = pred * podf; - } else { - div_max = (d->bm_podf >> d->bp_podf) + 1; - if (div > div_max) - div = div_max; - } - - return parent_rate / div; -} - -struct multiplexer { - struct clk *clk; - void __iomem *reg; - u32 bp; - u32 bm; - int pnum; - struct clk *parents[]; -}; - -static struct multiplexer axi_mux = { - .clk = &axi_clk, - .reg = CBCDR, - .bp = BP_CBCDR_AXI_SEL, - .bm = BM_CBCDR_AXI_SEL, - .parents = { - &periph_clk, - &pll2_pfd_400m, - &pll3_pfd_540m, - NULL - }, -}; - -static struct multiplexer periph_mux = { - .clk = &periph_clk, - .reg = CBCDR, - .bp = BP_CBCDR_PERIPH_CLK_SEL, - .bm = BM_CBCDR_PERIPH_CLK_SEL, - .parents = { - &periph_pre_clk, - &periph_clk2_clk, - NULL - }, -}; - -static struct multiplexer periph_pre_mux = { - .clk = &periph_pre_clk, - .reg = CBCMR, - .bp = BP_CBCMR_PRE_PERIPH_CLK_SEL, - .bm = BM_CBCMR_PRE_PERIPH_CLK_SEL, - .parents = { - &pll2_bus, - &pll2_pfd_400m, - &pll2_pfd_352m, - &pll2_200m, - NULL - }, -}; - -static struct multiplexer periph_clk2_mux = { - .clk = &periph_clk2_clk, - .reg = CBCMR, - .bp = BP_CBCMR_PERIPH_CLK2_SEL, - .bm = BM_CBCMR_PERIPH_CLK2_SEL, - .parents = { - &pll3_usb_otg, - &osc_clk, - NULL - }, -}; - -static struct multiplexer periph2_mux = { - .clk = &periph2_clk, - .reg = CBCDR, - .bp = BP_CBCDR_PERIPH2_CLK_SEL, - .bm = BM_CBCDR_PERIPH2_CLK_SEL, - .parents = { - &periph2_pre_clk, - &periph2_clk2_clk, - NULL - }, -}; - -static struct multiplexer periph2_pre_mux = { - .clk = &periph2_pre_clk, - .reg = CBCMR, - .bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL, - .bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL, - .parents = { - &pll2_bus, - &pll2_pfd_400m, - &pll2_pfd_352m, - &pll2_200m, - NULL - }, -}; - -static struct multiplexer periph2_clk2_mux = { - .clk = &periph2_clk2_clk, - .reg = CBCMR, - .bp = BP_CBCMR_PERIPH2_CLK2_SEL, - .bm = BM_CBCMR_PERIPH2_CLK2_SEL, - .parents = { - &pll3_usb_otg, - &osc_clk, - NULL - }, -}; - -static struct multiplexer gpu2d_axi_mux = { - .clk = &gpu2d_axi_clk, - .reg = CBCMR, - .bp = BP_CBCMR_GPU2D_AXI_SEL, - .bm = BM_CBCMR_GPU2D_AXI_SEL, - .parents = { - &axi_clk, - &ahb_clk, - NULL - }, -}; - -static struct multiplexer gpu3d_axi_mux = { - .clk = &gpu3d_axi_clk, - .reg = CBCMR, - .bp = BP_CBCMR_GPU3D_AXI_SEL, - .bm = BM_CBCMR_GPU3D_AXI_SEL, - .parents = { - &axi_clk, - &ahb_clk, - NULL - }, -}; - -static struct multiplexer gpu3d_core_mux = { - .clk = &gpu3d_core_clk, - .reg = CBCMR, - .bp = BP_CBCMR_GPU3D_CORE_SEL, - .bm = BM_CBCMR_GPU3D_CORE_SEL, - .parents = { - &mmdc_ch0_axi_clk, - &pll3_usb_otg, - &pll2_pfd_594m, - &pll2_pfd_400m, - NULL - }, -}; - -static struct multiplexer gpu3d_shader_mux = { - .clk = &gpu3d_shader_clk, - .reg = CBCMR, - .bp = BP_CBCMR_GPU3D_SHADER_SEL, - .bm = BM_CBCMR_GPU3D_SHADER_SEL, - .parents = { - &mmdc_ch0_axi_clk, - &pll3_usb_otg, - &pll2_pfd_594m, - &pll3_pfd_720m, - NULL - }, -}; - -static struct multiplexer pcie_axi_mux = { - .clk = &pcie_clk, - .reg = CBCMR, - .bp = BP_CBCMR_PCIE_AXI_SEL, - .bm = BM_CBCMR_PCIE_AXI_SEL, - .parents = { - &axi_clk, - &ahb_clk, - NULL - }, -}; - -static struct multiplexer vdo_axi_mux = { - .clk = &vdo_axi_clk, - .reg = CBCMR, - .bp = BP_CBCMR_VDO_AXI_SEL, - .bm = BM_CBCMR_VDO_AXI_SEL, - .parents = { - &axi_clk, - &ahb_clk, - NULL - }, -}; - -static struct multiplexer vpu_axi_mux = { - .clk = &vpu_clk, - .reg = CBCMR, - .bp = BP_CBCMR_VPU_AXI_SEL, - .bm = BM_CBCMR_VPU_AXI_SEL, - .parents = { - &axi_clk, - &pll2_pfd_400m, - &pll2_pfd_352m, - NULL - }, -}; - -static struct multiplexer gpu2d_core_mux = { - .clk = &gpu2d_core_clk, - .reg = CBCMR, - .bp = BP_CBCMR_GPU2D_CORE_SEL, - .bm = BM_CBCMR_GPU2D_CORE_SEL, - .parents = { - &axi_clk, - &pll3_usb_otg, - &pll2_pfd_352m, - &pll2_pfd_400m, - NULL - }, -}; - -#define DEF_SSI_MUX(id) \ - static struct multiplexer ssi##id##_mux = { \ - .clk = &ssi##id##_clk, \ - .reg = CSCMR1, \ - .bp = BP_CSCMR1_SSI##id##_SEL, \ - .bm = BM_CSCMR1_SSI##id##_SEL, \ - .parents = { \ - &pll3_pfd_508m, \ - &pll3_pfd_454m, \ - &pll4_audio, \ - NULL \ - }, \ - } - -DEF_SSI_MUX(1); -DEF_SSI_MUX(2); -DEF_SSI_MUX(3); - -#define DEF_USDHC_MUX(id) \ - static struct multiplexer usdhc##id##_mux = { \ - .clk = &usdhc##id##_clk, \ - .reg = CSCMR1, \ - .bp = BP_CSCMR1_USDHC##id##_SEL, \ - .bm = BM_CSCMR1_USDHC##id##_SEL, \ - .parents = { \ - &pll2_pfd_400m, \ - &pll2_pfd_352m, \ - NULL \ - }, \ - } - -DEF_USDHC_MUX(1); -DEF_USDHC_MUX(2); -DEF_USDHC_MUX(3); -DEF_USDHC_MUX(4); - -static struct multiplexer emi_mux = { - .clk = &emi_clk, - .reg = CSCMR1, - .bp = BP_CSCMR1_EMI_SEL, - .bm = BM_CSCMR1_EMI_SEL, - .parents = { - &axi_clk, - &pll3_usb_otg, - &pll2_pfd_400m, - &pll2_pfd_352m, - NULL - }, -}; - -static struct multiplexer emi_slow_mux = { - .clk = &emi_slow_clk, - .reg = CSCMR1, - .bp = BP_CSCMR1_EMI_SLOW_SEL, - .bm = BM_CSCMR1_EMI_SLOW_SEL, - .parents = { - &axi_clk, - &pll3_usb_otg, - &pll2_pfd_400m, - &pll2_pfd_352m, - NULL - }, -}; - -static struct multiplexer esai_mux = { - .clk = &esai_clk, - .reg = CSCMR2, - .bp = BP_CSCMR2_ESAI_SEL, - .bm = BM_CSCMR2_ESAI_SEL, - .parents = { - &pll4_audio, - &pll3_pfd_508m, - &pll3_pfd_454m, - &pll3_usb_otg, - NULL - }, -}; - -#define DEF_LDB_DI_MUX(id) \ - static struct multiplexer ldb_di##id##_mux = { \ - .clk = &ldb_di##id##_clk, \ - .reg = CS2CDR, \ - .bp = BP_CS2CDR_LDB_DI##id##_SEL, \ - .bm = BM_CS2CDR_LDB_DI##id##_SEL, \ - .parents = { \ - &pll5_video, \ - &pll2_pfd_352m, \ - &pll2_pfd_400m, \ - &pll3_pfd_540m, \ - &pll3_usb_otg, \ - NULL \ - }, \ - } - -DEF_LDB_DI_MUX(0); -DEF_LDB_DI_MUX(1); - -static struct multiplexer enfc_mux = { - .clk = &enfc_clk, - .reg = CS2CDR, - .bp = BP_CS2CDR_ENFC_SEL, - .bm = BM_CS2CDR_ENFC_SEL, - .parents = { - &pll2_pfd_352m, - &pll2_bus, - &pll3_usb_otg, - &pll2_pfd_400m, - NULL - }, -}; - -static struct multiplexer spdif_mux = { - .clk = &spdif_clk, - .reg = CDCDR, - .bp = BP_CDCDR_SPDIF_SEL, - .bm = BM_CDCDR_SPDIF_SEL, - .parents = { - &pll4_audio, - &pll3_pfd_508m, - &pll3_pfd_454m, - &pll3_usb_otg, - NULL - }, -}; - -static struct multiplexer asrc_serial_mux = { - .clk = &asrc_serial_clk, - .reg = CDCDR, - .bp = BP_CDCDR_ASRC_SERIAL_SEL, - .bm = BM_CDCDR_ASRC_SERIAL_SEL, - .parents = { - &pll4_audio, - &pll3_pfd_508m, - &pll3_pfd_454m, - &pll3_usb_otg, - NULL - }, -}; - -static struct multiplexer hsi_tx_mux = { - .clk = &hsi_tx_clk, - .reg = CDCDR, - .bp = BP_CDCDR_HSI_TX_SEL, - .bm = BM_CDCDR_HSI_TX_SEL, - .parents = { - &pll3_120m, - &pll2_pfd_400m, - NULL - }, -}; - -#define DEF_IPU_DI_PRE_MUX(r, i, d) \ - static struct multiplexer ipu##i##_di##d##_pre_mux = { \ - .clk = &ipu##i##_di##d##_pre_clk, \ - .reg = r, \ - .bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL, \ - .bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL, \ - .parents = { \ - &mmdc_ch0_axi_clk, \ - &pll3_usb_otg, \ - &pll5_video, \ - &pll2_pfd_352m, \ - &pll2_pfd_400m, \ - &pll3_pfd_540m, \ - NULL \ - }, \ - } - -DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0); -DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1); -DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0); -DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1); - -#define DEF_IPU_DI_MUX(r, i, d) \ - static struct multiplexer ipu##i##_di##d##_mux = { \ - .clk = &ipu##i##_di##d##_clk, \ - .reg = r, \ - .bp = BP_##r##_IPU##i##_DI##d##_SEL, \ - .bm = BM_##r##_IPU##i##_DI##d##_SEL, \ - .parents = { \ - &ipu##i##_di##d##_pre_clk, \ - &dummy_clk, \ - &dummy_clk, \ - &ldb_di0_clk, \ - &ldb_di1_clk, \ - NULL \ - }, \ - } - -DEF_IPU_DI_MUX(CHSCCDR, 1, 0); -DEF_IPU_DI_MUX(CHSCCDR, 1, 1); -DEF_IPU_DI_MUX(CSCDR2, 2, 0); -DEF_IPU_DI_MUX(CSCDR2, 2, 1); - -#define DEF_IPU_MUX(id) \ - static struct multiplexer ipu##id##_mux = { \ - .clk = &ipu##id##_clk, \ - .reg = CSCDR3, \ - .bp = BP_CSCDR3_IPU##id##_HSP_SEL, \ - .bm = BM_CSCDR3_IPU##id##_HSP_SEL, \ - .parents = { \ - &mmdc_ch0_axi_clk, \ - &pll2_pfd_400m, \ - &pll3_120m, \ - &pll3_pfd_540m, \ - NULL \ - }, \ - } - -DEF_IPU_MUX(1); -DEF_IPU_MUX(2); - -static struct multiplexer cko1_mux = { - .clk = &cko1_clk, - .reg = CCOSR, - .bp = BP_CCOSR_CKO1_SEL, - .bm = BM_CCOSR_CKO1_SEL, - .parents = { - &pll3_usb_otg, - &pll2_bus, - &pll1_sys, - &pll5_video, - &dummy_clk, - &axi_clk, - &enfc_clk, - &ipu1_di0_clk, - &ipu1_di1_clk, - &ipu2_di0_clk, - &ipu2_di1_clk, - &ahb_clk, - &ipg_clk, - &ipg_perclk, - &ckil_clk, - &pll4_audio, - NULL - }, -}; - -static struct multiplexer *multiplexers[] = { - &axi_mux, - &periph_mux, - &periph_pre_mux, - &periph_clk2_mux, - &periph2_mux, - &periph2_pre_mux, - &periph2_clk2_mux, - &gpu2d_axi_mux, - &gpu3d_axi_mux, - &gpu3d_core_mux, - &gpu3d_shader_mux, - &pcie_axi_mux, - &vdo_axi_mux, - &vpu_axi_mux, - &gpu2d_core_mux, - &ssi1_mux, - &ssi2_mux, - &ssi3_mux, - &usdhc1_mux, - &usdhc2_mux, - &usdhc3_mux, - &usdhc4_mux, - &emi_mux, - &emi_slow_mux, - &esai_mux, - &ldb_di0_mux, - &ldb_di1_mux, - &enfc_mux, - &spdif_mux, - &asrc_serial_mux, - &hsi_tx_mux, - &ipu1_di0_pre_mux, - &ipu1_di0_mux, - &ipu1_di1_pre_mux, - &ipu1_di1_mux, - &ipu2_di0_pre_mux, - &ipu2_di0_mux, - &ipu2_di1_pre_mux, - &ipu2_di1_mux, - &ipu1_mux, - &ipu2_mux, - &cko1_mux, -}; - -static int _clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct multiplexer *m; - int i, num; - u32 val; - - num = ARRAY_SIZE(multiplexers); - for (i = 0; i < num; i++) - if (multiplexers[i]->clk == clk) { - m = multiplexers[i]; - break; - } - if (i == num) - return -EINVAL; - - i = 0; - while (m->parents[i]) { - if (parent == m->parents[i]) - break; - i++; - } - if (!m->parents[i] || m->parents[i] == &dummy_clk) - return -EINVAL; - - val = readl_relaxed(m->reg); - val &= ~m->bm; - val |= i << m->bp; - writel_relaxed(val, m->reg); - - if (clk == &periph_clk) - return clk_busy_wait(clk); - - return 0; -} - -#define DEF_NG_CLK(name, p) \ - static struct clk name = { \ - .get_rate = _clk_get_rate, \ - .set_rate = _clk_set_rate, \ - .round_rate = _clk_round_rate, \ - .set_parent = _clk_set_parent, \ - .parent = p, \ - } - -DEF_NG_CLK(periph_clk2_clk, &osc_clk); -DEF_NG_CLK(periph_pre_clk, &pll2_bus); -DEF_NG_CLK(periph_clk, &periph_pre_clk); -DEF_NG_CLK(periph2_clk2_clk, &osc_clk); -DEF_NG_CLK(periph2_pre_clk, &pll2_bus); -DEF_NG_CLK(periph2_clk, &periph2_pre_clk); -DEF_NG_CLK(axi_clk, &periph_clk); -DEF_NG_CLK(emi_clk, &axi_clk); -DEF_NG_CLK(arm_clk, &pll1_sw_clk); -DEF_NG_CLK(ahb_clk, &periph_clk); -DEF_NG_CLK(ipg_clk, &ahb_clk); -DEF_NG_CLK(ipg_perclk, &ipg_clk); -DEF_NG_CLK(ipu1_di0_pre_clk, &pll3_pfd_540m); -DEF_NG_CLK(ipu1_di1_pre_clk, &pll3_pfd_540m); -DEF_NG_CLK(ipu2_di0_pre_clk, &pll3_pfd_540m); -DEF_NG_CLK(ipu2_di1_pre_clk, &pll3_pfd_540m); -DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg); - -#define DEF_CLK(name, er, es, p, s) \ - static struct clk name = { \ - .enable_reg = er, \ - .enable_shift = es, \ - .enable = _clk_enable, \ - .disable = _clk_disable, \ - .get_rate = _clk_get_rate, \ - .set_rate = _clk_set_rate, \ - .round_rate = _clk_round_rate, \ - .set_parent = _clk_set_parent, \ - .parent = p, \ - .secondary = s, \ - } - -#define DEF_CLK_1B(name, er, es, p, s) \ - static struct clk name = { \ - .enable_reg = er, \ - .enable_shift = es, \ - .enable = _clk_enable_1b, \ - .disable = _clk_disable_1b, \ - .get_rate = _clk_get_rate, \ - .set_rate = _clk_set_rate, \ - .round_rate = _clk_round_rate, \ - .set_parent = _clk_set_parent, \ - .parent = p, \ - .secondary = s, \ - } - -DEF_CLK(aips_tz1_clk, CCGR0, CG0, &ahb_clk, NULL); -DEF_CLK(aips_tz2_clk, CCGR0, CG1, &ahb_clk, NULL); -DEF_CLK(apbh_dma_clk, CCGR0, CG2, &ahb_clk, NULL); -DEF_CLK(asrc_clk, CCGR0, CG3, &pll4_audio, NULL); -DEF_CLK(can1_serial_clk, CCGR0, CG8, &pll3_usb_otg, NULL); -DEF_CLK(can1_clk, CCGR0, CG7, &pll3_usb_otg, &can1_serial_clk); -DEF_CLK(can2_serial_clk, CCGR0, CG10, &pll3_usb_otg, NULL); -DEF_CLK(can2_clk, CCGR0, CG9, &pll3_usb_otg, &can2_serial_clk); -DEF_CLK(ecspi1_clk, CCGR1, CG0, &pll3_60m, NULL); -DEF_CLK(ecspi2_clk, CCGR1, CG1, &pll3_60m, NULL); -DEF_CLK(ecspi3_clk, CCGR1, CG2, &pll3_60m, NULL); -DEF_CLK(ecspi4_clk, CCGR1, CG3, &pll3_60m, NULL); -DEF_CLK(ecspi5_clk, CCGR1, CG4, &pll3_60m, NULL); -DEF_CLK(enet_clk, CCGR1, CG5, &ipg_clk, NULL); -DEF_CLK(esai_clk, CCGR1, CG8, &pll3_usb_otg, NULL); -DEF_CLK(gpt_serial_clk, CCGR1, CG11, &ipg_perclk, NULL); -DEF_CLK(gpt_clk, CCGR1, CG10, &ipg_perclk, &gpt_serial_clk); -DEF_CLK(gpu2d_core_clk, CCGR1, CG12, &pll2_pfd_352m, &gpu2d_axi_clk); -DEF_CLK(gpu3d_core_clk, CCGR1, CG13, &pll2_pfd_594m, &gpu3d_axi_clk); -DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m, &gpu3d_axi_clk); -DEF_CLK(hdmi_iahb_clk, CCGR2, CG0, &ahb_clk, NULL); -DEF_CLK(hdmi_isfr_clk, CCGR2, CG2, &pll3_pfd_540m, &hdmi_iahb_clk); -DEF_CLK(i2c1_clk, CCGR2, CG3, &ipg_perclk, NULL); -DEF_CLK(i2c2_clk, CCGR2, CG4, &ipg_perclk, NULL); -DEF_CLK(i2c3_clk, CCGR2, CG5, &ipg_perclk, NULL); -DEF_CLK(iim_clk, CCGR2, CG6, &ipg_clk, NULL); -DEF_CLK(enfc_clk, CCGR2, CG7, &pll2_pfd_352m, NULL); -DEF_CLK(ipu1_clk, CCGR3, CG0, &mmdc_ch0_axi_clk, NULL); -DEF_CLK(ipu1_di0_clk, CCGR3, CG1, &ipu1_di0_pre_clk, NULL); -DEF_CLK(ipu1_di1_clk, CCGR3, CG2, &ipu1_di1_pre_clk, NULL); -DEF_CLK(ipu2_clk, CCGR3, CG3, &mmdc_ch0_axi_clk, NULL); -DEF_CLK(ipu2_di0_clk, CCGR3, CG4, &ipu2_di0_pre_clk, NULL); -DEF_CLK(ipu2_di1_clk, CCGR3, CG5, &ipu2_di1_pre_clk, NULL); -DEF_CLK(ldb_di0_clk, CCGR3, CG6, &pll3_pfd_540m, NULL); -DEF_CLK(ldb_di1_clk, CCGR3, CG7, &pll3_pfd_540m, NULL); -DEF_CLK(hsi_tx_clk, CCGR3, CG8, &pll2_pfd_400m, NULL); -DEF_CLK(mlb_clk, CCGR3, CG9, &pll6_mlb, NULL); -DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk, NULL); -DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk, &mmdc_ch0_ipg_clk); -DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk, NULL); -DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk, &mmdc_ch1_ipg_clk); -DEF_CLK(openvg_axi_clk, CCGR3, CG13, &axi_clk, NULL); -DEF_CLK(pwm1_clk, CCGR4, CG8, &ipg_perclk, NULL); -DEF_CLK(pwm2_clk, CCGR4, CG9, &ipg_perclk, NULL); -DEF_CLK(pwm3_clk, CCGR4, CG10, &ipg_perclk, NULL); -DEF_CLK(pwm4_clk, CCGR4, CG11, &ipg_perclk, NULL); -DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk, NULL); -DEF_CLK(gpmi_bch_clk, CCGR4, CG13, &usdhc4_clk, &gpmi_bch_apb_clk); -DEF_CLK(gpmi_apb_clk, CCGR4, CG15, &usdhc3_clk, &gpmi_bch_clk); -DEF_CLK(gpmi_io_clk, CCGR4, CG14, &enfc_clk, &gpmi_apb_clk); -DEF_CLK(sdma_clk, CCGR5, CG3, &ahb_clk, NULL); -DEF_CLK(spba_clk, CCGR5, CG6, &ipg_clk, NULL); -DEF_CLK(spdif_clk, CCGR5, CG7, &pll3_usb_otg, &spba_clk); -DEF_CLK(ssi1_clk, CCGR5, CG9, &pll3_pfd_508m, NULL); -DEF_CLK(ssi2_clk, CCGR5, CG10, &pll3_pfd_508m, NULL); -DEF_CLK(ssi3_clk, CCGR5, CG11, &pll3_pfd_508m, NULL); -DEF_CLK(uart_serial_clk, CCGR5, CG13, &pll3_usb_otg, NULL); -DEF_CLK(uart_clk, CCGR5, CG12, &pll3_80m, &uart_serial_clk); -DEF_CLK(usboh3_clk, CCGR6, CG0, &ipg_clk, NULL); -DEF_CLK(usdhc1_clk, CCGR6, CG1, &pll2_pfd_400m, NULL); -DEF_CLK(usdhc2_clk, CCGR6, CG2, &pll2_pfd_400m, NULL); -DEF_CLK(usdhc3_clk, CCGR6, CG3, &pll2_pfd_400m, NULL); -DEF_CLK(usdhc4_clk, CCGR6, CG4, &pll2_pfd_400m, NULL); -DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL); -DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL); -DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL); -DEF_CLK_1B(cko1_clk, CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL); - -static int pcie_clk_enable(struct clk *clk) -{ - u32 val; - - val = readl_relaxed(PLL8_ENET); - val |= BM_PLL_ENET_EN_PCIE; - writel_relaxed(val, PLL8_ENET); - - return _clk_enable(clk); -} - -static void pcie_clk_disable(struct clk *clk) -{ - u32 val; - - _clk_disable(clk); - - val = readl_relaxed(PLL8_ENET); - val &= BM_PLL_ENET_EN_PCIE; - writel_relaxed(val, PLL8_ENET); -} - -static struct clk pcie_clk = { - .enable_reg = CCGR4, - .enable_shift = CG0, - .enable = pcie_clk_enable, - .disable = pcie_clk_disable, - .set_parent = _clk_set_parent, - .parent = &axi_clk, - .secondary = &pll8_enet, -}; - -static int sata_clk_enable(struct clk *clk) -{ - u32 val; - - val = readl_relaxed(PLL8_ENET); - val |= BM_PLL_ENET_EN_SATA; - writel_relaxed(val, PLL8_ENET); - - return _clk_enable(clk); -} - -static void sata_clk_disable(struct clk *clk) -{ - u32 val; - - _clk_disable(clk); - - val = readl_relaxed(PLL8_ENET); - val &= BM_PLL_ENET_EN_SATA; - writel_relaxed(val, PLL8_ENET); -} - -static struct clk sata_clk = { - .enable_reg = CCGR5, - .enable_shift = CG2, - .enable = sata_clk_enable, - .disable = sata_clk_disable, - .parent = &ipg_clk, - .secondary = &pll8_enet, -}; - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - } - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK("2020000.uart", NULL, uart_clk), - _REGISTER_CLOCK("21e8000.uart", NULL, uart_clk), - _REGISTER_CLOCK("21ec000.uart", NULL, uart_clk), - _REGISTER_CLOCK("21f0000.uart", NULL, uart_clk), - _REGISTER_CLOCK("21f4000.uart", NULL, uart_clk), - _REGISTER_CLOCK("2188000.enet", NULL, enet_clk), - _REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk), - _REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk), - _REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk), - _REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk), - _REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk), - _REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk), - _REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk), - _REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk), - _REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk), - _REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk), - _REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk), - _REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk), - _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), - _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), - _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), - _REGISTER_CLOCK("smp_twd", NULL, twd_clk), - _REGISTER_CLOCK(NULL, "ckih", ckih_clk), - _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), - _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), - _REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk), - _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk), - _REGISTER_CLOCK(NULL, "can2_clk", can2_clk), - _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk), - _REGISTER_CLOCK(NULL, "iim_clk", iim_clk), - _REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk), - _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk), - _REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk), - _REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk), - _REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk), - _REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk), - _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk), - _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk), - _REGISTER_CLOCK(NULL, "sata_clk", sata_clk), - _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk), -}; - -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -{ - u32 val = readl_relaxed(CLPCR); - - val &= ~BM_CLPCR_LPM; - switch (mode) { - case WAIT_CLOCKED: - break; - case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; - break; - case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; - break; - case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; - break; - case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; - break; - default: - return -EINVAL; - } - writel_relaxed(val, CLPCR); - - return 0; -} - -static struct map_desc imx6q_clock_desc[] = { - imx_map_entry(MX6Q, CCM, MT_DEVICE), - imx_map_entry(MX6Q, ANATOP, MT_DEVICE), -}; - -void __init imx6q_clock_map_io(void) -{ - iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc)); -} - -int __init mx6q_clocks_init(void) -{ - struct device_node *np; - void __iomem *base; - int i, irq; - - /* retrieve the freqency of fixed clocks from device tree */ - for_each_compatible_node(np, NULL, "fixed-clock") { - u32 rate; - if (of_property_read_u32(np, "clock-frequency", &rate)) - continue; - - if (of_device_is_compatible(np, "fsl,imx-ckil")) - external_low_reference = rate; - else if (of_device_is_compatible(np, "fsl,imx-ckih1")) - external_high_reference = rate; - else if (of_device_is_compatible(np, "fsl,imx-osc")) - oscillator_reference = rate; - } - - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); - - /* only keep necessary clocks on */ - writel_relaxed(0x3 << CG0 | 0x3 << CG1 | 0x3 << CG2, CCGR0); - writel_relaxed(0x3 << CG8 | 0x3 << CG9 | 0x3 << CG10, CCGR2); - writel_relaxed(0x3 << CG10 | 0x3 << CG12, CCGR3); - writel_relaxed(0x3 << CG4 | 0x3 << CG6 | 0x3 << CG7, CCGR4); - writel_relaxed(0x3 << CG0, CCGR5); - writel_relaxed(0, CCGR6); - writel_relaxed(0, CCGR7); - - clk_enable(&uart_clk); - clk_enable(&mmdc_ch0_axi_clk); - - clk_set_rate(&pll4_audio, FREQ_650M); - clk_set_rate(&pll5_video, FREQ_650M); - clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk); - clk_set_parent(&ipu1_di0_pre_clk, &pll5_video); - clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m); - clk_set_rate(&gpu3d_shader_clk, FREQ_594M); - clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk); - clk_set_rate(&gpu3d_core_clk, FREQ_528M); - clk_set_parent(&asrc_serial_clk, &pll3_usb_otg); - clk_set_rate(&asrc_serial_clk, 1500000); - clk_set_rate(&enfc_clk, 11000000); - - /* - * Before pinctrl API is available, we have to rely on the pad - * configuration set up by bootloader. For usdhc example here, - * u-boot sets up the pads for 49.5 MHz case, and we have to lower - * the usdhc clock from 198 to 49.5 MHz to match the pad configuration. - * - * FIXME: This is should be removed after pinctrl API is available. - * At that time, usdhc driver can call pinctrl API to change pad - * configuration dynamically per different usdhc clock settings. - */ - clk_set_rate(&usdhc1_clk, 49500000); - clk_set_rate(&usdhc2_clk, 49500000); - clk_set_rate(&usdhc3_clk, 49500000); - clk_set_rate(&usdhc4_clk, 49500000); - - clk_set_parent(&cko1_clk, &ahb_clk); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(&gpt_clk, base, irq); - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/clock-mx51-mx53.c b/ANDROID_3.4.5/arch/arm/mach-imx/clock-mx51-mx53.c deleted file mode 100644 index 08470504..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/clock-mx51-mx53.c +++ /dev/null @@ -1,1675 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/mm.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/of.h> - -#include <asm/div64.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/clock.h> - -#include "crm-regs-imx5.h" - -/* External clock values passed-in by the board code */ -static unsigned long external_high_reference, external_low_reference; -static unsigned long oscillator_reference, ckih2_reference; - -static struct clk osc_clk; -static struct clk pll1_main_clk; -static struct clk pll1_sw_clk; -static struct clk pll2_sw_clk; -static struct clk pll3_sw_clk; -static struct clk mx53_pll4_sw_clk; -static struct clk lp_apm_clk; -static struct clk periph_apm_clk; -static struct clk ahb_clk; -static struct clk ipg_clk; -static struct clk usboh3_clk; -static struct clk emi_fast_clk; -static struct clk ipu_clk; -static struct clk mipi_hsc1_clk; -static struct clk esdhc1_clk; -static struct clk esdhc2_clk; -static struct clk esdhc3_mx53_clk; - -#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ - -/* calculate best pre and post dividers to get the required divider */ -static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post, - u32 max_pre, u32 max_post) -{ - if (div >= max_pre * max_post) { - *pre = max_pre; - *post = max_post; - } else if (div >= max_pre) { - u32 min_pre, temp_pre, old_err, err; - min_pre = DIV_ROUND_UP(div, max_post); - old_err = max_pre; - for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) { - err = div % temp_pre; - if (err == 0) { - *pre = temp_pre; - break; - } - err = temp_pre - err; - if (err < old_err) { - old_err = err; - *pre = temp_pre; - } - } - *post = DIV_ROUND_UP(div, *pre); - } else { - *pre = div; - *post = 1; - } -} - -static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) -{ - u32 reg = __raw_readl(clk->enable_reg); - - reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); - reg |= mode << clk->enable_shift; - - __raw_writel(reg, clk->enable_reg); -} - -static int _clk_ccgr_enable(struct clk *clk) -{ - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON); - return 0; -} - -static void _clk_ccgr_disable(struct clk *clk) -{ - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF); -} - -static int _clk_ccgr_enable_inrun(struct clk *clk) -{ - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); - return 0; -} - -static void _clk_ccgr_disable_inwait(struct clk *clk) -{ - _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); -} - -/* - * For the 4-to-1 muxed input clock - */ -static inline u32 _get_mux(struct clk *parent, struct clk *m0, - struct clk *m1, struct clk *m2, struct clk *m3) -{ - if (parent == m0) - return 0; - else if (parent == m1) - return 1; - else if (parent == m2) - return 2; - else if (parent == m3) - return 3; - else - BUG(); - - return -EINVAL; -} - -static inline void __iomem *_mx51_get_pll_base(struct clk *pll) -{ - if (pll == &pll1_main_clk) - return MX51_DPLL1_BASE; - else if (pll == &pll2_sw_clk) - return MX51_DPLL2_BASE; - else if (pll == &pll3_sw_clk) - return MX51_DPLL3_BASE; - else - BUG(); - - return NULL; -} - -static inline void __iomem *_mx53_get_pll_base(struct clk *pll) -{ - if (pll == &pll1_main_clk) - return MX53_DPLL1_BASE; - else if (pll == &pll2_sw_clk) - return MX53_DPLL2_BASE; - else if (pll == &pll3_sw_clk) - return MX53_DPLL3_BASE; - else if (pll == &mx53_pll4_sw_clk) - return MX53_DPLL4_BASE; - else - BUG(); - - return NULL; -} - -static inline void __iomem *_get_pll_base(struct clk *pll) -{ - if (cpu_is_mx51()) - return _mx51_get_pll_base(pll); - else - return _mx53_get_pll_base(pll); -} - -static unsigned long clk_pll_get_rate(struct clk *clk) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; - void __iomem *pllbase; - s64 temp; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - pllbase = _get_pll_base(clk); - - dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); - pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; - dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; - - if (pll_hfsm == 0) { - dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); - } else { - dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); - } - pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64) ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - void __iomem *pllbase; - - long mfi, pdf, mfn, mfd = 999999; - s64 temp64; - unsigned long quad_parent_rate; - unsigned long pll_hfsm, dp_ctl; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - pllbase = _get_pll_base(clk); - - quad_parent_rate = 4 * parent_rate; - pdf = mfi = -1; - while (++pdf < 16 && mfi < 5) - mfi = rate * (pdf+1) / quad_parent_rate; - if (mfi > 15) - return -EINVAL; - pdf--; - - temp64 = rate * (pdf+1) - quad_parent_rate * mfi; - do_div(temp64, quad_parent_rate/1000000); - mfn = (long)temp64; - - dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); - /* use dpdck0_2 */ - __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); - pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; - if (pll_hfsm == 0) { - reg = mfi << 4 | pdf; - __raw_writel(reg, pllbase + MXC_PLL_DP_OP); - __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); - __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); - } else { - reg = mfi << 4 | pdf; - __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); - __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); - __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); - } - - return 0; -} - -static int _clk_pll_enable(struct clk *clk) -{ - u32 reg; - void __iomem *pllbase; - int i = 0; - - pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); - if (reg & MXC_PLL_DP_CTL_UPEN) - return 0; - - reg |= MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); - - /* Wait for lock */ - do { - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); - if (reg & MXC_PLL_DP_CTL_LRF) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: pll locking failed\n"); - return -EINVAL; - } - - return 0; -} - -static void _clk_pll_disable(struct clk *clk) -{ - u32 reg; - void __iomem *pllbase; - - pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); -} - -static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, step; - - reg = __raw_readl(MXC_CCM_CCSR); - - /* When switching from pll_main_clk to a bypass clock, first select a - * multiplexed clock in 'step_sel', then shift the glitchless mux - * 'pll1_sw_clk_sel'. - * - * When switching back, do it in reverse order - */ - if (parent == &pll1_main_clk) { - /* Switch to pll1_main_clk */ - reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; - __raw_writel(reg, MXC_CCM_CCSR); - /* step_clk mux switched to lp_apm, to save power. */ - reg = __raw_readl(MXC_CCM_CCSR); - reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; - reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << - MXC_CCM_CCSR_STEP_SEL_OFFSET); - } else { - if (parent == &lp_apm_clk) { - step = MXC_CCM_CCSR_STEP_SEL_LP_APM; - } else if (parent == &pll2_sw_clk) { - step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; - } else if (parent == &pll3_sw_clk) { - step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; - } else - return -EINVAL; - - reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; - reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); - - __raw_writel(reg, MXC_CCM_CCSR); - /* Switch to step_clk */ - reg = __raw_readl(MXC_CCM_CCSR); - reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; - } - __raw_writel(reg, MXC_CCM_CCSR); - return 0; -} - -static unsigned long clk_pll1_sw_get_rate(struct clk *clk) -{ - u32 reg, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CCSR); - - if (clk->parent == &pll2_sw_clk) { - div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> - MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; - } else if (clk->parent == &pll3_sw_clk) { - div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> - MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; - } else - div = 1; - return parent_rate / div; -} - -static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CCSR); - - if (parent == &pll2_sw_clk) - reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; - else - reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; - - __raw_writel(reg, MXC_CCM_CCSR); - return 0; -} - -static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - if (parent == &osc_clk) - reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; - else - return -EINVAL; - - __raw_writel(reg, MXC_CCM_CCSR); - - return 0; -} - -static unsigned long clk_cpu_get_rate(struct clk *clk) -{ - u32 cacrr, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - cacrr = __raw_readl(MXC_CCM_CACRR); - div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; - - return parent_rate / div; -} - -static int clk_cpu_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, cpu_podf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - cpu_podf = parent_rate / rate - 1; - /* use post divider to change freq */ - reg = __raw_readl(MXC_CCM_CACRR); - reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; - reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CACRR); - - return 0; -} - -static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, mux; - int i = 0; - - mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); - - reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CBCMR); - - /* Wait for lock */ - do { - reg = __raw_readl(MXC_CCM_CDHIPR); - if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: Set parent for periph_apm clock failed\n"); - return -EINVAL; - } - - return 0; -} - -static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CBCDR); - - if (parent == &pll2_sw_clk) - reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; - else if (parent == &periph_apm_clk) - reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; - else - return -EINVAL; - - __raw_writel(reg, MXC_CCM_CBCDR); - - return 0; -} - -static struct clk main_bus_clk = { - .parent = &pll2_sw_clk, - .set_parent = _clk_main_bus_set_parent, -}; - -static unsigned long clk_ahb_get_rate(struct clk *clk) -{ - u32 reg, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; - return parent_rate / div; -} - - -static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div; - unsigned long parent_rate; - int i = 0; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div > 8 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; - reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CBCDR); - - /* Wait for lock */ - do { - reg = __raw_readl(MXC_CCM_CDHIPR); - if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: clk_ahb_set_rate failed\n"); - return -EINVAL; - } - - return 0; -} - -static unsigned long _clk_ahb_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div > 8) - div = 8; - else if (div == 0) - div++; - return parent_rate / div; -} - - -static int _clk_max_enable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_enable(clk); - - /* Handshake with MAX when LPM is entered. */ - reg = __raw_readl(MXC_CCM_CLPCR); - if (cpu_is_mx51()) - reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; - else if (cpu_is_mx53()) - reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); - - return 0; -} - -static void _clk_max_disable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_disable_inwait(clk); - - /* No Handshake with MAX when LPM is entered as its disabled. */ - reg = __raw_readl(MXC_CCM_CLPCR); - if (cpu_is_mx51()) - reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; - else if (cpu_is_mx53()) - reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); -} - -static unsigned long clk_ipg_get_rate(struct clk *clk) -{ - u32 reg, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> - MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; - - return parent_rate / div; -} - -static unsigned long clk_ipg_per_get_rate(struct clk *clk) -{ - u32 reg, prediv1, prediv2, podf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { - /* the main_bus_clk is the one before the DVFS engine */ - reg = __raw_readl(MXC_CCM_CBCDR); - prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> - MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; - prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> - MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; - podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> - MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; - return parent_rate / (prediv1 * prediv2 * podf); - } else if (clk->parent == &ipg_clk) - return parent_rate; - else - BUG(); -} - -static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CBCMR); - - reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; - reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; - - if (parent == &ipg_clk) - reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; - else if (parent == &lp_apm_clk) - reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; - else if (parent != &main_bus_clk) - return -EINVAL; - - __raw_writel(reg, MXC_CCM_CBCMR); - - return 0; -} - -#define clk_nfc_set_parent NULL - -static unsigned long clk_nfc_get_rate(struct clk *clk) -{ - unsigned long rate; - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> - MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; - rate = clk_get_rate(clk->parent) / div; - WARN_ON(rate == 0); - return rate; -} - -static unsigned long clk_nfc_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 div; - unsigned long parent_rate = clk_get_rate(clk->parent); - - if (!rate) - return -EINVAL; - - div = parent_rate / rate; - - if (parent_rate % rate) - div++; - - if (div > 8) - return -EINVAL; - - return parent_rate / div; - -} - -static int clk_nfc_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div; - - div = clk_get_rate(clk->parent) / rate; - if (div == 0) - div++; - if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8)) - return -EINVAL; - - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; - reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CBCDR); - - while (__raw_readl(MXC_CCM_CDHIPR) & - MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){ - } - - return 0; -} - -static unsigned long get_high_reference_clock_rate(struct clk *clk) -{ - return external_high_reference; -} - -static unsigned long get_low_reference_clock_rate(struct clk *clk) -{ - return external_low_reference; -} - -static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) -{ - return oscillator_reference; -} - -static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) -{ - return ckih2_reference; -} - -static unsigned long clk_emi_slow_get_rate(struct clk *clk) -{ - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> - MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; - - return clk_get_rate(clk->parent) / div; -} - -static unsigned long _clk_ddr_hf_get_rate(struct clk *clk) -{ - unsigned long rate; - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> - MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; - rate = clk_get_rate(clk->parent) / div; - - return rate; -} - -/* External high frequency clock */ -static struct clk ckih_clk = { - .get_rate = get_high_reference_clock_rate, -}; - -static struct clk ckih2_clk = { - .get_rate = get_ckih2_reference_clock_rate, -}; - -static struct clk osc_clk = { - .get_rate = get_oscillator_reference_clock_rate, -}; - -/* External low frequency (32kHz) clock */ -static struct clk ckil_clk = { - .get_rate = get_low_reference_clock_rate, -}; - -static struct clk pll1_main_clk = { - .parent = &osc_clk, - .get_rate = clk_pll_get_rate, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* Clock tree block diagram (WIP): - * CCM: Clock Controller Module - * - * PLL output -> | - * | CCM Switcher -> CCM_CLK_ROOT_GEN -> - * PLL bypass -> | - * - */ - -/* PLL1 SW supplies to ARM core */ -static struct clk pll1_sw_clk = { - .parent = &pll1_main_clk, - .set_parent = _clk_pll1_sw_set_parent, - .get_rate = clk_pll1_sw_get_rate, -}; - -/* PLL2 SW supplies to AXI/AHB/IP buses */ -static struct clk pll2_sw_clk = { - .parent = &osc_clk, - .get_rate = clk_pll_get_rate, - .set_rate = _clk_pll_set_rate, - .set_parent = _clk_pll2_sw_set_parent, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ -static struct clk pll3_sw_clk = { - .parent = &osc_clk, - .set_rate = _clk_pll_set_rate, - .get_rate = clk_pll_get_rate, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* PLL4 SW supplies to LVDS Display Bridge(LDB) */ -static struct clk mx53_pll4_sw_clk = { - .parent = &osc_clk, - .set_rate = _clk_pll_set_rate, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* Low-power Audio Playback Mode clock */ -static struct clk lp_apm_clk = { - .parent = &osc_clk, - .set_parent = _clk_lp_apm_set_parent, -}; - -static struct clk periph_apm_clk = { - .parent = &pll1_sw_clk, - .set_parent = _clk_periph_apm_set_parent, -}; - -static struct clk cpu_clk = { - .parent = &pll1_sw_clk, - .get_rate = clk_cpu_get_rate, - .set_rate = clk_cpu_set_rate, -}; - -static struct clk ahb_clk = { - .parent = &main_bus_clk, - .get_rate = clk_ahb_get_rate, - .set_rate = _clk_ahb_set_rate, - .round_rate = _clk_ahb_round_rate, -}; - -static struct clk iim_clk = { - .parent = &ipg_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, -}; - -/* Main IP interface clock for access to registers */ -static struct clk ipg_clk = { - .parent = &ahb_clk, - .get_rate = clk_ipg_get_rate, -}; - -static struct clk ipg_perclk = { - .parent = &lp_apm_clk, - .get_rate = clk_ipg_per_get_rate, - .set_parent = _clk_ipg_per_set_parent, -}; - -static struct clk ahb_max_clk = { - .parent = &ahb_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, -}; - -static struct clk aips_tz1_clk = { - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, -}; - -static struct clk aips_tz2_clk = { - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, -}; - -static struct clk gpc_dvfs_clk = { - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable, -}; - -static struct clk gpt_32k_clk = { - .id = 0, - .parent = &ckil_clk, -}; - -static struct clk dummy_clk = { - .id = 0, -}; - -static struct clk emi_slow_clk = { - .parent = &pll2_sw_clk, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, - .get_rate = clk_emi_slow_get_rate, -}; - -static int clk_ipu_enable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_enable(clk); - - /* Enable handshake with IPU when certain clock rates are changed */ - reg = __raw_readl(MXC_CCM_CCDR); - reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; - __raw_writel(reg, MXC_CCM_CCDR); - - /* Enable handshake with IPU when LPM is entered */ - reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); - - return 0; -} - -static void clk_ipu_disable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_disable(clk); - - /* Disable handshake with IPU whe dividers are changed */ - reg = __raw_readl(MXC_CCM_CCDR); - reg |= MXC_CCM_CCDR_IPU_HS_MASK; - __raw_writel(reg, MXC_CCM_CCDR); - - /* Disable handshake with IPU when LPM is entered */ - reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); -} - -static struct clk ahbmux1_clk = { - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, -}; - -static struct clk ipu_sec_clk = { - .parent = &emi_fast_clk, - .secondary = &ahbmux1_clk, -}; - -static struct clk ddr_hf_clk = { - .parent = &pll1_sw_clk, - .get_rate = _clk_ddr_hf_get_rate, -}; - -static struct clk ddr_clk = { - .parent = &ddr_hf_clk, -}; - -/* clock definitions for MIPI HSC unit which has been removed - * from documentation, but not from hardware - */ -static int _clk_hsc_enable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_enable(clk); - /* Handshake with IPU when certain clock rates are changed. */ - reg = __raw_readl(MXC_CCM_CCDR); - reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; - __raw_writel(reg, MXC_CCM_CCDR); - - reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); - - return 0; -} - -static void _clk_hsc_disable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_disable(clk); - /* No handshake with HSC as its not enabled. */ - reg = __raw_readl(MXC_CCM_CCDR); - reg |= MXC_CCM_CCDR_HSC_HS_MASK; - __raw_writel(reg, MXC_CCM_CCDR); - - reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); -} - -static struct clk mipi_hsp_clk = { - .parent = &ipu_clk, - .enable_reg = MXC_CCM_CCGR4, - .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, - .enable = _clk_hsc_enable, - .disable = _clk_hsc_disable, - .secondary = &mipi_hsc1_clk, -}; - -#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = pfx##_get_rate, \ - .set_rate = pfx##_set_rate, \ - .round_rate = pfx##_round_rate, \ - .set_parent = pfx##_set_parent, \ - .enable = _clk_ccgr_enable, \ - .disable = _clk_ccgr_disable, \ - .parent = p, \ - .secondary = s, \ - } - -#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = pfx##_get_rate, \ - .set_rate = pfx##_set_rate, \ - .set_parent = pfx##_set_parent, \ - .enable = _clk_max_enable, \ - .disable = _clk_max_disable, \ - .parent = p, \ - .secondary = s, \ - } - -#define CLK_GET_RATE(name, nr, bitsname) \ -static unsigned long clk_##name##_get_rate(struct clk *clk) \ -{ \ - u32 reg, pred, podf; \ - \ - reg = __raw_readl(MXC_CCM_CSCDR##nr); \ - pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \ - >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \ - podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \ - >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \ - \ - return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \ - (pred + 1) * (podf + 1)); \ -} - -#define CLK_SET_PARENT(name, nr, bitsname) \ -static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \ -{ \ - u32 reg, mux; \ - \ - mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \ - &pll3_sw_clk, &lp_apm_clk); \ - reg = __raw_readl(MXC_CCM_CSCMR##nr) & \ - ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \ - reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \ - __raw_writel(reg, MXC_CCM_CSCMR##nr); \ - \ - return 0; \ -} - -#define CLK_SET_RATE(name, nr, bitsname) \ -static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \ -{ \ - u32 reg, div, parent_rate; \ - u32 pre = 0, post = 0; \ - \ - parent_rate = clk_get_rate(clk->parent); \ - div = parent_rate / rate; \ - \ - if ((parent_rate / div) != rate) \ - return -EINVAL; \ - \ - __calc_pre_post_dividers(div, &pre, &post, \ - (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \ - MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \ - (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \ - MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\ - \ - /* Set sdhc1 clock divider */ \ - reg = __raw_readl(MXC_CCM_CSCDR##nr) & \ - ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \ - | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \ - reg |= (post - 1) << \ - MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \ - reg |= (pre - 1) << \ - MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \ - __raw_writel(reg, MXC_CCM_CSCDR##nr); \ - \ - return 0; \ -} - -/* UART */ -CLK_GET_RATE(uart, 1, UART) -CLK_SET_PARENT(uart, 1, UART) - -static struct clk uart_root_clk = { - .parent = &pll2_sw_clk, - .get_rate = clk_uart_get_rate, - .set_parent = clk_uart_set_parent, -}; - -/* USBOH3 */ -CLK_GET_RATE(usboh3, 1, USBOH3) -CLK_SET_PARENT(usboh3, 1, USBOH3) - -static struct clk usboh3_clk = { - .parent = &pll2_sw_clk, - .get_rate = clk_usboh3_get_rate, - .set_parent = clk_usboh3_set_parent, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable, - .enable_reg = MXC_CCM_CCGR2, - .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, -}; - -static struct clk usb_ahb_clk = { - .parent = &ipg_clk, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable, - .enable_reg = MXC_CCM_CCGR2, - .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, -}; - -static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; - - if (parent == &pll3_sw_clk) - reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET; - - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -static struct clk usb_phy1_clk = { - .parent = &pll3_sw_clk, - .set_parent = clk_usb_phy1_set_parent, - .enable = _clk_ccgr_enable, - .enable_reg = MXC_CCM_CCGR2, - .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, - .disable = _clk_ccgr_disable, -}; - -/* eCSPI */ -CLK_GET_RATE(ecspi, 2, CSPI) -CLK_SET_PARENT(ecspi, 1, CSPI) - -static struct clk ecspi_main_clk = { - .parent = &pll3_sw_clk, - .get_rate = clk_ecspi_get_rate, - .set_parent = clk_ecspi_set_parent, -}; - -/* eSDHC */ -CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1) -CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) -CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) - -/* mx51 specific */ -CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) -CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) -CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) - -static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &esdhc1_clk) - reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; - else if (parent == &esdhc2_clk) - reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; - else - return -EINVAL; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &esdhc1_clk) - reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; - else if (parent == &esdhc2_clk) - reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; - else - return -EINVAL; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -/* mx53 specific */ -static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &esdhc1_clk) - reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL; - else if (parent == &esdhc3_mx53_clk) - reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL; - else - return -EINVAL; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) -CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53) -CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) - -static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &esdhc1_clk) - reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; - else if (parent == &esdhc3_mx53_clk) - reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; - else - return -EINVAL; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .set_rate = sr, \ - .enable = e, \ - .disable = d, \ - .parent = p, \ - .secondary = s, \ - } - -#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ - DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s) - -/* Shared peripheral bus arbiter */ -DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, - NULL, NULL, &ipg_clk, NULL); - -/* UART */ -DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, - NULL, NULL, &ipg_clk, &aips_tz1_clk); -DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, - NULL, NULL, &ipg_clk, &aips_tz1_clk); -DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, - NULL, NULL, &ipg_clk, &spba_clk); -DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, &ipg_clk, &spba_clk); -DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &ipg_clk, &spba_clk); -DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, &uart_root_clk, &uart1_ipg_clk); -DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &uart_root_clk, &uart2_ipg_clk); -DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &uart_root_clk, &uart3_ipg_clk); -DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET, - NULL, NULL, &uart_root_clk, &uart4_ipg_clk); -DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET, - NULL, NULL, &uart_root_clk, &uart5_ipg_clk); - -/* GPT */ -DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_clk, &gpt_ipg_clk); - -DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &ipg_perclk, NULL); -DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &ipg_perclk, NULL); - -/* I2C */ -DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_perclk, NULL); -DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ipg_perclk, NULL); -DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, - NULL, NULL, &ipg_perclk, NULL); - -/* FEC */ -DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, - NULL, NULL, &ipg_clk, NULL); - -/* NFC */ -DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, - clk_nfc, &emi_slow_clk, NULL); - -/* SSI */ -DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk); -DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, - NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); -DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET, - NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk); - -/* eCSPI */ -DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, - &ipg_clk, &spba_clk); -DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk); -DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET, - NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, - &ipg_clk, &aips_tz2_clk); -DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET, - NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk); - -/* CSPI */ -DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_clk, &aips_tz2_clk); -DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET, - NULL, NULL, &ipg_clk, &cspi_ipg_clk); - -/* SDMA */ -DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, - NULL, NULL, &ahb_clk, NULL); - -/* eSDHC */ -DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); -DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, - clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); -DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); -DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); -DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); - -/* mx51 specific */ -DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, - clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); - -static struct clk esdhc3_clk = { - .id = 2, - .parent = &esdhc1_clk, - .set_parent = clk_esdhc3_set_parent, - .enable_reg = MXC_CCM_CCGR3, - .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, - .secondary = &esdhc3_ipg_clk, -}; -static struct clk esdhc4_clk = { - .id = 3, - .parent = &esdhc1_clk, - .set_parent = clk_esdhc4_set_parent, - .enable_reg = MXC_CCM_CCGR3, - .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, - .secondary = &esdhc4_ipg_clk, -}; - -/* mx53 specific */ -static struct clk esdhc2_mx53_clk = { - .id = 2, - .parent = &esdhc1_clk, - .set_parent = clk_esdhc2_mx53_set_parent, - .enable_reg = MXC_CCM_CCGR3, - .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, - .secondary = &esdhc3_ipg_clk, -}; - -DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, - clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk); - -static struct clk esdhc4_mx53_clk = { - .id = 3, - .parent = &esdhc1_clk, - .set_parent = clk_esdhc4_mx53_set_parent, - .enable_reg = MXC_CCM_CCGR3, - .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, - .secondary = &esdhc4_ipg_clk, -}; - -static struct clk sata_clk = { - .parent = &ipg_clk, - .enable = _clk_max_enable, - .enable_reg = MXC_CCM_CCGR4, - .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, - .disable = _clk_max_disable, -}; - -static struct clk ahci_phy_clk = { - .parent = &usb_phy1_clk, -}; - -static struct clk ahci_dma_clk = { - .parent = &ahb_clk, -}; - -DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); -DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); -DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); - -/* IPU */ -DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET, - NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk); - -DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET, - NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait, - &ddr_clk, NULL); - -DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, - NULL, NULL, &pll3_sw_clk, NULL); -DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &pll3_sw_clk, NULL); - -/* PATA */ -DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET, - NULL, NULL, &ipg_clk, &spba_clk); - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup mx51_lookups[] = { - /* i.mx51 has the i.mx21 type uart */ - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK(NULL, "gpt", gpt_clk) - /* i.mx51 has the i.mx27 type fec */ - _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk) - _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk) - _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) - _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk) - _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) - _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) - _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) - /* i.mx51 has the i.mx35 type sdma */ - _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) - _REGISTER_CLOCK(NULL, "ckih", ckih_clk) - _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) - _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk) - _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) - _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) - /* i.mx51 has the i.mx35 type cspi */ - _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk) - _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) - _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) - _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) - _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) - _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk) - _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) - _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) - _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) - _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) - _REGISTER_CLOCK("pata_imx", NULL, pata_clk) -}; - -static struct clk_lookup mx53_lookups[] = { - /* i.mx53 has the i.mx21 type uart */ - _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk) - _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk) - _REGISTER_CLOCK(NULL, "gpt", gpt_clk) - /* i.mx53 has the i.mx25 type fec */ - _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk) - _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) - _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) - _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) - _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk) - /* i.mx53 has the i.mx51 type ecspi */ - _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) - _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) - /* i.mx53 has the i.mx25 type cspi */ - _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk) - _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk) - _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) - _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) - /* i.mx53 has the i.mx35 type sdma */ - _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) - _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) - _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) - _REGISTER_CLOCK("pata_imx", NULL, pata_clk) - _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk) - _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk) - _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk) -}; - -static void clk_tree_init(void) -{ - u32 reg; - - ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); - - /* - * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at - * 8MHz, its derived from lp_apm. - * - * FIXME: Verify if true for all boards - */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; - reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; - reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; - reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); -} - -int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2) -{ - int i; - - external_low_reference = ckil; - external_high_reference = ckih1; - ckih2_reference = ckih2; - oscillator_reference = osc; - - for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) - clkdev_add(&mx51_lookups[i]); - - clk_tree_init(); - - clk_enable(&cpu_clk); - clk_enable(&main_bus_clk); - - clk_enable(&iim_clk); - imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable(&iim_clk); - - /* move usb_phy_clk to 24MHz */ - clk_set_parent(&usb_phy1_clk, &osc_clk); - - /* set the usboh3_clk parent to pll2_sw_clk */ - clk_set_parent(&usboh3_clk, &pll2_sw_clk); - - /* Set SDHC parents to be PLL2 */ - clk_set_parent(&esdhc1_clk, &pll2_sw_clk); - clk_set_parent(&esdhc2_clk, &pll2_sw_clk); - - /* set SDHC root clock as 166.25MHZ*/ - clk_set_rate(&esdhc1_clk, 166250000); - clk_set_rate(&esdhc2_clk, 166250000); - - /* System timer */ - mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), - MX51_INT_GPT); - return 0; -} - -int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2) -{ - int i; - - external_low_reference = ckil; - external_high_reference = ckih1; - ckih2_reference = ckih2; - oscillator_reference = osc; - - for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) - clkdev_add(&mx53_lookups[i]); - - clk_tree_init(); - - clk_set_parent(&uart_root_clk, &pll3_sw_clk); - clk_enable(&cpu_clk); - clk_enable(&main_bus_clk); - - clk_enable(&iim_clk); - imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable(&iim_clk); - - /* Set SDHC parents to be PLL2 */ - clk_set_parent(&esdhc1_clk, &pll2_sw_clk); - clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk); - - /* set SDHC root clock as 200MHZ*/ - clk_set_rate(&esdhc1_clk, 200000000); - clk_set_rate(&esdhc3_mx53_clk, 200000000); - - /* System timer */ - mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), - MX53_INT_GPT); - return 0; -} - -#ifdef CONFIG_OF -static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc, - unsigned long *ckih1, unsigned long *ckih2) -{ - struct device_node *np; - - /* retrieve the freqency of fixed clocks from device tree */ - for_each_compatible_node(np, NULL, "fixed-clock") { - u32 rate; - if (of_property_read_u32(np, "clock-frequency", &rate)) - continue; - - if (of_device_is_compatible(np, "fsl,imx-ckil")) - *ckil = rate; - else if (of_device_is_compatible(np, "fsl,imx-osc")) - *osc = rate; - else if (of_device_is_compatible(np, "fsl,imx-ckih1")) - *ckih1 = rate; - else if (of_device_is_compatible(np, "fsl,imx-ckih2")) - *ckih2 = rate; - } -} - -int __init mx51_clocks_init_dt(void) -{ - unsigned long ckil, osc, ckih1, ckih2; - - clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2); - return mx51_clocks_init(ckil, osc, ckih1, ckih2); -} - -int __init mx53_clocks_init_dt(void) -{ - unsigned long ckil, osc, ckih1, ckih2; - - clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2); - return mx53_clocks_init(ckil, osc, ckih1, ckih2); -} -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx25.c b/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx25.c deleted file mode 100644 index 6914bcbf..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx25.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * MX25 CPU type detection - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include <linux/module.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/iim.h> - -static int mx25_cpu_rev = -1; - -static int mx25_read_cpu_rev(void) -{ - u32 rev; - - rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); - switch (rev) { - case 0x00: - return IMX_CHIP_REVISION_1_0; - case 0x01: - return IMX_CHIP_REVISION_1_1; - default: - return IMX_CHIP_REVISION_UNKNOWN; - } -} - -int mx25_revision(void) -{ - if (mx25_cpu_rev == -1) - mx25_cpu_rev = mx25_read_cpu_rev(); - - return mx25_cpu_rev; -} -EXPORT_SYMBOL(mx25_revision); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx27.c b/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx27.c deleted file mode 100644 index ff38e150..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx27.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -/* - * i.MX27 specific CPU detection code - */ - -#include <linux/io.h> -#include <linux/module.h> - -#include <mach/hardware.h> - -static int mx27_cpu_rev = -1; -static int mx27_cpu_partnumber; - -#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ - -static int mx27_read_cpu_rev(void) -{ - u32 val; - /* - * now we have access to the IO registers. As we need - * the silicon revision very early we read it here to - * avoid any further hooks - */ - val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR - + SYS_CHIP_ID)); - - mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); - - switch (val >> 28) { - case 0: - return IMX_CHIP_REVISION_1_0; - case 1: - return IMX_CHIP_REVISION_2_0; - case 2: - return IMX_CHIP_REVISION_2_1; - default: - return IMX_CHIP_REVISION_UNKNOWN; - } -} - -/* - * Returns: - * the silicon revision of the cpu - * -EINVAL - not a mx27 - */ -int mx27_revision(void) -{ - if (mx27_cpu_rev == -1) - mx27_cpu_rev = mx27_read_cpu_rev(); - - if (mx27_cpu_partnumber != 0x8821) - return -EINVAL; - - return mx27_cpu_rev; -} -EXPORT_SYMBOL(mx27_revision); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx31.c b/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx31.c deleted file mode 100644 index 3f2345f0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx31.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * MX31 CPU type detection - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <linux/module.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/iim.h> -#include <mach/common.h> - -static int mx31_cpu_rev = -1; - -static struct { - u8 srev; - const char *name; - unsigned int rev; -} mx31_cpu_type[] = { - { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 }, - { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, - { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, - { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, - { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, - { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 }, - { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 }, - { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 }, - { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 }, -}; - -static int mx31_read_cpu_rev(void) -{ - u32 i, srev; - - /* read SREV register from IIM module */ - srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); - srev &= 0xff; - - for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) - if (srev == mx31_cpu_type[i].srev) { - imx_print_silicon_rev(mx31_cpu_type[i].name, - mx31_cpu_type[i].rev); - return mx31_cpu_type[i].rev; - } - - imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN); - return IMX_CHIP_REVISION_UNKNOWN; -} - -int mx31_revision(void) -{ - if (mx31_cpu_rev == -1) - mx31_cpu_rev = mx31_read_cpu_rev(); - - return mx31_cpu_rev; -} -EXPORT_SYMBOL(mx31_revision); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx35.c b/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx35.c deleted file mode 100644 index 846e46eb..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx35.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * MX35 CPU type detection - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include <linux/module.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/iim.h> - -static int mx35_cpu_rev = -1; - -static int mx35_read_cpu_rev(void) -{ - u32 rev; - - rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); - switch (rev) { - case 0x00: - return IMX_CHIP_REVISION_1_0; - case 0x10: - return IMX_CHIP_REVISION_2_0; - case 0x11: - return IMX_CHIP_REVISION_2_1; - default: - return IMX_CHIP_REVISION_UNKNOWN; - } -} - -int mx35_revision(void) -{ - if (mx35_cpu_rev == -1) - mx35_cpu_rev = mx35_read_cpu_rev(); - - return mx35_cpu_rev; -} -EXPORT_SYMBOL(mx35_revision); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx5.c b/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx5.c deleted file mode 100644 index aa15c517..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu-imx5.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * This file contains the CPU initialization code. - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <mach/hardware.h> -#include <linux/io.h> - -static int mx5_cpu_rev = -1; - -#define IIM_SREV 0x24 -#define MX50_HW_ADADIG_DIGPROG 0xB0 - -static int get_mx51_srev(void) -{ - void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); - u32 rev = readl(iim_base + IIM_SREV) & 0xff; - - switch (rev) { - case 0x0: - return IMX_CHIP_REVISION_2_0; - case 0x10: - return IMX_CHIP_REVISION_3_0; - default: - return IMX_CHIP_REVISION_UNKNOWN; - } -} - -/* - * Returns: - * the silicon revision of the cpu - * -EINVAL - not a mx51 - */ -int mx51_revision(void) -{ - if (!cpu_is_mx51()) - return -EINVAL; - - if (mx5_cpu_rev == -1) - mx5_cpu_rev = get_mx51_srev(); - - return mx5_cpu_rev; -} -EXPORT_SYMBOL(mx51_revision); - -#ifdef CONFIG_NEON - -/* - * All versions of the silicon before Rev. 3 have broken NEON implementations. - * Dependent on link order - so the assumption is that vfp_init is called - * before us. - */ -static int __init mx51_neon_fixup(void) -{ - if (!cpu_is_mx51()) - return 0; - - if (mx51_revision() < IMX_CHIP_REVISION_3_0 && - (elf_hwcap & HWCAP_NEON)) { - elf_hwcap &= ~HWCAP_NEON; - pr_info("Turning off NEON support, detected broken NEON implementation\n"); - } - return 0; -} - -late_initcall(mx51_neon_fixup); -#endif - -static int get_mx53_srev(void) -{ - void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); - u32 rev = readl(iim_base + IIM_SREV) & 0xff; - - switch (rev) { - case 0x0: - return IMX_CHIP_REVISION_1_0; - case 0x2: - return IMX_CHIP_REVISION_2_0; - case 0x3: - return IMX_CHIP_REVISION_2_1; - default: - return IMX_CHIP_REVISION_UNKNOWN; - } -} - -/* - * Returns: - * the silicon revision of the cpu - * -EINVAL - not a mx53 - */ -int mx53_revision(void) -{ - if (!cpu_is_mx53()) - return -EINVAL; - - if (mx5_cpu_rev == -1) - mx5_cpu_rev = get_mx53_srev(); - - return mx5_cpu_rev; -} -EXPORT_SYMBOL(mx53_revision); - -static int get_mx50_srev(void) -{ - void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K); - u32 rev; - - if (!anatop) { - mx5_cpu_rev = -EINVAL; - return 0; - } - - rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); - rev &= 0xff; - - iounmap(anatop); - if (rev == 0x0) - return IMX_CHIP_REVISION_1_0; - else if (rev == 0x1) - return IMX_CHIP_REVISION_1_1; - return 0; -} - -/* - * Returns: - * the silicon revision of the cpu - * -EINVAL - not a mx50 - */ -int mx50_revision(void) -{ - if (!cpu_is_mx50()) - return -EINVAL; - - if (mx5_cpu_rev == -1) - mx5_cpu_rev = get_mx50_srev(); - - return mx5_cpu_rev; -} -EXPORT_SYMBOL(mx50_revision); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu_op-mx51.c b/ANDROID_3.4.5/arch/arm/mach-imx/cpu_op-mx51.c deleted file mode 100644 index 7b92cd6d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu_op-mx51.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/bug.h> -#include <linux/types.h> -#include <mach/hardware.h> -#include <linux/kernel.h> - -static struct cpu_op mx51_cpu_op[] = { - { - .cpu_rate = 160000000,}, - { - .cpu_rate = 800000000,}, -}; - -struct cpu_op *mx51_get_cpu_op(int *op) -{ - *op = ARRAY_SIZE(mx51_cpu_op); - return mx51_cpu_op; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/cpu_op-mx51.h b/ANDROID_3.4.5/arch/arm/mach-imx/cpu_op-mx51.h deleted file mode 100644 index 97477fec..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/cpu_op-mx51.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -extern struct cpu_op *mx51_get_cpu_op(int *op); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/crm-regs-imx5.h b/ANDROID_3.4.5/arch/arm/mach-imx/crm-regs-imx5.h deleted file mode 100644 index 5e3f1f0f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/crm-regs-imx5.h +++ /dev/null @@ -1,600 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) -#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) -#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) -#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) -#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) -#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) - -/*MX53*/ -#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) -#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) -#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) -#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) -#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR) - -/* PLL Register Offsets */ -#define MXC_PLL_DP_CTL 0x00 -#define MXC_PLL_DP_CONFIG 0x04 -#define MXC_PLL_DP_OP 0x08 -#define MXC_PLL_DP_MFD 0x0C -#define MXC_PLL_DP_MFN 0x10 -#define MXC_PLL_DP_MFNMINUS 0x14 -#define MXC_PLL_DP_MFNPLUS 0x18 -#define MXC_PLL_DP_HFS_OP 0x1C -#define MXC_PLL_DP_HFS_MFD 0x20 -#define MXC_PLL_DP_HFS_MFN 0x24 -#define MXC_PLL_DP_MFN_TOGC 0x28 -#define MXC_PLL_DP_DESTAT 0x2c - -/* PLL Register Bit definitions */ -#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 -#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 -#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 -#define MXC_PLL_DP_CTL_ADE 0x800 -#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 -#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) -#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 -#define MXC_PLL_DP_CTL_HFSM 0x80 -#define MXC_PLL_DP_CTL_PRE 0x40 -#define MXC_PLL_DP_CTL_UPEN 0x20 -#define MXC_PLL_DP_CTL_RST 0x10 -#define MXC_PLL_DP_CTL_RCP 0x8 -#define MXC_PLL_DP_CTL_PLM 0x4 -#define MXC_PLL_DP_CTL_BRM0 0x2 -#define MXC_PLL_DP_CTL_LRF 0x1 - -#define MXC_PLL_DP_CONFIG_BIST 0x8 -#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 -#define MXC_PLL_DP_CONFIG_AREN 0x2 -#define MXC_PLL_DP_CONFIG_LDREQ 0x1 - -#define MXC_PLL_DP_OP_MFI_OFFSET 4 -#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) -#define MXC_PLL_DP_OP_PDF_OFFSET 0 -#define MXC_PLL_DP_OP_PDF_MASK 0xF - -#define MXC_PLL_DP_MFD_OFFSET 0 -#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF - -#define MXC_PLL_DP_MFN_OFFSET 0x0 -#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF - -#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) -#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) -#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 -#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF - -#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) -#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF - -/* Register addresses of CCM*/ -#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) -#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) -#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) -#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) -#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) -#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) -#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) -#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) -#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) -#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) -#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) -#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) -#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) -#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) -#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) -#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) -#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) -#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) -#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) -#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) -#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) -#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) -#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) -#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) -#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) -#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) -#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) -#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) -#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) -#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) -#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) -#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) -#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) - -#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_COSC_EN (1 << 12) -#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) -#define MXC_CCM_CCR_CAMP2_EN (1 << 10) -#define MXC_CCM_CCR_CAMP1_EN (1 << 9) -#define MXC_CCM_CCR_FPM_EN (1 << 8) -#define MXC_CCM_CCR_OSCNT_OFFSET (0) -#define MXC_CCM_CCR_OSCNT_MASK (0xFF) - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) -#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) -#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) - -/* Define the bits in register CSR */ -#define MXC_CCM_CSR_COSR_READY (1 << 5) -#define MXC_CCM_CSR_LVS_VALUE (1 << 4) -#define MXC_CCM_CSR_CAMP2_READY (1 << 3) -#define MXC_CCM_CSR_CAMP1_READY (1 << 2) -#define MXC_CCM_CSR_FPM_READY (1 << 1) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) - -/* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) -#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) -#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) -#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 -#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ -#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 -#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 -#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) -#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) -#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) -#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, - 1: step_clk */ -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) -#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) -#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) -#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) -#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) -#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) -#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) -#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) -#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) - -/* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) -#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) -#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) -#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) -#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) -#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) -#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) -#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) -#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) -#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) -#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) -#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) -#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) -#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) -#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) - -/* Define the bits in register CS1CDR and CS2CDR */ -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) - -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CDCDR */ -#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) -#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) -#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) -#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) -#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) -#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) - -/* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) -#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) -#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) -#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) -#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) - -/* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CSCDR4 */ -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CDHIPR */ -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) -#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) -#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) -#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) -#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) -#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) - -/* Define the bits in register CDCR */ -#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) -#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) -#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) -#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) -#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) -#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) -#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) -#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) -#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) -#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MXC_CCM_CLPCR_LPM_OFFSET (0) -#define MXC_CCM_CLPCR_LPM_MASK (0x3) - -/* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) -#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) -#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) -#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) -#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) -#define MXC_CCM_CISR_COSC_READY (0x1 << 6) -#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) -#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) -#define MXC_CCM_CISR_FPM_READY (0x1 << 3) -#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) -#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) -#define MXC_CCM_CISR_LRF_PLL1 (0x1) - -/* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) -#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) -#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) -#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) -#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) -#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) -#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) -#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) -#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) -#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) -#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) - -/* Define the bits in register CCOSR */ -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) -#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) -#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) -#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) -#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) - -/* Define the bits in registers CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) -#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) -#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) -#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) - -/* Define the bits in registers CCGRx */ -#define MXC_CCM_CCGRx_CG_MASK 0x3 -#define MXC_CCM_CCGRx_MOD_OFF 0x0 -#define MXC_CCM_CCGRx_MOD_ON 0x3 -#define MXC_CCM_CCGRx_MOD_IDLE 0x1 - -#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) -#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) -#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) -#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) -#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) -#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) - -#define MXC_CCM_CCGRx_CG15_OFFSET 30 -#define MXC_CCM_CCGRx_CG14_OFFSET 28 -#define MXC_CCM_CCGRx_CG13_OFFSET 26 -#define MXC_CCM_CCGRx_CG12_OFFSET 24 -#define MXC_CCM_CCGRx_CG11_OFFSET 22 -#define MXC_CCM_CCGRx_CG10_OFFSET 20 -#define MXC_CCM_CCGRx_CG9_OFFSET 18 -#define MXC_CCM_CCGRx_CG8_OFFSET 16 -#define MXC_CCM_CCGRx_CG7_OFFSET 14 -#define MXC_CCM_CCGRx_CG6_OFFSET 12 -#define MXC_CCM_CCGRx_CG5_OFFSET 10 -#define MXC_CCM_CCGRx_CG4_OFFSET 8 -#define MXC_CCM_CCGRx_CG3_OFFSET 6 -#define MXC_CCM_CCGRx_CG2_OFFSET 4 -#define MXC_CCM_CCGRx_CG1_OFFSET 2 -#define MXC_CCM_CCGRx_CG0_OFFSET 0 - -#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) -#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) -#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) -#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) -#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) -#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) -#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) -#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) -#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) -#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) -#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) -#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) -#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) - -/* CORTEXA8 platform */ -#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) - -/* DVFS CORE */ -#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) -#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) -#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) -#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) -#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) -#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) -#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) -#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) -#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) -#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) -#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) -#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) -#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) -#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) -#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) -#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) -#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) - -/* GPC */ -#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) -#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) -#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) -#define MXC_GPC_PGR_ARMPG_OFFSET 8 -#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) - -/* PGC */ -#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) -#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) -#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) -#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) -#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) -#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) - -#define MXC_PGCR_PCR 1 -#define MXC_SRPGCR_PCR 1 -#define MXC_EMPGCR_PCR 1 -#define MXC_PGSR_PSR 1 - - -#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) -#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) - -/* SRPG */ -#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) -#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) -#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) - -#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) -#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) -#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) - -#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) -#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) -#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) - -#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) -#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) -#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) - -#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) -#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) -#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) - -#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) -#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) -#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/crmregs-imx3.h b/ANDROID_3.4.5/arch/arm/mach-imx/crmregs-imx3.h deleted file mode 100644 index 53141273..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/crmregs-imx3.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ - -#define CKIH_CLK_FREQ 26000000 -#define CKIH_CLK_FREQ_27MHZ 27000000 -#define CKIL_CLK_FREQ 32768 - -#define MXC_CCM_BASE (cpu_is_mx31() ? \ -MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)) - -/* Register addresses */ -#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) -#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) -#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) -#define MX35_CCM_PDR2 (MXC_CCM_BASE + 0x0C) -#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C) -#define MX35_CCM_PDR3 (MXC_CCM_BASE + 0x10) -#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10) -#define MX35_CCM_PDR4 (MXC_CCM_BASE + 0x14) -#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14) -#define MX35_CCM_RCSR (MXC_CCM_BASE + 0x18) -#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18) -#define MX35_CCM_MPCTL (MXC_CCM_BASE + 0x1C) -#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C) -#define MX35_CCM_PPCTL (MXC_CCM_BASE + 0x20) -#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20) -#define MX35_CCM_ACMR (MXC_CCM_BASE + 0x24) -#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24) -#define MX35_CCM_COSR (MXC_CCM_BASE + 0x28) -#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28) -#define MX35_CCM_CGR0 (MXC_CCM_BASE + 0x2C) -#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C) -#define MX35_CCM_CGR1 (MXC_CCM_BASE + 0x30) -#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30) -#define MX35_CCM_CGR2 (MXC_CCM_BASE + 0x34) -#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34) -#define MX35_CCM_CGR3 (MXC_CCM_BASE + 0x38) -#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38) -#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C) -#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40) -#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44) -#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48) -#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C) -#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50) -#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54) -#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58) -#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C) -#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60) -#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64) - -/* Register bit definitions */ -#define MXC_CCM_CCMR_WBEN (1 << 27) -#define MXC_CCM_CCMR_CSCS (1 << 25) -#define MXC_CCM_CCMR_PERCS (1 << 24) -#define MXC_CCM_CCMR_SSI1S_OFFSET 18 -#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) -#define MXC_CCM_CCMR_SSI2S_OFFSET 21 -#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) -#define MXC_CCM_CCMR_LPM_OFFSET 14 -#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) -#define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) -#define MXC_CCM_CCMR_FIRS_OFFSET 11 -#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) -#define MXC_CCM_CCMR_UPE (1 << 9) -#define MXC_CCM_CCMR_SPE (1 << 8) -#define MXC_CCM_CCMR_MDS (1 << 7) -#define MXC_CCM_CCMR_SBYCS (1 << 4) -#define MXC_CCM_CCMR_MPE (1 << 3) -#define MXC_CCM_CCMR_PRCS_OFFSET 1 -#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) - -#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 -#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) -#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 -#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) -#define MXC_CCM_PDR0_PER_PODF_OFFSET 16 -#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) -#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 -#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) -#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 -#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) -#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 -#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) -#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 -#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) -#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 -#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 - -#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 -#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) -#define MXC_CCM_PDR1_USB_PODF_OFFSET 27 -#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) -#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 -#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) -#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 -#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) -#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 -#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) -#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 -#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) -#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 -#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) -#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 -#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F - -/* Bit definitions for RCSR */ -#define MXC_CCM_RCSR_NF16B 0x80000000 - -/* - * LTR0 register offsets - */ -#define MXC_CCM_LTR0_DIV3CK_OFFSET 1 -#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) -#define MXC_CCM_LTR0_DNTHR_OFFSET 16 -#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) -#define MXC_CCM_LTR0_UPTHR_OFFSET 22 -#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) - -/* - * LTR1 register offsets - */ -#define MXC_CCM_LTR1_PNCTHR_OFFSET 0 -#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F -#define MXC_CCM_LTR1_UPCNT_OFFSET 6 -#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) -#define MXC_CCM_LTR1_DNCNT_OFFSET 14 -#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) -#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 -#define MXC_CCM_LTR1_LTBRSR_OFFSET 22 -#define MXC_CCM_LTR1_LTBRSR 0x400000 -#define MXC_CCM_LTR1_LTBRSH 0x800000 - -/* - * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 - */ -#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) -#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ - MXC_CCM_LTR2_WSW_OFFSET((x))) -#define MXC_CCM_LTR2_EMAC_OFFSET 0 -#define MXC_CCM_LTR2_EMAC_MASK 0x1FF - -/* - * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 - */ -#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) -#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ - MXC_CCM_LTR3_WSW_OFFSET((x))) - -#define MXC_CCM_PMCR0_DFSUP1 0x80000000 -#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) -#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) -#define MXC_CCM_PMCR0_DFSUP0 0x40000000 -#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) -#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) -#define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) - -#define DVSUP_TURBO 0 -#define DVSUP_HIGH 1 -#define DVSUP_MEDIUM 2 -#define DVSUP_LOW 3 -#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) -#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) -#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) -#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) -#define MXC_CCM_PMCR0_DVSUP_OFFSET 28 -#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) -#define MXC_CCM_PMCR0_UDSC 0x08000000 -#define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) -#define MXC_CCM_PMCR0_UDSC_UP (1 << 27) -#define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) - -#define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) -#define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) -#define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) -#define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) -#define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) -#define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) -#define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) -#define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) -#define MXC_CCM_PMCR0_VSCNT_OFFSET 24 -#define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) -#define MXC_CCM_PMCR0_DVFEV 0x00800000 -#define MXC_CCM_PMCR0_DVFIS 0x00400000 -#define MXC_CCM_PMCR0_LBMI 0x00200000 -#define MXC_CCM_PMCR0_LBFL 0x00100000 -#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) -#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) -#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) -#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) -#define MXC_CCM_PMCR0_LBCF_OFFSET 18 -#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) -#define MXC_CCM_PMCR0_PTVIS 0x00020000 -#define MXC_CCM_PMCR0_UPDTEN 0x00010000 -#define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) -#define MXC_CCM_PMCR0_FSVAIM 0x00008000 -#define MXC_CCM_PMCR0_FSVAI_OFFSET 13 -#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) -#define MXC_CCM_PMCR0_DPVCR 0x00001000 -#define MXC_CCM_PMCR0_DPVV 0x00000800 -#define MXC_CCM_PMCR0_WFIM 0x00000400 -#define MXC_CCM_PMCR0_DRCE3 0x00000200 -#define MXC_CCM_PMCR0_DRCE2 0x00000100 -#define MXC_CCM_PMCR0_DRCE1 0x00000080 -#define MXC_CCM_PMCR0_DRCE0 0x00000040 -#define MXC_CCM_PMCR0_DCR 0x00000020 -#define MXC_CCM_PMCR0_DVFEN 0x00000010 -#define MXC_CCM_PMCR0_PTVAIM 0x00000008 -#define MXC_CCM_PMCR0_PTVAI_OFFSET 1 -#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) -#define MXC_CCM_PMCR0_DPTEN 0x00000001 - -#define MXC_CCM_PMCR1_DVGP_OFFSET 0 -#define MXC_CCM_PMCR1_DVGP_MASK (0xF) - -#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) -#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) - -#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) -#define MXC_CCM_DCVR_ULV_OFFSET 22 -#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) -#define MXC_CCM_DCVR_LLV_OFFSET 12 -#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) -#define MXC_CCM_DCVR_ELV_OFFSET 2 - -#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) -#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 -#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F -#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 - -#define MXC_CCM_COSR_CLKOSEL_MASK 0x0F -#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 -#define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) -#define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 -#define MXC_CCM_COSR_CLKOEN (1 << 9) - -/* - * PMCR0 register offsets - */ -#define MXC_CCM_PMCR0_LBFL_OFFSET 20 -#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 -#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 - -#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx1.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx1.h deleted file mode 100644 index 3aad1e70..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx1.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx1.h> -#include <mach/devices-common.h> - -extern const struct imx_imx_fb_data imx1_imx_fb_data; -#define imx1_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx1_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx1_imx_i2c_data; -#define imx1_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) - -extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[]; -#define imx1_add_imx_uart(id, pdata) \ - imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) -#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) -#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) - -extern const struct imx_spi_imx_data imx1_cspi_data[]; -#define imx1_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx1_cspi_data[id], pdata) - -#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata) -#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx21.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx21.h deleted file mode 100644 index 2628e0c4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx21.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx21.h> -#include <mach/devices-common.h> - -extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data; -#define imx21_add_imx21_hcd(pdata) \ - imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) - -extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; -#define imx21_add_imx2_wdt(pdata) \ - imx_add_imx2_wdt(&imx21_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx21_imx_fb_data; -#define imx21_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx21_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx21_imx_i2c_data; -#define imx21_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) - -extern const struct imx_imx_keypad_data imx21_imx_keypad_data; -#define imx21_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx21_imx_ssi_data[]; -#define imx21_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[]; -#define imx21_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) -#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) -#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata) -#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) -#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) - -extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[]; -#define imx21_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx21_mxc_nand_data; -#define imx21_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx21_mxc_w1_data; -#define imx21_add_mxc_w1(pdata) \ - imx_add_mxc_w1(&imx21_mxc_w1_data) - -extern const struct imx_spi_imx_data imx21_cspi_data[]; -#define imx21_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx21_cspi_data[id], pdata) -#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) -#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx25.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx25.h deleted file mode 100644 index efa0761c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx25.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx25.h> -#include <mach/devices-common.h> - -extern const struct imx_fec_data imx25_fec_data; -#define imx25_add_fec(pdata) \ - imx_add_fec(&imx25_fec_data, pdata) - -extern const struct imx_flexcan_data imx25_flexcan_data[]; -#define imx25_add_flexcan(id, pdata) \ - imx_add_flexcan(&imx25_flexcan_data[id], pdata) -#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata) -#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata) - -extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data; -#define imx25_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) - -extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; -#define imx25_add_imxdi_rtc(pdata) \ - imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) - -extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; -#define imx25_add_imx2_wdt(pdata) \ - imx_add_imx2_wdt(&imx25_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx25_imx_fb_data; -#define imx25_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx25_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx25_imx_i2c_data[]; -#define imx25_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) -#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) -#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) -#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx25_imx_keypad_data; -#define imx25_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx25_imx_ssi_data[]; -#define imx25_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[]; -#define imx25_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) -#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) -#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata) -#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata) -#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) -#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) - -extern const struct imx_mx2_camera_data imx25_mx2_camera_data; -#define imx25_add_mx2_camera(pdata) \ - imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) - -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data; -#define imx25_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data; -#define imx25_add_mxc_ehci_hs(pdata) \ - imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) - -extern const struct imx_mxc_nand_data imx25_mxc_nand_data; -#define imx25_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[]; -#define imx25_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx25_cspi_data[]; -#define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_cspi_data[id], pdata) -#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) -#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) -#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[]; -#define imx25_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx27.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx27.h deleted file mode 100644 index 28537a5d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx27.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx27.h> -#include <mach/devices-common.h> - -extern const struct imx_fec_data imx27_fec_data; -#define imx27_add_fec(pdata) \ - imx_add_fec(&imx27_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; -#define imx27_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; -#define imx27_add_imx2_wdt(pdata) \ - imx_add_imx2_wdt(&imx27_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx27_imx_fb_data; -#define imx27_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx27_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx27_imx_i2c_data[]; -#define imx27_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) - -extern const struct imx_imx_keypad_data imx27_imx_keypad_data; -#define imx27_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx27_imx_ssi_data[]; -#define imx27_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[]; -#define imx27_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) -#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) -#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata) -#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata) -#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata) -#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) -#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) - -extern const struct imx_mx2_camera_data imx27_mx2_camera_data; -#define imx27_add_mx2_camera(pdata) \ - imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) -#define imx27_add_mx2_emmaprp(pdata) \ - imx_add_mx2_emmaprp(&imx27_mx2_camera_data) - -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; -#define imx27_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[]; -#define imx27_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[]; -#define imx27_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx27_mxc_nand_data; -#define imx27_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx27_mxc_w1_data; -#define imx27_add_mxc_w1(pdata) \ - imx_add_mxc_w1(&imx27_mxc_w1_data) - -extern const struct imx_spi_imx_data imx27_cspi_data[]; -#define imx27_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx27_cspi_data[id], pdata) -#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) -#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) -#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) - -extern const struct imx_pata_imx_data imx27_pata_imx_data; -#define imx27_add_pata_imx() \ - imx_add_pata_imx(&imx27_pata_imx_data) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx31.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx31.h deleted file mode 100644 index 488e241a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx31.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx31.h> -#include <mach/devices-common.h> - -extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data; -#define imx31_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; -#define imx31_add_imx2_wdt(pdata) \ - imx_add_imx2_wdt(&imx31_imx2_wdt_data) - -extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; -#define imx31_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) -#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) -#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) -#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx31_imx_keypad_data; -#define imx31_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx31_imx_ssi_data[]; -#define imx31_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[]; -#define imx31_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) -#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) -#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata) -#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata) -#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) -#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) - -extern const struct imx_ipu_core_data imx31_ipu_core_data; -#define imx31_add_ipu_core(pdata) \ - imx_add_ipu_core(&imx31_ipu_core_data, pdata) -#define imx31_alloc_mx3_camera(pdata) \ - imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata) -#define imx31_add_mx3_sdc_fb(pdata) \ - imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata) - -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data; -#define imx31_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[]; -#define imx31_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[]; -#define imx31_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx31_mxc_nand_data; -#define imx31_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) - -extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; -#define imx31_add_mxc_rtc(pdata) \ - imx_add_mxc_rtc(&imx31_mxc_rtc_data) - -extern const struct imx_mxc_w1_data imx31_mxc_w1_data; -#define imx31_add_mxc_w1(pdata) \ - imx_add_mxc_w1(&imx31_mxc_w1_data) - -extern const struct imx_spi_imx_data imx31_cspi_data[]; -#define imx31_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx31_cspi_data[id], pdata) -#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) -#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) -#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) - -extern const struct imx_pata_imx_data imx31_pata_imx_data; -#define imx31_add_pata_imx() \ - imx_add_pata_imx(&imx31_pata_imx_data) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx35.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx35.h deleted file mode 100644 index 7b99ef0b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx35.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx35.h> -#include <mach/devices-common.h> - -extern const struct imx_fec_data imx35_fec_data; -#define imx35_add_fec(pdata) \ - imx_add_fec(&imx35_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data; -#define imx35_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) - -extern const struct imx_flexcan_data imx35_flexcan_data[]; -#define imx35_add_flexcan(id, pdata) \ - imx_add_flexcan(&imx35_flexcan_data[id], pdata) -#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata) -#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) - -extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; -#define imx35_add_imx2_wdt(pdata) \ - imx_add_imx2_wdt(&imx35_imx2_wdt_data) - -extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; -#define imx35_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) -#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) -#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) -#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx35_imx_keypad_data; -#define imx35_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx35_imx_ssi_data[]; -#define imx35_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[]; -#define imx35_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) -#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) -#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) -#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) - -extern const struct imx_ipu_core_data imx35_ipu_core_data; -#define imx35_add_ipu_core(pdata) \ - imx_add_ipu_core(&imx35_ipu_core_data, pdata) -#define imx35_alloc_mx3_camera(pdata) \ - imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata) -#define imx35_add_mx3_sdc_fb(pdata) \ - imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata) - -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data; -#define imx35_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data; -#define imx35_add_mxc_ehci_hs(pdata) \ - imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) - -extern const struct imx_mxc_nand_data imx35_mxc_nand_data; -#define imx35_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx35_mxc_w1_data; -#define imx35_add_mxc_w1(pdata) \ - imx_add_mxc_w1(&imx35_mxc_w1_data) - -extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; -#define imx35_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx35_cspi_data[]; -#define imx35_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx35_cspi_data[id], pdata) -#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) -#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) - -extern const struct imx_pata_imx_data imx35_pata_imx_data; -#define imx35_add_pata_imx() \ - imx_add_pata_imx(&imx35_pata_imx_data) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx50.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx50.h deleted file mode 100644 index 7216667e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx50.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <mach/mx50.h> -#include <mach/devices-common.h> - -extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[]; -#define imx50_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) - -extern const struct imx_fec_data imx50_fec_data; -#define imx50_add_fec(pdata) \ - imx_add_fec(&imx50_fec_data, pdata) - -extern const struct imx_imx_i2c_data imx50_imx_i2c_data[]; -#define imx50_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx51.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx51.h deleted file mode 100644 index af488bc0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx51.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx51.h> -#include <mach/devices-common.h> - -extern const struct imx_fec_data imx51_fec_data; -#define imx51_add_fec(pdata) \ - imx_add_fec(&imx51_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data; -#define imx51_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; -#define imx51_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) -#define imx51_add_hsi2c(pdata) \ - imx51_add_imx_i2c(2, pdata) - -extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; -#define imx51_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[]; -#define imx51_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) - -extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data; -#define imx51_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[]; -#define imx51_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_nand_data imx51_mxc_nand_data; -#define imx51_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[]; -#define imx51_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx51_cspi_data; -#define imx51_add_cspi(pdata) \ - imx_add_spi_imx(&imx51_cspi_data, pdata) - -extern const struct imx_spi_imx_data imx51_ecspi_data[]; -#define imx51_add_ecspi(id, pdata) \ - imx_add_spi_imx(&imx51_ecspi_data[id], pdata) - -extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; -#define imx51_add_imx2_wdt(id, pdata) \ - imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) - -extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; -#define imx51_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) - -extern const struct imx_imx_keypad_data imx51_imx_keypad_data; -#define imx51_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) - -extern const struct imx_pata_imx_data imx51_pata_imx_data; -#define imx51_add_pata_imx() \ - imx_add_pata_imx(&imx51_pata_imx_data) diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx53.h b/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx53.h deleted file mode 100644 index 6e1e5d1f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/devices-imx53.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx53.h> -#include <mach/devices-common.h> - -extern const struct imx_fec_data imx53_fec_data; -#define imx53_add_fec(pdata) \ - imx_add_fec(&imx53_fec_data, pdata) - -extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[]; -#define imx53_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) - - -extern const struct imx_imx_i2c_data imx53_imx_i2c_data[]; -#define imx53_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[]; -#define imx53_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx53_ecspi_data[]; -#define imx53_add_ecspi(id, pdata) \ - imx_add_spi_imx(&imx53_ecspi_data[id], pdata) - -extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; -#define imx53_add_imx2_wdt(id, pdata) \ - imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) - -extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; -#define imx53_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata) - -extern const struct imx_imx_keypad_data imx53_imx_keypad_data; -#define imx53_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) - -extern const struct imx_pata_imx_data imx53_pata_imx_data; -#define imx53_add_pata_imx() \ - imx_add_pata_imx(&imx53_pata_imx_data) - -extern struct platform_device *__init imx53_add_ahci_imx(void); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/efika.h b/ANDROID_3.4.5/arch/arm/mach-imx/efika.h deleted file mode 100644 index 014aa985..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/efika.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _EFIKA_H -#define _EFIKA_H - -#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16) -#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10) -#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9) - -void __init efika_board_common_init(void); - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx25.c b/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx25.c deleted file mode 100644 index 865daf0b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx25.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/mxc_ehci.h> - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX25_OTG_SIC_SHIFT 29 -#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) - -#define MX25_H1_SIC_SHIFT 21 -#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PM_BIT (1 << 8) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) - -int mx25_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT | - MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX25_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX25_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX25_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX25_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} - diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx27.c b/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx27.c deleted file mode 100644 index fa69419e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx27.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/mxc_ehci.h> - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX27_OTG_SIC_SHIFT 29 -#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT) -#define MX27_OTG_PM_BIT (1 << 24) - -#define MX27_H2_SIC_SHIFT 21 -#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT) -#define MX27_H2_PM_BIT (1 << 16) -#define MX27_H2_DT_BIT (1 << 5) - -#define MX27_H1_SIC_SHIFT 13 -#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT) -#define MX27_H1_PM_BIT (1 << 8) -#define MX27_H1_DT_BIT (1 << 4) - -int mx27_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_OTG_PM_BIT; - break; - case 1: /* H1 port */ - v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX27_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX27_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} - diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx31.c b/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx31.c deleted file mode 100644 index faad0f15..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx31.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/mxc_ehci.h> - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -int mx31_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx35.c b/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx35.c deleted file mode 100644 index 001ec397..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx35.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/mxc_ehci.h> - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PM_BIT (1 << 8) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) - -int mx35_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | - MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX35_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX35_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX35_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX35_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx5.c b/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx5.c deleted file mode 100644 index c17fa131..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/ehci-imx5.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/mxc_ehci.h> - -#define MXC_OTG_OFFSET 0 -#define MXC_H1_OFFSET 0x200 -#define MXC_H2_OFFSET 0x400 - -/* USB_CTRL */ -#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ -#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ -#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ -#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ - -/* USB_PHY_CTRL_FUNC */ -#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ -#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ - -/* USBH2CTRL */ -#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) -#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) -#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) - -#define MXC_USBCMD_OFFSET 0x140 - -/* USBCMD */ -#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ - -int mx51_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - void __iomem *usb_base; - void __iomem *usbotg_base; - void __iomem *usbother_base; - int ret = 0; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) { - printk(KERN_ERR "%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - switch (port) { - case 0: /* OTG port */ - usbotg_base = usb_base + MXC_OTG_OFFSET; - break; - case 1: /* Host 1 port */ - usbotg_base = usb_base + MXC_H1_OFFSET; - break; - case 2: /* Host 2 port */ - usbotg_base = usb_base + MXC_H2_OFFSET; - break; - default: - printk(KERN_ERR"%s no such port %d\n", __func__, port); - ret = -ENOENT; - goto error; - } - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - switch (port) { - case 0: /*OTG port */ - if (flags & MXC_EHCI_INTERNAL_PHY) { - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) { - /* OC/USBPWR is not used */ - v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; - } else { - /* OC/USBPWR is used */ - v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; - } - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) - v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ - else - v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= MXC_OTG_UCTRL_OPM_BIT; - else - v &= ~MXC_OTG_UCTRL_OPM_BIT; - __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); - } - break; - case 1: /* Host 1 */ - /*Host ULPI */ - v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) { - /* HOST1 wakeup/ULPI intr enable */ - v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); - } else { - /* HOST1 wakeup/ULPI intr disable */ - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); - } - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ - else - v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ - __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); - - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ - else - v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); - if (flags & MXC_EHCI_ITC_NO_THRESHOLD) - /* Interrupt Threshold Control:Immediate (no threshold) */ - v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; - __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); - break; - case 2: /* Host 2 ULPI */ - v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) { - /* HOST1 wakeup/ULPI intr enable */ - v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); - } else { - /* HOST1 wakeup/ULPI intr disable */ - v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); - } - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ - else - v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ - __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); - break; - } - -error: - iounmap(usb_base); - return ret; -} - diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c deleted file mode 100644 index 5f2f91d1..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/spi/ads7846.h> -#include <linux/backlight.h> -#include <video/platform_lcd.h> - -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/iomux-mx27.h> -#include <mach/hardware.h> - -#include "devices-imx27.h" - -static const int eukrea_mbimx27_pins[] __initconst = { - /* UART2 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART3 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* UART4 */ -#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, -#endif - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* SPI1 */ - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* SSI4 */ -#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \ - || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE) - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD | GPIO_PUEN, - PC18_PF_SSI4_TXD | GPIO_PUEN, - PC19_PF_SSI4_CLK, -#endif -}; - -static const uint32_t eukrea_mbimx27_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), -}; - -static const struct matrix_keymap_data -eukrea_mbimx27_keymap_data __initconst = { - .keymap = eukrea_mbimx27_keymap, - .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), -}; - -static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_PORTF | 16, - }, - { - .name = "led2", - .default_trigger = "none", - .active_low = 1, - .gpio = GPIO_PORTF | 19, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimx27_gpio_led_info __initconst = { - .leds = eukrea_mbimx27_gpio_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds), -}; - -static struct imx_fb_videomode eukrea_mbimx27_modes[] = { - { - .mode = { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = 156000, - .hsync_len = 30, - .left_margin = 38, - .right_margin = 20, - .vsync_len = 3, - .upper_margin = 15, - .lower_margin = 4, - }, - .pcr = 0xFAD08B80, - .bpp = 16, - }, { - .mode = { - .name = "DVI-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 32000, - .hsync_len = 1, - .left_margin = 35, - .right_margin = 0, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 0, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, { - .mode = { - .name = "DVI-SVGA", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .hsync_len = 1, - .left_margin = 35, - .right_margin = 0, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 0, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = { - .mode = eukrea_mbimx27_modes, - .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00040060, -}; - -static void eukrea_mbimx27_bl_set_intensity(int intensity) -{ - if (intensity) - gpio_direction_output(GPIO_PORTE | 5, 1); - else - gpio_direction_output(GPIO_PORTE | 5, 0); -} - -static struct generic_bl_info eukrea_mbimx27_bl_info = { - .name = "eukrea_mbimx27-bl", - .max_intensity = 0xff, - .default_intensity = 0xff, - .set_bl_intensity = eukrea_mbimx27_bl_set_intensity, -}; - -static struct platform_device eukrea_mbimx27_bl_dev = { - .name = "generic-bl", - .id = 1, - .dev = { - .platform_data = &eukrea_mbimx27_bl_info, - }, -}; - -static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_PORTA | 25, 1); - else - gpio_direction_output(GPIO_PORTA | 25, 0); -} - -static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = { - .set_power = eukrea_mbimx27_lcd_power_set, -}; - -static struct platform_device eukrea_mbimx27_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimx27_lcd_power_data, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define ADS7846_PENDOWN (GPIO_PORTD | 25) - -static void __maybe_unused ads7846_dev_init(void) -{ - if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { - printk(KERN_ERR "can't get ads746 pen down GPIO\n"); - return; - } - gpio_direction_input(ADS7846_PENDOWN); -} - -static int ads7846_get_pendown_state(void) -{ - return !gpio_get_value(ADS7846_PENDOWN); -} - -static struct ads7846_platform_data ads7846_config __initdata = { - .get_pendown_state = ads7846_get_pendown_state, - .keep_vref_on = 1, -}; - -static struct spi_board_info __maybe_unused - eukrea_mbimx27_spi_board_info[] __initdata = { - [0] = { - .modalias = "ads7846", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 1500000, - .irq = IRQ_GPIOD(25), - .platform_data = &ads7846_config, - .mode = SPI_MODE_2, - }, -}; - -static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28}; - -static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = { - .chipselect = eukrea_mbimx27_spi_cs, - .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs), -}; - -static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .dat3_card_detect = 1, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = { - .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, -}; - -/* - * system init for baseboard usage. Will be called by cpuimx27 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimx27_baseboard_init(void) -{ - mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, - ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); - - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); -#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) - imx27_add_imx_uart3(&uart_pdata); -#endif - - imx27_add_imx_fb(&eukrea_mbimx27_fb_data); - imx27_add_mxc_mmc(0, &sdhc_pdata); - - i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, - ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); - - imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata); - -#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ - || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) - /* ADS7846 Touchscreen controller init */ - mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN); - ads7846_dev_init(); -#endif - - /* SPI_CS0 init */ - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); - imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); - spi_register_board_info(eukrea_mbimx27_spi_board_info, - ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); - - /* Leds configuration */ - mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT); - mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT); - /* Backlight */ - mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT); - gpio_request(GPIO_PORTE | 5, "backlight"); - platform_device_register(&eukrea_mbimx27_bl_dev); - /* LCD Reset */ - mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT); - gpio_request(GPIO_PORTA | 25, "lcd_enable"); - platform_device_register(&eukrea_mbimx27_lcd_powerdev); - - imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); - - gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c deleted file mode 100644 index a6a3ab8f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * - * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/i2c/tsc2007.h> -#include <linux/leds.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/mach/arch.h> - -#include "devices-imx51.h" - -#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) -#define MBIMX51_LED0 IMX_GPIO_NR(3, 5) -#define MBIMX51_LED1 IMX_GPIO_NR(3, 6) -#define MBIMX51_LED2 IMX_GPIO_NR(3, 7) -#define MBIMX51_LED3 IMX_GPIO_NR(3, 8) - -static const struct gpio_led mbimx51_leds[] __initconst = { - { - .name = "led0", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = MBIMX51_LED0, - }, - { - .name = "led1", - .default_trigger = "nand-disk", - .active_low = 1, - .gpio = MBIMX51_LED1, - }, - { - .name = "led2", - .default_trigger = "mmc0", - .active_low = 1, - .gpio = MBIMX51_LED2, - }, - { - .name = "led3", - .default_trigger = "default-on", - .active_low = 1, - .gpio = MBIMX51_LED3, - }, -}; - -static const struct gpio_led_platform_data mbimx51_leds_info __initconst = { - .leds = mbimx51_leds, - .num_leds = ARRAY_SIZE(mbimx51_leds), -}; - -static iomux_v3_cfg_t mbimx51_pads[] = { - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - - /* UART3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - MX51_PAD_KEY_COL4__UART3_RTS, - MX51_PAD_KEY_COL5__UART3_CTS, - - /* TSC2007 IRQ */ - MX51_PAD_NANDF_D10__GPIO3_30, - - /* LEDS */ - MX51_PAD_DISPB2_SER_DIN__GPIO3_5, - MX51_PAD_DISPB2_SER_DIO__GPIO3_6, - MX51_PAD_DISPB2_SER_CLK__GPIO3_7, - MX51_PAD_DISPB2_SER_RS__GPIO3_8, - - /* KPP */ - MX51_PAD_KEY_ROW0__KEY_ROW0, - MX51_PAD_KEY_ROW1__KEY_ROW1, - MX51_PAD_KEY_ROW2__KEY_ROW2, - MX51_PAD_KEY_ROW3__KEY_ROW3, - MX51_PAD_KEY_COL0__KEY_COL0, - MX51_PAD_KEY_COL1__KEY_COL1, - MX51_PAD_KEY_COL2__KEY_COL2, - MX51_PAD_KEY_COL3__KEY_COL3, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int mbimx51_keymap[] = { - KEY(0, 0, KEY_1), - KEY(0, 1, KEY_2), - KEY(0, 2, KEY_3), - KEY(0, 3, KEY_UP), - - KEY(1, 0, KEY_4), - KEY(1, 1, KEY_5), - KEY(1, 2, KEY_6), - KEY(1, 3, KEY_LEFT), - - KEY(2, 0, KEY_7), - KEY(2, 1, KEY_8), - KEY(2, 2, KEY_9), - KEY(2, 3, KEY_RIGHT), - - KEY(3, 0, KEY_0), - KEY(3, 1, KEY_DOWN), - KEY(3, 2, KEY_ESC), - KEY(3, 3, KEY_ENTER), -}; - -static const struct matrix_keymap_data mbimx51_map_data __initconst = { - .keymap = mbimx51_keymap, - .keymap_size = ARRAY_SIZE(mbimx51_keymap), -}; - -static int tsc2007_get_pendown_state(void) -{ - return !gpio_get_value(MBIMX51_TSC2007_GPIO); -} - -struct tsc2007_platform_data tsc2007_data = { - .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = tsc2007_get_pendown_state, -}; - -static struct i2c_board_info mbimx51_i2c_devices[] = { - { - I2C_BOARD_INFO("tsc2007", 0x49), - .irq = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO), - .platform_data = &tsc2007_data, - }, { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -/* - * baseboard initialization. - */ -void __init eukrea_mbimx51_baseboard_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, - ARRAY_SIZE(mbimx51_pads)); - - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); - - gpio_request(MBIMX51_LED0, "LED0"); - gpio_direction_output(MBIMX51_LED0, 1); - gpio_free(MBIMX51_LED0); - gpio_request(MBIMX51_LED1, "LED1"); - gpio_direction_output(MBIMX51_LED1, 1); - gpio_free(MBIMX51_LED1); - gpio_request(MBIMX51_LED2, "LED2"); - gpio_direction_output(MBIMX51_LED2, 1); - gpio_free(MBIMX51_LED2); - gpio_request(MBIMX51_LED3, "LED3"); - gpio_direction_output(MBIMX51_LED3, 1); - gpio_free(MBIMX51_LED3); - - gpio_led_register_device(-1, &mbimx51_leds_info); - - imx51_add_imx_keypad(&mbimx51_map_data); - - gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); - gpio_direction_input(MBIMX51_TSC2007_GPIO); - irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO), - IRQF_TRIGGER_FALLING); - i2c_register_board_info(1, mbimx51_i2c_devices, - ARRAY_SIZE(mbimx51_i2c_devices)); - - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_sdhci_esdhc_imx(1, NULL); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c deleted file mode 100644 index aaa592fd..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/i2c.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx51.h> - -#include "devices-imx51.h" - -static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { - /* LED */ - MX51_PAD_NANDF_D10__GPIO3_30, - /* SWITCH */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - /* UART 3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - MX51_PAD_KEY_COL4__UART3_RTS, - MX51_PAD_KEY_COL5__UART3_CTS, - /* SD */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - /* SD1 CD */ - NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), -}; - -#define GPIO_LED1 IMX_GPIO_NR(3, 30) -#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31) - -static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_LED1, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimxsd_led_info __initconst = { - .leds = eukrea_mbimxsd_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), -}; - -static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { - { - .gpio = GPIO_SWITCH1, - .code = BTN_0, - .desc = "BP1", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data - eukrea_mbimxsd_button_data __initconst = { - .buttons = eukrea_mbimxsd_gpio_buttons, - .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -/* - * system init for baseboard usage. Will be called by cpuimx51sd init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimxsd51_baseboard_init(void) -{ - if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, - ARRAY_SIZE(eukrea_mbimxsd_pads))) - printk(KERN_ERR "error setting mbimxsd pads !\n"); - - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); - - imx51_add_sdhci_esdhc_imx(0, NULL); - - gpio_request(GPIO_LED1, "LED1"); - gpio_direction_output(GPIO_LED1, 1); - gpio_free(GPIO_LED1); - - gpio_request(GPIO_SWITCH1, "SWITCH1"); - gpio_direction_input(GPIO_SWITCH1); - gpio_free(GPIO_SWITCH1); - - i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, - ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); - - gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); - imx_add_gpio_keys(&eukrea_mbimxsd_button_data); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c deleted file mode 100644 index 2cf603e1..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <video/platform_lcd.h> - -#include <mach/hardware.h> -#include <mach/iomux-mx25.h> -#include <mach/common.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/mx25.h> - -#include "devices-imx25.h" - -static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { - /* LCD */ - MX25_PAD_LD0__LD0, - MX25_PAD_LD1__LD1, - MX25_PAD_LD2__LD2, - MX25_PAD_LD3__LD3, - MX25_PAD_LD4__LD4, - MX25_PAD_LD5__LD5, - MX25_PAD_LD6__LD6, - MX25_PAD_LD7__LD7, - MX25_PAD_LD8__LD8, - MX25_PAD_LD9__LD9, - MX25_PAD_LD10__LD10, - MX25_PAD_LD11__LD11, - MX25_PAD_LD12__LD12, - MX25_PAD_LD13__LD13, - MX25_PAD_LD14__LD14, - MX25_PAD_LD15__LD15, - MX25_PAD_GPIO_E__LD16, - MX25_PAD_GPIO_F__LD17, - MX25_PAD_HSYNC__HSYNC, - MX25_PAD_VSYNC__VSYNC, - MX25_PAD_LSCLK__LSCLK, - MX25_PAD_OE_ACD__OE_ACD, - MX25_PAD_CONTRAST__CONTRAST, - /* LCD_PWR */ - MX25_PAD_PWM__GPIO_1_26, - /* LED */ - MX25_PAD_POWER_FAIL__GPIO_3_19, - /* SWITCH */ - MX25_PAD_VSTBY_ACK__GPIO_3_18, - /* UART2 */ - MX25_PAD_UART2_RTS__UART2_RTS, - MX25_PAD_UART2_CTS__UART2_CTS, - MX25_PAD_UART2_TXD__UART2_TXD, - MX25_PAD_UART2_RXD__UART2_RXD, - /* SD1 */ - MX25_PAD_SD1_CMD__SD1_CMD, - MX25_PAD_SD1_CLK__SD1_CLK, - MX25_PAD_SD1_DATA0__SD1_DATA0, - MX25_PAD_SD1_DATA1__SD1_DATA1, - MX25_PAD_SD1_DATA2__SD1_DATA2, - MX25_PAD_SD1_DATA3__SD1_DATA3, - /* SD1 CD */ - MX25_PAD_DE_B__GPIO_2_20, - /* I2S */ - MX25_PAD_KPP_COL3__AUD5_TXFS, - MX25_PAD_KPP_COL2__AUD5_TXC, - MX25_PAD_KPP_COL1__AUD5_RXD, - MX25_PAD_KPP_COL0__AUD5_TXD, - /* CAN */ - MX25_PAD_GPIO_D__CAN2_RX, - MX25_PAD_GPIO_C__CAN2_TX, -}; - -#define GPIO_LED1 83 -#define GPIO_SWITCH1 82 -#define GPIO_SD1CD 52 -#define GPIO_LCDPWR 26 - -static struct imx_fb_videomode eukrea_mximxsd_modes[] = { - { - .mode = { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = KHZ2PICOS(6500), - .left_margin = 30, - .right_margin = 38, - .upper_margin = 20, - .lower_margin = 3, - .hsync_len = 15, - .vsync_len = 4, - }, - .bpp = 16, - .pcr = 0xCAD08B80, - }, { - .mode = { - .name = "DVI-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 32000, - .hsync_len = 7, - .left_margin = 100, - .right_margin = 100, - .vsync_len = 7, - .upper_margin = 7, - .lower_margin = 100, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, { - .mode = { - .name = "DVI-SVGA", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .hsync_len = 7, - .left_margin = 75, - .right_margin = 75, - .vsync_len = 7, - .upper_margin = 7, - .lower_margin = 75, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = { - .mode = eukrea_mximxsd_modes, - .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00040060, -}; - -static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_LCDPWR, 1); - else - gpio_direction_output(GPIO_LCDPWR, 0); -} - -static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { - .set_power = eukrea_mbimxsd_lcd_power_set, -}; - -static struct platform_device eukrea_mbimxsd_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, -}; - -static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_LED1, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimxsd_led_info __initconst = { - .leds = eukrea_mbimxsd_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), -}; - -static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { - { - .gpio = GPIO_SWITCH1, - .code = BTN_0, - .desc = "BP1", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data - eukrea_mbimxsd_button_data __initconst = { - .buttons = eukrea_mbimxsd_gpio_buttons, - .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), -}; - -static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_lcd_powerdev, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { - .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_gpio = GPIO_SD1CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -/* - * system init for baseboard usage. Will be called by cpuimx25 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimxsd25_baseboard_init(void) -{ - if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, - ARRAY_SIZE(eukrea_mbimxsd_pads))) - printk(KERN_ERR "error setting mbimxsd pads !\n"); - - imx25_add_imx_uart1(&uart_pdata); - imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata); - imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); - - imx25_add_flexcan1(NULL); - imx25_add_sdhci_esdhc_imx(0, &sd1_pdata); - - gpio_request(GPIO_LED1, "LED1"); - gpio_direction_output(GPIO_LED1, 1); - gpio_free(GPIO_LED1); - - gpio_request(GPIO_SWITCH1, "SWITCH1"); - gpio_direction_input(GPIO_SWITCH1); - gpio_free(GPIO_SWITCH1); - - gpio_request(GPIO_LCDPWR, "LCDPWR"); - gpio_direction_output(GPIO_LCDPWR, 1); - gpio_free(GPIO_SWITCH1); - - i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, - ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); - imx_add_gpio_keys(&eukrea_mbimxsd_button_data); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c deleted file mode 100644 index fd8bf8a4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <video/platform_lcd.h> -#include <linux/i2c.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx35.h> - -#include "devices-imx35.h" - -static const struct fb_videomode fb_modedb[] = { - { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = KHZ2PICOS(6500), - .left_margin = 68, - .right_margin = 20, - .upper_margin = 15, - .lower_margin = 4, - .hsync_len = 30, - .vsync_len = 3, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - { - .name = "DVI-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 32000, - .left_margin = 100, - .right_margin = 100, - .upper_margin = 7, - .lower_margin = 100, - .hsync_len = 7, - .vsync_len = 7, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - { - .name = "DVI-SVGA", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .left_margin = 75, - .right_margin = 75, - .upper_margin = 7, - .lower_margin = 75, - .hsync_len = 7, - .vsync_len = 7, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "CMO-QVGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { - /* LCD */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - /* Backlight */ - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - /* LCD_PWR */ - MX35_PAD_D3_CLS__GPIO1_4, - /* LED */ - MX35_PAD_LD23__GPIO3_29, - /* SWITCH */ - MX35_PAD_LD19__GPIO3_25, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* I2S */ - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, - MX35_PAD_STXD4__AUDMUX_AUD4_TXD, - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, - MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* CAN2 */ - MX35_PAD_TX5_RX0__CAN2_TXCAN, - MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1 CD */ - MX35_PAD_LD18__GPIO3_24, -}; - -#define GPIO_LED1 IMX_GPIO_NR(3, 29) -#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) -#define GPIO_LCDPWR IMX_GPIO_NR(1, 4) -#define GPIO_SD1CD IMX_GPIO_NR(3, 24) - -static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_LCDPWR, 1); - else - gpio_direction_output(GPIO_LCDPWR, 0); -} - -static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { - .set_power = eukrea_mbimxsd_lcd_power_set, -}; - -static struct platform_device eukrea_mbimxsd_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, -}; - -static struct gpio_led eukrea_mbimxsd_leds[] = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_LED1, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimxsd_led_info __initconst = { - .leds = eukrea_mbimxsd_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), -}; - -static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { - { - .gpio = GPIO_SWITCH1, - .code = BTN_0, - .desc = "BP1", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data - eukrea_mbimxsd_button_data __initconst = { - .buttons = eukrea_mbimxsd_gpio_buttons, - .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), -}; - -static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_lcd_powerdev, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { - .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_gpio = GPIO_SD1CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -/* - * system init for baseboard usage. Will be called by cpuimx35 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimxsd35_baseboard_init(void) -{ - if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, - ARRAY_SIZE(eukrea_mbimxsd_pads))) - printk(KERN_ERR "error setting mbimxsd pads !\n"); - - imx35_add_imx_uart1(&uart_pdata); - imx35_add_ipu_core(&mx3_ipu_data); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); - - imx35_add_flexcan1(NULL); - imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); - - gpio_request(GPIO_LED1, "LED1"); - gpio_direction_output(GPIO_LED1, 1); - gpio_free(GPIO_LED1); - - gpio_request(GPIO_SWITCH1, "SWITCH1"); - gpio_direction_input(GPIO_SWITCH1); - gpio_free(GPIO_SWITCH1); - - gpio_request(GPIO_LCDPWR, "LCDPWR"); - gpio_direction_output(GPIO_LCDPWR, 1); - - i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, - ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); - imx_add_gpio_keys(&eukrea_mbimxsd_button_data); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/gpc.c b/ANDROID_3.4.5/arch/arm/mach-imx/gpc.c deleted file mode 100644 index e1537f9e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/gpc.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <asm/hardware/gic.h> - -#define GPC_IMR1 0x008 -#define GPC_PGC_CPU_PDN 0x2a0 - -#define IMR_NUM 4 - -static void __iomem *gpc_base; -static u32 gpc_wake_irqs[IMR_NUM]; -static u32 gpc_saved_imrs[IMR_NUM]; - -void imx_gpc_pre_suspend(void) -{ - void __iomem *reg_imr1 = gpc_base + GPC_IMR1; - int i; - - /* Tell GPC to power off ARM core when suspend */ - writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); - - for (i = 0; i < IMR_NUM; i++) { - gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); - writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); - } -} - -void imx_gpc_post_resume(void) -{ - void __iomem *reg_imr1 = gpc_base + GPC_IMR1; - int i; - - /* Keep ARM core powered on for other low-power modes */ - writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN); - - for (i = 0; i < IMR_NUM; i++) - writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); -} - -static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) -{ - unsigned int idx = d->irq / 32 - 1; - u32 mask; - - /* Sanity check for SPI irq */ - if (d->irq < 32) - return -EINVAL; - - mask = 1 << d->irq % 32; - gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : - gpc_wake_irqs[idx] & ~mask; - - return 0; -} - -static void imx_gpc_irq_unmask(struct irq_data *d) -{ - void __iomem *reg; - u32 val; - - /* Sanity check for SPI irq */ - if (d->irq < 32) - return; - - reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4; - val = readl_relaxed(reg); - val &= ~(1 << d->irq % 32); - writel_relaxed(val, reg); -} - -static void imx_gpc_irq_mask(struct irq_data *d) -{ - void __iomem *reg; - u32 val; - - /* Sanity check for SPI irq */ - if (d->irq < 32) - return; - - reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4; - val = readl_relaxed(reg); - val |= 1 << (d->irq % 32); - writel_relaxed(val, reg); -} - -void __init imx_gpc_init(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); - gpc_base = of_iomap(np, 0); - WARN_ON(!gpc_base); - - /* Register GPC as the secondary interrupt controller behind GIC */ - gic_arch_extn.irq_mask = imx_gpc_irq_mask; - gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; - gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/head-v7.S b/ANDROID_3.4.5/arch/arm/mach-imx/head-v7.S deleted file mode 100644 index 7e49deb1..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/head-v7.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> -#include <asm/hardware/cache-l2x0.h> - - .section ".text.head", "ax" - -/* - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - -#ifdef CONFIG_SMP -ENTRY(v7_secondary_startup) - bl v7_invalidate_l1 - b secondary_startup -ENDPROC(v7_secondary_startup) -#endif - -#ifdef CONFIG_PM -/* - * The following code is located into the .data section. This is to - * allow phys_l2x0_saved_regs to be accessed with a relative load - * as we are running on physical address here. - */ - .data - .align - -#ifdef CONFIG_CACHE_L2X0 - .macro pl310_resume - ldr r2, phys_l2x0_saved_regs - ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 - ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value - str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl - mov r1, #0x1 - str r1, [r0, #L2X0_CTRL] @ re-enable L2 - .endm - - .globl phys_l2x0_saved_regs -phys_l2x0_saved_regs: - .long 0 -#else - .macro pl310_resume - .endm -#endif - -ENTRY(v7_cpu_resume) - bl v7_invalidate_l1 - pl310_resume - b cpu_resume -ENDPROC(v7_cpu_resume) -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/hotplug.c b/ANDROID_3.4.5/arch/arm/mach-imx/hotplug.c deleted file mode 100644 index 20ed2d56..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/hotplug.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/errno.h> -#include <asm/cacheflush.h> -#include <asm/cp15.h> -#include <mach/common.h> - -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - flush_cache_all(); - asm volatile( - "mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %3\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( - "mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void platform_cpu_die(unsigned int cpu) -{ - cpu_enter_lowpower(); - imx_enable_cpu(cpu, false); - cpu_do_idle(); - cpu_leave_lowpower(); - - /* We should never return from idle */ - panic("cpu %d unexpectedly exit from shutdown\n", cpu); -} - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/imx27-dt.c b/ANDROID_3.4.5/arch/arm/mach-imx/imx27-dt.c deleted file mode 100644 index ed38d03c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/imx27-dt.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/common.h> -#include <mach/mx27.h> - -static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = { - OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL), - OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL), - OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL), - OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL), - OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx-i2c.0", NULL), - OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx-i2c.1", NULL), - OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL), - OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL), - OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL), - OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL), - { /* sentinel */ } -}; - -static int __init imx27_avic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - -static int __init imx27_gpio_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - - gpio_irq_base -= 32; - irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, - NULL); - - return 0; -} - -static const struct of_device_id imx27_irq_match[] __initconst = { - { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, }, - { .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, }, - { /* sentinel */ } -}; - -static void __init imx27_dt_init(void) -{ - of_irq_init(imx27_irq_match); - - of_platform_populate(NULL, of_default_bus_match_table, - imx27_auxdata_lookup, NULL); -} - -static void __init imx27_timer_init(void) -{ - mx27_clocks_init_dt(); -} - -static struct sys_timer imx27_timer = { - .init = imx27_timer_init, -}; - -static const char *imx27_dt_board_compat[] __initdata = { - "fsl,imx27", - NULL -}; - -DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &imx27_timer, - .init_machine = imx27_dt_init, - .dt_compat = imx27_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/imx51-dt.c b/ANDROID_3.4.5/arch/arm/mach-imx/imx51-dt.c deleted file mode 100644 index 5cca5739..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/imx51-dt.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/common.h> -#include <mach/mx51.h> - -/* - * Lookup table for attaching a specific name and platform_data pointer to - * devices as they get created by of_platform_populate(). Ideally this table - * would not exist, but the current clock implementation depends on some devices - * having a specific name. - */ -static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { - OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL), - OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL), - OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL), - OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL), - OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL), - OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL), - OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL), - OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL), - OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL), - OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL), - OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL), - OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL), - OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL), - OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL), - OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL), - { /* sentinel */ } -}; - -static int __init imx51_tzic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - -static int __init imx51_gpio_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - - gpio_irq_base -= 32; - irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL); - - return 0; -} - -static const struct of_device_id imx51_irq_match[] __initconst = { - { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, }, - { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, }, - { /* sentinel */ } -}; - -static const struct of_device_id imx51_iomuxc_of_match[] __initconst = { - { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, }, - { /* sentinel */ } -}; - -static void __init imx51_dt_init(void) -{ - struct device_node *node; - const struct of_device_id *of_id; - void (*func)(void); - - of_irq_init(imx51_irq_match); - - node = of_find_matching_node(NULL, imx51_iomuxc_of_match); - if (node) { - of_id = of_match_node(imx51_iomuxc_of_match, node); - func = of_id->data; - func(); - of_node_put(node); - } - - of_platform_populate(NULL, of_default_bus_match_table, - imx51_auxdata_lookup, NULL); -} - -static void __init imx51_timer_init(void) -{ - mx51_clocks_init_dt(); -} - -static struct sys_timer imx51_timer = { - .init = imx51_timer_init, -}; - -static const char *imx51_dt_board_compat[] __initdata = { - "fsl,imx51-babbage", - "fsl,imx51", - NULL -}; - -DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &imx51_timer, - .init_machine = imx51_dt_init, - .dt_compat = imx51_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/imx53-dt.c b/ANDROID_3.4.5/arch/arm/mach-imx/imx53-dt.c deleted file mode 100644 index 4172279b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/imx53-dt.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/common.h> -#include <mach/mx53.h> - -/* - * Lookup table for attaching a specific name and platform_data pointer to - * devices as they get created by of_platform_populate(). Ideally this table - * would not exist, but the current clock implementation depends on some devices - * having a specific name. - */ -static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { - OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL), - OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL), - OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL), - OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL), - OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL), - OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL), - OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL), - OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL), - OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL), - OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL), - OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL), - OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL), - OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL), - OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL), - OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL), - OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL), - OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL), - OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL), - { /* sentinel */ } -}; - -static int __init imx53_tzic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - -static int __init imx53_gpio_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - - gpio_irq_base -= 32; - irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL); - - return 0; -} - -static const struct of_device_id imx53_irq_match[] __initconst = { - { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, }, - { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, }, - { /* sentinel */ } -}; - -static const struct of_device_id imx53_iomuxc_of_match[] __initconst = { - { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, }, - { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, }, - { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, }, - { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, }, - { /* sentinel */ } -}; - -static void __init imx53_dt_init(void) -{ - struct device_node *node; - const struct of_device_id *of_id; - void (*func)(void); - - of_irq_init(imx53_irq_match); - - node = of_find_matching_node(NULL, imx53_iomuxc_of_match); - if (node) { - of_id = of_match_node(imx53_iomuxc_of_match, node); - func = of_id->data; - func(); - of_node_put(node); - } - - of_platform_populate(NULL, of_default_bus_match_table, - imx53_auxdata_lookup, NULL); -} - -static void __init imx53_timer_init(void) -{ - mx53_clocks_init_dt(); -} - -static struct sys_timer imx53_timer = { - .init = imx53_timer_init, -}; - -static const char *imx53_dt_board_compat[] __initdata = { - "fsl,imx53-ard", - "fsl,imx53-evk", - "fsl,imx53-qsb", - "fsl,imx53-smd", - "fsl,imx53", - NULL -}; - -DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &imx53_timer, - .init_machine = imx53_dt_init, - .dt_compat = imx53_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/ANDROID_3.4.5/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h deleted file mode 100644 index df5f522d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __MACH_DMA_MX1_MX2_H__ -#define __MACH_DMA_MX1_MX2_H__ -/* - * Don't use this header in new code, it will go away when all users are - * converted to mach/dma-v1.h - */ - -#include <mach/dma-v1.h> - -#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */ diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/iomux-imx31.c b/ANDROID_3.4.5/arch/arm/mach-imx/iomux-imx31.c deleted file mode 100644 index 82bd4403..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/iomux-imx31.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <mach/hardware.h> -#include <mach/iomux-mx3.h> - -/* - * IOMUX register (base) addresses - */ -#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) -#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) -#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) -#define IOMUXGPR (IOMUX_BASE + 0x008) -#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C) -#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154) - -static DEFINE_SPINLOCK(gpio_mux_lock); - -#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) - -unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; -/* - * set the mode for a IOMUX pin. - */ -int mxc_iomux_mode(unsigned int pin_mode) -{ - u32 field, l, mode, ret = 0; - void __iomem *reg; - - reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); - field = pin_mode & 0x3; - mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; - - spin_lock(&gpio_mux_lock); - - l = __raw_readl(reg); - l &= ~(0xff << (field * 8)); - l |= mode << (field * 8); - __raw_writel(l, reg); - - spin_unlock(&gpio_mux_lock); - - return ret; -} -EXPORT_SYMBOL(mxc_iomux_mode); - -/* - * This function configures the pad value for a IOMUX pin. - */ -void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) -{ - u32 field, l; - void __iomem *reg; - - pin &= IOMUX_PADNUM_MASK; - reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; - field = (pin + 2) % 3; - - pr_debug("%s: reg offset = 0x%x, field = %d\n", - __func__, (pin + 2) / 3, field); - - spin_lock(&gpio_mux_lock); - - l = __raw_readl(reg); - l &= ~(0x1ff << (field * 10)); - l |= config << (field * 10); - __raw_writel(l, reg); - - spin_unlock(&gpio_mux_lock); -} -EXPORT_SYMBOL(mxc_iomux_set_pad); - -/* - * allocs a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - */ -int mxc_iomux_alloc_pin(unsigned int pin, const char *label) -{ - unsigned pad = pin & IOMUX_PADNUM_MASK; - - if (pad >= (PIN_MAX + 1)) { - printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", - pad, label ? label : "?"); - return -EINVAL; - } - - if (test_and_set_bit(pad, mxc_pin_alloc_map)) { - printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", - pad, label ? label : "?"); - return -EBUSY; - } - mxc_iomux_mode(pin); - - return 0; -} -EXPORT_SYMBOL(mxc_iomux_alloc_pin); - -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label) -{ - const unsigned int *p = pin_list; - int i; - int ret = -EINVAL; - - for (i = 0; i < count; i++) { - ret = mxc_iomux_alloc_pin(*p, label); - if (ret) - goto setup_error; - p++; - } - return 0; - -setup_error: - mxc_iomux_release_multiple_pins(pin_list, i); - return ret; -} -EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); - -void mxc_iomux_release_pin(unsigned int pin) -{ - unsigned pad = pin & IOMUX_PADNUM_MASK; - - if (pad < (PIN_MAX + 1)) - clear_bit(pad, mxc_pin_alloc_map); -} -EXPORT_SYMBOL(mxc_iomux_release_pin); - -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) -{ - const unsigned int *p = pin_list; - int i; - - for (i = 0; i < count; i++) { - mxc_iomux_release_pin(*p); - p++; - } -} -EXPORT_SYMBOL(mxc_iomux_release_multiple_pins); - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en) -{ - u32 l; - - spin_lock(&gpio_mux_lock); - l = __raw_readl(IOMUXGPR); - if (en) - l |= gp; - else - l &= ~gp; - - __raw_writel(l, IOMUXGPR); - spin_unlock(&gpio_mux_lock); -} -EXPORT_SYMBOL(mxc_iomux_set_gpr); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/lluart.c b/ANDROID_3.4.5/arch/arm/mach-imx/lluart.c deleted file mode 100644 index 0213f8dc..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/lluart.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <asm/page.h> -#include <asm/sizes.h> -#include <asm/mach/map.h> -#include <mach/hardware.h> - -static struct map_desc imx_lluart_desc = { -#ifdef CONFIG_DEBUG_IMX6Q_UART4 - .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR), - .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR), - .length = MX6Q_UART4_SIZE, - .type = MT_DEVICE, -#endif -}; - -void __init imx_lluart_map_io(void) -{ - if (imx_lluart_desc.virtual) - iotable_init(&imx_lluart_desc, 1); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-apf9328.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-apf9328.c deleted file mode 100644 index f4a63ee9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-apf9328.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * linux/arch/arm/mach-imx/mach-apf9328.c - * - * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com> - * - * This work is based on mach-scb9328.c which is: - * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> - * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/dm9000.h> -#include <linux/i2c.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/iomux-mx1.h> - -#include "devices-imx1.h" - -static const int apf9328_pins[] __initconst = { - /* UART1 */ - PC9_PF_UART1_CTS, - PC10_PF_UART1_RTS, - PC11_PF_UART1_TXD, - PC12_PF_UART1_RXD, - /* UART2 */ - PB28_PF_UART2_CTS, - PB29_PF_UART2_RTS, - PB30_PF_UART2_TXD, - PB31_PF_UART2_RXD, - /* I2C */ - PA15_PF_I2C_SDA, - PA16_PF_I2C_SCL, -}; - -/* - * The APF9328 can have up to 32MB NOR Flash - */ -static struct resource flash_resource = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct physmap_flash_data apf9328_flash_data = { - .width = 2, -}; - -static struct platform_device apf9328_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &apf9328_flash_data, - }, - .resource = &flash_resource, - .num_resources = 1, -}; - -/* - * APF9328 has a DM9000 Ethernet controller - */ -static struct dm9000_plat_data dm9000_setup = { - .flags = DM9000_PLATF_16BITONLY -}; - -static struct resource dm9000_resources[] = { - { - .start = MX1_CS4_PHYS + 0x00C00000, - .end = MX1_CS4_PHYS + 0x00C00001, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_CS4_PHYS + 0x00C00002, - .end = MX1_CS4_PHYS + 0x00C00003, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_GPIOB(14), - .end = IRQ_GPIOB(14), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct platform_device dm9000x_device = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9000_resources), - .resource = dm9000_resources, - .dev = { - .platform_data = &dm9000_setup, - } -}; - -static const struct imxuart_platform_data uart1_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data apf9328_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct platform_device *devices[] __initdata = { - &apf9328_flash_device, - &dm9000x_device, -}; - -static void __init apf9328_init(void) -{ - imx1_soc_init(); - - mxc_gpio_setup_multiple_pins(apf9328_pins, - ARRAY_SIZE(apf9328_pins), - "APF9328"); - - imx1_add_imx_uart0(NULL); - imx1_add_imx_uart1(&uart1_pdata); - - imx1_add_imx_i2c(&apf9328_i2c_data); - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init apf9328_timer_init(void) -{ - mx1_clocks_init(32768); -} - -static struct sys_timer apf9328_timer = { - .init = apf9328_timer_init, -}; - -MACHINE_START(APF9328, "Armadeus APF9328") - /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */ - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .timer = &apf9328_timer, - .init_machine = apf9328_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-armadillo5x0.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-armadillo5x0.c deleted file mode 100644 index c650145d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-armadillo5x0.c +++ /dev/null @@ -1,574 +0,0 @@ -/* - * armadillo5x0.c - * - * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * updates in http://alberdroid.blogspot.com/ - * - * Based on Atmark Techno, Inc. armadillo 500 BSP 2008 - * Based on mx31ads.c and pcm037.c Great Work! - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/delay.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/iomux-mx3.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" -#include "crmregs-imx3.h" - -static int armadillo5x0_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* UART2 */ - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - /* LAN9118_IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ - /* I2C2 */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - /* OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /* USB host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), -}; - -/* USB */ - -#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4) -#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6) -#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3) - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbotg_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - /* Chip already enabled by hardware */ - /* OTG phy reset*/ - err = gpio_request(OTG_RESET, "USB-OTG-RESET"); - if (err) { - pr_err("Failed to request the usb otg reset gpio\n"); - return err; - } - - err = gpio_direction_output(OTG_RESET, 1/*HIGH*/); - if (err) { - pr_err("Failed to reset the usb otg phy\n"); - goto otg_free_reset; - } - - gpio_set_value(OTG_RESET, 0/*LOW*/); - mdelay(5); - gpio_set_value(OTG_RESET, 1/*HIGH*/); - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); - -otg_free_reset: - gpio_free(OTG_RESET); - return err; -} - -static int usbh2_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - - /* Enable the chip */ - err = gpio_request(USBH2_CS, "USB-H2-CS"); - if (err) { - pr_err("Failed to request the usb host 2 CS gpio\n"); - return err; - } - - err = gpio_direction_output(USBH2_CS, 0/*Enabled*/); - if (err) { - pr_err("Failed to drive the usb host 2 CS gpio\n"); - goto h2_free_cs; - } - - /* H2 phy reset*/ - err = gpio_request(USBH2_RESET, "USB-H2-RESET"); - if (err) { - pr_err("Failed to request the usb host 2 reset gpio\n"); - goto h2_free_cs; - } - - err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/); - if (err) { - pr_err("Failed to reset the usb host 2 phy\n"); - goto h2_free_reset; - } - - gpio_set_value(USBH2_RESET, 0/*LOW*/); - mdelay(5); - gpio_set_value(USBH2_RESET, 1/*HIGH*/); - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); - -h2_free_reset: - gpio_free(USBH2_RESET); -h2_free_cs: - gpio_free(USBH2_CS); - return err; -} - -static struct mxc_usbh_platform_data usbotg_pdata __initdata = { - .init = usbotg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* RTC over I2C*/ -#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) - -static struct i2c_board_info armadillo5x0_i2c_rtc = { - I2C_BOARD_INFO("s35390a", 0x30), -}; - -/* GPIO BUTTONS */ -static struct gpio_keys_button armadillo5x0_buttons[] = { - { - .code = KEY_ENTER, /*28*/ - .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0), - .active_low = 1, - .desc = "menu", - .wakeup = 1, - }, { - .code = KEY_BACK, /*158*/ - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0), - .active_low = 1, - .desc = "back", - .wakeup = 1, - } -}; - -static const struct gpio_keys_platform_data - armadillo5x0_button_data __initconst = { - .buttons = armadillo5x0_buttons, - .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), -}; - -/* - * NAND Flash - */ -static const struct mxc_nand_platform_data -armadillo5x0_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -/* - * MTD NOR Flash - */ -static struct mtd_partition armadillo5x0_nor_flash_partitions[] = { - { - .name = "nor.bootloader", - .offset = 0x00000000, - .size = 4*32*1024, - }, { - .name = "nor.kernel", - .offset = MTDPART_OFS_APPEND, - .size = 16*128*1024, - }, { - .name = "nor.userland", - .offset = MTDPART_OFS_APPEND, - .size = 110*128*1024, - }, { - .name = "nor.config", - .offset = MTDPART_OFS_APPEND, - .size = 1*128*1024, - }, -}; - -static const struct physmap_flash_data - armadillo5x0_nor_flash_pdata __initconst = { - .width = 2, - .parts = armadillo5x0_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), -}; - -static const struct resource armadillo5x0_nor_flash_resource __initconst = { - .flags = IORESOURCE_MEM, - .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 640x480 @ 60 Hz */ - .name = "CRT-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 35, - .right_margin = 115, - .upper_margin = 43, - .lower_margin = 1, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, {/* 800x600 @ 56 Hz */ - .name = "CRT-SVGA", - .refresh = 56, - .xres = 800, - .yres = 600, - .pixclock = 30000, - .left_margin = 30, - .right_margin = 108, - .upper_margin = 13, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "CRT-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* - * SDHC 1 - * MMC support - */ -static int armadillo5x0_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static int armadillo5x0_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - int gpio_det, gpio_wp; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B); - - ret = gpio_request(gpio_det, "sdhc-card-detect"); - if (ret) - return ret; - - gpio_direction_input(gpio_det); - - ret = gpio_request(gpio_wp, "sdhc-write-protect"); - if (ret) - goto err_gpio_free; - - gpio_direction_input(gpio_wp); - - /* When supported the trigger type have to be BOTH */ - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(gpio_wp); - -err_gpio_free: - gpio_free(gpio_det); - - return ret; - -} - -static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .get_ro = armadillo5x0_sdhc1_get_ro, - .init = armadillo5x0_sdhc1_init, - .exit = armadillo5x0_sdhc1_exit, -}; - -/* - * SMSC 9118 - * Network support - */ -static struct resource armadillo5x0_smc911x_resources[] = { - { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device armadillo5x0_smc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources), - .resource = armadillo5x0_smc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -/* UART device data */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &armadillo5x0_smc911x_device, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -/* - * Perform board specific initializations - */ -static void __init armadillo5x0_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(armadillo5x0_pins, - ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx_add_gpio_keys(&armadillo5x0_button_data); - imx31_add_imx_i2c1(NULL); - - /* Register UART */ - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); - - /* SMSC9118 IRQ pin */ - gpio_direction_input(MX31_PIN_GPIO1_0); - - /* Register SDHC */ - imx31_add_mxc_mmc(0, &sdhc_pdata); - - /* Register FB */ - imx31_add_ipu_core(&mx3_ipu_data); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* Register NOR Flash */ - platform_device_register_resndata(NULL, "physmap-flash", -1, - &armadillo5x0_nor_flash_resource, 1, - &armadillo5x0_nor_flash_pdata, - sizeof(armadillo5x0_nor_flash_pdata)); - - /* Register NAND Flash */ - imx31_add_mxc_nand(&armadillo5x0_nand_board_info); - - /* set NAND page size to 2k if not configured via boot mode pins */ - __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); - - /* RTC */ - /* Get RTC IRQ and register the chip */ - if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) { - if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0) - armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO); - else - gpio_free(ARMADILLO5X0_RTC_GPIO); - } - if (armadillo5x0_i2c_rtc.irq == 0) - pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); - i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); - - /* USB */ - - usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbotg_pdata.otg) - imx31_add_mxc_ehci_otg(&usbotg_pdata); - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -static void __init armadillo5x0_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer armadillo5x0_timer = { - .init = armadillo5x0_timer_init, -}; - -MACHINE_START(ARMADILLO5X0, "Armadillo-500") - /* Maintainer: Alberto Panizzo */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &armadillo5x0_timer, - .init_machine = armadillo5x0_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-bug.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-bug.c deleted file mode 100644 index 9a989774..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-bug.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <mach/iomux-mx3.h> -#include <mach/hardware.h> -#include <mach/common.h> - -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include "devices-imx31.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const unsigned int bug_pins[] __initconst = { - MX31_PIN_PC_RST__CTS5, - MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, - MX31_PIN_PC_BVD1__RXD5, -}; - -static void __init bug_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(bug_pins, - ARRAY_SIZE(bug_pins), "uart-4"); - imx31_add_imx_uart4(&uart_pdata); -} - -static void __init bug_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer bug_timer = { - .init = bug_timer_init, -}; - -MACHINE_START(BUG, "BugLabs BUGBase") - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &bug_timer, - .init_machine = bug_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx27.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx27.c deleted file mode 100644 index d085aea0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx27.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (C) 2009 Eric Benard - eric@eukrea.com - * - * Based on pcm038.c which is : - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/io.h> -#include <linux/mtd/plat-ram.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <mach/eukrea-baseboards.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx27.h> -#include <mach/ulpi.h> - -#include "devices-imx27.h" - -static const int eukrea_cpuimx27_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART4 */ -#if defined(MACH_EUKREA_CPUIMX27_USEUART4) - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, -#endif - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* SDHC2 */ -#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -#endif -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) - /* Quad UART's IRQ */ - GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN, - GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN, - GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN, - GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN, -#endif - /* OTG */ - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* USBH2 */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, -}; - -static struct physmap_flash_data eukrea_cpuimx27_flash_data = { - .width = 2, -}; - -static struct resource eukrea_cpuimx27_flash_resource = { - .start = 0xc0000000, - .end = 0xc3ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device eukrea_cpuimx27_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &eukrea_cpuimx27_flash_data, - }, - .num_resources = 1, - .resource = &eukrea_cpuimx27_flash_resource, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -cpuimx27_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct platform_device *platform_devices[] __initdata = { - &eukrea_cpuimx27_nor_mtd_device, -}; - -static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) -static struct plat_serial8250_port serial_platform_data[] = { - { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000), - .irq = IRQ_GPIOB(23), - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000), - .irq = IRQ_GPIOB(22), - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000), - .irq = IRQ_GPIOB(27), - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000), - .irq = IRQ_GPIOB(30), - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - } -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_platform_data, - }, -}; -#endif - -static int eukrea_cpuimx27_otg_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = eukrea_cpuimx27_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = eukrea_cpuimx27_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static int otg_mode_host; - -static int __init eukrea_cpuimx27_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", eukrea_cpuimx27_otg_mode); - -static void __init eukrea_cpuimx27_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, - ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27"); - - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_mxc_nand(&cpuimx27_nand_board_info); - - i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); - - imx27_add_imx_i2c(0, &cpuimx27_i2c1_data); - - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx27_add_imx2_wdt(NULL); - imx27_add_mxc_w1(NULL); - -#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) - /* SDHC2 can be used for Wifi */ - imx27_add_mxc_mmc(1, NULL); -#endif -#if defined(MACH_EUKREA_CPUIMX27_USEUART4) - /* in which case UART4 is also used for Bluetooth */ - imx27_add_imx_uart3(&uart_pdata); -#endif - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) - platform_device_register(&serial_device); -#endif - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } else { - imx27_add_fsl_usb2_udc(&otg_device_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); - -#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD - eukrea_mbimx27_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx27_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer eukrea_cpuimx27_timer = { - .init = eukrea_cpuimx27_timer_init, -}; - -MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &eukrea_cpuimx27_timer, - .init_machine = eukrea_cpuimx27_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx35.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx35.c deleted file mode 100644 index 8ecc872b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx35.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * Copyright (C) 2009 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/i2c/tsc2007.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/i2c-gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <mach/eukrea-baseboards.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx35.h> - -#include "devices-imx35.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data - eukrea_cpuimx35_i2c0_data __initconst = { - .bitrate = 100000, -}; - -#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2) -static int tsc2007_get_pendown_state(void) -{ - return !gpio_get_value(TSC2007_IRQGPIO); -} - -static struct tsc2007_platform_data tsc2007_info = { - .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = tsc2007_get_pendown_state, -}; - -static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("tsc2007", 0x48), - .type = "tsc2007", - .platform_data = &tsc2007_info, - .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO), - }, -}; - -static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* TSC2007 IRQ */ - MX35_PAD_ATA_DA2__GPIO3_2, -}; - -static const struct mxc_nand_platform_data - eukrea_cpuimx35_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static int eukrea_cpuimx35_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static const struct mxc_usbh_platform_data otg_pdata __initconst = { - .init = eukrea_cpuimx35_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = eukrea_cpuimx35_usbh1_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -}; - -static int otg_mode_host; - -static int __init eukrea_cpuimx35_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", eukrea_cpuimx35_otg_mode); - -/* - * Board specific initialization. - */ -static void __init eukrea_cpuimx35_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, - ARRAY_SIZE(eukrea_cpuimx35_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(NULL); - - imx35_add_imx_uart0(&uart_pdata); - imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); - - i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx35_i2c_devices)); - imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); - - if (otg_mode_host) - imx35_add_mxc_ehci_otg(&otg_pdata); - else - imx35_add_fsl_usb2_udc(&otg_device_pdata); - - imx35_add_mxc_ehci_hs(&usbh1_pdata); - -#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD - eukrea_mbimxsd35_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx35_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer eukrea_cpuimx35_timer = { - .init = eukrea_cpuimx35_timer_init, -}; - -MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") - /* Maintainer: Eukrea Electromatique */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .timer = &eukrea_cpuimx35_timer, - .init_machine = eukrea_cpuimx35_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx51.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx51.c deleted file mode 100644 index 944025da..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx51.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * - * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> - * - * based on board-mx51_babbage.c which is - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/interrupt.h> - -#include <mach/eukrea-baseboards.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" - -#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) -#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) -#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) -#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) -#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) -#define CPUIMX51_QUART_XTAL 14745600 -#define CPUIMX51_QUART_REGSHIFT 17 - -/* USB_CTRL_1 */ -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) - -#define MX51_USB_PLLDIV_12_MHZ 0x00 -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 -#define MX51_USB_PLL_DIV_24_MHZ 0x02 - -static struct plat_serial8250_port serial_platform_data[] = { - { - .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), - .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO), - .irqflags = IRQF_TRIGGER_HIGH, - .uartclk = CPUIMX51_QUART_XTAL, - .regshift = CPUIMX51_QUART_REGSHIFT, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), - .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO), - .irqflags = IRQF_TRIGGER_HIGH, - .uartclk = CPUIMX51_QUART_XTAL, - .regshift = CPUIMX51_QUART_REGSHIFT, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), - .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO), - .irqflags = IRQF_TRIGGER_HIGH, - .uartclk = CPUIMX51_QUART_XTAL, - .regshift = CPUIMX51_QUART_REGSHIFT, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), - .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO), - .irqflags = IRQF_TRIGGER_HIGH, - .uartclk = CPUIMX51_QUART_XTAL, - .regshift = CPUIMX51_QUART_REGSHIFT, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - } -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static struct platform_device *devices[] __initdata = { - &serial_device, -}; - -static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* I2C2 */ - MX51_PAD_GPIO1_2__I2C2_SCL, - MX51_PAD_GPIO1_3__I2C2_SDA, - MX51_PAD_NANDF_D10__GPIO3_30, - - /* QUART IRQ */ - MX51_PAD_NANDF_D15__GPIO3_25, - MX51_PAD_NANDF_D14__GPIO3_26, - MX51_PAD_NANDF_D13__GPIO3_27, - MX51_PAD_NANDF_D12__GPIO3_28, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - MX51_PAD_USBH1_STP__USBH1_STP, -}; - -static const struct mxc_nand_platform_data - eukrea_cpuimx51_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const -struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -/* This function is board specific as the bit mask for the plldiv will also -be different for other Freescale SoCs, thus a common bitmask is not -possible and cannot get place in /plat-mxc/ehci.c.*/ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* The clock for the USBH1 ULPI port will come externally from the PHY. */ - v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_ITC_NO_THRESHOLD); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -static const struct mxc_usbh_platform_data usbh1_config __initconst = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int otg_mode_host; - -static int __init eukrea_cpuimx51_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", eukrea_cpuimx51_otg_mode); - -/* - * Board specific initialization. - */ -static void __init eukrea_cpuimx51_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, - ARRAY_SIZE(eukrea_cpuimx51_pads)); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info); - - gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); - gpio_direction_input(CPUIMX51_QUARTA_GPIO); - gpio_free(CPUIMX51_QUARTA_GPIO); - gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq"); - gpio_direction_input(CPUIMX51_QUARTB_GPIO); - gpio_free(CPUIMX51_QUARTB_GPIO); - gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq"); - gpio_direction_input(CPUIMX51_QUARTC_GPIO); - gpio_free(CPUIMX51_QUARTC_GPIO); - gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq"); - gpio_direction_input(CPUIMX51_QUARTD_GPIO); - gpio_free(CPUIMX51_QUARTD_GPIO); - - imx51_add_fec(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data); - i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); - - if (otg_mode_host) - imx51_add_mxc_ehci_otg(&dr_utmi_config); - else { - initialize_otg_port(NULL); - imx51_add_fsl_usb2_udc(&usb_pdata); - } - imx51_add_mxc_ehci_hs(1, &usbh1_config); - -#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD - eukrea_mbimx51_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx51_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mxc_timer = { - .init = eukrea_cpuimx51_timer_init, -}; - -MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") - /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mxc_timer, - .init_machine = eukrea_cpuimx51_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx51sd.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx51sd.c deleted file mode 100644 index 9fbe923c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-cpuimx51sd.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * - * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> - * - * based on board-mx51_babbage.c which is - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/i2c/tsc2007.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/i2c-gpio.h> -#include <linux/spi/spi.h> -#include <linux/can/platform/mcp251x.h> - -#include <mach/eukrea-baseboards.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "cpu_op-mx51.h" - -#define USBH1_RST IMX_GPIO_NR(2, 28) -#define ETH_RST IMX_GPIO_NR(2, 31) -#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12) -#define CAN_IRQGPIO IMX_GPIO_NR(1, 1) -#define CAN_RST IMX_GPIO_NR(4, 15) -#define CAN_NCS IMX_GPIO_NR(4, 24) -#define CAN_RXOBF IMX_GPIO_NR(1, 4) -#define CAN_RX1BF IMX_GPIO_NR(1, 6) -#define CAN_TXORTS IMX_GPIO_NR(1, 7) -#define CAN_TX1RTS IMX_GPIO_NR(1, 8) -#define CAN_TX2RTS IMX_GPIO_NR(1, 9) -#define I2C_SCL IMX_GPIO_NR(4, 16) -#define I2C_SDA IMX_GPIO_NR(4, 17) - -/* USB_CTRL_1 */ -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) - -#define MX51_USB_PLLDIV_12_MHZ 0x00 -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 -#define MX51_USB_PLL_DIV_24_MHZ 0x02 - -static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */ - - /* FEC */ - MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */ - - /* HSI2C */ - MX51_PAD_I2C1_CLK__GPIO4_16, - MX51_PAD_I2C1_DAT__GPIO4_17, - - /* CAN */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */ - MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */ - MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */ - MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */ - MX51_PAD_GPIO1_6__GPIO1_6, - MX51_PAD_GPIO1_7__GPIO1_7, - MX51_PAD_GPIO1_8__GPIO1_8, - MX51_PAD_GPIO1_9__GPIO1_9, - - /* Touchscreen */ - /* IRQ */ - NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct tsc2007_platform_data tsc2007_info = { - .model = 2007, - .x_plate_ohms = 180, -}; - -static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("tsc2007", 0x49), - .type = "tsc2007", - .platform_data = &tsc2007_info, - .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO), - }, -}; - -static const struct mxc_nand_platform_data - eukrea_cpuimx51sd_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -/* This function is board specific as the bit mask for the plldiv will also -be different for other Freescale SoCs, thus a common bitmask is not -possible and cannot get place in /plat-mxc/ehci.c.*/ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* The clock for the USBH1 ULPI port will come from the PHY. */ - v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, - usbother_base + MX51_USB_CTRL_1_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_ITC_NO_THRESHOLD); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -static const struct mxc_usbh_platform_data usbh1_config __initconst = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int otg_mode_host; - -static int __init eukrea_cpuimx51sd_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode); - -static struct i2c_gpio_platform_data pdata = { - .sda_pin = I2C_SDA, - .sda_is_open_drain = 0, - .scl_pin = I2C_SCL, - .scl_is_open_drain = 0, - .udelay = 2, -}; - -static struct platform_device hsi2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev.platform_data = &pdata, -}; - -static struct mcp251x_platform_data mcp251x_info = { - .oscillator_frequency = 24E6, -}; - -static struct spi_board_info cpuimx51sd_spi_device[] = { - { - .modalias = "mcp2515", - .max_speed_hz = 10000000, - .bus_num = 0, - .mode = SPI_MODE_0, - .chip_select = 0, - .platform_data = &mcp251x_info, - .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO) - }, -}; - -static int cpuimx51sd_spi1_cs[] = { - CAN_NCS, -}; - -static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = { - .chipselect = cpuimx51sd_spi1_cs, - .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs), -}; - -static struct platform_device *platform_devices[] __initdata = { - &hsi2c_gpio_device, -}; - -static void __init eukrea_cpuimx51sd_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, - ARRAY_SIZE(eukrea_cpuimx51sd_pads)); - -#if defined(CONFIG_CPU_FREQ_IMX) - get_cpu_op = mx51_get_cpu_op; -#endif - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); - - gpio_request(ETH_RST, "eth_rst"); - gpio_set_value(ETH_RST, 1); - imx51_add_fec(NULL); - - gpio_request(CAN_IRQGPIO, "can_irq"); - gpio_direction_input(CAN_IRQGPIO); - gpio_free(CAN_IRQGPIO); - gpio_request(CAN_NCS, "can_ncs"); - gpio_direction_output(CAN_NCS, 1); - gpio_free(CAN_NCS); - gpio_request(CAN_RST, "can_rst"); - gpio_direction_output(CAN_RST, 0); - msleep(20); - gpio_set_value(CAN_RST, 1); - imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata); - spi_register_board_info(cpuimx51sd_spi_device, - ARRAY_SIZE(cpuimx51sd_spi_device)); - - gpio_request(TSC2007_IRQGPIO, "tsc2007_irq"); - gpio_direction_input(TSC2007_IRQGPIO); - gpio_free(TSC2007_IRQGPIO); - - i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices)); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - - if (otg_mode_host) - imx51_add_mxc_ehci_otg(&dr_utmi_config); - else { - initialize_otg_port(NULL); - imx51_add_fsl_usb2_udc(&usb_pdata); - } - - gpio_request(USBH1_RST, "usb_rst"); - gpio_direction_output(USBH1_RST, 0); - msleep(20); - gpio_set_value(USBH1_RST, 1); - imx51_add_mxc_ehci_hs(1, &usbh1_config); - -#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD - eukrea_mbimxsd51_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx51sd_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mxc_timer = { - .init = eukrea_cpuimx51sd_timer_init, -}; - -MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") - /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mxc_timer, - .init_machine = eukrea_cpuimx51sd_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-eukrea_cpuimx25.c deleted file mode 100644 index 76a97a59..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> - * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <mach/eukrea-baseboards.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> -#include <mach/common.h> -#include <mach/mx25.h> -#include <mach/iomux-mx25.h> - -#include "devices-imx25.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = { - /* FEC - RMII */ - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - /* I2C1 */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, -}; - -static const struct fec_platform_data mx25_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct mxc_nand_platform_data -eukrea_cpuimx25_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static const struct imxi2c_platform_data -eukrea_cpuimx25_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -static int eukrea_cpuimx25_otg_init(struct platform_device *pdev) -{ - return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static const struct mxc_usbh_platform_data otg_pdata __initconst = { - .init = eukrea_cpuimx25_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev) -{ - return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { - .init = eukrea_cpuimx25_usbh2_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -static int otg_mode_host; - -static int __init eukrea_cpuimx25_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", eukrea_cpuimx25_otg_mode); - -static void __init eukrea_cpuimx25_init(void) -{ - imx25_soc_init(); - - if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, - ARRAY_SIZE(eukrea_cpuimx25_pads))) - printk(KERN_ERR "error setting cpuimx25 pads !\n"); - - imx25_add_imx_uart0(&uart_pdata); - imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); - imx25_add_imxdi_rtc(NULL); - imx25_add_fec(&mx25_fec_pdata); - - i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); - imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); - - if (otg_mode_host) - imx25_add_mxc_ehci_otg(&otg_pdata); - else - imx25_add_fsl_usb2_udc(&otg_device_pdata); - - imx25_add_mxc_ehci_hs(&usbh2_pdata); - -#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD - eukrea_mbimxsd25_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx25_timer_init(void) -{ - mx25_clocks_init(); -} - -static struct sys_timer eukrea_cpuimx25_timer = { - .init = eukrea_cpuimx25_timer_init, -}; - -MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") - /* Maintainer: Eukrea Electromatique */ - .atag_offset = 0x100, - .map_io = mx25_map_io, - .init_early = imx25_init_early, - .init_irq = mx25_init_irq, - .handle_irq = imx25_handle_irq, - .timer = &eukrea_cpuimx25_timer, - .init_machine = eukrea_cpuimx25_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27_visstrim_m10.c deleted file mode 100644 index f7b074f4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ /dev/null @@ -1,422 +0,0 @@ -/* - * mach-imx27_visstrim_m10.c - * - * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com> - * - * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/i2c/pca953x.h> -#include <linux/input.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/leds.h> -#include <linux/memblock.h> -#include <media/soc_camera.h> -#include <sound/tlv320aic32x4.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/common.h> -#include <mach/iomux-mx27.h> - -#include "devices-imx27.h" - -#define TVP5150_RSTN (GPIO_PORTC + 18) -#define TVP5150_PWDN (GPIO_PORTC + 19) -#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) -#define SDHC1_IRQ IRQ_GPIOB(25) - -static const int visstrim_m10_pins[] __initconst = { - /* UART1 (console) */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* Both I2Cs */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* USB OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC9_PF_USBOTG_DATA0, - PC11_PF_USBOTG_DATA1, - PC10_PF_USBOTG_DATA2, - PC13_PF_USBOTG_DATA3, - PC12_PF_USBOTG_DATA4, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PE25_PF_USBOTG_DATA7, - PE24_PF_USBOTG_CLK, - PE2_PF_USBOTG_DIR, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PB23_PF_USB_PWR, - PB24_PF_USB_OC, - /* CSI */ - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, -}; - -/* Camera */ -static int visstrim_camera_power(struct device *dev, int on) -{ - gpio_set_value(TVP5150_PWDN, on); - - return 0; -}; - -static int visstrim_camera_reset(struct device *dev) -{ - gpio_set_value(TVP5150_RSTN, 0); - ndelay(500); - gpio_set_value(TVP5150_RSTN, 1); - - return 0; -}; - -static struct i2c_board_info visstrim_i2c_camera = { - I2C_BOARD_INFO("tvp5150", 0x5d), -}; - -static struct soc_camera_link iclink_tvp5150 = { - .bus_id = 0, - .board_info = &visstrim_i2c_camera, - .i2c_adapter_id = 0, - .power = visstrim_camera_power, - .reset = visstrim_camera_reset, -}; - -static struct mx2_camera_platform_data visstrim_camera = { - .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | - MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING, - .clk = 100000, -}; - -static phys_addr_t mx2_camera_base __initdata; -#define MX2_CAMERA_BUF_SIZE SZ_8M - -static void __init visstrim_camera_init(void) -{ - struct platform_device *pdev; - int dma; - - /* Initialize tvp5150 gpios */ - mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT); - mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT); - gpio_set_value(TVP5150_RSTN, 1); - gpio_set_value(TVP5150_PWDN, 0); - ndelay(1); - - gpio_set_value(TVP5150_PWDN, 1); - ndelay(1); - gpio_set_value(TVP5150_RSTN, 0); - ndelay(500); - gpio_set_value(TVP5150_RSTN, 1); - ndelay(200000); - - pdev = imx27_add_mx2_camera(&visstrim_camera); - if (IS_ERR(pdev)) - return; - - dma = dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base, mx2_camera_base, - MX2_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - return; -} - -static void __init visstrim_reserve(void) -{ - /* reserve 4 MiB for mx2-camera */ - mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE); - memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE); - memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE); -} - -/* GPIOs used as events for applications */ -static struct gpio_keys_button visstrim_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_RESTART, - .gpio = (GPIO_PORTC + 15), - .desc = "Default config", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_RECORD, - .gpio = (GPIO_PORTF + 14), - .desc = "Record", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_STOP, - .gpio = (GPIO_PORTF + 13), - .desc = "Stop", - .active_low = 0, - .wakeup = 1, - } -}; - -static const struct gpio_keys_platform_data - visstrim_gpio_keys_platform_data __initconst = { - .buttons = visstrim_gpio_keys, - .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), -}; - -/* led */ -static const struct gpio_led visstrim_m10_leds[] __initconst = { - { - .name = "visstrim:ld0", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 29), - }, - { - .name = "visstrim:ld1", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 24), - }, - { - .name = "visstrim:ld2", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 28), - }, - { - .name = "visstrim:ld3", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 25), - }, -}; - -static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = { - .leds = visstrim_m10_leds, - .num_leds = ARRAY_SIZE(visstrim_m10_leds), -}; - -/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ -static int visstrim_m10_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING, - "mmc-detect", data); - return ret; -} - -static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(SDHC1_IRQ, data); -} - -static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { - .init = visstrim_m10_sdhc1_init, - .exit = visstrim_m10_sdhc1_exit, -}; - -/* Visstrim_SM10 NOR flash */ -static struct physmap_flash_data visstrim_m10_flash_data = { - .width = 2, -}; - -static struct resource visstrim_m10_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device visstrim_m10_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &visstrim_m10_flash_data, - }, - .num_resources = 1, - .resource = &visstrim_m10_flash_resource, -}; - -static struct platform_device *platform_devices[] __initdata = { - &visstrim_m10_nor_mtd_device, -}; - -/* Visstrim_M10 uses UART0 as console */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* I2C */ -static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { - .gpio_base = 240, /* After MX27 internal GPIOs */ - .invert = 0, -}; - -static struct aic32x4_pdata visstrim_m10_aic32x4_pdata = { - .power_cfg = AIC32X4_PWR_MICBIAS_2075_LDOIN | - AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE | - AIC32X4_PWR_AIC32X4_LDO_ENABLE | - AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 | - AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED, - .micpga_routing = AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K | - AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K, - .swapdacs = false, -}; - -static struct i2c_board_info visstrim_m10_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9555", 0x20), - .platform_data = &visstrim_m10_pca9555_pdata, - }, - { - I2C_BOARD_INFO("tlv320aic32x4", 0x18), - .platform_data = &visstrim_m10_aic32x4_pdata, - }, - { - I2C_BOARD_INFO("m41t00", 0x68), - } -}; - -/* USB OTG */ -static int otg_phy_init(struct platform_device *pdev) -{ - gpio_set_value(OTG_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static const struct mxc_usbh_platform_data -visstrim_m10_usbotg_pdata __initconst = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* SSI */ -static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = { - .flags = IMX_SSI_DMA | IMX_SSI_SYN, -}; - -static void __init visstrim_m10_board_init(void) -{ - int ret; - - imx27_soc_init(); - - ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, - ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); - if (ret) - pr_err("Failed to setup pins (%d)\n", ret); - - imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata); - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); - imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); - i2c_register_board_info(0, visstrim_m10_i2c_devices, - ARRAY_SIZE(visstrim_m10_i2c_devices)); - - imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); - imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); - imx27_add_fec(NULL); - imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0); - platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0, - &iclink_tvp5150, sizeof(iclink_tvp5150)); - gpio_led_register_device(0, &visstrim_m10_led_data); - visstrim_camera_init(); -} - -static void __init visstrim_m10_timer_init(void) -{ - mx27_clocks_init((unsigned long)25000000); -} - -static struct sys_timer visstrim_m10_timer = { - .init = visstrim_m10_timer_init, -}; - -MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") - .atag_offset = 0x100, - .reserve = visstrim_reserve, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &visstrim_m10_timer, - .init_machine = visstrim_m10_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27ipcam.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27ipcam.c deleted file mode 100644 index c9d350c5..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27ipcam.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx27.h> - -#include "devices-imx27.h" - -static const int mx27ipcam_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, -}; - -static void __init mx27ipcam_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins), - "mx27ipcam"); - - imx27_add_imx_uart0(NULL); - imx27_add_fec(NULL); - imx27_add_imx2_wdt(NULL); -} - -static void __init mx27ipcam_timer_init(void) -{ - mx27_clocks_init(25000000); -} - -static struct sys_timer mx27ipcam_timer = { - .init = mx27ipcam_timer_init, -}; - -MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &mx27ipcam_timer, - .init_machine = mx27ipcam_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27lite.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27lite.c deleted file mode 100644 index 1f45b918..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx27lite.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx27.h> - -#include "devices-imx27.h" - -static const int mx27lite_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mx27lite_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), - "imx27lite"); - imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); -} - -static void __init mx27lite_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer mx27lite_timer = { - .init = mx27lite_timer_init, -}; - -MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &mx27lite_timer, - .init_machine = mx27lite_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx6q.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx6q.c deleted file mode 100644 index da6c1d9a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-imx6q.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <linux/phy.h> -#include <linux/micrel_phy.h> -#include <asm/smp_twd.h> -#include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/system_misc.h> -#include <mach/common.h> -#include <mach/hardware.h> - -void imx6q_restart(char mode, const char *cmd) -{ - struct device_node *np; - void __iomem *wdog_base; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); - wdog_base = of_iomap(np, 0); - if (!wdog_base) - goto soft; - - imx_src_prepare_restart(); - - /* enable wdog */ - writew_relaxed(1 << 2, wdog_base); - /* write twice to ensure the request will not get ignored */ - writew_relaxed(1 << 2, wdog_base); - - /* wait for reset to assert ... */ - mdelay(500); - - pr_err("Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); - -soft: - /* we'll take a jump through zero as a poor second */ - soft_restart(0); -} - -/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ -static int ksz9021rn_phy_fixup(struct phy_device *phydev) -{ - /* min rx data delay */ - phy_write(phydev, 0x0b, 0x8105); - phy_write(phydev, 0x0c, 0x0000); - - /* max rx/tx clock delay, min rx/tx control delay */ - phy_write(phydev, 0x0b, 0x8104); - phy_write(phydev, 0x0c, 0xf0f0); - phy_write(phydev, 0x0b, 0x104); - - return 0; -} - -static void __init imx6q_init_machine(void) -{ - if (of_machine_is_compatible("fsl,imx6q-sabrelite")) - phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, - ksz9021rn_phy_fixup); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - imx6q_pm_init(); -} - -static void __init imx6q_map_io(void) -{ - imx_lluart_map_io(); - imx_scu_map_io(); - imx6q_clock_map_io(); -} - -static int __init imx6q_gpio_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - - gpio_irq_base -= 32; - irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, - NULL); - - return 0; -} - -static const struct of_device_id imx6q_irq_match[] __initconst = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - { .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, }, - { /* sentinel */ } -}; - -static void __init imx6q_init_irq(void) -{ - l2x0_of_init(0, ~0UL); - imx_src_init(); - imx_gpc_init(); - of_irq_init(imx6q_irq_match); -} - -static void __init imx6q_timer_init(void) -{ - mx6q_clocks_init(); - twd_local_timer_of_register(); -} - -static struct sys_timer imx6q_timer = { - .init = imx6q_timer_init, -}; - -static const char *imx6q_dt_compat[] __initdata = { - "fsl,imx6q-arm2", - "fsl,imx6q-sabrelite", - "fsl,imx6q", - NULL, -}; - -DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)") - .map_io = imx6q_map_io, - .init_irq = imx6q_init_irq, - .handle_irq = imx6q_handle_irq, - .timer = &imx6q_timer, - .init_machine = imx6q_init_machine, - .dt_compat = imx6q_dt_compat, - .restart = imx6q_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-kzm_arm11_01.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-kzm_arm11_01.c deleted file mode 100644 index 15a26e90..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * KZM-ARM11-01 support - * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> - * - * based on code for MX31ADS, - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/smsc911x.h> -#include <linux/types.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/irq.h> -#include <asm/mach-types.h> -#include <asm/memory.h> -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include <mach/clock.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx3.h> - -#include "devices-imx31.h" - -#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ - IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ - IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \ - MX31_IO_ADDRESS(x)) - -/* - * KZM-ARM11-01 Board Control Registers on FPGA - */ -#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) - -/* - * External UART for touch panel on FPGA - */ -#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) -/* - * KZM-ARM11-01 has an external UART on FPGA - */ -static struct plat_serial8250_port serial_platform_data[] = { - { - .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550), - .mapbase = KZM_ARM11_16550, - .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), - .irqflags = IRQ_TYPE_EDGE_RISING, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_BUGGY_UART, - }, - {}, -}; - -static struct resource serial8250_resources[] = { - { - .start = KZM_ARM11_16550, - .end = KZM_ARM11_16550 + 0x10, - .flags = IORESOURCE_MEM, - }, - { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, - .num_resources = ARRAY_SIZE(serial8250_resources), - .resource = serial8250_resources, -}; - -static int __init kzm_init_ext_uart(void) -{ - u8 tmp; - - /* - * GPIO 1-1: external UART interrupt line - */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* - * Unmask UART interrupt - */ - tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); - tmp |= 0x2; - __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); - - return platform_device_register(&serial_device); -} -#else -static inline int kzm_init_ext_uart(void) -{ - return 0; -} -#endif - -/* - * SMSC LAN9118 - */ -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -static struct smsc911x_platform_config kzm_smsc9118_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, -}; - -static struct resource kzm_smsc9118_resources[] = { - { - .start = MX31_CS5_BASE_ADDR, - .end = MX31_CS5_BASE_ADDR + SZ_128K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device kzm_smsc9118_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(kzm_smsc9118_resources), - .resource = kzm_smsc9118_resources, - .dev = { - .platform_data = &kzm_smsc9118_config, - }, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static int __init kzm_init_smsc9118(void) -{ - /* - * GPIO 1-2: SMSC9118 interrupt line - */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - return platform_device_register(&kzm_smsc9118_device); -} -#else -static inline int kzm_init_smsc9118(void) -{ - return 0; -} -#endif - -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init kzm_init_imx_uart(void) -{ - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); -} -#else -static inline void kzm_init_imx_uart(void) -{ -} -#endif - -static int kzm_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_DCD_DCE1__DCD_DCE1, - MX31_PIN_RI_DCE1__RI_DCE1, - MX31_PIN_DSR_DCE1__DSR_DCE1, - MX31_PIN_DTR_DCE1__DTR_DCE1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_DCD_DTE1__DCD_DTE2, - MX31_PIN_RI_DTE1__RI_DTE2, - MX31_PIN_DSR_DTE1__DSR_DTE2, - MX31_PIN_DTR_DTE1__DTR_DTE2, -}; - -/* - * Board specific initialization. - */ -static void __init kzm_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(kzm_pins, - ARRAY_SIZE(kzm_pins), "kzm"); - kzm_init_ext_uart(); - kzm_init_smsc9118(); - kzm_init_imx_uart(); - - pr_info("Clock input source is 26MHz\n"); -} - -/* - * This structure defines static mappings for the kzm-arm11-01 board. - */ -static struct map_desc kzm_io_desc[] __initdata = { - { - .virtual = MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = MX31_CS4_SIZE, - .type = MT_DEVICE - }, - { - .virtual = MX31_CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), - .length = MX31_CS5_SIZE, - .type = MT_DEVICE - }, -}; - -/* - * Set up static virtual mappings. - */ -static void __init kzm_map_io(void) -{ - mx31_map_io(); - iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc)); -} - -static void __init kzm_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer kzm_timer = { - .init = kzm_timer_init, -}; - -MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") - .atag_offset = 0x100, - .map_io = kzm_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &kzm_timer, - .init_machine = kzm_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx1ads.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx1ads.c deleted file mode 100644 index 97046088..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx1ads.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * arch/arm/mach-imx/mach-mx1ads.c - * - * Initially based on: - * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c - * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/i2c.h> -#include <linux/i2c/pcf857x.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx1.h> -#include <mach/irqs.h> - -#include "devices-imx1.h" - -static const int mx1ads_pins[] __initconst = { - /* UART1 */ - PC9_PF_UART1_CTS, - PC10_PF_UART1_RTS, - PC11_PF_UART1_TXD, - PC12_PF_UART1_RXD, - /* UART2 */ - PB28_PF_UART2_CTS, - PB29_PF_UART2_RTS, - PB30_PF_UART2_TXD, - PB31_PF_UART2_RXD, - /* I2C */ - PA15_PF_I2C_SDA, - PA16_PF_I2C_SCL, - /* SPI */ - PC13_PF_SPI1_SPI_RDY, - PC14_PF_SPI1_SCLK, - PC15_PF_SPI1_SS, - PC16_PF_SPI1_MISO, - PC17_PF_SPI1_MOSI, -}; - -/* - * UARTs platform data - */ - -static const struct imxuart_platform_data uart0_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxuart_platform_data uart1_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* - * Physmap flash - */ - -static const struct physmap_flash_data mx1ads_flash_data __initconst = { - .width = 4, /* bankwidth in bytes */ -}; - -static const struct resource flash_resource __initconst = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -/* - * I2C - */ -static struct pcf857x_platform_data pcf857x_data[] = { - { - .gpio_base = 4 * 32, - }, { - .gpio_base = 4 * 32 + 16, - } -}; - -static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mx1ads_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8575", 0x22), - .platform_data = &pcf857x_data[0], - }, { - I2C_BOARD_INFO("pcf8575", 0x24), - .platform_data = &pcf857x_data[1], - }, -}; - -/* - * Board init - */ -static void __init mx1ads_init(void) -{ - imx1_soc_init(); - - mxc_gpio_setup_multiple_pins(mx1ads_pins, - ARRAY_SIZE(mx1ads_pins), "mx1ads"); - - /* UART */ - imx1_add_imx_uart0(&uart0_pdata); - imx1_add_imx_uart1(&uart1_pdata); - - /* Physmap flash */ - platform_device_register_resndata(NULL, "physmap-flash", 0, - &flash_resource, 1, - &mx1ads_flash_data, sizeof(mx1ads_flash_data)); - - /* I2C */ - i2c_register_board_info(0, mx1ads_i2c_devices, - ARRAY_SIZE(mx1ads_i2c_devices)); - - imx1_add_imx_i2c(&mx1ads_i2c_data); -} - -static void __init mx1ads_timer_init(void) -{ - mx1_clocks_init(32000); -} - -struct sys_timer mx1ads_timer = { - .init = mx1ads_timer_init, -}; - -MACHINE_START(MX1ADS, "Freescale MX1ADS") - /* Maintainer: Sascha Hauer, Pengutronix */ - .atag_offset = 0x100, - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .timer = &mx1ads_timer, - .init_machine = mx1ads_init, - .restart = mxc_restart, -MACHINE_END - -MACHINE_START(MXLADS, "Freescale MXLADS") - .atag_offset = 0x100, - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .timer = &mx1ads_timer, - .init_machine = mx1ads_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx21ads.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx21ads.c deleted file mode 100644 index 4460d25f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx21ads.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/physmap.h> -#include <linux/gpio.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <mach/iomux-mx21.h> - -#include "devices-imx21.h" - -/* - * Memory-mapped I/O on MX21ADS base board - */ -#define MX21ADS_MMIO_BASE_ADDR 0xf5000000 -#define MX21ADS_MMIO_SIZE 0xc00000 - -#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ - (MX21ADS_MMIO_BASE_ADDR + (offset)) - -#define MX21ADS_CS8900A_MMIO_SIZE 0x200000 -#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) -#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) -#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) -#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) - -/* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP 0x0001 /* read */ -#define MX21ADS_IO_TP6 0x0001 /* write */ -#define MX21ADS_IO_SW_SEL 0x0002 /* read */ -#define MX21ADS_IO_TP7 0x0002 /* write */ -#define MX21ADS_IO_RESET_E_UART 0x0004 -#define MX21ADS_IO_RESET_BASE 0x0008 -#define MX21ADS_IO_CSI_CTL2 0x0010 -#define MX21ADS_IO_CSI_CTL1 0x0020 -#define MX21ADS_IO_CSI_CTL0 0x0040 -#define MX21ADS_IO_UART1_EN 0x0080 -#define MX21ADS_IO_UART4_EN 0x0100 -#define MX21ADS_IO_LCDON 0x0200 -#define MX21ADS_IO_IRDA_EN 0x0400 -#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 -#define MX21ADS_IO_IRDA_MD0_B 0x1000 -#define MX21ADS_IO_IRDA_MD1 0x2000 -#define MX21ADS_IO_LED4_ON 0x4000 -#define MX21ADS_IO_LED3_ON 0x8000 - -static const int mx21ads_pins[] __initconst = { - - /* CS8900A */ - (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), - - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - - /* UART3 (IrDA) - only TXD and RXD */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - - /* UART4 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - - /* LCDC */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA24_PF_REV, /* Sharp panel dedicated signal */ - PA25_PF_CLS, /* Sharp panel dedicated signal */ - PA26_PF_PS, /* Sharp panel dedicated signal */ - PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */ - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - - /* MMC/SDHC */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - - /* NFC */ - PF0_PF_NRFB, - PF1_PF_NFCE, - PF2_PF_NFWP, - PF3_PF_NFCLE, - PF4_PF_NFALE, - PF5_PF_NFRE, - PF6_PF_NFWE, - PF7_PF_NFIO0, - PF8_PF_NFIO1, - PF9_PF_NFIO2, - PF10_PF_NFIO3, - PF11_PF_NFIO4, - PF12_PF_NFIO5, - PF13_PF_NFIO6, - PF14_PF_NFIO7, -}; - -/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */ -static struct physmap_flash_data mx21ads_flash_data = { - .width = 4, -}; - -static struct resource mx21ads_flash_resource = { - .start = MX21_CS0_BASE_ADDR, - .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx21ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx21ads_flash_data, - }, - .num_resources = 1, - .resource = &mx21ads_flash_resource, -}; - -static const struct resource mx21ads_cs8900_resources[] __initconst = { - DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), - DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ), -}; - -static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = { - .name = "cs89x0", - .id = 0, - .res = mx21ads_cs8900_resources, - .num_res = ARRAY_SIZE(mx21ads_cs8900_resources), -}; - -static const struct imxuart_platform_data uart_pdata_rts __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxuart_platform_data uart_pdata_norts __initconst = { -}; - -static int mx21ads_fb_init(struct platform_device *pdev) -{ - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp |= MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); - return 0; -} - -static void mx21ads_fb_exit(struct platform_device *pdev) -{ - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp &= ~MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); -} - -/* - * Connected is a portrait Sharp-QVGA display - * of type: LQ035Q7DB02 - */ -static struct imx_fb_videomode mx21ads_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 2, - .left_margin = 6, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 8, - .lower_margin = 10, - }, - .pcr = 0xfb108bc7, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { - .mode = mx21ads_modes, - .num_modes = ARRAY_SIZE(mx21ads_modes), - - .pwmr = 0x00a903ff, - .lscr1 = 0x00120300, - .dmacr = 0x00020008, - - .init = mx21ads_fb_init, - .exit = mx21ads_fb_exit, -}; - -static int mx21ads_sdhc_get_ro(struct device *dev) -{ - return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; -} - -static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(IRQ_GPIOD(25), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); -} - -static void mx21ads_sdhc_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOD(25), data); -} - -static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { - .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ - .get_ro = mx21ads_sdhc_get_ro, - .init = mx21ads_sdhc_init, - .exit = mx21ads_sdhc_exit, -}; - -static const struct mxc_nand_platform_data -mx21ads_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct map_desc mx21ads_io_desc[] __initdata = { - /* - * Memory-mapped I/O on MX21ADS Base board: - * - CS8900A Ethernet controller - * - ST16C2552CJ UART - * - CPU and Base board version - * - Base board I/O register - */ - { - .virtual = MX21ADS_MMIO_BASE_ADDR, - .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR), - .length = MX21ADS_MMIO_SIZE, - .type = MT_DEVICE, - }, -}; - -static void __init mx21ads_map_io(void) -{ - mx21_map_io(); - iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc)); -} - -static struct platform_device *platform_devices[] __initdata = { - &mx21ads_nor_mtd_device, -}; - -static void __init mx21ads_board_init(void) -{ - imx21_soc_init(); - - mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), - "mx21ads"); - - imx21_add_imx_uart0(&uart_pdata_rts); - imx21_add_imx_uart2(&uart_pdata_norts); - imx21_add_imx_uart3(&uart_pdata_rts); - imx21_add_imx_fb(&mx21ads_fb_data); - imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); - imx21_add_mxc_nand(&mx21ads_nand_board_info); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - platform_device_register_full( - (struct platform_device_info *)&mx21ads_cs8900_devinfo); -} - -static void __init mx21ads_timer_init(void) -{ - mx21_clocks_init(32768, 26000000); -} - -static struct sys_timer mx21ads_timer = { - .init = mx21ads_timer_init, -}; - -MACHINE_START(MX21ADS, "Freescale i.MX21ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx21ads_map_io, - .init_early = imx21_init_early, - .init_irq = mx21_init_irq, - .handle_irq = imx21_handle_irq, - .timer = &mx21ads_timer, - .init_machine = mx21ads_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx25_3ds.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx25_3ds.c deleted file mode 100644 index f2673429..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx25_3ds.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -/* - * This machine is known as: - * - i.MX25 3-Stack Development System - * - i.MX25 Platform Development Kit (i.MX25 PDK) - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/usb/otg.h> - -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> -#include <mach/common.h> -#include <mach/mx25.h> -#include <mach/iomux-mx25.h> - -#include "devices-imx25.h" - -#define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6) - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static iomux_v3_cfg_t mx25pdk_pads[] = { - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */ - MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */ - - /* LCD */ - MX25_PAD_LD0__LD0, - MX25_PAD_LD1__LD1, - MX25_PAD_LD2__LD2, - MX25_PAD_LD3__LD3, - MX25_PAD_LD4__LD4, - MX25_PAD_LD5__LD5, - MX25_PAD_LD6__LD6, - MX25_PAD_LD7__LD7, - MX25_PAD_LD8__LD8, - MX25_PAD_LD9__LD9, - MX25_PAD_LD10__LD10, - MX25_PAD_LD11__LD11, - MX25_PAD_LD12__LD12, - MX25_PAD_LD13__LD13, - MX25_PAD_LD14__LD14, - MX25_PAD_LD15__LD15, - MX25_PAD_GPIO_E__LD16, - MX25_PAD_GPIO_F__LD17, - MX25_PAD_HSYNC__HSYNC, - MX25_PAD_VSYNC__VSYNC, - MX25_PAD_LSCLK__LSCLK, - MX25_PAD_OE_ACD__OE_ACD, - MX25_PAD_CONTRAST__CONTRAST, - - /* Keypad */ - MX25_PAD_KPP_ROW0__KPP_ROW0, - MX25_PAD_KPP_ROW1__KPP_ROW1, - MX25_PAD_KPP_ROW2__KPP_ROW2, - MX25_PAD_KPP_ROW3__KPP_ROW3, - MX25_PAD_KPP_COL0__KPP_COL0, - MX25_PAD_KPP_COL1__KPP_COL1, - MX25_PAD_KPP_COL2__KPP_COL2, - MX25_PAD_KPP_COL3__KPP_COL3, - - /* SD1 */ - MX25_PAD_SD1_CMD__SD1_CMD, - MX25_PAD_SD1_CLK__SD1_CLK, - MX25_PAD_SD1_DATA0__SD1_DATA0, - MX25_PAD_SD1_DATA1__SD1_DATA1, - MX25_PAD_SD1_DATA2__SD1_DATA2, - MX25_PAD_SD1_DATA3__SD1_DATA3, - MX25_PAD_A14__GPIO_2_0, /* WriteProtect */ - MX25_PAD_A15__GPIO_2_1, /* CardDetect */ - - /* I2C1 */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, - - /* CAN1 */ - MX25_PAD_GPIO_A__CAN1_TX, - MX25_PAD_GPIO_B__CAN1_RX, - MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */ -}; - -static const struct fec_platform_data mx25_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3) -#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8) - -static void __init mx25pdk_fec_reset(void) -{ - gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable"); - gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset"); - - gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ - gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ - udelay(2); - - /* turn on PHY power and lift reset */ - gpio_set_value(FEC_ENABLE_GPIO, 1); - gpio_set_value(FEC_RESET_B_GPIO, 1); -} - -static const struct mxc_nand_platform_data -mx25pdk_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct imx_fb_videomode mx25pdk_modes[] = { - { - .mode = { - .name = "CRT-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39683, - .left_margin = 45, - .right_margin = 114, - .upper_margin = 33, - .lower_margin = 11, - .hsync_len = 1, - .vsync_len = 1, - }, - .bpp = 16, - .pcr = 0xFA208B80, - }, -}; - -static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = { - .mode = mx25pdk_modes, - .num_modes = ARRAY_SIZE(mx25pdk_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static const uint32_t mx25pdk_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(0, 2, KEY_VOLUMEDOWN), - KEY(0, 3, KEY_HOME), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(1, 3, KEY_VOLUMEUP), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), - KEY(3, 0, KEY_F1), - KEY(3, 1, KEY_F2), - KEY(3, 2, KEY_F3), - KEY(3, 3, KEY_POWER), -}; - -static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = { - .keymap = mx25pdk_keymap, - .keymap_size = ARRAY_SIZE(mx25pdk_keymap), -}; - -static int mx25pdk_usbh2_init(struct platform_device *pdev) -{ - return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { - .init = mx25pdk_usbh2_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -#define SD1_GPIO_WP IMX_GPIO_NR(2, 0) -#define SD1_GPIO_CD IMX_GPIO_NR(2, 1) - -static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = { - .wp_gpio = SD1_GPIO_WP, - .cd_gpio = SD1_GPIO_CD, - .wp_type = ESDHC_WP_GPIO, - .cd_type = ESDHC_CD_GPIO, -}; - -static void __init mx25pdk_init(void) -{ - imx25_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, - ARRAY_SIZE(mx25pdk_pads)); - - imx25_add_imx_uart0(&uart_pdata); - imx25_add_fsl_usb2_udc(&otg_device_pdata); - imx25_add_mxc_ehci_hs(&usbh2_pdata); - imx25_add_mxc_nand(&mx25pdk_nand_board_info); - imx25_add_imxdi_rtc(NULL); - imx25_add_imx_fb(&mx25pdk_fb_pdata); - imx25_add_imx2_wdt(NULL); - - mx25pdk_fec_reset(); - imx25_add_fec(&mx25_fec_pdata); - imx25_add_imx_keypad(&mx25pdk_keymap_data); - - imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata); - imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); - - gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn"); - imx25_add_flexcan0(NULL); -} - -static void __init mx25pdk_timer_init(void) -{ - mx25_clocks_init(); -} - -static struct sys_timer mx25pdk_timer = { - .init = mx25pdk_timer_init, -}; - -MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx25_map_io, - .init_early = imx25_init_early, - .init_irq = mx25_init_irq, - .handle_irq = imx25_handle_irq, - .timer = &mx25pdk_timer, - .init_machine = mx25pdk_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx27_3ds.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx27_3ds.c deleted file mode 100644 index c6d385c5..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx27_3ds.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This machine is known as: - * - i.MX27 3-Stack Development System - * - i.MX27 Platform Development Kit (i.MX27 PDK) - */ - -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/delay.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/regulator/machine.h> -#include <linux/spi/l4f00242t03.h> - -#include <media/soc_camera.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx27.h> -#include <mach/ulpi.h> -#include <mach/irqs.h> -#include <mach/3ds_debugboard.h> - -#include "devices-imx27.h" - -#define SD1_EN_GPIO IMX_GPIO_NR(2, 25) -#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23) -#define SPI2_SS0 IMX_GPIO_NR(4, 21) -#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28)) -#define PMIC_INT IMX_GPIO_NR(3, 14) -#define SPI1_SS0 IMX_GPIO_NR(4, 28) -#define SD1_CD IMX_GPIO_NR(2, 26) -#define LCD_RESET IMX_GPIO_NR(1, 3) -#define LCD_ENABLE IMX_GPIO_NR(1, 31) -#define CSI_PWRDWN IMX_GPIO_NR(4, 19) -#define CSI_RESET IMX_GPIO_NR(3, 6) - -static const int mx27pdk_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, - /* OTG */ - OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* CSPI1 */ - PD31_PF_CSPI1_MOSI, - PD30_PF_CSPI1_MISO, - PD29_PF_CSPI1_SCLK, - PD25_PF_CSPI1_RDY, - SPI1_SS0 | GPIO_GPIO | GPIO_OUT, - /* CSPI2 */ - PD22_PF_CSPI2_SCLK, - PD23_PF_CSPI2_MISO, - PD24_PF_CSPI2_MOSI, - SPI2_SS0 | GPIO_GPIO | GPIO_OUT, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* PMIC INT */ - PMIC_INT | GPIO_GPIO | GPIO_IN, - /* LCD */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - LCD_ENABLE | GPIO_GPIO | GPIO_OUT, - LCD_RESET | GPIO_GPIO | GPIO_OUT, - /* CSI */ - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, - CSI_PWRDWN | GPIO_GPIO | GPIO_OUT, - CSI_RESET | GPIO_GPIO | GPIO_OUT, -}; - -static struct gpio mx27_3ds_camera_gpios[] = { - { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" }, - { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" }, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* - * Matrix keyboard - */ - -static const uint32_t mx27_3ds_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), -}; - -static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { - .keymap = mx27_3ds_keymap, - .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), -}; - -static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(SD1_CD), detect_irq, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); -} - -static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SD1_CD), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mx27_3ds_sdhc1_init, - .exit = mx27_3ds_sdhc1_exit, -}; - -static void mx27_3ds_sdhc1_enable_level_translator(void) -{ - /* Turn on TXB0108 OE pin */ - gpio_request(SD1_EN_GPIO, "sd1_enable"); - gpio_direction_output(SD1_EN_GPIO, 1); -} - - -static int otg_phy_init(void) -{ - gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); - gpio_direction_output(OTG_PHY_RESET_GPIO, 0); - mdelay(1); - gpio_set_value(OTG_PHY_RESET_GPIO, 1); - return 0; -} - -static int mx27_3ds_otg_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx27_3ds_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static int otg_mode_host; - -static int __init mx27_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", mx27_3ds_otg_mode); - -/* Regulators */ -static struct regulator_init_data gpo_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("vcore", "spi0.0"), - REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vmmc1_init = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), - .consumer_supplies = vmmc1_consumers, -}; - -static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd", "spi0.0"), -}; - -static struct regulator_init_data vgen_init = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), - .consumer_supplies = vgen_consumers, -}; - -static struct regulator_consumer_supply vvib_consumers[] = { - REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vvib_init = { - .constraints = { - .min_uV = 1300000, - .max_uV = 1300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), - .consumer_supplies = vvib_consumers, -}; - -static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { - { - .id = MC13783_REG_VMMC1, - .init_data = &vmmc1_init, - }, { - .id = MC13783_REG_VGEN, - .init_data = &vgen_init, - }, { - .id = MC13783_REG_GPO1, /* Turn on 1.8V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_GPO3, /* Turn on 3.3V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_VVIB, /* Power OV2640 */ - .init_data = &vvib_init, - }, -}; - -/* MC13783 */ -static struct mc13xxx_platform_data mc13783_pdata = { - .regulators = { - .regulators = mx27_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), - - }, - .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, -}; - -/* SPI */ -static int spi1_chipselect[] = {SPI1_SS0}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi1_chipselect, - .num_chipselect = ARRAY_SIZE(spi1_chipselect), -}; - -static int spi2_chipselect[] = {SPI2_SS0}; - -static const struct spi_imx_master spi2_pdata __initconst = { - .chipselect = spi2_chipselect, - .num_chipselect = ARRAY_SIZE(spi2_chipselect), -}; - -static int mx27_3ds_camera_power(struct device *dev, int on) -{ - /* enable or disable the camera */ - pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); - gpio_set_value(CSI_PWRDWN, on ? 0 : 1); - - if (!on) - goto out; - - /* If enabled, give a reset impulse */ - gpio_set_value(CSI_RESET, 0); - msleep(20); - gpio_set_value(CSI_RESET, 1); - msleep(100); - -out: - return 0; -} - -static struct i2c_board_info mx27_3ds_i2c_camera = { - I2C_BOARD_INFO("ov2640", 0x30), -}; - -static struct regulator_bulk_data mx27_3ds_camera_regs[] = { - { .supply = "cmos_vcore" }, - { .supply = "cmos_2v8" }, -}; - -static struct soc_camera_link iclink_ov2640 = { - .bus_id = 0, - .board_info = &mx27_3ds_i2c_camera, - .i2c_adapter_id = 0, - .power = mx27_3ds_camera_power, - .regulators = mx27_3ds_camera_regs, - .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs), -}; - -static struct platform_device mx27_3ds_ov2640 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_ov2640, - }, -}; - -static struct imx_fb_videomode mx27_3ds_modes[] = { - { /* 480x640 @ 60 Hz */ - .mode = { - .name = "Epson-VGA", - .refresh = 60, - .xres = 480, - .yres = 640, - .pixclock = 41701, - .left_margin = 20, - .right_margin = 41, - .upper_margin = 10, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH | - FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - .bpp = 16, - .pcr = 0xFAC08B82, - }, -}; - -static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { - .mode = mx27_3ds_modes, - .num_modes = ARRAY_SIZE(mx27_3ds_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -/* LCD */ -static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { - .reset_gpio = LCD_RESET, - .data_enable_gpio = LCD_ENABLE, -}; - -static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, /* SS0 */ - .platform_data = &mc13783_pdata, - .irq = IMX_GPIO_TO_IRQ(PMIC_INT), - .mode = SPI_CS_HIGH, - }, { - .modalias = "l4f00242t03", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, /* SS0 */ - .platform_data = &mx27_3ds_lcd_pdata, - }, -}; - -static struct platform_device *devices[] __initdata = { - &mx27_3ds_ov2640, -}; - -static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = { - .clk = 26000000, -}; - -static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static void __init mx27pdk_init(void) -{ - int ret; - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), - "mx27pdk"); - mx27_3ds_sdhc1_enable_level_translator(); - imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); - imx27_add_imx_keypad(&mx27_3ds_keymap_data); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_imx2_wdt(NULL); - otg_phy_init(); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } - - if (!otg_mode_host) - imx27_add_fsl_usb2_udc(&otg_device_pdata); - - imx27_add_spi_imx1(&spi2_pdata); - imx27_add_spi_imx0(&spi1_pdata); - spi_register_board_info(mx27_3ds_spi_devs, - ARRAY_SIZE(mx27_3ds_spi_devs)); - - if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) - pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); - imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx27_add_imx_fb(&mx27_3ds_fb_data); - - ret = gpio_request_array(mx27_3ds_camera_gpios, - ARRAY_SIZE(mx27_3ds_camera_gpios)); - if (ret) { - pr_err("Failed to request camera gpios"); - iclink_ov2640.power = NULL; - } - - imx27_add_mx2_camera(&mx27_3ds_cam_pdata); -} - -static void __init mx27pdk_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer mx27pdk_timer = { - .init = mx27pdk_timer_init, -}; - -MACHINE_START(MX27_3DS, "Freescale MX27PDK") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &mx27pdk_timer, - .init_machine = mx27pdk_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx27ads.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx27ads.c deleted file mode 100644 index 0228d2e0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx27ads.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/irq.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <mach/iomux-mx27.h> - -#include "devices-imx27.h" - -/* - * Base address of PBC controller, CS4 - */ -#define PBC_BASE_ADDRESS 0xf4300000 -#define PBC_REG_ADDR(offset) (void __force __iomem *) \ - (PBC_BASE_ADDRESS + (offset)) - -/* When the PBC address connection is fixed in h/w, defined as 1 */ -#define PBC_ADDR_SH 0 - -/* Offsets for the PBC Controller register */ -/* - * PBC Board version register offset - */ -#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 set address. - */ -#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 clear address. - */ -#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) - -/* PBC Board Control Register 1 bit definitions */ -#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ - -/* to determine the correct external crystal reference */ -#define CKIH_27MHZ_BIT_SET (1 << 3) - -static const int mx27ads_pins[] __initconst = { - /* UART0 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART1 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART2 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* UART3 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - /* UART4 */ - PB18_AF_UART5_TXD, - PB19_AF_UART5_RXD, - PB20_AF_UART5_CTS, - PB21_AF_UART5_RTS, - /* UART5 */ - PB10_AF_UART6_TXD, - PB12_AF_UART6_CTS, - PB11_AF_UART6_RXD, - PB13_AF_UART6_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* FB */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* OWIRE */ - PE16_AF_OWIRE, - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* SDHC2*/ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -}; - -static const struct mxc_nand_platform_data -mx27ads_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -/* ADS's NOR flash */ -static struct physmap_flash_data mx27ads_flash_data = { - .width = 2, -}; - -static struct resource mx27ads_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + 0x02000000 - 1, - .flags = IORESOURCE_MEM, - -}; - -static struct platform_device mx27ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx27ads_flash_data, - }, - .num_resources = 1, - .resource = &mx27ads_flash_resource, -}; - -static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mx27ads_i2c_devices[] = { -}; - -void lcd_power(int on) -{ - if (on) - __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); - else - __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); -} - -static struct imx_fb_videomode mx27ads_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 1, - .left_margin = 9, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - }, - .bpp = 16, - .pcr = 0xFB008BC0, - }, -}; - -static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { - .mode = mx27ads_modes, - .num_modes = ARRAY_SIZE(mx27ads_modes), - - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, - - .lcd_power = lcd_power, -}; - -static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING, - "sdhc1-card-detect", data); -} - -static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING, - "sdhc2-card-detect", data); -} - -static void mx27ads_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOE(21), data); -} - -static void mx27ads_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOB(7), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mx27ads_sdhc1_init, - .exit = mx27ads_sdhc1_exit, -}; - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .init = mx27ads_sdhc2_init, - .exit = mx27ads_sdhc2_exit, -}; - -static struct platform_device *platform_devices[] __initdata = { - &mx27ads_nor_mtd_device, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mx27ads_board_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), - "mx27ads"); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - imx27_add_imx_uart3(&uart_pdata); - imx27_add_imx_uart4(&uart_pdata); - imx27_add_imx_uart5(&uart_pdata); - imx27_add_mxc_nand(&mx27ads_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, mx27ads_i2c_devices, - ARRAY_SIZE(mx27ads_i2c_devices)); - imx27_add_imx_i2c(1, &mx27ads_i2c1_data); - imx27_add_imx_fb(&mx27ads_fb_data); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_mxc_mmc(1, &sdhc2_pdata); - - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx27_add_mxc_w1(NULL); -} - -static void __init mx27ads_timer_init(void) -{ - unsigned long fref = 26000000; - - if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) - fref = 27000000; - - mx27_clocks_init(fref); -} - -static struct sys_timer mx27ads_timer = { - .init = mx27ads_timer_init, -}; - -static struct map_desc mx27ads_io_desc[] __initdata = { - { - .virtual = PBC_BASE_ADDRESS, - .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - -static void __init mx27ads_map_io(void) -{ - mx27_map_io(); - iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); -} - -MACHINE_START(MX27ADS, "Freescale i.MX27ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27ads_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &mx27ads_timer, - .init_machine = mx27ads_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31_3ds.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31_3ds.c deleted file mode 100644 index 4d1aab15..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31_3ds.c +++ /dev/null @@ -1,773 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/spi/l4f00242t03.h> -#include <linux/regulator/machine.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/memblock.h> - -#include <media/soc_camera.h> - -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> -#include <mach/common.h> -#include <mach/iomux-mx3.h> -#include <mach/3ds_debugboard.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" - -/* CPLD IRQ line for external uart, external ethernet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) - -static int mx31_3ds_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), - /*SPI0*/ - IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), - /* SPI 1 */ - MX31_PIN_CSPI2_SCLK__SCLK, - MX31_PIN_CSPI2_MOSI__MOSI, - MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, - MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ - /* MC13783 IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), - /* USB OTG reset */ - IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /*Keyboard*/ - MX31_PIN_KEY_ROW0_KEY_ROW0, - MX31_PIN_KEY_ROW1_KEY_ROW1, - MX31_PIN_KEY_ROW2_KEY_ROW2, - MX31_PIN_KEY_COL0_KEY_COL0, - MX31_PIN_KEY_COL1_KEY_COL1, - MX31_PIN_KEY_COL2_KEY_COL2, - MX31_PIN_KEY_COL3_KEY_COL3, - /* USB Host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), - /* USB Host2 reset */ - IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), - /* I2C1 */ - MX31_PIN_I2C_CLK__I2C1_SCL, - MX31_PIN_I2C_DAT__I2C1_SDA, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ - MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_CONTRAST__CONTRAST, - /* CSI */ - MX31_PIN_CSI_D6__CSI_D6, - MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, - MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, - MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, - MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, - MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, - MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, - MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */ - IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */ -}; - -/* - * Camera support - */ -static phys_addr_t mx3_camera_base __initdata; -#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M - -#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5) -#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1) - -static struct gpio mx31_3ds_camera_gpios[] = { - { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" }, - { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, -}; - -static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = { - .flags = MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 2600, -}; - -static int __init mx31_3ds_init_camera(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev = - imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); - - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - if (!mx3_camera_base) - goto err; - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX31_3DS_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; -} - -static int mx31_3ds_camera_power(struct device *dev, int on) -{ - /* enable or disable the camera */ - pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); - gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1); - - if (!on) - goto out; - - /* If enabled, give a reset impulse */ - gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0); - msleep(20); - gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1); - msleep(100); - -out: - return 0; -} - -static struct i2c_board_info mx31_3ds_i2c_camera = { - I2C_BOARD_INFO("ov2640", 0x30), -}; - -static struct regulator_bulk_data mx31_3ds_camera_regs[] = { - { .supply = "cmos_vcore" }, - { .supply = "cmos_2v8" }, -}; - -static struct soc_camera_link iclink_ov2640 = { - .bus_id = 0, - .board_info = &mx31_3ds_i2c_camera, - .i2c_adapter_id = 0, - .power = mx31_3ds_camera_power, - .regulators = mx31_3ds_camera_regs, - .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs), -}; - -static struct platform_device mx31_3ds_ov2640 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_ov2640, - }, -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 480x640 @ 60 Hz */ - .name = "Epson-VGA", - .refresh = 60, - .xres = 480, - .yres = 640, - .pixclock = 41701, - .left_margin = 20, - .right_margin = 41, - .upper_margin = 10, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct ipu_platform_data mx3_ipu_data = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Epson-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* LCD */ -static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { - .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), - .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), -}; - -/* - * Support for SD card slot in personality board - */ -#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) - -static struct gpio mx31_3ds_sdhc1_gpios[] = { - { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, - { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, -}; - -static int mx31_3ds_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); - if (ret) { - pr_warning("Unable to request the SD/MMC GPIOs.\n"); - return ret; - } - - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), - detect_irq, IRQF_DISABLED | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "sdhc1-detect", data); - if (ret) { - pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); - goto gpio_free; - } - - return 0; - -gpio_free: - gpio_free_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); - return ret; -} - -static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data); - gpio_free_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); -} - -static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) -{ - /* - * While the voltage stuff is done by the driver, activate the - * Buffer Enable Pin only if there is a card in slot to fix the card - * voltage issue caused by bi-directional chip TXB0108 on 3Stack. - * Done here because at this stage we have for sure a debounced value - * of the presence of the card, showed by the value of vdd. - * 7 == ilog2(MMC_VDD_165_195) - */ - if (vdd > 7) - gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); - else - gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); -} - -static struct imxmmc_platform_data sdhc1_pdata = { - .init = mx31_3ds_sdhc1_init, - .exit = mx31_3ds_sdhc1_exit, - .setpower = mx31_3ds_sdhc1_setpower, -}; - -/* - * Matrix keyboard - */ - -static const uint32_t mx31_3ds_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), -}; - -static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { - .keymap = mx31_3ds_keymap, - .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), -}; - -/* Regulators */ -static struct regulator_init_data pwgtx_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - }, -}; - -static struct regulator_init_data gpo_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_consumer_supply vmmc2_consumers[] = { - REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"), -}; - -static struct regulator_init_data vmmc2_init = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), - .consumer_supplies = vmmc2_consumers, -}; - -static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("vcore", "spi0.0"), - REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vmmc1_init = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), - .consumer_supplies = vmmc1_consumers, -}; - -static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd", "spi0.0"), -}; - -static struct regulator_init_data vgen_init = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), - .consumer_supplies = vgen_consumers, -}; - -static struct regulator_consumer_supply vvib_consumers[] = { - REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vvib_init = { - .constraints = { - .min_uV = 1300000, - .max_uV = 1300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), - .consumer_supplies = vvib_consumers, -}; - -static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { - { - .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ - .init_data = &pwgtx_init, - }, { - .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ - .init_data = &pwgtx_init, - }, { - - .id = MC13783_REG_GPO1, /* Turn on 1.8V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_GPO3, /* Turn on 3.3V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ - .init_data = &vmmc2_init, - }, { - .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ - .init_data = &vmmc1_init, - }, { - .id = MC13783_REG_VGEN, /* Power LCD */ - .init_data = &vgen_init, - }, { - .id = MC13783_REG_VVIB, /* Power CMOS */ - .init_data = &vvib_init, - }, -}; - -/* MC13783 */ -static struct mc13xxx_platform_data mc13783_pdata = { - .regulators = { - .regulators = mx31_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - }, - .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, -}; - -/* SPI */ -static int spi0_internal_chipselect[] = { - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi0_pdata __initconst = { - .chipselect = spi0_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect), -}; - -static int spi1_internal_chipselect[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi1_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), -}; - -static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 1, /* SS2 */ - .platform_data = &mc13783_pdata, - .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), - .mode = SPI_CS_HIGH, - }, { - .modalias = "l4f00242t03", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, /* SS2 */ - .platform_data = &mx31_3ds_l4f00242t03_pdata, - }, -}; - -/* - * NAND Flash - */ -static const struct mxc_nand_platform_data -mx31_3ds_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT - .flash_bbt = 1, -#endif -}; - -/* - * USB OTG - */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) -#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) - -static int mx31_3ds_usbotg_init(void) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - err = gpio_request(USBOTG_RST_B, "otgusb-reset"); - if (err) { - pr_err("Failed to request the USB OTG reset gpio\n"); - return err; - } - - err = gpio_direction_output(USBOTG_RST_B, 0); - if (err) { - pr_err("Failed to drive the USB OTG reset gpio\n"); - goto usbotg_free_reset; - } - - mdelay(1); - gpio_set_value(USBOTG_RST_B, 1); - return 0; - -usbotg_free_reset: - gpio_free(USBOTG_RST_B); - return err; -} - -static int mx31_3ds_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static int mx31_3ds_host2_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); - - err = gpio_request(USBH2_RST_B, "usbh2-reset"); - if (err) { - pr_err("Failed to request the USB Host 2 reset gpio\n"); - return err; - } - - err = gpio_direction_output(USBH2_RST_B, 0); - if (err) { - pr_err("Failed to drive the USB Host 2 reset gpio\n"); - goto usbotg_free_reset; - } - - mdelay(1); - gpio_set_value(USBH2_RST_B, 1); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); - -usbotg_free_reset: - gpio_free(USBH2_RST_B); - return err; -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx31_3ds_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = mx31_3ds_host2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static int otg_mode_host; - -static int __init mx31_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", mx31_3ds_otg_mode); - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static struct platform_device *devices[] __initdata = { - &mx31_3ds_ov2640, -}; - -static void __init mx31_3ds_init(void) -{ - int ret; - - imx31_soc_init(); - - /* Configure SPI1 IOMUX */ - mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); - - mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), - "mx31_3ds"); - - imx31_add_imx_uart0(&uart_pdata); - imx31_add_mxc_nand(&mx31_3ds_nand_board_info); - - imx31_add_spi_imx1(&spi1_pdata); - spi_register_board_info(mx31_3ds_spi_devs, - ARRAY_SIZE(mx31_3ds_spi_devs)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx31_add_imx_keypad(&mx31_3ds_keymap_data); - - mx31_3ds_usbotg_init(); - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx31_add_mxc_ehci_otg(&otg_pdata); - } - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - if (!otg_mode_host) - imx31_add_fsl_usb2_udc(&usbotg_pdata); - - if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) - printk(KERN_WARNING "Init of the debug board failed, all " - "devices on the debug board are unusable.\n"); - imx31_add_imx2_wdt(NULL); - imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); - imx31_add_mxc_mmc(0, &sdhc1_pdata); - - imx31_add_spi_imx0(&spi0_pdata); - imx31_add_ipu_core(&mx3_ipu_data); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* CSI */ - /* Camera power: default - off */ - ret = gpio_request_array(mx31_3ds_camera_gpios, - ARRAY_SIZE(mx31_3ds_camera_gpios)); - if (ret) { - pr_err("Failed to request camera gpios"); - iclink_ov2640.power = NULL; - } - - mx31_3ds_init_camera(); -} - -static void __init mx31_3ds_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer mx31_3ds_timer = { - .init = mx31_3ds_timer_init, -}; - -static void __init mx31_3ds_reserve(void) -{ - /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE, - MX31_3DS_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &mx31_3ds_timer, - .init_machine = mx31_3ds_init, - .reserve = mx31_3ds_reserve, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31ads.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31ads.c deleted file mode 100644 index 4518e544..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31ads.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/irq.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> -#include <mach/common.h> -#include <mach/iomux-mx3.h> - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -#include <linux/mfd/wm8350/audio.h> -#include <linux/mfd/wm8350/core.h> -#include <linux/mfd/wm8350/pmic.h> -#endif - -#include "devices-imx31.h" - -/* Base address of PBC controller */ -#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT - -/* PBC Board interrupt status register */ -#define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ -#define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ -#define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ -#define PBC_INTMASK_CLEAR 0x00001C - -/* External UART A */ -#define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ -#define PBC_SC16C652_UARTB 0x010010 - -#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) -#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) -#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) - -#define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) - -#define MXC_MAX_EXP_IO_LINES 16 - -/* CS8900 */ -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define CS4_CS8900_MMIO_START 0x20000 - -/* - * The serial port definition structure. - */ -static struct plat_serial8250_port serial_platform_data[] = { - { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), - .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA), - .irq = EXPIO_INT_XUART_INTA, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), - .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB), - .irq = EXPIO_INT_XUART_INTB, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, - {}, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static const struct resource mx31ads_cs8900_resources[] __initconst = { - DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K), - DEFINE_RES_IRQ(EXPIO_INT_ENET_INT), -}; - -static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = { - .name = "cs89x0", - .id = 0, - .res = mx31ads_cs8900_resources, - .num_res = ARRAY_SIZE(mx31ads_cs8900_resources), -}; - -static int __init mxc_init_extuart(void) -{ - return platform_device_register(&serial_device); -} - -static void __init mxc_init_ext_ethernet(void) -{ - platform_device_register_full( - (struct platform_device_info *)&mx31ads_cs8900_devinfo); -} - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static unsigned int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 -}; - -static inline void mxc_init_imx_uart(void) -{ - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - imx31_add_imx_uart0(&uart_pdata); -} - -static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) -{ - u32 imr_val; - u32 int_valid; - u32 expio_irq; - - imr_val = __raw_readw(PBC_INTMASK_SET_REG); - int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val; - - expio_irq = MXC_EXP_IO_BASE; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - - generic_handle_irq(expio_irq); - } -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param d an expio virtual irq description - */ -static void expio_mask_irq(struct irq_data *d) -{ - u32 expio = MXC_IRQ_TO_EXPIO(d->irq); - /* mask the interrupt */ - __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); - __raw_readw(PBC_INTMASK_CLEAR_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param d an expio virtual irq description - */ -static void expio_ack_irq(struct irq_data *d) -{ - u32 expio = MXC_IRQ_TO_EXPIO(d->irq); - /* clear the interrupt status */ - __raw_writew(1 << expio, PBC_INTSTATUS_REG); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param d an expio virtual irq description - */ -static void expio_unmask_irq(struct irq_data *d) -{ - u32 expio = MXC_IRQ_TO_EXPIO(d->irq); - /* unmask the interrupt */ - __raw_writew(1 << expio, PBC_INTMASK_SET_REG); -} - -static struct irq_chip expio_irq_chip = { - .name = "EXPIO(CPLD)", - .irq_ack = expio_ack_irq, - .irq_mask = expio_mask_irq, - .irq_unmask = expio_unmask_irq, -}; - -static void __init mx31ads_init_expio(void) -{ - int i; - - printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); - - /* - * Configure INT line as GPIO input - */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); - - /* disable the interrupt and clear the status */ - __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); - __raw_writew(0xFFFF, PBC_INTSTATUS_REG); - for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); - i++) { - irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); - irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); -} - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -/* This section defines setup for the Wolfson Microelectronics - * 1133-EV1 PMU/audio board. When other PMU boards are supported the - * regulator definitions may be shared with them, but for now they can - * only be used with this board so would generate warnings about - * unused statics and some of the configuration is specific to this - * module. - */ - -/* CPU */ -static struct regulator_consumer_supply sw1a_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_init_data sw1a_data = { - .constraints = { - .name = "SW1A", - .min_uV = 1275000, - .max_uV = 1600000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .state_mem = { - .uV = 1400000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), - .consumer_supplies = sw1a_consumers, -}; - -/* System IO - High */ -static struct regulator_init_data viohi_data = { - .constraints = { - .name = "VIOHO", - .min_uV = 2800000, - .max_uV = 2800000, - .state_mem = { - .uV = 2800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* System IO - Low */ -static struct regulator_init_data violo_data = { - .constraints = { - .name = "VIOLO", - .min_uV = 1800000, - .max_uV = 1800000, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* DDR RAM */ -static struct regulator_init_data sw2a_data = { - .constraints = { - .name = "SW2A", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .state_disk = { - .mode = REGULATOR_MODE_NORMAL, - .enabled = 0, - }, - .always_on = 1, - .boot_on = 1, - .initial_state = PM_SUSPEND_MEM, - }, -}; - -static struct regulator_init_data ldo1_data = { - .constraints = { - .name = "VCAM/VMMC1/VMMC2", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, -}; - -static struct regulator_consumer_supply ldo2_consumers[] = { - { .supply = "AVDD", .dev_name = "1-001a" }, - { .supply = "HPVDD", .dev_name = "1-001a" }, -}; - -/* CODEC and SIM */ -static struct regulator_init_data ldo2_data = { - .constraints = { - .name = "VESIM/VSIM/AVDD", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), - .consumer_supplies = ldo2_consumers, -}; - -/* General */ -static struct regulator_init_data vdig_data = { - .constraints = { - .name = "VDIG", - .min_uV = 1500000, - .max_uV = 1500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* Tranceivers */ -static struct regulator_init_data ldo4_data = { - .constraints = { - .name = "VRF1/CVDD_2.775", - .min_uV = 2500000, - .max_uV = 2500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - .boot_on = 1, - }, -}; - -static struct wm8350_led_platform_data wm8350_led_data = { - .name = "wm8350:white", - .default_trigger = "heartbeat", - .max_uA = 27899, -}; - -static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { - .vmid_discharge_msecs = 1000, - .drain_msecs = 30, - .cap_discharge_msecs = 700, - .vmid_charge_msecs = 700, - .vmid_s_curve = WM8350_S_CURVE_SLOW, - .dis_out4 = WM8350_DISCHARGE_SLOW, - .dis_out3 = WM8350_DISCHARGE_SLOW, - .dis_out2 = WM8350_DISCHARGE_SLOW, - .dis_out1 = WM8350_DISCHARGE_SLOW, - .vroi_out4 = WM8350_TIE_OFF_500R, - .vroi_out3 = WM8350_TIE_OFF_500R, - .vroi_out2 = WM8350_TIE_OFF_500R, - .vroi_out1 = WM8350_TIE_OFF_500R, - .vroi_enable = 0, - .codec_current_on = WM8350_CODEC_ISEL_1_0, - .codec_current_standby = WM8350_CODEC_ISEL_0_5, - .codec_current_charge = WM8350_CODEC_ISEL_1_5, -}; - -static int mx31_wm8350_init(struct wm8350 *wm8350) -{ - wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, - WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_ON); - - wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, - WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_ON); - - wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, - WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, - WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, - WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, - WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, - WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data); - wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data); - wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data); - wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data); - wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data); - - /* LEDs */ - wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1, - WM8350_DC5_ERRACT_SHUTDOWN_CONV); - wm8350_isink_set_flash(wm8350, WM8350_ISINK_A, - WM8350_ISINK_FLASH_DISABLE, - WM8350_ISINK_FLASH_TRIG_BIT, - WM8350_ISINK_FLASH_DUR_32MS, - WM8350_ISINK_FLASH_ON_INSTANT, - WM8350_ISINK_FLASH_OFF_INSTANT, - WM8350_ISINK_FLASH_MODE_EN); - wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5, - WM8350_ISINK_MODE_BOOST, - WM8350_ISINK_ILIM_NORMAL, - WM8350_DC5_RMP_20V, - WM8350_DC5_FBSRC_ISINKA); - wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A, - &wm8350_led_data); - - wm8350->codec.platform_data = &imx32ads_wm8350_setup; - - regulator_has_full_constraints(); - - return 0; -} - -static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { - .init = mx31_wm8350_init, - .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES, -}; -#endif - -static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 - { - I2C_BOARD_INFO("wm8350", 0x1a), - .platform_data = &mx31_wm8350_pdata, - .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), - }, -#endif -}; - -static void __init mxc_init_i2c(void) -{ - i2c_register_board_info(1, mx31ads_i2c1_devices, - ARRAY_SIZE(mx31ads_i2c1_devices)); - - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); - - imx31_add_imx_i2c1(NULL); -} - -static unsigned int ssi_pins[] = { - MX31_PIN_SFS5__SFS5, - MX31_PIN_SCK5__SCK5, - MX31_PIN_SRXD5__SRXD5, - MX31_PIN_STXD5__STXD5, -}; - -static void __init mxc_init_audio(void) -{ - imx31_add_imx_ssi(0, NULL); - mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); -} - -/* - * Static mappings, starting from the CS4 start address up to the start address - * of the CS8900. - */ -static struct map_desc mx31ads_io_desc[] __initdata = { - { - .virtual = MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = CS4_CS8900_MMIO_START, - .type = MT_DEVICE - }, -}; - -static void __init mx31ads_map_io(void) -{ - mx31_map_io(); - iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); -} - -static void __init mx31ads_init_irq(void) -{ - mx31_init_irq(); - mx31ads_init_expio(); -} - -static void __init mx31ads_init(void) -{ - imx31_soc_init(); - - mxc_init_extuart(); - mxc_init_imx_uart(); - mxc_init_i2c(); - mxc_init_audio(); - mxc_init_ext_ethernet(); -} - -static void __init mx31ads_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer mx31ads_timer = { - .init = mx31ads_timer_init, -}; - -MACHINE_START(MX31ADS, "Freescale MX31ADS") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31ads_map_io, - .init_early = imx31_init_early, - .init_irq = mx31ads_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &mx31ads_timer, - .init_machine = mx31ads_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31lilly.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31lilly.c deleted file mode 100644 index 83714b0c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31lilly.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * LILLY-1131 module support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/moduleparam.h> -#include <linux/smsc911x.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13783.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx3.h> -#include <mach/board-mx31lilly.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" - -/* - * This file contains module-specific initialization routines for LILLY-1131. - * Initialization of peripherals found on the baseboard is implemented in the - * appropriate baseboard support code. - */ - -/* SMSC ethernet support */ - -static struct resource smsc91x_resources[] = { - { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 0xffff, - .flags = IORESOURCE_MEM, - }, - { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, - } -}; - -static struct smsc911x_platform_config smsc911x_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT | - SMSC911X_SAVE_MAC_ADDRESS | - SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc91x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc91x_resources), - .resource = smsc91x_resources, - .dev = { - .platform_data = &smsc911x_config, - } -}; - -/* NOR flash */ -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - -/* USB */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbh1_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_MISO__USBH1_RXDP, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, - MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, - MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -static int usbh2_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_USBH2_CLK__USBH2_CLK, - MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, - MX31_PIN_USBH2_STP__USBH2_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), - "USBH2_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = usbh1_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static void __init lilly1131_usb_init(void) -{ - imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -/* SPI */ - -static int spi_internal_chipselect[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(1), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi0_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, -}; - -static struct spi_board_info mc13783_dev __initdata = { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), -}; - -static struct platform_device *devices[] __initdata = { - &smsc91x_device, - &physmap_flash_device, -}; - -static int mx31lilly_baseboard; -core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static void __init mx31lilly_board_init(void) -{ - imx31_soc_init(); - - switch (mx31lilly_baseboard) { - case MX31LILLY_NOBOARD: - break; - case MX31LILLY_DB: - mx31lilly_db_init(); - break; - default: - printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n", - mx31lilly_baseboard); - } - - mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); - - /* SPI */ - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2"); - - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); - - imx31_add_spi_imx0(&spi0_pdata); - imx31_add_spi_imx1(&spi1_pdata); - spi_register_board_info(&mc13783_dev, 1); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* USB */ - lilly1131_usb_init(); -} - -static void __init mx31lilly_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer mx31lilly_timer = { - .init = mx31lilly_timer_init, -}; - -MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &mx31lilly_timer, - .init_machine = mx31lilly_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31lite.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31lite.c deleted file mode 100644 index 0abef5f1..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31lite.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/memory.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/moduleparam.h> -#include <linux/smsc911x.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/mtd/physmap.h> -#include <linux/delay.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/page.h> -#include <asm/setup.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/board-mx31lite.h> -#include <mach/iomux-mx3.h> -#include <mach/irqs.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" - -/* - * This file contains the module-specific initialization routines. - */ - -static unsigned int mx31lite_pins[] = { - /* LAN9117 IRQ pin */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), - /* SPI 1 */ - MX31_PIN_CSPI2_SCLK__SCLK, - MX31_PIN_CSPI2_MOSI__MOSI, - MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, - MX31_PIN_CSPI2_SS1__SS1, - MX31_PIN_CSPI2_SS2__SS2, -}; - -static const struct mxc_nand_platform_data -mx31lite_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT, -}; - -static struct resource smsc911x_resources[] = { - { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), - .end = IOMUX_TO_IRQ(MX31_PIN_SFS6), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -/* - * SPI - * - * The MC13783 is the only hard-wired SPI device on the module. - */ - -static int spi_internal_chipselect[] = { - MXC_SPI_CS(0), -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .flags = MC13XXX_USE_RTC, -}; - -static struct spi_board_info mc13783_spi_dev __initdata = { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), -}; - -/* - * USB - */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbh2_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_USBH2_CLK__USBH2_CLK, - MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, - MX31_PIN_USBH2_STP__USBH2_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), - "USBH2_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* - * NOR flash - */ - -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - - - -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31lite_io_desc[] __initdata = { - { - .virtual = MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = MX31_CS4_SIZE, - .type = MT_DEVICE - } -}; - -/* - * Set up static virtual mappings. - */ -void __init mx31lite_map_io(void) -{ - mx31_map_io(); - iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); -} - -static int mx31lite_baseboard; -core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static void __init mx31lite_init(void) -{ - int ret; - - imx31_soc_init(); - - switch (mx31lite_baseboard) { - case MX31LITE_NOBOARD: - break; - case MX31LITE_DB: - mx31lite_db_init(); - break; - default: - printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n", - mx31lite_baseboard); - } - - mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), - "mx31lite"); - - /* NOR and NAND flash */ - platform_device_register(&physmap_flash_device); - imx31_add_mxc_nand(&mx31lite_nand_board_info); - - imx31_add_spi_imx1(&spi1_pdata); - spi_register_board_info(&mc13783_spi_dev, 1); - - /* USB */ - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - /* SMSC9117 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - platform_device_register(&smsc911x_device); - } -} - -static void __init mx31lite_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -struct sys_timer mx31lite_timer = { - .init = mx31lite_timer_init, -}; - -MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31lite_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &mx31lite_timer, - .init_machine = mx31lite_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31moboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31moboard.c deleted file mode 100644 index f17a15f2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx31moboard.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/gfp.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/moduleparam.h> -#include <linux/leds.h> -#include <linux/memory.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/types.h> -#include <linux/memblock.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/input.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> -#include <mach/board-mx31moboard.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx3.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" - -static unsigned int moboard_pins[] = { - /* UART0 */ - MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS1__GPIO2_7, - /* UART4 */ - MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, - /* I2C0 */ - MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL, - /* I2C1 */ - MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, - /* USB reset */ - MX31_PIN_GPIO1_0__GPIO1_0, - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, - MX31_PIN_USB_OC__GPIO1_30, - /* USB H2 */ - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3, - MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5, - MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7, - MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP, - MX31_PIN_SCK6__GPIO1_25, - /* LEDs */ - MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, - MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, - /* SPI1 */ - MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2, - /* Atlas IRQ */ - MX31_PIN_GPIO1_3__GPIO1_3, - /* SPI2 */ - MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO, - MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS1__CSPI3_SS1, -}; - -static struct physmap_flash_data mx31moboard_flash_data = { - .width = 2, -}; - -static struct resource mx31moboard_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx31moboard_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx31moboard_flash_data, - }, - .resource = &mx31moboard_flash_resource, - .num_resources = 1, -}; - -static int moboard_uart0_init(struct platform_device *pdev) -{ - int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); - if (ret) - return ret; - - ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - if (ret) - gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); - - return ret; -} - -static void moboard_uart0_exit(struct platform_device *pdev) -{ - gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); -} - -static const struct imxuart_platform_data uart0_pdata __initconst = { - .init = moboard_uart0_init, - .exit = moboard_uart0_exit, -}; - -static const struct imxuart_platform_data uart4_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data moboard_i2c0_data __initconst = { - .bitrate = 400000, -}; - -static const struct imxi2c_platform_data moboard_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static int moboard_spi1_cs[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master moboard_spi1_pdata __initconst = { - .chipselect = moboard_spi1_cs, - .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), -}; - -static struct regulator_consumer_supply sdhc_consumers[] = { - { - .dev_name = "mxc-mmc.0", - .supply = "sdhc0_vcc", - }, - { - .dev_name = "mxc-mmc.1", - .supply = "sdhc1_vcc", - }, -}; - -static struct regulator_init_data sdhc_vreg_data = { - .constraints = { - .min_uV = 2700000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers), - .consumer_supplies = sdhc_consumers, -}; - -static struct regulator_consumer_supply cam_consumers[] = { - { - .dev_name = "mx3_camera.0", - .supply = "cam_vcc", - }, -}; - -static struct regulator_init_data cam_vreg_data = { - .constraints = { - .min_uV = 2700000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(cam_consumers), - .consumer_supplies = cam_consumers, -}; - -static struct mc13xxx_regulator_init_data moboard_regulators[] = { - { - .id = MC13783_REG_VMMC1, - .init_data = &sdhc_vreg_data, - }, - { - .id = MC13783_REG_VCAM, - .init_data = &cam_vreg_data, - }, -}; - -static struct mc13xxx_led_platform_data moboard_led[] = { - { - .id = MC13783_LED_R1, - .name = "coreboard-led-4:red", - .max_current = 2, - }, - { - .id = MC13783_LED_G1, - .name = "coreboard-led-4:green", - .max_current = 2, - }, - { - .id = MC13783_LED_B1, - .name = "coreboard-led-4:blue", - .max_current = 2, - }, - { - .id = MC13783_LED_R2, - .name = "coreboard-led-5:red", - .max_current = 3, - }, - { - .id = MC13783_LED_G2, - .name = "coreboard-led-5:green", - .max_current = 3, - }, - { - .id = MC13783_LED_B2, - .name = "coreboard-led-5:blue", - .max_current = 3, - }, -}; - -static struct mc13xxx_leds_platform_data moboard_leds = { - .num_leds = ARRAY_SIZE(moboard_led), - .led = moboard_led, - .flags = MC13783_LED_SLEWLIMTC, - .abmode = MC13783_LED_AB_DISABLED, - .tc1_period = MC13783_LED_PERIOD_10MS, - .tc2_period = MC13783_LED_PERIOD_10MS, -}; - -static struct mc13xxx_buttons_platform_data moboard_buttons = { - .b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE | - MC13783_BUTTON_POL_INVERT, - .b1on_key = KEY_POWER, -}; - -static struct mc13xxx_platform_data moboard_pmic = { - .regulators = { - .regulators = moboard_regulators, - .num_regulators = ARRAY_SIZE(moboard_regulators), - }, - .leds = &moboard_leds, - .buttons = &moboard_buttons, - .flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC, -}; - -static struct spi_board_info moboard_spi_board_info[] __initdata = { - { - .modalias = "mc13783", - .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &moboard_pmic, - .mode = SPI_CS_HIGH, - }, -}; - -static int moboard_spi2_cs[] = { - MXC_SPI_CS(1), -}; - -static const struct spi_imx_master moboard_spi2_pdata __initconst = { - .chipselect = moboard_spi2_cs, - .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), -}; - -#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) -#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) - -static int moboard_sdhc1_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC1_WP); -} - -static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_CD); - - ret = gpio_request(SDHC1_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_WP); - - ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc1-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC1_WP); -err_gpio_free: - gpio_free(SDHC1_CD); - - return ret; -} - -static void moboard_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC1_CD), data); - gpio_free(SDHC1_WP); - gpio_free(SDHC1_CD); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .get_ro = moboard_sdhc1_get_ro, - .init = moboard_sdhc1_init, - .exit = moboard_sdhc1_exit, -}; - -/* - * this pin is dedicated for all mx31moboard systems, so we do it here - */ -#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS) - -#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) -#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) - -static void usb_xcvr_reset(void) -{ - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - - gpio_request(OTG_EN_B, "usb-udc-en"); - gpio_direction_output(OTG_EN_B, 0); - gpio_request(USBH2_EN_B, "usbh2-en"); - gpio_direction_output(USBH2_EN_B, 0); - - gpio_request(USB_RESET_B, "usb-reset"); - gpio_direction_output(USB_RESET_B, 0); - mdelay(1); - gpio_set_value(USB_RESET_B, 1); - mdelay(1); -} - -static int moboard_usbh2_init_hw(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = moboard_usbh2_init_hw, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static int __init moboard_usbh2_init(void) -{ - struct platform_device *pdev; - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (!usbh2_pdata.otg) - return -ENODEV; - - pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - -static const struct gpio_led mx31moboard_leds[] __initconst = { - { - .name = "coreboard-led-0:red:running", - .default_trigger = "heartbeat", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), - }, { - .name = "coreboard-led-1:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), - }, { - .name = "coreboard-led-2:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0), - }, { - .name = "coreboard-led-3:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0), - }, -}; - -static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = { - .num_leds = ARRAY_SIZE(mx31moboard_leds), - .leds = mx31moboard_leds, -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct platform_device *devices[] __initdata = { - &mx31moboard_flash, -}; - -static struct mx3_camera_pdata camera_pdata __initdata = { - .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 4800, -}; - -static phys_addr_t mx3_camera_base __initdata; -#define MX3_CAMERA_BUF_SIZE SZ_4M - -static int __init mx31moboard_init_cam(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev; - - imx31_add_ipu_core(&mx3_ipu_data); - - pdev = imx31_alloc_mx3_camera(&camera_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX3_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; - -} - -static void mx31moboard_poweroff(void) -{ - struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); - - if (!IS_ERR(clk)) - clk_prepare_enable(clk); - - mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); - - __raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); -} - -static int mx31moboard_baseboard; -core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); - -/* - * Board specific initialization. - */ -static void __init mx31moboard_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), - "moboard"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - gpio_led_register_device(-1, &mx31moboard_led_pdata); - - imx31_add_imx2_wdt(NULL); - - imx31_add_imx_uart0(&uart0_pdata); - imx31_add_imx_uart4(&uart4_pdata); - - imx31_add_imx_i2c0(&moboard_i2c0_data); - imx31_add_imx_i2c1(&moboard_i2c1_data); - - imx31_add_spi_imx1(&moboard_spi1_pdata); - imx31_add_spi_imx2(&moboard_spi2_pdata); - - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(moboard_spi_board_info, - ARRAY_SIZE(moboard_spi_board_info)); - - imx31_add_mxc_mmc(0, &sdhc1_pdata); - - mx31moboard_init_cam(); - - usb_xcvr_reset(); - - moboard_usbh2_init(); - - pm_power_off = mx31moboard_poweroff; - - switch (mx31moboard_baseboard) { - case MX31NOBOARD: - break; - case MX31DEVBOARD: - mx31moboard_devboard_init(); - break; - case MX31MARXBOT: - mx31moboard_marxbot_init(); - break; - case MX31SMARTBOT: - case MX31EYEBOT: - mx31moboard_smartbot_init(mx31moboard_baseboard); - break; - default: - printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", - mx31moboard_baseboard); - } -} - -static void __init mx31moboard_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -struct sys_timer mx31moboard_timer = { - .init = mx31moboard_timer_init, -}; - -static void __init mx31moboard_reserve(void) -{ - /* reserve 4 MiB for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE, - MX3_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") - /* Maintainer: Philippe Retornaz, EPFL Mobots group */ - .atag_offset = 0x100, - .reserve = mx31moboard_reserve, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &mx31moboard_timer, - .init_machine = mx31moboard_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx35_3ds.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx35_3ds.c deleted file mode 100644 index 6ae51c6b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx35_3ds.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * Copyright (C) 2011 Meprolight, Ltd. - * Alex Gershgorin <alexg@meprolight.com> - * - * Modified from i.MX31 3-Stack Development System - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This machine is known as: - * - i.MX35 3-Stack Development System - * - i.MX35 Platform Development Kit (i.MX35 PDK) - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> - -#include <linux/mtd/physmap.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx35.h> -#include <mach/irqs.h> -#include <mach/3ds_debugboard.h> -#include <video/platform_lcd.h> - -#include <media/soc_camera.h> - -#include "devices-imx35.h" - -#define GPIO_MC9S08DZ60_GPS_ENABLE 0 -#define GPIO_MC9S08DZ60_HDD_ENABLE 4 -#define GPIO_MC9S08DZ60_WIFI_ENABLE 5 -#define GPIO_MC9S08DZ60_LCD_ENABLE 6 -#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8 - -static const struct fb_videomode fb_modedb[] = { - { - /* 800x480 @ 55 Hz */ - .name = "Ceramate-CLAA070VC01", - .refresh = 55, - .xres = 800, - .yres = 480, - .pixclock = 40000, - .left_margin = 40, - .right_margin = 40, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Ceramate-CLAA070VC01", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct i2c_board_info __initdata i2c_devices_3ds[] = { - { - I2C_BOARD_INFO("mc9s08dz60", 0x69), - }, -}; - -static int lcd_power_gpio = -ENXIO; - -static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, - const void *data) -{ - return !strcmp(chip->label, data); -} - -static void mx35_3ds_lcd_set_power( - struct plat_lcd_data *pd, unsigned int power) -{ - struct gpio_chip *chip; - - if (!gpio_is_valid(lcd_power_gpio)) { - chip = gpiochip_find( - "mc9s08dz60", mc9s08dz60_gpiochip_match); - if (chip) { - lcd_power_gpio = - chip->base + GPIO_MC9S08DZ60_LCD_ENABLE; - if (gpio_request(lcd_power_gpio, "lcd_power") < 0) { - pr_err("error: gpio already requested!\n"); - lcd_power_gpio = -ENXIO; - } - } else { - pr_err("error: didn't find mc9s08dz60 gpio chip\n"); - } - } - - if (gpio_is_valid(lcd_power_gpio)) - gpio_set_value_cansleep(lcd_power_gpio, power); -} - -static struct plat_lcd_data mx35_3ds_lcd_data = { - .set_power = mx35_3ds_lcd_set_power, -}; - -static struct platform_device mx35_3ds_lcd = { - .name = "platform-lcd", - .dev.platform_data = &mx35_3ds_lcd_data, -}; - -#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1)) - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct physmap_flash_data mx35pdk_flash_data = { - .width = 2, -}; - -static struct resource mx35pdk_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx35pdk_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx35pdk_flash_data, - }, - .resource = &mx35pdk_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct platform_device *devices[] __initdata = { - &mx35pdk_flash, -}; - -static iomux_v3_cfg_t mx35pdk_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* USBH1 */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - /* CSI */ - MX35_PAD_TX1__IPU_CSI_D_6, - MX35_PAD_TX0__IPU_CSI_D_7, - MX35_PAD_CSI_D8__IPU_CSI_D_8, - MX35_PAD_CSI_D9__IPU_CSI_D_9, - MX35_PAD_CSI_D10__IPU_CSI_D_10, - MX35_PAD_CSI_D11__IPU_CSI_D_11, - MX35_PAD_CSI_D12__IPU_CSI_D_12, - MX35_PAD_CSI_D13__IPU_CSI_D_13, - MX35_PAD_CSI_D14__IPU_CSI_D_14, - MX35_PAD_CSI_D15__IPU_CSI_D_15, - MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC, - MX35_PAD_CSI_MCLK__IPU_CSI_MCLK, - MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK, - MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC, -}; - -/* - * Camera support -*/ -static phys_addr_t mx3_camera_base __initdata; -#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M - -static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = { - .flags = MX3_CAMERA_DATAWIDTH_8, - .mclk_10khz = 2000, -}; - -static int __init imx35_3ds_init_camera(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev = - imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata); - - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - if (!mx3_camera_base) - goto err; - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX35_3DS_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; -} - -static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct i2c_board_info mx35_3ds_i2c_camera = { - I2C_BOARD_INFO("ov2640", 0x30), -}; - -static struct soc_camera_link iclink_ov2640 = { - .bus_id = 0, - .board_info = &mx35_3ds_i2c_camera, - .i2c_adapter_id = 0, - .power = NULL, -}; - -static struct platform_device mx35_3ds_ov2640 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_ov2640, - }, -}; - -static int mx35_3ds_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -/* OTG config */ -static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -/* - * ENGCM09152 also requires a hardware change. - * Please check the MX35 Chip Errata document for details. - */ -}; - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx35_3ds_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int mx35_3ds_usbh_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY); -} - -/* USB HOST config */ -static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .init = mx35_3ds_usbh_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static int otg_mode_host; - -static int __init mx35_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", mx35_3ds_otg_mode); - -static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -/* - * Board specific initialization. - */ -static void __init mx35_3ds_init(void) -{ - struct platform_device *imx35_fb_pdev; - - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx35_add_imx_uart0(&uart_pdata); - - if (otg_mode_host) - imx35_add_mxc_ehci_otg(&otg_pdata); - - imx35_add_mxc_ehci_hs(&usb_host_pdata); - - if (!otg_mode_host) - imx35_add_fsl_usb2_udc(&usb_otg_pdata); - - imx35_add_mxc_nand(&mx35pdk_nand_board_info); - imx35_add_sdhci_esdhc_imx(0, NULL); - - if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) - pr_warn("Init of the debugboard failed, all " - "devices on the debugboard are unusable.\n"); - imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); - - i2c_register_board_info( - 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds)); - - imx35_add_ipu_core(&mx35_3ds_ipu_data); - platform_device_register(&mx35_3ds_ov2640); - imx35_3ds_init_camera(); - - imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata); - mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev; - platform_device_register(&mx35_3ds_lcd); -} - -static void __init mx35pdk_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer mx35pdk_timer = { - .init = mx35pdk_timer_init, -}; - -static void __init mx35_3ds_reserve(void) -{ - /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE, - MX35_3DS_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX35_3DS, "Freescale MX35PDK") - /* Maintainer: Freescale Semiconductor, Inc */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .timer = &mx35pdk_timer, - .init_machine = mx35_3ds_init, - .reserve = mx35_3ds_reserve, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx50_rdp.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx50_rdp.c deleted file mode 100644 index 42b66e8d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx50_rdp.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx50.h> - -#include <asm/irq.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx50.h" - -#define FEC_EN IMX_GPIO_NR(6, 23) -#define FEC_RESET_B IMX_GPIO_NR(4, 12) - -static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { - /* SD1 */ - MX50_PAD_ECSPI2_SS0__GPIO_4_19, - MX50_PAD_EIM_CRE__GPIO_1_27, - MX50_PAD_SD1_CMD__SD1_CMD, - - MX50_PAD_SD1_CLK__SD1_CLK, - MX50_PAD_SD1_D0__SD1_D0, - MX50_PAD_SD1_D1__SD1_D1, - MX50_PAD_SD1_D2__SD1_D2, - MX50_PAD_SD1_D3__SD1_D3, - - /* SD2 */ - MX50_PAD_SD2_CD__GPIO_5_17, - MX50_PAD_SD2_WP__GPIO_5_16, - MX50_PAD_SD2_CMD__SD2_CMD, - MX50_PAD_SD2_CLK__SD2_CLK, - MX50_PAD_SD2_D0__SD2_D0, - MX50_PAD_SD2_D1__SD2_D1, - MX50_PAD_SD2_D2__SD2_D2, - MX50_PAD_SD2_D3__SD2_D3, - MX50_PAD_SD2_D4__SD2_D4, - MX50_PAD_SD2_D5__SD2_D5, - MX50_PAD_SD2_D6__SD2_D6, - MX50_PAD_SD2_D7__SD2_D7, - - /* SD3 */ - MX50_PAD_SD3_CMD__SD3_CMD, - MX50_PAD_SD3_CLK__SD3_CLK, - MX50_PAD_SD3_D0__SD3_D0, - MX50_PAD_SD3_D1__SD3_D1, - MX50_PAD_SD3_D2__SD3_D2, - MX50_PAD_SD3_D3__SD3_D3, - MX50_PAD_SD3_D4__SD3_D4, - MX50_PAD_SD3_D5__SD3_D5, - MX50_PAD_SD3_D6__SD3_D6, - MX50_PAD_SD3_D7__SD3_D7, - - /* PWR_INT */ - MX50_PAD_ECSPI2_MISO__GPIO_4_18, - - /* UART pad setting */ - MX50_PAD_UART1_TXD__UART1_TXD, - MX50_PAD_UART1_RXD__UART1_RXD, - MX50_PAD_UART1_RTS__UART1_RTS, - MX50_PAD_UART2_TXD__UART2_TXD, - MX50_PAD_UART2_RXD__UART2_RXD, - MX50_PAD_UART2_CTS__UART2_CTS, - MX50_PAD_UART2_RTS__UART2_RTS, - - MX50_PAD_I2C1_SCL__I2C1_SCL, - MX50_PAD_I2C1_SDA__I2C1_SDA, - MX50_PAD_I2C2_SCL__I2C2_SCL, - MX50_PAD_I2C2_SDA__I2C2_SDA, - - MX50_PAD_EPITO__USBH1_PWR, - /* Need to comment below line if - * one needs to debug owire. - */ - MX50_PAD_OWIRE__USBH1_OC, - /* using gpio to control otg pwr */ - MX50_PAD_PWM2__GPIO_6_25, - MX50_PAD_I2C3_SCL__USBOTG_OC, - - MX50_PAD_SSI_RXC__FEC_MDIO, - MX50_PAD_SSI_RXFS__FEC_MDC, - MX50_PAD_DISP_D0__FEC_TXCLK, - MX50_PAD_DISP_D1__FEC_RX_ER, - MX50_PAD_DISP_D2__FEC_RX_DV, - MX50_PAD_DISP_D3__FEC_RXD1, - MX50_PAD_DISP_D4__FEC_RXD0, - MX50_PAD_DISP_D5__FEC_TX_EN, - MX50_PAD_DISP_D6__FEC_TXD1, - MX50_PAD_DISP_D7__FEC_TXD0, - MX50_PAD_I2C3_SDA__GPIO_6_23, - MX50_PAD_ECSPI1_SCLK__GPIO_4_12, - - MX50_PAD_CSPI_SS0__CSPI_SS0, - MX50_PAD_ECSPI1_MOSI__CSPI_SS1, - MX50_PAD_CSPI_MOSI__CSPI_MOSI, - MX50_PAD_CSPI_MISO__CSPI_MISO, - - /* SGTL500_OSC_EN */ - MX50_PAD_UART1_CTS__GPIO_6_8, - - /* SGTL_AMP_SHDN */ - MX50_PAD_UART3_RXD__GPIO_6_15, - - /* Keypad */ - MX50_PAD_KEY_COL0__KEY_COL0, - MX50_PAD_KEY_ROW0__KEY_ROW0, - MX50_PAD_KEY_COL1__KEY_COL1, - MX50_PAD_KEY_ROW1__KEY_ROW1, - MX50_PAD_KEY_COL2__KEY_COL2, - MX50_PAD_KEY_ROW2__KEY_ROW2, - MX50_PAD_KEY_COL3__KEY_COL3, - MX50_PAD_KEY_ROW3__KEY_ROW3, - MX50_PAD_EIM_DA0__KEY_COL4, - MX50_PAD_EIM_DA1__KEY_ROW4, - MX50_PAD_EIM_DA2__KEY_COL5, - MX50_PAD_EIM_DA3__KEY_ROW5, - MX50_PAD_EIM_DA4__KEY_COL6, - MX50_PAD_EIM_DA5__KEY_ROW6, - MX50_PAD_EIM_DA6__KEY_COL7, - MX50_PAD_EIM_DA7__KEY_ROW7, - /*EIM pads */ - MX50_PAD_EIM_DA8__GPIO_1_8, - MX50_PAD_EIM_DA9__GPIO_1_9, - MX50_PAD_EIM_DA10__GPIO_1_10, - MX50_PAD_EIM_DA11__GPIO_1_11, - MX50_PAD_EIM_DA12__GPIO_1_12, - MX50_PAD_EIM_DA13__GPIO_1_13, - MX50_PAD_EIM_DA14__GPIO_1_14, - MX50_PAD_EIM_DA15__GPIO_1_15, - MX50_PAD_EIM_CS2__GPIO_1_16, - MX50_PAD_EIM_CS1__GPIO_1_17, - MX50_PAD_EIM_CS0__GPIO_1_18, - MX50_PAD_EIM_EB0__GPIO_1_19, - MX50_PAD_EIM_EB1__GPIO_1_20, - MX50_PAD_EIM_WAIT__GPIO_1_21, - MX50_PAD_EIM_BCLK__GPIO_1_22, - MX50_PAD_EIM_RDY__GPIO_1_23, - MX50_PAD_EIM_OE__GPIO_1_24, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct fec_platform_data fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static inline void mx50_rdp_fec_reset(void) -{ - gpio_request(FEC_EN, "fec-en"); - gpio_direction_output(FEC_EN, 0); - gpio_request(FEC_RESET_B, "fec-reset_b"); - gpio_direction_output(FEC_RESET_B, 0); - msleep(1); - gpio_set_value(FEC_RESET_B, 1); -} - -static const struct imxi2c_platform_data i2c_data __initconst = { - .bitrate = 100000, -}; - -/* - * Board specific initialization. - */ -static void __init mx50_rdp_board_init(void) -{ - imx50_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads, - ARRAY_SIZE(mx50_rdp_pads)); - - imx50_add_imx_uart(0, &uart_pdata); - imx50_add_imx_uart(1, &uart_pdata); - mx50_rdp_fec_reset(); - imx50_add_fec(&fec_data); - imx50_add_imx_i2c(0, &i2c_data); - imx50_add_imx_i2c(1, &i2c_data); - imx50_add_imx_i2c(2, &i2c_data); -} - -static void __init mx50_rdp_timer_init(void) -{ - mx50_clocks_init(32768, 24000000, 22579200); -} - -static struct sys_timer mx50_rdp_timer = { - .init = mx50_rdp_timer_init, -}; - -MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") - .map_io = mx50_map_io, - .init_early = imx50_init_early, - .init_irq = mx50_init_irq, - .handle_irq = imx50_handle_irq, - .timer = &mx50_rdp_timer, - .init_machine = mx50_rdp_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_3ds.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_3ds.c deleted file mode 100644 index 83eab417..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_3ds.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx51.h> -#include <mach/3ds_debugboard.h> - -#include "devices-imx51.h" - -#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6)) -#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) - -static iomux_v3_cfg_t mx51_3ds_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - MX51_PAD_EIM_D25__UART2_CTS, - MX51_PAD_EIM_D26__UART2_RTS, - - /* UART3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - MX51_PAD_EIM_D24__UART3_CTS, - MX51_PAD_EIM_D27__UART3_RTS, - - /* CPLD PARENT IRQ PIN */ - MX51_PAD_GPIO1_6__GPIO1_6, - - /* KPP */ - MX51_PAD_KEY_ROW0__KEY_ROW0, - MX51_PAD_KEY_ROW1__KEY_ROW1, - MX51_PAD_KEY_ROW2__KEY_ROW2, - MX51_PAD_KEY_ROW3__KEY_ROW3, - MX51_PAD_KEY_COL0__KEY_COL0, - MX51_PAD_KEY_COL1__KEY_COL1, - MX51_PAD_KEY_COL2__KEY_COL2, - MX51_PAD_KEY_COL3__KEY_COL3, - MX51_PAD_KEY_COL4__KEY_COL4, - MX51_PAD_KEY_COL5__KEY_COL5, - - /* eCSPI2 */ - MX51_PAD_NANDF_RB2__ECSPI2_SCLK, - MX51_PAD_NANDF_RB3__ECSPI2_MISO, - MX51_PAD_NANDF_D15__ECSPI2_MOSI, - MX51_PAD_NANDF_D12__GPIO3_28, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int mx51_3ds_board_keymap[] = { - KEY(0, 0, KEY_1), - KEY(0, 1, KEY_2), - KEY(0, 2, KEY_3), - KEY(0, 3, KEY_F1), - KEY(0, 4, KEY_UP), - KEY(0, 5, KEY_F2), - - KEY(1, 0, KEY_4), - KEY(1, 1, KEY_5), - KEY(1, 2, KEY_6), - KEY(1, 3, KEY_LEFT), - KEY(1, 4, KEY_SELECT), - KEY(1, 5, KEY_RIGHT), - - KEY(2, 0, KEY_7), - KEY(2, 1, KEY_8), - KEY(2, 2, KEY_9), - KEY(2, 3, KEY_F3), - KEY(2, 4, KEY_DOWN), - KEY(2, 5, KEY_F4), - - KEY(3, 0, KEY_0), - KEY(3, 1, KEY_OK), - KEY(3, 2, KEY_ESC), - KEY(3, 3, KEY_ENTER), - KEY(3, 4, KEY_MENU), - KEY(3, 5, KEY_BACK) -}; - -static const struct matrix_keymap_data mx51_3ds_map_data __initconst = { - .keymap = mx51_3ds_board_keymap, - .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), -}; - -static int mx51_3ds_spi2_cs[] = { - MXC_SPI_CS(0), - MX51_3DS_ECSPI2_CS, -}; - -static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = { - .chipselect = mx51_3ds_spi2_cs, - .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs), -}; - -static struct spi_board_info mx51_3ds_spi_nor_device[] = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL,}, -}; - -/* - * Board specific initialization. - */ -static void __init mx51_3ds_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, - ARRAY_SIZE(mx51_3ds_pads)); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); - - imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); - spi_register_board_info(mx51_3ds_spi_nor_device, - ARRAY_SIZE(mx51_3ds_spi_nor_device)); - - if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) - printk(KERN_WARNING "Init of the debugboard failed, all " - "devices on the board are unusable.\n"); - - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_imx_keypad(&mx51_3ds_map_data); - imx51_add_imx2_wdt(0, NULL); -} - -static void __init mx51_3ds_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx51_3ds_timer = { - .init = mx51_3ds_timer_init, -}; - -MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mx51_3ds_timer, - .init_machine = mx51_3ds_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_babbage.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_babbage.c deleted file mode 100644 index e4b822e9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_babbage.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "cpu_op-mx51.h" - -#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) -#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) -#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5) -#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) -#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) -#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) -#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) -#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6) -#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5) - -/* USB_CTRL_1 */ -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) - -#define MX51_USB_PLLDIV_12_MHZ 0x00 -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 -#define MX51_USB_PLL_DIV_24_MHZ 0x02 - -static struct gpio_keys_button babbage_buttons[] = { - { - .gpio = BABBAGE_POWER_KEY, - .code = BTN_0, - .desc = "PWR", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data imx_button_data __initconst = { - .buttons = babbage_buttons, - .nbuttons = ARRAY_SIZE(babbage_buttons), -}; - -static iomux_v3_cfg_t mx51babbage_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - - /* UART3 */ - MX51_PAD_EIM_D25__UART3_RXD, - MX51_PAD_EIM_D26__UART3_TXD, - MX51_PAD_EIM_D27__UART3_RTS, - MX51_PAD_EIM_D24__UART3_CTS, - - /* I2C1 */ - MX51_PAD_EIM_D16__I2C1_SDA, - MX51_PAD_EIM_D19__I2C1_SCL, - - /* I2C2 */ - MX51_PAD_KEY_COL4__I2C2_SCL, - MX51_PAD_KEY_COL5__I2C2_SDA, - - /* HSI2C */ - MX51_PAD_I2C1_CLK__I2C1_CLK, - MX51_PAD_I2C1_DAT__I2C1_DAT, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - /* USB HUB reset line*/ - MX51_PAD_GPIO1_7__GPIO1_7, - - /* USB PHY reset line */ - MX51_PAD_EIM_D21__GPIO2_5, - - /* FEC */ - MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDATA1, - MX51_PAD_EIM_CS2__FEC_RDATA2, - MX51_PAD_EIM_CS3__FEC_RDATA3, - MX51_PAD_EIM_CS4__FEC_RX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RX_CLK, - MX51_PAD_NANDF_D9__FEC_RDATA0, - MX51_PAD_NANDF_D8__FEC_TDATA0, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDATA1, - MX51_PAD_NANDF_CS5__FEC_TDATA2, - MX51_PAD_NANDF_CS6__FEC_TDATA3, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - - /* FEC PHY reset line */ - MX51_PAD_EIM_A20__GPIO2_14, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - /* CD/WP from controller */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - /* CD/WP gpio */ - MX51_PAD_GPIO1_6__GPIO1_6, - MX51_PAD_GPIO1_5__GPIO1_5, - - /* eCSPI1 */ - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data babbage_i2c_data __initconst = { - .bitrate = 100000, -}; - -static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = { - .bitrate = 400000, -}; - -static struct gpio mx51_babbage_usbh1_gpios[] = { - { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" }, - { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" }, -}; - -static int gpio_usbh1_active(void) -{ - iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27; - int ret; - - /* Set USBH1_STP to GPIO and toggle it */ - mxc_iomux_v3_setup_pad(usbh1stp_gpio); - ret = gpio_request_array(mx51_babbage_usbh1_gpios, - ARRAY_SIZE(mx51_babbage_usbh1_gpios)); - - if (ret) { - pr_debug("failed to get USBH1 pins: %d\n", ret); - return ret; - } - - msleep(100); - gpio_set_value(BABBAGE_USBH1_STP, 1); - gpio_set_value(BABBAGE_USB_PHY_RESET, 1); - gpio_free_array(mx51_babbage_usbh1_gpios, - ARRAY_SIZE(mx51_babbage_usbh1_gpios)); - return 0; -} - -static inline void babbage_usbhub_reset(void) -{ - int ret; - - /* Reset USB hub */ - ret = gpio_request_one(BABBAGE_USB_HUB_RESET, - GPIOF_OUT_INIT_LOW, "GPIO1_7"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); - return; - } - - msleep(2); - /* Deassert reset */ - gpio_set_value(BABBAGE_USB_HUB_RESET, 1); -} - -static inline void babbage_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request_one(BABBAGE_FEC_PHY_RESET, - GPIOF_OUT_INIT_LOW, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - msleep(1); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); -} - -/* This function is board specific as the bit mask for the plldiv will also -be different for other Freescale SoCs, thus a common bitmask is not -possible and cannot get place in /plat-mxc/ehci.c.*/ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* The clock for the USBH1 ULPI port will come externally from the PHY. */ - v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_ITC_NO_THRESHOLD); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -static const struct mxc_usbh_platform_data usbh1_config __initconst = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int otg_mode_host; - -static int __init babbage_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", babbage_otg_mode); - -static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = { - { - .modalias = "mtd_dataflash", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL, - }, -}; - -static int mx51_babbage_spi_cs[] = { - BABBAGE_ECSPI1_CS0, - BABBAGE_ECSPI1_CS1, -}; - -static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { - .chipselect = mx51_babbage_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), -}; - -static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { - .cd_gpio = BABBAGE_SD2_CD, - .wp_gpio = BABBAGE_SD2_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -void __init imx51_babbage_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, - ARRAY_SIZE(mx51babbage_pads)); -} - -/* - * Board specific initialization. - */ -static void __init mx51_babbage_init(void) -{ - iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, - PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH); - - imx51_soc_init(); - -#if defined(CONFIG_CPU_FREQ_IMX) - get_cpu_op = mx51_get_cpu_op; -#endif - imx51_babbage_common_init(); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); - - babbage_fec_reset(); - imx51_add_fec(NULL); - - /* Set the PAD settings for the pwr key. */ - mxc_iomux_v3_setup_pad(power_key); - imx_add_gpio_keys(&imx_button_data); - - imx51_add_imx_i2c(0, &babbage_i2c_data); - imx51_add_imx_i2c(1, &babbage_i2c_data); - imx51_add_hsi2c(&babbage_hsi2c_data); - - if (otg_mode_host) - imx51_add_mxc_ehci_otg(&dr_utmi_config); - else { - initialize_otg_port(NULL); - imx51_add_fsl_usb2_udc(&usb_pdata); - } - - gpio_usbh1_active(); - imx51_add_mxc_ehci_hs(1, &usbh1_config); - /* setback USBH1_STP to be function */ - mxc_iomux_v3_setup_pad(usbh1stp); - babbage_usbhub_reset(); - - imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); - imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); - - spi_register_board_info(mx51_babbage_spi_board_info, - ARRAY_SIZE(mx51_babbage_spi_board_info)); - imx51_add_ecspi(0, &mx51_babbage_spi_pdata); - imx51_add_imx2_wdt(0, NULL); -} - -static void __init mx51_babbage_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx51_babbage_timer = { - .init = mx51_babbage_timer_init, -}; - -MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") - /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mx51_babbage_timer, - .init_machine = mx51_babbage_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_efikamx.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_efikamx.c deleted file mode 100644 index 586e9f82..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_efikamx.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (C) 2010 Linaro Limited - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/consumer.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/system_info.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "efika.h" - -#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) -#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) -#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) - -#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) -#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) -#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) - -#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) - -/* board 1.1 doesn't have same reset gpio */ -#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) -#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) - -#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13) - -#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) - -/* the pci ids pin have pull up. they're driven low according to board id */ -#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) - -static iomux_v3_cfg_t mx51efikamx_pads[] = { - /* board id */ - MX51_PAD_PCBID0, - MX51_PAD_PCBID1, - MX51_PAD_PCBID2, - - /* leds */ - MX51_PAD_CSI1_D9__GPIO3_13, - MX51_PAD_CSI1_VSYNC__GPIO3_14, - MX51_PAD_CSI1_HSYNC__GPIO3_15, - - /* power key */ - MX51_PAD_PWRKEY, - - /* reset */ - MX51_PAD_DI1_PIN13__GPIO3_2, - MX51_PAD_GPIO1_4__GPIO1_4, - - /* power off */ - MX51_PAD_CSI2_VSYNC__GPIO4_13, -}; - -/* PCBID2 PCBID1 PCBID0 STATE - 1 1 1 ER1:rev1.1 - 1 1 0 ER2:rev1.2 - 1 0 1 ER3:rev1.3 - 1 0 0 ER4:rev1.4 -*/ -static void __init mx51_efikamx_board_id(void) -{ - int id; - - /* things are taking time to settle */ - msleep(150); - - gpio_request(EFIKAMX_PCBID0, "pcbid0"); - gpio_direction_input(EFIKAMX_PCBID0); - gpio_request(EFIKAMX_PCBID1, "pcbid1"); - gpio_direction_input(EFIKAMX_PCBID1); - gpio_request(EFIKAMX_PCBID2, "pcbid2"); - gpio_direction_input(EFIKAMX_PCBID2); - - id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0; - id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1; - id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2; - - switch (id) { - case 7: - system_rev = 0x11; - break; - case 6: - system_rev = 0x12; - break; - case 5: - system_rev = 0x13; - break; - case 4: - system_rev = 0x14; - break; - default: - system_rev = 0x10; - break; - } - - if ((system_rev == 0x10) - || (system_rev == 0x12) - || (system_rev == 0x14)) { - printk(KERN_WARNING - "EfikaMX: Unsupported board revision 1.%u!\n", - system_rev & 0xf); - } -} - -static struct gpio_led mx51_efikamx_leds[] __initdata = { - { - .name = "efikamx:green", - .default_trigger = "default-on", - .gpio = EFIKAMX_GREEN_LED, - }, - { - .name = "efikamx:red", - .default_trigger = "ide-disk", - .gpio = EFIKAMX_RED_LED, - }, - { - .name = "efikamx:blue", - .default_trigger = "mmc0", - .gpio = EFIKAMX_BLUE_LED, - }, -}; - -static const struct gpio_led_platform_data - mx51_efikamx_leds_data __initconst = { - .leds = mx51_efikamx_leds, - .num_leds = ARRAY_SIZE(mx51_efikamx_leds), -}; - -static struct esdhc_platform_data sd_pdata = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct gpio_keys_button mx51_efikamx_powerkey[] = { - { - .code = KEY_POWER, - .gpio = EFIKAMX_POWER_KEY, - .type = EV_PWR, - .desc = "Power Button (CM)", - .wakeup = 1, - .debounce_interval = 10, /* ms */ - }, -}; - -static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { - .buttons = mx51_efikamx_powerkey, - .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), -}; - -static void mx51_efikamx_restart(char mode, const char *cmd) -{ - if (system_rev == 0x11) - gpio_direction_output(EFIKAMX_RESET1_1, 0); - else - gpio_direction_output(EFIKAMX_RESET, 0); -} - -static struct regulator *pwgt1, *pwgt2, *coincell; - -static void mx51_efikamx_power_off(void) -{ - if (!IS_ERR(coincell)) - regulator_disable(coincell); - - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_disable(pwgt2); - regulator_disable(pwgt1); - } - gpio_direction_output(EFIKAMX_POWEROFF, 1); -} - -static int __init mx51_efikamx_power_init(void) -{ - if (machine_is_mx51_efikamx()) { - pwgt1 = regulator_get(NULL, "pwgt1"); - pwgt2 = regulator_get(NULL, "pwgt2"); - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_enable(pwgt1); - regulator_enable(pwgt2); - } - gpio_request(EFIKAMX_POWEROFF, "poweroff"); - pm_power_off = mx51_efikamx_power_off; - - /* enable coincell charger. maybe need a small power driver ? */ - coincell = regulator_get(NULL, "coincell"); - if (!IS_ERR(coincell)) { - regulator_set_voltage(coincell, 3000000, 3000000); - regulator_enable(coincell); - } - - regulator_has_full_constraints(); - } - - return 0; -} -late_initcall(mx51_efikamx_power_init); - -static void __init mx51_efikamx_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, - ARRAY_SIZE(mx51efikamx_pads)); - efika_board_common_init(); - - mx51_efikamx_board_id(); - - /* on < 1.2 boards both SD controllers are used */ - if (system_rev < 0x12) { - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_sdhci_esdhc_imx(1, &sd_pdata); - mx51_efikamx_leds[2].default_trigger = "mmc1"; - } else - imx51_add_sdhci_esdhc_imx(0, &sd_pdata); - - gpio_led_register_device(-1, &mx51_efikamx_leds_data); - imx_add_gpio_keys(&mx51_efikamx_powerkey_data); - - if (system_rev == 0x11) { - gpio_request(EFIKAMX_RESET1_1, "reset"); - gpio_direction_output(EFIKAMX_RESET1_1, 1); - } else { - gpio_request(EFIKAMX_RESET, "reset"); - gpio_direction_output(EFIKAMX_RESET, 1); - } - - /* - * enable wifi by default only on mx - * sb and mx have same wlan pin but the value to enable it are - * different :/ - */ - gpio_request(EFIKA_WLAN_EN, "wlan_en"); - gpio_direction_output(EFIKA_WLAN_EN, 0); - msleep(10); - - gpio_request(EFIKA_WLAN_RESET, "wlan_rst"); - gpio_direction_output(EFIKA_WLAN_RESET, 0); - msleep(10); - gpio_set_value(EFIKA_WLAN_RESET, 1); -} - -static void __init mx51_efikamx_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mx51_efikamx_timer = { - .init = mx51_efikamx_timer_init, -}; - -MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") - /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mx51_efikamx_timer, - .init_machine = mx51_efikamx_init, - .restart = mx51_efikamx_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_efikasb.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_efikasb.c deleted file mode 100644 index 24aded9e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx51_efikasb.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org> - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/consumer.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <mach/ulpi.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/system_info.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "efika.h" - -#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) -#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3) -#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25) -#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28) -#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29) -#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31) -#define EFIKASB_LID IMX_GPIO_NR(3, 14) -#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13) -#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) - -#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) -#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL) - -static iomux_v3_cfg_t mx51efikasb_pads[] = { - /* USB HOST2 */ - MX51_PAD_EIM_D16__USBH2_DATA0, - MX51_PAD_EIM_D17__USBH2_DATA1, - MX51_PAD_EIM_D18__USBH2_DATA2, - MX51_PAD_EIM_D19__USBH2_DATA3, - MX51_PAD_EIM_D20__USBH2_DATA4, - MX51_PAD_EIM_D21__USBH2_DATA5, - MX51_PAD_EIM_D22__USBH2_DATA6, - MX51_PAD_EIM_D23__USBH2_DATA7, - MX51_PAD_EIM_A24__USBH2_CLK, - MX51_PAD_EIM_A25__USBH2_DIR, - MX51_PAD_EIM_A26__USBH2_STP, - MX51_PAD_EIM_A27__USBH2_NXT, - - /* leds */ - MX51_PAD_EIM_CS0__GPIO2_25, - MX51_PAD_GPIO1_3__GPIO1_3, - - /* pcb id */ - MX51_PAD_EIM_CS3__GPIO2_28, - MX51_PAD_EIM_CS4__GPIO2_29, - - /* lid */ - MX51_PAD_CSI1_VSYNC__GPIO3_14, - - /* power key*/ - MX51_PAD_PWRKEY, - - /* wifi/bt button */ - MX51_PAD_DI1_PIN12__GPIO3_1, - - /* power off */ - MX51_PAD_CSI2_VSYNC__GPIO4_13, - - /* wdog reset */ - MX51_PAD_GPIO1_4__WDOG1_WDOG_B, - - /* BT */ - MX51_PAD_EIM_A17__GPIO2_11, - - MX51_PAD_SD1_CD, -}; - -static int initialize_usbh2_port(struct platform_device *pdev) -{ - iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; - iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; - - mxc_iomux_v3_setup_pad(usbh2gpio); - gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); - gpio_direction_output(EFIKASB_USBH2_STP, 0); - msleep(1); - gpio_set_value(EFIKASB_USBH2_STP, 1); - msleep(1); - - gpio_free(EFIKASB_USBH2_STP); - mxc_iomux_v3_setup_pad(usbh2stp); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); -} - -static struct mxc_usbh_platform_data usbh2_config __initdata = { - .init = initialize_usbh2_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void __init mx51_efikasb_usb(void) -{ - usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - if (usbh2_config.otg) - imx51_add_mxc_ehci_hs(2, &usbh2_config); -} - -static const struct gpio_led mx51_efikasb_leds[] __initconst = { - { - .name = "efikasb:green", - .default_trigger = "default-on", - .gpio = EFIKASB_GREEN_LED, - .active_low = 1, - }, - { - .name = "efikasb:white", - .default_trigger = "caps", - .gpio = EFIKASB_WHITE_LED, - }, -}; - -static const struct gpio_led_platform_data - mx51_efikasb_leds_data __initconst = { - .leds = mx51_efikasb_leds, - .num_leds = ARRAY_SIZE(mx51_efikasb_leds), -}; - -static struct gpio_keys_button mx51_efikasb_keys[] = { - { - .code = KEY_POWER, - .gpio = EFIKASB_PWRKEY, - .type = EV_KEY, - .desc = "Power Button", - .wakeup = 1, - .active_low = 1, - }, - { - .code = SW_LID, - .gpio = EFIKASB_LID, - .type = EV_SW, - .desc = "Lid Switch", - .active_low = 1, - }, - { - .code = KEY_RFKILL, - .gpio = EFIKASB_RFKILL, - .type = EV_KEY, - .desc = "rfkill", - .active_low = 1, - }, -}; - -static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = { - .buttons = mx51_efikasb_keys, - .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), -}; - -static struct esdhc_platform_data sd0_pdata = { -#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27) - .cd_gpio = EFIKASB_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct regulator *pwgt1, *pwgt2; - -static void mx51_efikasb_power_off(void) -{ - gpio_set_value(EFIKA_USB_PHY_RESET, 0); - - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_disable(pwgt2); - regulator_disable(pwgt1); - } - gpio_direction_output(EFIKASB_POWEROFF, 1); -} - -static int __init mx51_efikasb_power_init(void) -{ - if (machine_is_mx51_efikasb()) { - pwgt1 = regulator_get(NULL, "pwgt1"); - pwgt2 = regulator_get(NULL, "pwgt2"); - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_enable(pwgt1); - regulator_enable(pwgt2); - } - gpio_request(EFIKASB_POWEROFF, "poweroff"); - pm_power_off = mx51_efikasb_power_off; - - regulator_has_full_constraints(); - } - - return 0; -} -late_initcall(mx51_efikasb_power_init); - -/* 01 R1.3 board - 10 R2.0 board */ -static void __init mx51_efikasb_board_id(void) -{ - int id; - - gpio_request(EFIKASB_PCBID0, "pcb id0"); - gpio_direction_input(EFIKASB_PCBID0); - gpio_request(EFIKASB_PCBID1, "pcb id1"); - gpio_direction_input(EFIKASB_PCBID1); - - id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0; - id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1; - - switch (id) { - default: - break; - case 1: - system_rev = 0x13; - break; - case 2: - system_rev = 0x20; - break; - } -} - -static void __init efikasb_board_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, - ARRAY_SIZE(mx51efikasb_pads)); - efika_board_common_init(); - - mx51_efikasb_board_id(); - mx51_efikasb_usb(); - imx51_add_sdhci_esdhc_imx(0, &sd0_pdata); - imx51_add_sdhci_esdhc_imx(1, &sd1_pdata); - - gpio_led_register_device(-1, &mx51_efikasb_leds_data); - imx_add_gpio_keys(&mx51_efikasb_keys_data); -} - -static void __init mx51_efikasb_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mx51_efikasb_timer = { - .init = mx51_efikasb_timer_init, -}; - -MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook") - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_machine = efikasb_board_init, - .timer = &mx51_efikasb_timer, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_ard.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_ard.c deleted file mode 100644 index 05641980..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_ard.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx53.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx53.h" - -#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) -#define ARD_SD1_CD IMX_GPIO_NR(1, 1) -#define ARD_SD1_WP IMX_GPIO_NR(1, 9) -#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3) -#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0) -#define ARD_HOME IMX_GPIO_NR(5, 10) -#define ARD_BACK IMX_GPIO_NR(5, 11) -#define ARD_PROG IMX_GPIO_NR(5, 12) -#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13) - -static iomux_v3_cfg_t mx53_ard_pads[] = { - /* UART1 */ - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - /* WEIM for CS1 */ - MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ - MX53_PAD_EIM_D16__EMI_WEIM_D_16, - MX53_PAD_EIM_D17__EMI_WEIM_D_17, - MX53_PAD_EIM_D18__EMI_WEIM_D_18, - MX53_PAD_EIM_D19__EMI_WEIM_D_19, - MX53_PAD_EIM_D20__EMI_WEIM_D_20, - MX53_PAD_EIM_D21__EMI_WEIM_D_21, - MX53_PAD_EIM_D22__EMI_WEIM_D_22, - MX53_PAD_EIM_D23__EMI_WEIM_D_23, - MX53_PAD_EIM_D24__EMI_WEIM_D_24, - MX53_PAD_EIM_D25__EMI_WEIM_D_25, - MX53_PAD_EIM_D26__EMI_WEIM_D_26, - MX53_PAD_EIM_D27__EMI_WEIM_D_27, - MX53_PAD_EIM_D28__EMI_WEIM_D_28, - MX53_PAD_EIM_D29__EMI_WEIM_D_29, - MX53_PAD_EIM_D30__EMI_WEIM_D_30, - MX53_PAD_EIM_D31__EMI_WEIM_D_31, - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, - MX53_PAD_EIM_OE__EMI_WEIM_OE, - MX53_PAD_EIM_RW__EMI_WEIM_RW, - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, - /* SDHC1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - MX53_PAD_PATA_DATA8__ESDHC1_DAT4, - MX53_PAD_PATA_DATA9__ESDHC1_DAT5, - MX53_PAD_PATA_DATA10__ESDHC1_DAT6, - MX53_PAD_PATA_DATA11__ESDHC1_DAT7, - MX53_PAD_GPIO_1__GPIO1_1, - MX53_PAD_GPIO_9__GPIO1_9, - /* I2C2 */ - MX53_PAD_EIM_EB2__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* I2C3 */ - MX53_PAD_GPIO_3__I2C3_SCL, - MX53_PAD_GPIO_16__I2C3_SDA, - /* GPIO */ - MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */ - MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */ - MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */ - MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */ - MX53_PAD_GPIO_10__GPIO4_0, /* vol down */ -}; - -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ -{ \ - .gpio = gpio_num, \ - .type = EV_KEY, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ - .wakeup = wake, \ -} - -static struct gpio_keys_button ard_buttons[] = { - GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), - GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), - GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), - GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), -}; - -static const struct gpio_keys_platform_data ard_button_data __initconst = { - .buttons = ard_buttons, - .nbuttons = ARRAY_SIZE(ard_buttons), -}; - -static struct resource ard_smsc911x_resources[] = { - { - .start = MX53_CS1_64MB_BASE_ADDR, - .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B), - .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B), - .flags = IORESOURCE_IRQ, - }, -}; - -struct smsc911x_platform_config ard_smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_32BIT, -}; - -static struct platform_device ard_smsc_lan9220_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(ard_smsc911x_resources), - .resource = ard_smsc911x_resources, - .dev = { - .platform_data = &ard_smsc911x_config, - }, -}; - -static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { - .cd_gpio = ARD_SD1_CD, - .wp_gpio = ARD_SD1_WP, -}; - -static struct imxi2c_platform_data mx53_ard_i2c2_data = { - .bitrate = 50000, -}; - -static struct imxi2c_platform_data mx53_ard_i2c3_data = { - .bitrate = 400000, -}; - -static void __init mx53_ard_io_init(void) -{ - gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); - gpio_direction_input(ARD_ETHERNET_INT_B); - - gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); - gpio_direction_output(ARD_I2CPORTEXP_B, 1); -} - -/* Config CS1 settings for ethernet controller */ -static int weim_cs_config(void) -{ - u32 reg; - void __iomem *weim_base, *iomuxc_base; - - weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); - if (!weim_base) - return -ENOMEM; - - iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); - if (!iomuxc_base) { - iounmap(weim_base); - return -ENOMEM; - } - - /* CS1 timings for LAN9220 */ - writel(0x20001, (weim_base + 0x18)); - writel(0x0, (weim_base + 0x1C)); - writel(0x16000202, (weim_base + 0x20)); - writel(0x00000002, (weim_base + 0x24)); - writel(0x16002082, (weim_base + 0x28)); - writel(0x00000000, (weim_base + 0x2C)); - writel(0x00000000, (weim_base + 0x90)); - - /* specify 64 MB on CS1 and CS0 on GPR1 */ - reg = readl(iomuxc_base + 0x4); - reg &= ~0x3F; - reg |= 0x1B; - writel(reg, (iomuxc_base + 0x4)); - - iounmap(iomuxc_base); - iounmap(weim_base); - - return 0; -} - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -void __init imx53_ard_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, - ARRAY_SIZE(mx53_ard_pads)); - weim_cs_config(); -} - -static struct platform_device *devices[] __initdata = { - &ard_smsc_lan9220_device, -}; - -static void __init mx53_ard_board_init(void) -{ - imx53_soc_init(); - imx53_add_imx_uart(0, NULL); - - imx53_ard_common_init(); - mx53_ard_io_init(); - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); - imx53_add_imx2_wdt(0, NULL); - imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); - imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); - imx_add_gpio_keys(&ard_button_data); - imx53_add_ahci_imx(); -} - -static void __init mx53_ard_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_ard_timer = { - .init = mx53_ard_timer_init, -}; - -MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_ard_timer, - .init_machine = mx53_ard_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_evk.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_evk.c deleted file mode 100644 index 5a72188b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_evk.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/iomux-mx53.h> - -#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) -#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) -#define MX53EVK_LED IMX_GPIO_NR(7, 7) - -#include "devices-imx53.h" - -static iomux_v3_cfg_t mx53_evk_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_INTRQ__UART2_CTS, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - - MX53_PAD_EIM_D16__ECSPI1_SCLK, - MX53_PAD_EIM_D17__ECSPI1_MISO, - MX53_PAD_EIM_D18__ECSPI1_MOSI, - - /* ecspi chip select lines */ - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_EIM_D19__GPIO3_19, - /* LED */ - MX53_PAD_PATA_DA_1__GPIO7_7, -}; - -static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct gpio_led mx53evk_leds[] __initconst = { - { - .name = "green", - .default_trigger = "heartbeat", - .gpio = MX53EVK_LED, - }, -}; - -static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { - .leds = mx53evk_leds, - .num_leds = ARRAY_SIZE(mx53evk_leds), -}; - -static inline void mx53_evk_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, &mx53_evk_uart_pdata); - imx53_add_imx_uart(2, NULL); -} - -static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { - .bitrate = 100000, -}; - -static inline void mx53_evk_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, - "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - msleep(1); - gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_evk_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static struct spi_board_info mx53_evk_spi_board_info[] __initdata = { - { - .modalias = "mtd_dataflash", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL, - }, -}; - -static int mx53_evk_spi_cs[] = { - EVK_ECSPI1_CS0, - EVK_ECSPI1_CS1, -}; - -static const struct spi_imx_master mx53_evk_spi_data __initconst = { - .chipselect = mx53_evk_spi_cs, - .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), -}; - -void __init imx53_evk_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, - ARRAY_SIZE(mx53_evk_pads)); -} - -static void __init mx53_evk_board_init(void) -{ - imx53_soc_init(); - imx53_evk_common_init(); - - mx53_evk_init_uart(); - mx53_evk_fec_reset(); - imx53_add_fec(&mx53_evk_fec_pdata); - - imx53_add_imx_i2c(0, &mx53_evk_i2c_data); - imx53_add_imx_i2c(1, &mx53_evk_i2c_data); - - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); - - spi_register_board_info(mx53_evk_spi_board_info, - ARRAY_SIZE(mx53_evk_spi_board_info)); - imx53_add_ecspi(0, &mx53_evk_spi_data); - imx53_add_imx2_wdt(0, NULL); - gpio_led_register_device(-1, &mx53evk_leds_data); -} - -static void __init mx53_evk_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_evk_timer = { - .init = mx53_evk_timer_init, -}; - -MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_evk_timer, - .init_machine = mx53_evk_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_loco.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_loco.c deleted file mode 100644 index 37f67cac..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_loco.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/i2c.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx53.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx53.h" - -#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) -#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) -#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) -#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define LOCO_LED IMX_GPIO_NR(7, 7) -#define LOCO_SD3_CD IMX_GPIO_NR(3, 11) -#define LOCO_SD3_WP IMX_GPIO_NR(3, 12) -#define LOCO_SD1_CD IMX_GPIO_NR(3, 13) -#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14) - -static iomux_v3_cfg_t mx53_loco_pads[] = { - /* FEC */ - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - /* FEC_nRST */ - MX53_PAD_PATA_DA_0__GPIO7_6, - /* FEC_nINT */ - MX53_PAD_PATA_DATA4__GPIO2_4, - /* AUDMUX5 */ - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */ - /* I2C2 */ - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1_CD */ - MX53_PAD_EIM_DA13__GPIO3_13, - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - /* SD3_CD */ - MX53_PAD_EIM_DA11__GPIO3_11, - /* SD3_WP */ - MX53_PAD_EIM_DA12__GPIO3_12, - /* VGA */ - MX53_PAD_EIM_OE__IPU_DI1_PIN7, - MX53_PAD_EIM_RW__IPU_DI1_PIN8, - /* DISPLB */ - MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, - MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, - MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, - MX53_PAD_EIM_D23__IPU_DI0_D0_CS, - /* DISP0_POWER_EN */ - MX53_PAD_EIM_D24__GPIO3_24, - /* DISP0 DET INT */ - MX53_PAD_EIM_D31__GPIO3_31, - /* LVDS */ - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* UART1 */ - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - /* CSI0 */ - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, - /* DISPLAY */ - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, - /* Audio CLK*/ - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, - /* PWM */ - MX53_PAD_GPIO_1__PWM2_PWMO, - /* SPDIF */ - MX53_PAD_GPIO_7__SPDIF_PLOCK, - MX53_PAD_GPIO_17__SPDIF_OUT1, - /* GPIO */ - MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ - MX53_PAD_PATA_DA_2__GPIO7_8, - MX53_PAD_PATA_DATA5__GPIO2_5, - MX53_PAD_PATA_DATA6__GPIO2_6, - MX53_PAD_PATA_DATA14__GPIO2_14, - MX53_PAD_PATA_DATA15__GPIO2_15, - MX53_PAD_PATA_INTRQ__GPIO7_2, - MX53_PAD_EIM_WAIT__GPIO5_0, - MX53_PAD_NANDF_WP_B__GPIO6_9, - MX53_PAD_NANDF_RB0__GPIO6_10, - MX53_PAD_NANDF_CS1__GPIO6_14, - MX53_PAD_NANDF_CS2__GPIO6_15, - MX53_PAD_NANDF_CS3__GPIO6_16, - MX53_PAD_GPIO_5__GPIO1_5, - MX53_PAD_GPIO_16__GPIO7_11, - MX53_PAD_GPIO_8__GPIO1_8, -}; - -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ -{ \ - .gpio = gpio_num, \ - .type = EV_KEY, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ - .wakeup = wake, \ -} - -static struct gpio_keys_button loco_buttons[] = { - GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), - GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), -}; - -static const struct gpio_keys_platform_data loco_button_data __initconst = { - .buttons = loco_buttons, - .nbuttons = ARRAY_SIZE(loco_buttons), -}; - -static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { - .cd_gpio = LOCO_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { - .cd_gpio = LOCO_SD3_CD, - .wp_gpio = LOCO_SD3_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -static inline void mx53_loco_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(LOCO_FEC_PHY_RST, 0); - msleep(1); - gpio_set_value(LOCO_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_loco_fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { - .bitrate = 100000, -}; - -static const struct gpio_led mx53loco_leds[] __initconst = { - { - .name = "green", - .default_trigger = "heartbeat", - .gpio = LOCO_LED, - }, -}; - -static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { - .leds = mx53loco_leds, - .num_leds = ARRAY_SIZE(mx53loco_leds), -}; - -void __init imx53_qsb_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, - ARRAY_SIZE(mx53_loco_pads)); -} - -static struct i2c_board_info mx53loco_i2c_devices[] = { - { - I2C_BOARD_INFO("mma8450", 0x1C), - }, -}; - -static void __init mx53_loco_board_init(void) -{ - int ret; - imx53_soc_init(); - imx53_qsb_common_init(); - - imx53_add_imx_uart(0, NULL); - mx53_loco_fec_reset(); - imx53_add_fec(&mx53_loco_fec_data); - imx53_add_imx2_wdt(0, NULL); - - ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); - if (ret) - pr_err("Cannot request ACCEL_EN pin: %d\n", ret); - - i2c_register_board_info(0, mx53loco_i2c_devices, - ARRAY_SIZE(mx53loco_i2c_devices)); - imx53_add_imx_i2c(0, &mx53_loco_i2c_data); - imx53_add_imx_i2c(1, &mx53_loco_i2c_data); - imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); - imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); - imx_add_gpio_keys(&loco_button_data); - gpio_led_register_device(-1, &mx53loco_leds_data); - imx53_add_ahci_imx(); -} - -static void __init mx53_loco_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 0, 0); -} - -static struct sys_timer mx53_loco_timer = { - .init = mx53_loco_timer_init, -}; - -MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_loco_timer, - .init_machine = mx53_loco_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_smd.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_smd.c deleted file mode 100644 index 8e972c5c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mx53_smd.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx53.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx53.h" - -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) - -static iomux_v3_cfg_t mx53_smd_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD2 */ - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, -}; - -static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static inline void mx53_smd_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, NULL); - imx53_add_imx_uart(2, &mx53_smd_uart_data); -} - -static inline void mx53_smd_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(SMD_FEC_PHY_RST, 0); - msleep(1); - gpio_set_value(SMD_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_smd_fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { - .bitrate = 100000, -}; - -static inline void mx53_smd_ahci_pwr_on(void) -{ - int ret; - - /* Enable SATA PWR */ - ret = gpio_request_one(MX53_SMD_SATA_PWR_EN, - GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr"); - if (ret) { - pr_err("failed to enable SATA_PWR_EN: %d\n", ret); - return; - } -} - -void __init imx53_smd_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, - ARRAY_SIZE(mx53_smd_pads)); -} - -static void __init mx53_smd_board_init(void) -{ - imx53_soc_init(); - imx53_smd_common_init(); - - mx53_smd_init_uart(); - mx53_smd_fec_reset(); - imx53_add_fec(&mx53_smd_fec_data); - imx53_add_imx2_wdt(0, NULL); - imx53_add_imx_i2c(0, &mx53_smd_i2c_data); - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); - imx53_add_sdhci_esdhc_imx(2, NULL); - mx53_smd_ahci_pwr_on(); - imx53_add_ahci_imx(); -} - -static void __init mx53_smd_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_smd_timer = { - .init = mx53_smd_timer_init, -}; - -MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_smd_timer, - .init_machine = mx53_smd_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mxt_td60.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-mxt_td60.c deleted file mode 100644 index 8b3d3f07..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-mxt_td60.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/irq.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <linux/gpio.h> -#include <mach/iomux-mx27.h> -#include <linux/i2c/pca953x.h> - -#include "devices-imx27.h" - -static const int mxt_td60_pins[] __initconst = { - /* UART0 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART1 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART2 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* FB */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA25_PF_CLS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* OWIRE */ - PE16_AF_OWIRE, - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - PF8_AF_ATA_IORDY, - /* SDHC2*/ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -}; - -static const struct mxc_nand_platform_data -mxt_td60_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = { - .bitrate = 100000, -}; - -/* PCA9557 */ -static int mxt_td60_pca9557_setup(struct i2c_client *client, - unsigned gpio_base, unsigned ngpio, - void *context) -{ - static int mxt_td60_gpio_value[] = { - -1, -1, -1, -1, -1, -1, -1, 1 - }; - int n; - - for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) { - gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp"); - if (mxt_td60_gpio_value[n] < 0) - gpio_direction_input(gpio_base + n); - else - gpio_direction_output(gpio_base + n, - mxt_td60_gpio_value[n]); - gpio_export(gpio_base + n, 0); - } - - return 0; -} - -static struct pca953x_platform_data mxt_td60_pca9557_pdata = { - .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */ - .invert = 0, /* Do not invert */ - .setup = mxt_td60_pca9557_setup, -}; - -static struct i2c_board_info mxt_td60_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9557", 0x18), - .platform_data = &mxt_td60_pca9557_pdata, - }, -}; - -static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mxt_td60_i2c2_devices[] = { -}; - -static struct imx_fb_videomode mxt_td60_modes[] = { - { - .mode = { - .name = "Chimei LW700AT9003", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 30303, - .hsync_len = 64, - .left_margin = 0x67, - .right_margin = 0x68, - .vsync_len = 16, - .upper_margin = 0x0f, - .lower_margin = 0x0f, - }, - .bpp = 16, - .pcr = 0xFA208B83, - }, -}; - -static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = { - .mode = mxt_td60_modes, - .num_modes = ARRAY_SIZE(mxt_td60_modes), - - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING, - "sdhc1-card-detect", data); -} - -static void mxt_td60_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOF(8), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mxt_td60_sdhc1_init, - .exit = mxt_td60_sdhc1_exit, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mxt_td60_board_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), - "MXT_TD60"); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - imx27_add_mxc_nand(&mxt_td60_nand_board_info); - - i2c_register_board_info(0, mxt_td60_i2c_devices, - ARRAY_SIZE(mxt_td60_i2c_devices)); - - i2c_register_board_info(1, mxt_td60_i2c2_devices, - ARRAY_SIZE(mxt_td60_i2c2_devices)); - - imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); - imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); - imx27_add_imx_fb(&mxt_td60_fb_data); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_fec(NULL); -} - -static void __init mxt_td60_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer mxt_td60_timer = { - .init = mxt_td60_timer_init, -}; - -MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") - /* maintainer: Maxtrack Industrial */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &mxt_td60_timer, - .init_machine = mxt_td60_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pca100.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-pca100.c deleted file mode 100644 index 541152e4..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pca100.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/dma-mapping.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx27.h> -#include <asm/mach/time.h> -#include <mach/irqs.h> -#include <mach/ulpi.h> - -#include "devices-imx27.h" - -#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) -#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) -#define SPI1_SS0 (GPIO_PORTD + 28) -#define SPI1_SS1 (GPIO_PORTD + 27) -#define SD2_CD (GPIO_PORTC + 29) - -static const int pca100_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* SDHC */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - SD2_CD | GPIO_GPIO | GPIO_IN, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* onboard I2C */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* external I2C */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* SPI1 */ - PD25_PF_CSPI1_RDY, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* USBH2 */ - USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA26_PF_PS, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA31_PF_OE_ACD, - /* free GPIO */ - GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */ - GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */ - GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */ -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -pca100_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pca100_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("lm75", 0x4a), - } -}; - -static struct spi_eeprom at25320 = { - .name = "at25320an", - .byte_len = 4096, - .page_size = 32, - .flags = EE_ADDR2, -}; - -static struct spi_board_info pca100_spi_board_info[] __initdata = { - { - .modalias = "at25", - .max_speed_hz = 30000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &at25320, - }, -}; - -static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1}; - -static const struct spi_imx_master pca100_spi0_data __initconst = { - .chipselect = pca100_spi_cs, - .num_chipselect = ARRAY_SIZE(pca100_spi_cs), -}; - -static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) -{ - mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); - gpio_set_value(GPIO_PORTC + 20, 1); - udelay(2); - gpio_set_value(GPIO_PORTC + 20, 0); - mxc_gpio_mode(PC20_PF_SSI1_FS); - msleep(2); -} - -static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) -{ - mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */ - gpio_set_value(GPIO_PORTC + 20, 0); - mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */ - gpio_set_value(GPIO_PORTC + 22, 0); - mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */ - gpio_set_value(GPIO_PORTC + 28, 0); - udelay(10); - gpio_set_value(GPIO_PORTC + 28, 1); - mxc_gpio_mode(PC20_PF_SSI1_FS); - mxc_gpio_mode(PC22_PF_SSI1_TXD); - msleep(2); -} - -static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = { - .ac97_reset = pca100_ac97_cold_reset, - .ac97_warm_reset = pca100_ac97_warm_reset, - .flags = IMX_SSI_USE_AC97, -}; - -static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = request_irq(IRQ_GPIOC(29), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "imx-mmc-detect", data); - if (ret) - printk(KERN_ERR - "pca100: Failed to reuest irq for sd/mmc detection\n"); - - return ret; -} - -static void pca100_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOC(29), data); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .init = pca100_sdhc2_init, - .exit = pca100_sdhc2_exit, -}; - -static int otg_phy_init(struct platform_device *pdev) -{ - gpio_set_value(OTG_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int usbh2_phy_init(struct platform_device *pdev) -{ - gpio_set_value(USBH2_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_phy_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static int otg_mode_host; - -static int __init pca100_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", pca100_otg_mode); - -/* framebuffer info */ -static struct imx_fb_videomode pca100_fb_modes[] = { - { - .mode = { - .name = "EMERGING-ETV570G0DHU", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39722, /* in ps (25.175 MHz) */ - .hsync_len = 30, - .left_margin = 114, - .right_margin = 16, - .vsync_len = 3, - .upper_margin = 32, - .lower_margin = 0, - }, - /* - * TFT - * Pixel pol active high - * HSYNC active low - * VSYNC active low - * use HSYNC for ACD count - * line clock disable while idle - * always enable line clock even if no data - */ - .pcr = 0xf0c08080, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data pca100_fb_data __initconst = { - .mode = pca100_fb_modes, - .num_modes = ARRAY_SIZE(pca100_fb_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static void __init pca100_init(void) -{ - int ret; - - imx27_soc_init(); - - ret = mxc_gpio_setup_multiple_pins(pca100_pins, - ARRAY_SIZE(pca100_pins), "PCA100"); - if (ret) - printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); - - imx27_add_imx_ssi(0, &pca100_ssi_pdata); - - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_mxc_mmc(1, &sdhc_pdata); - - imx27_add_mxc_nand(&pca100_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, pca100_i2c_devices, - ARRAY_SIZE(pca100_i2c_devices)); - - imx27_add_imx_i2c(1, &pca100_i2c1_data); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); - mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); - spi_register_board_info(pca100_spi_board_info, - ARRAY_SIZE(pca100_spi_board_info)); - imx27_add_spi_imx0(&pca100_spi0_data); - - gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); - gpio_direction_output(OTG_PHY_CS_GPIO, 1); - gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); - gpio_direction_output(USBH2_PHY_CS_GPIO, 1); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } else { - gpio_set_value(OTG_PHY_CS_GPIO, 0); - imx27_add_fsl_usb2_udc(&otg_device_pdata); - } - - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - if (usbh2_pdata.otg) - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); - - imx27_add_imx_fb(&pca100_fb_data); - - imx27_add_fec(NULL); - imx27_add_imx2_wdt(NULL); - imx27_add_mxc_w1(NULL); -} - -static void __init pca100_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer pca100_timer = { - .init = pca100_timer_init, -}; - -MACHINE_START(PCA100, "phyCARD-i.MX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_machine = pca100_init, - .timer = &pca100_timer, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm037.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm037.c deleted file mode 100644 index 5fddf94c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm037.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/delay.h> -#include <linux/spi/spi.h> -#include <linux/irq.h> -#include <linux/can/platform/sja1000.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/gfp.h> -#include <linux/memblock.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <media/soc_camera.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx3.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" -#include "pcm037.h" - -static enum pcm037_board_variant pcm037_instance = PCM037_PCM970; - -static int __init pcm037_variant_setup(char *str) -{ - if (!strcmp("eet", str)) - pcm037_instance = PCM037_EET; - else if (strcmp("pcm970", str)) - pr_warning("Unknown pcm037 baseboard variant %s\n", str); - - return 1; -} - -/* Supported values: "pcm970" (default) and "eet" */ -__setup("pcm037_variant=", pcm037_variant_setup); - -enum pcm037_board_variant pcm037_variant(void) -{ - return pcm037_instance; -} - -/* UART1 with RTS/CTS handshake signals */ -static unsigned int pcm037_uart1_handshake_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, -}; - -/* UART1 without RTS/CTS handshake signals */ -static unsigned int pcm037_uart1_pins[] = { - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, -}; - -static unsigned int pcm037_pins[] = { - /* I2C */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - MX31_PIN_CSPI2_SS2__I2C3_SDA, - MX31_PIN_CSPI2_SCLK__I2C3_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ - /* SPI1 */ - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* UART2 */ - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - /* UART3 */ - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - /* LAN9217 irq pin */ - IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), - /* Onewire */ - MX31_PIN_BATT_LINE__OWIRE, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_D3_REV__D3_REV, - MX31_PIN_CONTRAST__CONTRAST, - MX31_PIN_D3_SPL__D3_SPL, - MX31_PIN_D3_CLS__D3_CLS, - MX31_PIN_LCS0__GPI03_23, - /* CSI */ - IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO), - MX31_PIN_CSI_D6__CSI_D6, - MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, - MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, - MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, - MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, - MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, - MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, - MX31_PIN_CSI_VSYNC__CSI_VSYNC, - /* GPIO */ - IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), - /* OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /* USB host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), -}; - -static struct physmap_flash_data pcm037_flash_data = { - .width = 2, -}; - -static struct resource pcm037_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm037_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm037_flash_data, - }, - .resource = &pcm037_flash_resource, - .num_resources = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct resource smsc911x_resources[] = { - { - .start = MX31_CS1_BASE_ADDR + 0x300, - .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), - .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY | - SMSC911X_SAVE_MAC_ADDRESS, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device pcm037_eth = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -static struct platdata_mtd_ram pcm038_sram_data = { - .bankwidth = 2, -}; - -static struct resource pcm038_sram_resource = { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm037_sram_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &pcm038_sram_data, - }, - .num_resources = 1, - .resource = &pcm038_sram_resource, -}; - -static const struct mxc_nand_platform_data -pcm037_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = { - .bitrate = 20000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static int pcm037_camera_power(struct device *dev, int on) -{ - /* disable or enable the camera in X7 or X8 PCM970 connector */ - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on); - return 0; -} - -static struct i2c_board_info pcm037_i2c_camera[] = { - { - I2C_BOARD_INFO("mt9t031", 0x5d), - }, { - I2C_BOARD_INFO("mt9v022", 0x48), - }, -}; - -static struct soc_camera_link iclink_mt9v022 = { - .bus_id = 0, /* Must match with the camera ID */ - .board_info = &pcm037_i2c_camera[1], - .i2c_adapter_id = 2, -}; - -static struct soc_camera_link iclink_mt9t031 = { - .bus_id = 0, /* Must match with the camera ID */ - .power = pcm037_camera_power, - .board_info = &pcm037_i2c_camera[0], - .i2c_adapter_id = 2, -}; - -static struct i2c_board_info pcm037_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - } -}; - -static struct platform_device pcm037_mt9t031 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_mt9t031, - }, -}; - -static struct platform_device pcm037_mt9v022 = { - .name = "soc-camera-pdrv", - .id = 1, - .dev = { - .platform_data = &iclink_mt9v022, - }, -}; - -/* Not connected by default */ -#ifdef PCM970_SDHC_RW_SWITCH -static int pcm970_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6)); -} -#endif - -#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6) -#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6) - -static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_GPIO_DET); - -#ifdef PCM970_SDHC_RW_SWITCH - ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_GPIO_WP); -#endif - - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: -#ifdef PCM970_SDHC_RW_SWITCH - gpio_free(SDHC1_GPIO_WP); -err_gpio_free: -#endif - gpio_free(SDHC1_GPIO_DET); - - return ret; -} - -static void pcm970_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data); - gpio_free(SDHC1_GPIO_DET); - gpio_free(SDHC1_GPIO_WP); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { -#ifdef PCM970_SDHC_RW_SWITCH - .get_ro = pcm970_sdhc1_get_ro, -#endif - .init = pcm970_sdhc1_init, - .exit = pcm970_sdhc1_exit, -}; - -struct mx3_camera_pdata camera_pdata __initdata = { - .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 2000, -}; - -static phys_addr_t mx3_camera_base __initdata; -#define MX3_CAMERA_BUF_SIZE SZ_4M - -static int __init pcm037_init_camera(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata); - - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX3_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; -} - -static struct platform_device *devices[] __initdata = { - &pcm037_flash, - &pcm037_sram_device, - &pcm037_mt9t031, - &pcm037_mt9v022, -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz Sharp */ - .name = "Sharp-LQ035Q7DH06-QVGA", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | - FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "CMEL-OLED", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata = { - .name = "Sharp-LQ035Q7DH06-QVGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct resource pcm970_sja1000_resources[] = { - { - .start = MX31_CS5_BASE_ADDR, - .end = MX31_CS5_BASE_ADDR + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), - .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -struct sja1000_platform_data pcm970_sja1000_platform_data = { - .osc_freq = 16000000, - .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, - .cdr = CDR_CBP, -}; - -static struct platform_device pcm970_sja1000 = { - .name = "sja1000_platform", - .dev = { - .platform_data = &pcm970_sja1000_platform_data, - }, - .resource = pcm970_sja1000_resources, - .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), -}; - -static int pcm037_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = pcm037_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int pcm037_usbh2_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = pcm037_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static int otg_mode_host; - -static int __init pcm037_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", pcm037_otg_mode); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -/* - * Board specific initialization. - */ -static void __init pcm037_init(void) -{ - int ret; - - imx31_soc_init(); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - mxc_iomux_set_gpr(MUX_PGP_UH2, 1); - - mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), - "pcm037"); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ - | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - if (pcm037_variant() == PCM037_EET) - mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, - ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); - else - mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins, - ARRAY_SIZE(pcm037_uart1_handshake_pins), - "pcm037_uart1"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx31_add_imx2_wdt(NULL); - imx31_add_imx_uart0(&uart_pdata); - /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ - imx31_add_imx_uart1(&uart_pdata); - imx31_add_imx_uart2(&uart_pdata); - - imx31_add_mxc_w1(NULL); - - /* LAN9217 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - platform_device_register(&pcm037_eth); - } - - - /* I2C adapters and devices */ - i2c_register_board_info(1, pcm037_i2c_devices, - ARRAY_SIZE(pcm037_i2c_devices)); - - imx31_add_imx_i2c1(&pcm037_i2c1_data); - imx31_add_imx_i2c2(&pcm037_i2c2_data); - - imx31_add_mxc_nand(&pcm037_nand_board_info); - imx31_add_mxc_mmc(0, &sdhc_pdata); - imx31_add_ipu_core(&mx3_ipu_data); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* CSI */ - /* Camera power: default - off */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power"); - if (!ret) - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); - else - iclink_mt9t031.power = NULL; - - pcm037_init_camera(); - - platform_device_register(&pcm970_sja1000); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx31_add_mxc_ehci_otg(&otg_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - if (!otg_mode_host) - imx31_add_fsl_usb2_udc(&otg_device_pdata); - -} - -static void __init pcm037_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -struct sys_timer pcm037_timer = { - .init = pcm037_timer_init, -}; - -static void __init pcm037_reserve(void) -{ - /* reserve 4 MiB for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE, - MX3_CAMERA_BUF_SIZE); -} - -MACHINE_START(PCM037, "Phytec Phycore pcm037") - /* Maintainer: Pengutronix */ - .atag_offset = 0x100, - .reserve = pcm037_reserve, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &pcm037_timer, - .init_machine = pcm037_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm037_eet.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm037_eet.c deleted file mode 100644 index 1b7606be..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm037_eet.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> - -#include <mach/common.h> -#include <mach/iomux-mx3.h> - -#include <asm/mach-types.h> - -#include "pcm037.h" -#include "devices-imx31.h" - -static unsigned int pcm037_eet_pins[] = { - /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */ - IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO), - /* GPIO keys */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */ - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */ - IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */ - IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */ - IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */ - IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */ - IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */ - IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */ - IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */ - IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */ - IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */ - IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */ - IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */ - IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */ - - /* LEDs */ - IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */ - IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */ - IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */ - IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */ -}; - -/* SPI */ -static struct spi_board_info pcm037_spi_dev[] = { - { - .modalias = "dac124s085", - .max_speed_hz = 400000, - .bus_num = 0, - .chip_select = 0, /* Index in pcm037_spi1_cs[] */ - .mode = SPI_CPHA, - }, -}; - -/* Platform Data for MXC CSPI */ -static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)}; - -static const struct spi_imx_master pcm037_spi1_pdata __initconst = { - .chipselect = pcm037_spi1_cs, - .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs), -}; - -/* GPIO-keys input device */ -static struct gpio_keys_button pcm037_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_L, - .gpio = 0, - .desc = "Wheel Manual", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_A, - .gpio = 1, - .desc = "Wheel AF", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_V, - .gpio = 2, - .desc = "Wheel View", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_M, - .gpio = 3, - .desc = "Wheel Menu", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_UP, - .gpio = 32, - .desc = "Nav Pad Up", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_RIGHT, - .gpio = 33, - .desc = "Nav Pad Right", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_DOWN, - .gpio = 34, - .desc = "Nav Pad Down", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_LEFT, - .gpio = 35, - .desc = "Nav Pad Left", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_ENTER, - .gpio = 38, - .desc = "Nav Pad Ok", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_O, - .gpio = 39, - .desc = "Wheel Off", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_FORWARD, - .gpio = 50, - .desc = "Focus Forward", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_BACK, - .gpio = 51, - .desc = "Focus Backward", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_MIDDLE, - .gpio = 52, - .desc = "Release Half", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_EXTRA, - .gpio = 53, - .desc = "Release Full", - .wakeup = 0, - }, -}; - -static const struct gpio_keys_platform_data - pcm037_gpio_keys_platform_data __initconst = { - .buttons = pcm037_gpio_keys, - .nbuttons = ARRAY_SIZE(pcm037_gpio_keys), - .rep = 0, /* No auto-repeat */ -}; - -static int __init eet_init_devices(void) -{ - if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET) - return 0; - - mxc_iomux_setup_multiple_pins(pcm037_eet_pins, - ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet"); - - /* SPI */ - spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); - imx31_add_spi_imx0(&pcm037_spi1_pdata); - - imx_add_gpio_keys(&pcm037_gpio_keys_platform_data); - - return 0; -} -late_initcall(eet_init_devices); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm038.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm038.c deleted file mode 100644 index 2f3debe2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm038.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/io.h> -#include <linux/mtd/plat-ram.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/irq.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/board-pcm038.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx27.h> -#include <mach/ulpi.h> - -#include "devices-imx27.h" - -static const int pcm038_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART2 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART3 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* SPI1 */ - PD25_PF_CSPI1_RDY, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* SSI4 */ - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD, - PC18_PF_SSI4_TXD, - PC19_PF_SSI4_CLK, - /* USB host */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, -}; - -/* - * Phytec's PCM038 comes with 2MiB battery buffered SRAM, - * 16 bit width - */ - -static struct platdata_mtd_ram pcm038_sram_data = { - .bankwidth = 2, -}; - -static struct resource pcm038_sram_resource = { - .start = MX27_CS1_BASE_ADDR, - .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm038_sram_mtd_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &pcm038_sram_data, - }, - .num_resources = 1, - .resource = &pcm038_sram_resource, -}; - -/* - * Phytec's phyCORE-i.MX27 comes with 32MiB flash, - * 16 bit width - */ -static struct physmap_flash_data pcm038_flash_data = { - .width = 2, -}; - -static struct resource pcm038_flash_resource = { - .start = 0xc0000000, - .end = 0xc1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm038_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm038_flash_data, - }, - .num_resources = 1, - .resource = &pcm038_flash_resource, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -pcm038_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct platform_device *platform_devices[] __initdata = { - &pcm038_nor_mtd_device, - &pcm038_sram_mtd_device, -}; - -/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and - * setup other stuffs to access the sram. */ -static void __init pcm038_init_sram(void) -{ - __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1))); - __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1))); - __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1))); -} - -static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pcm038_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("lm75", 0x4a), - } -}; - -static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; - -static const struct spi_imx_master pcm038_spi0_data __initconst = { - .chipselect = pcm038_spi_cs, - .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), -}; - -static struct regulator_consumer_supply sdhc1_consumers[] = { - { - .dev_name = "mxc-mmc.1", - .supply = "sdhc_vcc", - }, -}; - -static struct regulator_init_data sdhc1_data = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3400000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 0, - }, - .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers), - .consumer_supplies = sdhc1_consumers, -}; - -static struct regulator_consumer_supply cam_consumers[] = { - { - .dev_name = NULL, - .supply = "imx_cam_vcc", - }, -}; - -static struct regulator_init_data cam_data = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3400000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 0, - }, - .num_consumer_supplies = ARRAY_SIZE(cam_consumers), - .consumer_supplies = cam_consumers, -}; - -static struct mc13xxx_regulator_init_data pcm038_regulators[] = { - { - .id = MC13783_REG_VCAM, - .init_data = &cam_data, - }, { - .id = MC13783_REG_VMMC1, - .init_data = &sdhc1_data, - }, -}; - -static struct mc13xxx_platform_data pcm038_pmic = { - .regulators = { - .regulators = pcm038_regulators, - .num_regulators = ARRAY_SIZE(pcm038_regulators), - }, - .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, -}; - -static struct spi_board_info pcm038_spi_board_info[] __initdata = { - { - .modalias = "mc13783", - .irq = IRQ_GPIOB(23), - .max_speed_hz = 300000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &pcm038_pmic, - .mode = SPI_CS_HIGH, - } -}; - -static int pcm038_usbh2_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { - .init = pcm038_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void __init pcm038_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), - "PCM038"); - - pcm038_init_sram(); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - - mxc_gpio_mode(PE16_AF_OWIRE); - imx27_add_mxc_nand(&pcm038_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, pcm038_i2c_devices, - ARRAY_SIZE(pcm038_i2c_devices)); - - imx27_add_imx_i2c(1, &pcm038_i2c1_data); - - /* PE18 for user-LED D40 */ - mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); - - /* MC13783 IRQ */ - mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN); - - imx27_add_spi_imx0(&pcm038_spi0_data); - spi_register_board_info(pcm038_spi_board_info, - ARRAY_SIZE(pcm038_spi_board_info)); - - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); - - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx27_add_imx2_wdt(NULL); - imx27_add_mxc_w1(NULL); - -#ifdef CONFIG_MACH_PCM970_BASEBOARD - pcm970_baseboard_init(); -#endif -} - -static void __init pcm038_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -static struct sys_timer pcm038_timer = { - .init = pcm038_timer_init, -}; - -MACHINE_START(PCM038, "phyCORE-i.MX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .timer = &pcm038_timer, - .init_machine = pcm038_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm043.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm043.c deleted file mode 100644 index 237474fc..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-pcm043.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Copyright (C) 2009 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/smc911x.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx35.h> -#include <mach/ulpi.h> - -#include "devices-imx35.h" - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz */ - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Sharp-LQ035Q7", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data pcm043_flash_data = { - .width = 2, -}; - -static struct resource pcm043_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm043_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm043_flash_data, - }, - .resource = &pcm043_flash_resource, - .num_resources = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { - .bitrate = 50000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pcm043_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -static struct platform_device *devices[] __initdata = { - &pcm043_flash, -}; - -static iomux_v3_cfg_t pcm043_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - /* gpio */ - MX35_PAD_ATA_CS0__GPIO2_6, - /* USB host */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, - /* SSI */ - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, - MX35_PAD_STXD4__AUDMUX_AUD4_TXD, - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, - MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* CAN2 */ - MX35_PAD_TX5_RX0__CAN2_TXCAN, - MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* esdhc */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ - MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ -}; - -#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) -#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) -#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) -#define SD1_GPIO_WP IMX_GPIO_NR(2, 23) -#define SD1_GPIO_CD IMX_GPIO_NR(2, 24) - -static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) -{ - iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - int ret; - - ret = gpio_request(AC97_GPIO_TXFS, "SSI"); - if (ret) { - printk("failed to get GPIO_TXFS: %d\n", ret); - return; - } - - mxc_iomux_v3_setup_pad(txfs_gpio); - - /* warm reset */ - gpio_direction_output(AC97_GPIO_TXFS, 1); - udelay(2); - gpio_set_value(AC97_GPIO_TXFS, 0); - - gpio_free(AC97_GPIO_TXFS); - mxc_iomux_v3_setup_pad(txfs); -} - -static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) -{ - iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; - iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; - iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; - int ret; - - ret = gpio_request(AC97_GPIO_TXFS, "SSI"); - if (ret) - goto err1; - - ret = gpio_request(AC97_GPIO_TXD, "SSI"); - if (ret) - goto err2; - - ret = gpio_request(AC97_GPIO_RESET, "SSI"); - if (ret) - goto err3; - - mxc_iomux_v3_setup_pad(txfs_gpio); - mxc_iomux_v3_setup_pad(txd_gpio); - mxc_iomux_v3_setup_pad(reset_gpio); - - gpio_direction_output(AC97_GPIO_TXFS, 0); - gpio_direction_output(AC97_GPIO_TXD, 0); - - /* cold reset */ - gpio_direction_output(AC97_GPIO_RESET, 0); - udelay(10); - gpio_direction_output(AC97_GPIO_RESET, 1); - - mxc_iomux_v3_setup_pad(txd); - mxc_iomux_v3_setup_pad(txfs); - - gpio_free(AC97_GPIO_RESET); -err3: - gpio_free(AC97_GPIO_TXD); -err2: - gpio_free(AC97_GPIO_TXFS); -err1: - if (ret) - printk("%s failed with %d\n", __func__, ret); - mdelay(1); -} - -static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { - .ac97_reset = pcm043_ac97_cold_reset, - .ac97_warm_reset = pcm043_ac97_warm_reset, - .flags = IMX_SSI_USE_AC97, -}; - -static const struct mxc_nand_platform_data -pcm037_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static int pcm043_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = pcm043_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int pcm043_usbh1_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = pcm043_usbh1_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -static int otg_mode_host; - -static int __init pcm043_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = 1; - else if (!strcmp(options, "device")) - otg_mode_host = 0; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 0; -} -__setup("otg_mode=", pcm043_otg_mode); - -static struct esdhc_platform_data sd1_pdata = { - .wp_gpio = SD1_GPIO_WP, - .cd_gpio = SD1_GPIO_CD, - .wp_type = ESDHC_WP_GPIO, - .cd_type = ESDHC_CD_GPIO, -}; - -/* - * Board specific initialization. - */ -static void __init pcm043_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - - imx35_add_fec(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx35_add_imx2_wdt(NULL); - - imx35_add_imx_uart0(&uart_pdata); - imx35_add_mxc_nand(&pcm037_nand_board_info); - imx35_add_imx_ssi(0, &pcm043_ssi_pdata); - - imx35_add_imx_uart1(&uart_pdata); - - i2c_register_board_info(0, pcm043_i2c_devices, - ARRAY_SIZE(pcm043_i2c_devices)); - - imx35_add_imx_i2c0(&pcm043_i2c0_data); - - imx35_add_ipu_core(&mx3_ipu_data); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx35_add_mxc_ehci_otg(&otg_pdata); - } - imx35_add_mxc_ehci_hs(&usbh1_pdata); - - if (!otg_mode_host) - imx35_add_fsl_usb2_udc(&otg_device_pdata); - - imx35_add_flexcan1(NULL); - imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); -} - -static void __init pcm043_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer pcm043_timer = { - .init = pcm043_timer_init, -}; - -MACHINE_START(PCM043, "Phytec Phycore pcm043") - /* Maintainer: Pengutronix */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .timer = &pcm043_timer, - .init_machine = pcm043_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-qong.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-qong.c deleted file mode 100644 index 26062105..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-qong.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/memory.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/nand.h> -#include <linux/gpio.h> - -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <mach/common.h> -#include <asm/page.h> -#include <asm/setup.h> -#include <mach/iomux-mx3.h> - -#include "devices-imx31.h" - -/* FPGA defines */ -#define QONG_FPGA_VERSION(major, minor, rev) \ - (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) - -#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR -#define QONG_FPGA_PERIPH_SIZE (1 << 24) - -#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR -#define QONG_FPGA_CTRL_SIZE 0x10 -/* FPGA control registers */ -#define QONG_FPGA_CTRL_VERSION 0x00 - -#define QONG_DNET_ID 1 -#define QONG_DNET_BASEADDR \ - (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) -#define QONG_DNET_SIZE 0x00001000 - -#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 -}; - -static inline void __init mxc_init_imx_uart(void) -{ - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), - "uart-0"); - imx31_add_imx_uart0(&uart_pdata); -} - -static struct resource dnet_resources[] = { - { - .name = "dnet-memory", - .start = QONG_DNET_BASEADDR, - .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .start = QONG_FPGA_IRQ, - .end = QONG_FPGA_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dnet_device = { - .name = "dnet", - .id = -1, - .num_resources = ARRAY_SIZE(dnet_resources), - .resource = dnet_resources, -}; - -static int __init qong_init_dnet(void) -{ - int ret; - - ret = platform_device_register(&dnet_device); - return ret; -} - -/* MTD NOR flash */ - -static struct physmap_flash_data qong_flash_data = { - .width = 2, -}; - -static struct resource qong_flash_resource = { - .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + SZ_128M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device qong_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &qong_flash_data, - }, - .resource = &qong_flash_resource, - .num_resources = 1, -}; - -static void qong_init_nor_mtd(void) -{ - (void)platform_device_register(&qong_nor_mtd_device); -} - -/* - * Hardware specific access to control-lines - */ -static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *nand_chip = mtd->priv; - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24)); - else - writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23)); -} - -/* - * Read the Device Ready pin. - */ -static int qong_nand_device_ready(struct mtd_info *mtd) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB)); -} - -static void qong_nand_select_chip(struct mtd_info *mtd, int chip) -{ - if (chip >= 0) - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); - else - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1); -} - -static struct platform_nand_data qong_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 20, - .options = 0, - }, - .ctrl = { - .cmd_ctrl = qong_nand_cmd_ctrl, - .dev_ready = qong_nand_device_ready, - .select_chip = qong_nand_select_chip, - } -}; - -static struct resource qong_nand_resource = { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device qong_nand_device = { - .name = "gen_nand", - .id = -1, - .dev = { - .platform_data = &qong_nand_data, - }, - .num_resources = 1, - .resource = &qong_nand_resource, -}; - -static void __init qong_init_nand_mtd(void) -{ - /* init CS */ - __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); - __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); - __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); - - mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); - - /* enable pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); - - /* ready/busy pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); - - /* write protect pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); - - platform_device_register(&qong_nand_device); -} - -static void __init qong_init_fpga(void) -{ - void __iomem *regs; - u32 fpga_ver; - - regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE); - if (!regs) { - printk(KERN_ERR "%s: failed to map registers, aborting.\n", - __func__); - return; - } - - fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION); - iounmap(regs); - printk(KERN_INFO "Qong FPGA version %d.%d.%d\n", - (fpga_ver & 0xF000) >> 12, - (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF); - if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) { - printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based " - "devices won't be registered!\n"); - return; - } - - /* register FPGA-based devices */ - qong_init_nand_mtd(); - qong_init_dnet(); -} - -/* - * Board specific initialization. - */ -static void __init qong_init(void) -{ - imx31_soc_init(); - - mxc_init_imx_uart(); - qong_init_nor_mtd(); - qong_init_fpga(); - imx31_add_imx2_wdt(NULL); -} - -static void __init qong_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static struct sys_timer qong_timer = { - .init = qong_timer_init, -}; - -MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") - /* Maintainer: DENX Software Engineering GmbH */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .timer = &qong_timer, - .init_machine = qong_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-scb9328.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-scb9328.c deleted file mode 100644 index cb9ceae2..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-scb9328.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * linux/arch/arm/mach-mx1/mach-scb9328.c - * - * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> - * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/interrupt.h> -#include <linux/dm9000.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/iomux-mx1.h> - -#include "devices-imx1.h" - -/* - * This scb9328 has a 32MiB flash - */ -static struct resource flash_resource = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1, - .flags = IORESOURCE_MEM, -}; - -static struct physmap_flash_data scb_flash_data = { - .width = 2, -}; - -static struct platform_device scb_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &scb_flash_data, - }, - .resource = &flash_resource, - .num_resources = 1, -}; - -/* - * scb9328 has a DM9000 network controller - * connected to CS5, with 16 bit data path - * and interrupt connected to GPIO 3 - */ - -/* - * internal datapath is fixed 16 bit - */ -static struct dm9000_plat_data dm9000_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -/* - * the DM9000 drivers wants two defined address spaces - * to gain access to address latch registers and the data path. - */ -static struct resource dm9000x_resources[] = { - { - .name = "address area", - .start = MX1_CS5_PHYS, - .end = MX1_CS5_PHYS + 1, - .flags = IORESOURCE_MEM, /* address access */ - }, { - .name = "data area", - .start = MX1_CS5_PHYS + 4, - .end = MX1_CS5_PHYS + 5, - .flags = IORESOURCE_MEM, /* data access */ - }, { - .start = IRQ_GPIOC(3), - .end = IRQ_GPIOC(3), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct platform_device dm9000x_device = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9000x_resources), - .resource = dm9000x_resources, - .dev = { - .platform_data = &dm9000_platdata, - } -}; - -static const int mxc_uart1_pins[] = { - PC9_PF_UART1_CTS, - PC10_PF_UART1_RTS, - PC11_PF_UART1_TXD, - PC12_PF_UART1_RXD, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &scb_flash_device, - &dm9000x_device, -}; - -/* - * scb9328_init - Init the CPU card itself - */ -static void __init scb9328_init(void) -{ - imx1_soc_init(); - - mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), "UART1"); - - imx1_add_imx_uart0(&uart_pdata); - - printk(KERN_INFO"Scb9328: Adding devices\n"); - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init scb9328_timer_init(void) -{ - mx1_clocks_init(32000); -} - -static struct sys_timer scb9328_timer = { - .init = scb9328_timer_init, -}; - -MACHINE_START(SCB9328, "Synertronixx scb9328") - /* Sascha Hauer */ - .atag_offset = 100, - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .timer = &scb9328_timer, - .init_machine = scb9328_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mach-vpr200.c b/ANDROID_3.4.5/arch/arm/mach-imx/mach-vpr200.c deleted file mode 100644 index 033257e5..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mach-vpr200.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix - * Copyright 2010 Creative Product Design - * - * Derived from mx35 3stack. - * Original author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/memory.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx35.h> -#include <mach/irqs.h> - -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/mfd/mc13xxx.h> - -#include "devices-imx35.h" - -#define GPIO_LCDPWR IMX_GPIO_NR(1, 2) -#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) - -#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4) -#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5) -#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7) -#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8) -#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9) -#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10) -#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11) -#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12) - -static const struct fb_videomode fb_modedb[] = { - { - /* 800x480 @ 60 Hz */ - .name = "PT0708048", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(33260), - .left_margin = 50, - .right_margin = 156, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 800x480 @ 60 Hz */ - .name = "CTP-CLAA070LC0ACW", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(27000), - .left_margin = 50, - .right_margin = 50, /* whole line should have 900 clocks */ - .upper_margin = 10, - .lower_margin = 10, /* whole frame should have 500 lines */ - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - } -}; - -static const struct ipu_platform_data mx3_ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "PT0708048", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data vpr200_flash_data = { - .width = 2, -}; - -static struct resource vpr200_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device vpr200_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &vpr200_flash_data, - }, - .resource = &vpr200_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data - vpr200_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#define VPR_KEY_DEBOUNCE 500 -static struct gpio_keys_button vpr200_gpio_keys_table[] = { - {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE}, - {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE}, - {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE}, - {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE}, - {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE}, - {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE}, - {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE}, - {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE}, -}; - -static const struct gpio_keys_platform_data - vpr200_gpio_keys_data __initconst = { - .buttons = vpr200_gpio_keys_table, - .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table), -}; - -static struct mc13xxx_platform_data vpr200_pmic = { - .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, -}; - -static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = { - .bitrate = 50000, -}; - -static struct at24_platform_data vpr200_eeprom = { - .byte_len = 2048 / 8, - .page_size = 1, -}; - -static struct i2c_board_info vpr200_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */ - .platform_data = &vpr200_eeprom, - }, { - I2C_BOARD_INFO("mc13892", 0x08), - .platform_data = &vpr200_pmic, - .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT), - } -}; - -static iomux_v3_cfg_t vpr200_pads[] = { - /* UART1 */ - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART3 */ - MX35_PAD_ATA_DATA10__UART3_RXD_MUX, - MX35_PAD_ATA_DATA11__UART3_TXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - /* LCD Enable */ - MX35_PAD_D3_VSYNC__GPIO1_2, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* PMIC */ - MX35_PAD_GPIO2_0__GPIO2_0, - /* GPIO keys */ - MX35_PAD_SCKR__GPIO1_4, - MX35_PAD_COMPARE__GPIO1_5, - MX35_PAD_SCKT__GPIO1_7, - MX35_PAD_FST__GPIO1_8, - MX35_PAD_HCKT__GPIO1_9, - MX35_PAD_TX5_RX0__GPIO1_10, - MX35_PAD_TX4_RX1__GPIO1_11, - MX35_PAD_TX3_RX2__GPIO1_12, -}; - -/* USB Device config */ -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -}; - -static int vpr200_usbh_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, - MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY); -} - -/* USB HOST config */ -static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .init = vpr200_usbh_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static struct platform_device *devices[] __initdata = { - &vpr200_flash, -}; - -/* - * Board specific initialization. - */ -static void __init vpr200_board_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(NULL); - imx_add_gpio_keys(&vpr200_gpio_keys_data); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR")) - printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n"); - else - gpio_direction_output(GPIO_LCDPWR, 0); - - if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT")) - printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n"); - else - gpio_direction_input(GPIO_PMIC_INT); - - imx35_add_imx_uart0(NULL); - imx35_add_imx_uart2(NULL); - - imx35_add_ipu_core(&mx3_ipu_data); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - imx35_add_fsl_usb2_udc(&otg_device_pdata); - imx35_add_mxc_ehci_hs(&usb_host_pdata); - - imx35_add_mxc_nand(&vpr200_nand_board_info); - imx35_add_sdhci_esdhc_imx(0, NULL); - - i2c_register_board_info(0, vpr200_i2c_devices, - ARRAY_SIZE(vpr200_i2c_devices)); - - imx35_add_imx_i2c0(&vpr200_i2c0_data); -} - -static void __init vpr200_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer vpr200_timer = { - .init = vpr200_timer_init, -}; - -MACHINE_START(VPR200, "VPR200") - /* Maintainer: Creative Product Design */ - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .timer = &vpr200_timer, - .init_machine = vpr200_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx1.c b/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx1.c deleted file mode 100644 index 2bded591..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx1.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX1 machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/iomux-v1.h> - -static struct map_desc imx_io_desc[] __initdata = { - imx_map_entry(MX1, IO, MT_DEVICE), -}; - -void __init mx1_map_io(void) -{ - iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); -} - -void __init imx1_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX1); - mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); - imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), - MX1_NUM_GPIO_PORT); -} - -void __init mx1_init_irq(void) -{ - mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); -} - -void __init imx1_soc_init(void) -{ - mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTA, 0); - mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTB, 0); - mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTC, 0); - mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTD, 0); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx21.c b/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx21.c deleted file mode 100644 index 14d540ed..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx21.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-imx/mm-imx21.c - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/devices-common.h> -#include <asm/pgtable.h> -#include <asm/mach/map.h> -#include <mach/irqs.h> -#include <mach/iomux-v1.h> - -/* MX21 memory map definition */ -static struct map_desc imx21_io_desc[] __initdata = { - /* - * this fixed mapping covers: - * - AIPI1 - * - AIPI2 - * - AITC - * - ROM Patch - * - and some reserved space - */ - imx_map_entry(MX21, AIPI, MT_DEVICE), - /* - * this fixed mapping covers: - * - CSI - * - ATA - */ - imx_map_entry(MX21, SAHB1, MT_DEVICE), - /* - * this fixed mapping covers: - * - EMI - */ - imx_map_entry(MX21, X_MEMC, MT_DEVICE), -}; - -/* - * Initialize the memory map. It is called during the - * system startup to create static physical to virtual - * memory map for the IO modules. - */ -void __init mx21_map_io(void) -{ - iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); -} - -void __init imx21_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX21); - mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); - imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), - MX21_NUM_GPIO_PORT); -} - -void __init mx21_init_irq(void) -{ - mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); -} - -static const struct resource imx21_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K), -}; - -void __init imx21_soc_init(void) -{ - mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - - imx_add_imx_dma(); - platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, - ARRAY_SIZE(imx21_audmux_res)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx25.c b/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx25.c deleted file mode 100644 index 153b457a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx25.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/err.h> - -#include <asm/pgtable.h> -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/devices-common.h> -#include <mach/hardware.h> -#include <mach/mx25.h> -#include <mach/iomux-v3.h> -#include <mach/irqs.h> - -/* - * This table defines static virtual address mappings for I/O regions. - * These are the mappings common across all MX25 boards. - */ -static struct map_desc mx25_io_desc[] __initdata = { - imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx25_map_io(void) -{ - iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); -} - -void __init imx25_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX25); - mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); -} - -void __init mx25_init_irq(void) -{ - mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx25_sdma_script __initdata = { - .ap_2_ap_addr = 729, - .uart_2_mcu_addr = 904, - .per_2_app_addr = 1255, - .mcu_2_app_addr = 834, - .uartsh_2_mcu_addr = 1120, - .per_2_shp_addr = 1329, - .mcu_2_shp_addr = 1048, - .ata_2_mcu_addr = 1560, - .mcu_2_ata_addr = 1479, - .app_2_per_addr = 1189, - .app_2_mcu_addr = 770, - .shp_2_per_addr = 1407, - .shp_2_mcu_addr = 979, -}; - -static struct sdma_platform_data imx25_sdma_pdata __initdata = { - .fw_name = "sdma-imx25.bin", - .script_addrs = &imx25_sdma_script, -}; - -static const struct resource imx25_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx25_soc_init(void) -{ - /* i.mx25 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); - mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); - - /* i.mx25 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); - /* i.mx25 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res, - ARRAY_SIZE(imx25_audmux_res)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx27.c b/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx27.c deleted file mode 100644 index 8cb3f5e3..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx27.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-imx/mm-imx27.c - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/devices-common.h> -#include <asm/pgtable.h> -#include <asm/mach/map.h> -#include <mach/irqs.h> -#include <mach/iomux-v1.h> - -/* MX27 memory map definition */ -static struct map_desc imx27_io_desc[] __initdata = { - /* - * this fixed mapping covers: - * - AIPI1 - * - AIPI2 - * - AITC - * - ROM Patch - * - and some reserved space - */ - imx_map_entry(MX27, AIPI, MT_DEVICE), - /* - * this fixed mapping covers: - * - CSI - * - ATA - */ - imx_map_entry(MX27, SAHB1, MT_DEVICE), - /* - * this fixed mapping covers: - * - EMI - */ - imx_map_entry(MX27, X_MEMC, MT_DEVICE), -}; - -/* - * Initialize the memory map. It is called during the - * system startup to create static physical to virtual - * memory map for the IO modules. - */ -void __init mx27_map_io(void) -{ - iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); -} - -void __init imx27_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX27); - mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), - MX27_NUM_GPIO_PORT); -} - -void __init mx27_init_irq(void) -{ - mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); -} - -static const struct resource imx27_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K), -}; - -void __init imx27_soc_init(void) -{ - /* i.mx27 has the i.mx21 type gpio */ - mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - - imx_add_imx_dma(); - /* imx27 has the imx21 type audmux */ - platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, - ARRAY_SIZE(imx27_audmux_res)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx3.c b/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx3.c deleted file mode 100644 index 74127389..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx3.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/err.h> - -#include <asm/pgtable.h> -#include <asm/system_misc.h> -#include <asm/hardware/cache-l2x0.h> -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/devices-common.h> -#include <mach/hardware.h> -#include <mach/iomux-v3.h> -#include <mach/irqs.h> - -static void imx3_idle(void) -{ - unsigned long reg = 0; - - mx3_cpu_lp_set(MX3_WAIT); - - __asm__ __volatile__( - /* disable I and D cache */ - "mrc p15, 0, %0, c1, c0, 0\n" - "bic %0, %0, #0x00001000\n" - "bic %0, %0, #0x00000004\n" - "mcr p15, 0, %0, c1, c0, 0\n" - /* invalidate I cache */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c5, 0\n" - /* clear and invalidate D cache */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c14, 0\n" - /* WFI */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c0, 4\n" - "nop\n" "nop\n" "nop\n" "nop\n" - "nop\n" "nop\n" "nop\n" - /* enable I and D cache */ - "mrc p15, 0, %0, c1, c0, 0\n" - "orr %0, %0, #0x00001000\n" - "orr %0, %0, #0x00000004\n" - "mcr p15, 0, %0, c1, c0, 0\n" - : "=r" (reg)); -} - -static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size, - unsigned int mtype, void *caller) -{ - if (mtype == MT_DEVICE) { - /* - * Access all peripherals below 0x80000000 as nonshared device - * on mx3, but leave l2cc alone. Otherwise cache corruptions - * can occur. - */ - if (phys_addr < 0x80000000 && - !addr_in_module(phys_addr, MX3x_L2CC)) - mtype = MT_DEVICE_NONSHARED; - } - - return __arm_ioremap_caller(phys_addr, size, mtype, caller); -} - -void __init imx3_init_l2x0(void) -{ - void __iomem *l2x0_base; - void __iomem *clkctl_base; - -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value. - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (IS_ERR(l2x0_base)) { - printk(KERN_ERR "remapping L2 cache area failed with %ld\n", - PTR_ERR(l2x0_base)); - return; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); -} - -#ifdef CONFIG_SOC_IMX31 -static struct map_desc mx31_io_desc[] __initdata = { - imx_map_entry(MX31, X_MEMC, MT_DEVICE), - imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx31_map_io(void) -{ - iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); -} - -void __init imx31_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX31); - mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); - arch_ioremap_caller = imx3_ioremap_caller; - arm_pm_idle = imx3_idle; -} - -void __init mx31_init_irq(void) -{ - mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { - .per_2_per_addr = 1677, -}; - -static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { - .ap_2_ap_addr = 423, - .ap_2_bp_addr = 829, - .bp_2_ap_addr = 1029, -}; - -static struct sdma_platform_data imx31_sdma_pdata __initdata = { - .fw_name = "sdma-imx31-to2.bin", - .script_addrs = &imx31_to2_sdma_script, -}; - -static const struct resource imx31_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx31_soc_init(void) -{ - int to_version = mx31_revision() >> 4; - - imx3_init_l2x0(); - - mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); - - if (to_version == 1) { - strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", - strlen(imx31_sdma_pdata.fw_name)); - imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; - } - - imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); - - imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); - imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); - - platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, - ARRAY_SIZE(imx31_audmux_res)); -} -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -static struct map_desc mx35_io_desc[] __initdata = { - imx_map_entry(MX35, X_MEMC, MT_DEVICE), - imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), -}; - -void __init mx35_map_io(void) -{ - iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); -} - -void __init imx35_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); - arm_pm_idle = imx3_idle; - arch_ioremap_caller = imx3_ioremap_caller; -} - -void __init mx35_init_irq(void) -{ - mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .uart_2_mcu_addr = 817, - .mcu_2_app_addr = 747, - .uartsh_2_mcu_addr = 1183, - .per_2_shp_addr = 1033, - .mcu_2_shp_addr = 961, - .ata_2_mcu_addr = 1333, - .mcu_2_ata_addr = 1252, - .app_2_mcu_addr = 683, - .shp_2_per_addr = 1111, - .shp_2_mcu_addr = 892, -}; - -static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { - .ap_2_ap_addr = 729, - .uart_2_mcu_addr = 904, - .per_2_app_addr = 1597, - .mcu_2_app_addr = 834, - .uartsh_2_mcu_addr = 1270, - .per_2_shp_addr = 1120, - .mcu_2_shp_addr = 1048, - .ata_2_mcu_addr = 1429, - .mcu_2_ata_addr = 1339, - .app_2_per_addr = 1531, - .app_2_mcu_addr = 770, - .shp_2_per_addr = 1198, - .shp_2_mcu_addr = 979, -}; - -static struct sdma_platform_data imx35_sdma_pdata __initdata = { - .fw_name = "sdma-imx35-to2.bin", - .script_addrs = &imx35_to2_sdma_script, -}; - -static const struct resource imx35_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx35_soc_init(void) -{ - int to_version = mx35_revision() >> 4; - - imx3_init_l2x0(); - - /* i.mx35 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); - - if (to_version == 1) { - strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", - strlen(imx35_sdma_pdata.fw_name)); - imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; - } - - imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); - imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); - - /* i.mx35 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, - ARRAY_SIZE(imx35_audmux_res)); -} -#endif /* ifdef CONFIG_SOC_IMX35 */ diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx5.c b/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx5.c deleted file mode 100644 index e10f3914..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mm-imx5.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Create static mapping between physical to virtual memory. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/clk.h> - -#include <asm/system_misc.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/devices-common.h> -#include <mach/iomux-v3.h> - -static struct clk *gpc_dvfs_clk; - -static void imx5_idle(void) -{ - /* gpc clock is needed for SRPG */ - if (gpc_dvfs_clk == NULL) { - gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); - if (IS_ERR(gpc_dvfs_clk)) - return; - } - clk_enable(gpc_dvfs_clk); - mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - if (!tzic_enable_wake()) - cpu_do_idle(); - clk_disable(gpc_dvfs_clk); -} - -/* - * Define the MX50 memory map. - */ -static struct map_desc mx50_io_desc[] __initdata = { - imx_map_entry(MX50, TZIC, MT_DEVICE), - imx_map_entry(MX50, SPBA0, MT_DEVICE), - imx_map_entry(MX50, AIPS1, MT_DEVICE), - imx_map_entry(MX50, AIPS2, MT_DEVICE), -}; - -/* - * Define the MX51 memory map. - */ -static struct map_desc mx51_io_desc[] __initdata = { - imx_map_entry(MX51, TZIC, MT_DEVICE), - imx_map_entry(MX51, IRAM, MT_DEVICE), - imx_map_entry(MX51, AIPS1, MT_DEVICE), - imx_map_entry(MX51, SPBA0, MT_DEVICE), - imx_map_entry(MX51, AIPS2, MT_DEVICE), -}; - -/* - * Define the MX53 memory map. - */ -static struct map_desc mx53_io_desc[] __initdata = { - imx_map_entry(MX53, TZIC, MT_DEVICE), - imx_map_entry(MX53, AIPS1, MT_DEVICE), - imx_map_entry(MX53, SPBA0, MT_DEVICE), - imx_map_entry(MX53, AIPS2, MT_DEVICE), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx50_map_io(void) -{ - iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); -} - -void __init mx51_map_io(void) -{ - iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); -} - -void __init mx53_map_io(void) -{ - iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); -} - -void __init imx50_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX50); - mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); -} - -void __init imx51_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX51); - mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); - arm_pm_idle = imx5_idle; -} - -void __init imx53_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX53); - mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); -} - -void __init mx50_init_irq(void) -{ - tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); -} - -void __init mx51_init_irq(void) -{ - tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); -} - -void __init mx53_init_irq(void) -{ - tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx51_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .uart_2_mcu_addr = 817, - .mcu_2_app_addr = 747, - .mcu_2_shp_addr = 961, - .ata_2_mcu_addr = 1473, - .mcu_2_ata_addr = 1392, - .app_2_per_addr = 1033, - .app_2_mcu_addr = 683, - .shp_2_per_addr = 1251, - .shp_2_mcu_addr = 892, -}; - -static struct sdma_platform_data imx51_sdma_pdata __initdata = { - .fw_name = "sdma-imx51.bin", - .script_addrs = &imx51_sdma_script, -}; - -static struct sdma_script_start_addrs imx53_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .app_2_mcu_addr = 683, - .mcu_2_app_addr = 747, - .uart_2_mcu_addr = 817, - .shp_2_mcu_addr = 891, - .mcu_2_shp_addr = 960, - .uartsh_2_mcu_addr = 1032, - .spdif_2_mcu_addr = 1100, - .mcu_2_spdif_addr = 1134, - .firi_2_mcu_addr = 1193, - .mcu_2_firi_addr = 1290, -}; - -static struct sdma_platform_data imx53_sdma_pdata __initdata = { - .fw_name = "sdma-imx53.bin", - .script_addrs = &imx53_sdma_script, -}; - -static const struct resource imx50_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), -}; - -static const struct resource imx51_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), -}; - -static const struct resource imx53_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx50_soc_init(void) -{ - /* i.mx50 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); - mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); - mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); - mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); - mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); - mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); - - /* i.mx50 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res, - ARRAY_SIZE(imx50_audmux_res)); -} - -void __init imx51_soc_init(void) -{ - /* i.mx51 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); - mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); - mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); - mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); - - /* i.mx51 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR)); - imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); - - /* i.mx51 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, - ARRAY_SIZE(imx51_audmux_res)); -} - -void __init imx53_soc_init(void) -{ - /* i.mx53 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); - mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); - mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); - mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); - mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); - mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); - mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); - - /* i.mx53 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); - imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); - - /* i.mx53 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, - ARRAY_SIZE(imx53_audmux_res)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mmdc.c b/ANDROID_3.4.5/arch/arm/mach-imx/mmdc.c deleted file mode 100644 index c461e984..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mmdc.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> - -#define MMDC_MAPSR 0x404 -#define BP_MMDC_MAPSR_PSD 0 -#define BP_MMDC_MAPSR_PSS 4 - -static int __devinit imx_mmdc_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - void __iomem *mmdc_base, *reg; - u32 val; - int timeout = 0x400; - - mmdc_base = of_iomap(np, 0); - WARN_ON(!mmdc_base); - - reg = mmdc_base + MMDC_MAPSR; - - /* Enable automatic power saving */ - val = readl_relaxed(reg); - val &= ~(1 << BP_MMDC_MAPSR_PSD); - writel_relaxed(val, reg); - - /* Ensure it's successfully enabled */ - while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout) - cpu_relax(); - - if (unlikely(!timeout)) { - pr_warn("%s: failed to enable automatic power saving\n", - __func__); - return -EBUSY; - } - - return 0; -} - -static struct of_device_id imx_mmdc_dt_ids[] = { - { .compatible = "fsl,imx6q-mmdc", }, - { /* sentinel */ } -}; - -static struct platform_driver imx_mmdc_driver = { - .driver = { - .name = "imx-mmdc", - .owner = THIS_MODULE, - .of_match_table = imx_mmdc_dt_ids, - }, - .probe = imx_mmdc_probe, -}; - -static int __init imx_mmdc_init(void) -{ - return platform_driver_register(&imx_mmdc_driver); -} -postcore_initcall(imx_mmdc_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx1-camera-fiq-ksym.c deleted file mode 100644 index b09ee12a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx1-camera-fiq-ksym.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Exported ksyms of ARCH_MX1 - * - * Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/module.h> - -#include <mach/mx1_camera.h> - -/* IMX camera FIQ handler */ -EXPORT_SYMBOL(mx1_camera_sof_fiq_start); -EXPORT_SYMBOL(mx1_camera_sof_fiq_end); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx1-camera-fiq.S b/ANDROID_3.4.5/arch/arm/mach-imx/mx1-camera-fiq.S deleted file mode 100644 index 9c69aa65..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx1-camera-fiq.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * Based on linux/arch/arm/lib/floppydma.S - * Copyright (C) 1995, 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> - - .text - .global mx1_camera_sof_fiq_end - .global mx1_camera_sof_fiq_start -mx1_camera_sof_fiq_start: - @ enable dma - ldr r12, [r9] - orr r12, r12, #0x00000001 - str r12, [r9] - @ unmask DMA interrupt - ldr r12, [r8] - bic r12, r12, r13 - str r12, [r8] - @ disable SOF interrupt - ldr r12, [r10] - bic r12, r12, #0x00010000 - str r12, [r10] - @ clear SOF flag - mov r12, #0x00010000 - str r12, [r11] - @ return from FIQ - subs pc, lr, #4 -mx1_camera_sof_fiq_end: diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx31lilly-db.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx31lilly-db.c deleted file mode 100644 index 7d26f766..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx31lilly-db.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * LILLY-1131 development board support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx3.h> -#include <mach/board-mx31lilly.h> - -#include "devices-imx31.h" - -/* - * This file contains board-specific initialization routines for the - * LILLY-1131 development board. If you design an own baseboard for the - * module, use this file as base for support code. - */ - -static unsigned int lilly_db_board_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_CONTRAST__CONTRAST, -}; - -/* UART */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* MMC support */ - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); -} - -static int gpio_det, gpio_wp; - -#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); - - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); -} - -static const struct imxmmc_platform_data mmc_pdata __initconst = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* Framebuffer support */ -static const struct ipu_platform_data ipu_data __initconst = { - .irq_base = MXC_IPU_IRQ_START, -}; - -static const struct fb_videomode fb_modedb = { - /* 640x480 TFT panel (IPS-056T) */ - .name = "CRT-VGA", - .refresh = 64, - .xres = 640, - .yres = 480, - .pixclock = 30000, - .left_margin = 200, - .right_margin = 2, - .upper_margin = 2, - .lower_margin = 2, - .hsync_len = 3, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct mx3fb_platform_data fb_pdata __initdata = { - .name = "CRT-VGA", - .mode = &fb_modedb, - .num_modes = 1, -}; - -#define LCD_VCC_EN_GPIO (7) - -static void __init mx31lilly_init_fb(void) -{ - if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) { - printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n"); - return; - } - - imx31_add_ipu_core(&ipu_data); - imx31_add_mx3_sdc_fb(&fb_pdata); - gpio_direction_output(LCD_VCC_EN_GPIO, 1); -} - -void __init mx31lilly_db_init(void) -{ - mxc_iomux_setup_multiple_pins(lilly_db_board_pins, - ARRAY_SIZE(lilly_db_board_pins), - "development board pins"); - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); - imx31_add_imx_uart2(&uart_pdata); - imx31_add_mxc_mmc(0, &mmc_pdata); - mx31lilly_init_fb(); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx31lite-db.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx31lite-db.c deleted file mode 100644 index bf0fb879..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx31lite-db.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * LogicPD i.MX31 SOM-LV development board support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-mx3.h> -#include <mach/board-mx31lite.h> - -#include "devices-imx31.h" - -/* - * This file contains board-specific initialization routines for the - * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'. - * If you design an own baseboard for the module, use this file as base - * for support code. - */ - -static unsigned int litekit_db_board_pins[] __initdata = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* SPI 0 */ - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* SDHC1 */ - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, -}; - -/* UART */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* MMC */ - -static int gpio_det, gpio_wp; - -#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS) - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6)); -} - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); - - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); -} - -static const struct imxmmc_platform_data mmc_pdata __initconst = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* SPI */ - -static int spi_internal_chipselect[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(1), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi0_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -/* GPIO LEDs */ - -static const struct gpio_led litekit_leds[] __initconst = { - { - .name = "GPIO0", - .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE), - .active_low = 1, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, - { - .name = "GPIO1", - .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE), - .active_low = 1, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - } -}; - -static const struct gpio_led_platform_data - litekit_led_platform_data __initconst = { - .leds = litekit_leds, - .num_leds = ARRAY_SIZE(litekit_leds), -}; - -void __init mx31lite_db_init(void) -{ - mxc_iomux_setup_multiple_pins(litekit_db_board_pins, - ARRAY_SIZE(litekit_db_board_pins), - "development board pins"); - imx31_add_imx_uart0(&uart_pdata); - imx31_add_mxc_mmc(0, &mmc_pdata); - imx31_add_spi_imx0(&spi0_pdata); - gpio_led_register_device(-1, &litekit_led_platform_data); - imx31_add_imx2_wdt(NULL); - imx31_add_mxc_rtc(NULL); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-devboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-devboard.c deleted file mode 100644 index cc285e50..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-devboard.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> - -#include <mach/common.h> -#include <mach/iomux-mx3.h> -#include <mach/hardware.h> -#include <mach/ulpi.h> - -#include "devices-imx31.h" - -static unsigned int devboard_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* USB H1 */ - MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, - MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int devboard_sdhc2_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC2_WP); -} - -static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void devboard_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .get_ro = devboard_sdhc2_get_ro, - .init = devboard_sdhc2_init, - .exit = devboard_sdhc2_exit, -}; - -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void devboard_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int devboard_usbh1_hw_init(struct platform_device *pdev) -{ - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) -#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) - -static int devboard_isp1105_init(struct usb_phy *otg) -{ - int ret = gpio_request(USBH1_MODE, "usbh1-mode"); - if (ret) - return ret; - /* single ended */ - gpio_direction_output(USBH1_MODE, 0); - - ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); - if (ret) { - gpio_free(USBH1_MODE); - return ret; - } - gpio_direction_output(USBH1_VBUSEN_B, 1); - - return 0; -} - - -static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on) -{ - if (on) - gpio_set_value(USBH1_VBUSEN_B, 0); - else - gpio_set_value(USBH1_VBUSEN_B, 1); - - return 0; -} - -static struct mxc_usbh_platform_data usbh1_pdata __initdata = { - .init = devboard_usbh1_hw_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static int __init devboard_usbh1_init(void) -{ - struct usb_phy *phy; - struct platform_device *pdev; - - phy = kzalloc(sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); - if (!phy->otg) { - kfree(phy); - return -ENOMEM; - } - - phy->label = "ISP1105"; - phy->init = devboard_isp1105_init; - phy->otg->set_vbus = devboard_isp1105_set_vbus; - - usbh1_pdata.otg = phy; - - pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_devboard_init(void) -{ - printk(KERN_INFO "Initializing mx31devboard peripherals\n"); - - mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), - "devboard"); - - imx31_add_imx_uart1(&uart_pdata); - - imx31_add_mxc_mmc(1, &sdhc2_pdata); - - devboard_init_sel_gpios(); - - imx31_add_fsl_usb2_udc(&usb_pdata); - - devboard_usbh1_init(); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-marxbot.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-marxbot.c deleted file mode 100644 index 135c90e3..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-marxbot.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/spi/spi.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx3.h> -#include <mach/ulpi.h> - -#include <media/soc_camera.h> - -#include "devices-imx31.h" - -static unsigned int marxbot_pins[] = { - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* CSI */ - MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5, - MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, - MX31_PIN_TXD2__GPIO1_28, - /* dsPIC resets */ - MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, - /*battery detection */ - MX31_PIN_LCS0__GPIO3_23, - /* USB H1 */ - MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, - MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int marxbot_sdhc2_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC2_WP); -} - -static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void marxbot_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .get_ro = marxbot_sdhc2_get_ro, - .init = marxbot_sdhc2_init, - .exit = marxbot_sdhc2_exit, -}; - -#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5) -#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5) - -static void dspics_resets_init(void) -{ - if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 0); - gpio_export(TRSLAT_RST_B, false); - } - - if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { - gpio_direction_output(DSPICS_RST_B, 0); - gpio_export(DSPICS_RST_B, false); - } -} - -static struct spi_board_info marxbot_spi_board_info[] __initdata = { - { - .modalias = "spidev", - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 1, /* according spi1_cs[] ! */ - }, -}; - -#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5) -#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) -#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4) -#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2) - -static int marxbot_basecam_power(struct device *dev, int on) -{ - gpio_set_value(BASECAM_POWER, !on); - return 0; -} - -static int marxbot_basecam_reset(struct device *dev) -{ - gpio_set_value(BASECAM_RST_B, 0); - udelay(100); - gpio_set_value(BASECAM_RST_B, 1); - return 0; -} - -static struct i2c_board_info marxbot_i2c_devices[] = { - { - I2C_BOARD_INFO("mt9t031", 0x5d), - }, -}; - -static struct soc_camera_link base_iclink = { - .bus_id = 0, /* Must match with the camera ID */ - .power = marxbot_basecam_power, - .reset = marxbot_basecam_reset, - .board_info = &marxbot_i2c_devices[0], - .i2c_adapter_id = 0, -}; - -static struct platform_device marxbot_camera[] = { - { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &base_iclink, - }, - }, -}; - -static struct platform_device *marxbot_cameras[] __initdata = { - &marxbot_camera[0], -}; - -static int __init marxbot_cam_init(void) -{ - int ret = gpio_request(CAM_CHOICE, "cam-choice"); - if (ret) - return ret; - gpio_direction_output(CAM_CHOICE, 0); - - ret = gpio_request(BASECAM_RST_B, "basecam-reset"); - if (ret) - return ret; - gpio_direction_output(BASECAM_RST_B, 1); - ret = gpio_request(BASECAM_POWER, "basecam-standby"); - if (ret) - return ret; - gpio_direction_output(BASECAM_POWER, 0); - - ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset"); - if (ret) - return ret; - gpio_direction_output(TURRETCAM_RST_B, 1); - ret = gpio_request(TURRETCAM_POWER, "turretcam-standby"); - if (ret) - return ret; - gpio_direction_output(TURRETCAM_POWER, 0); - - return 0; -} - -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void marxbot_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int marxbot_usbh1_hw_init(struct platform_device *pdev) -{ - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) -#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) - -static int marxbot_isp1105_init(struct usb_phy *otg) -{ - int ret = gpio_request(USBH1_MODE, "usbh1-mode"); - if (ret) - return ret; - /* single ended */ - gpio_direction_output(USBH1_MODE, 0); - - ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); - if (ret) { - gpio_free(USBH1_MODE); - return ret; - } - gpio_direction_output(USBH1_VBUSEN_B, 1); - - return 0; -} - - -static int marxbot_isp1105_set_vbus(struct usb_otg *otg, bool on) -{ - if (on) - gpio_set_value(USBH1_VBUSEN_B, 0); - else - gpio_set_value(USBH1_VBUSEN_B, 1); - - return 0; -} - -static struct mxc_usbh_platform_data usbh1_pdata __initdata = { - .init = marxbot_usbh1_hw_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static int __init marxbot_usbh1_init(void) -{ - struct usb_phy *phy; - struct platform_device *pdev; - - phy = kzalloc(sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); - if (!phy->otg) { - kfree(phy); - return -ENOMEM; - } - - phy->label = "ISP1105"; - phy->init = marxbot_isp1105_init; - phy->otg->set_vbus = marxbot_isp1105_set_vbus; - - usbh1_pdata.otg = phy; - - pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_marxbot_init(void) -{ - printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), - "marxbot"); - - marxbot_init_sel_gpios(); - - dspics_resets_init(); - - imx31_add_mxc_mmc(1, &sdhc2_pdata); - - spi_register_board_info(marxbot_spi_board_info, - ARRAY_SIZE(marxbot_spi_board_info)); - - marxbot_cam_init(); - platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras)); - - /* battery present pin */ - gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); - gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); - - imx31_add_fsl_usb2_udc(&usb_pdata); - - marxbot_usbh1_init(); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-smartbot.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-smartbot.c deleted file mode 100644 index fabb801e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx31moboard-smartbot.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx3.h> -#include <mach/board-mx31moboard.h> -#include <mach/ulpi.h> - -#include <media/soc_camera.h> - -#include "devices-imx31.h" - -static unsigned int smartbot_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* CSI */ - MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, - MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, - /* ENABLES */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) - -static int smartbot_cam_power(struct device *dev, int on) -{ - gpio_set_value(CAM_POWER, !on); - return 0; -} - -static int smartbot_cam_reset(struct device *dev) -{ - gpio_set_value(CAM_RST_B, 0); - udelay(100); - gpio_set_value(CAM_RST_B, 1); - return 0; -} - -static struct i2c_board_info smartbot_i2c_devices[] = { - { - I2C_BOARD_INFO("mt9t031", 0x5d), - }, -}; - -static struct soc_camera_link base_iclink = { - .bus_id = 0, /* Must match with the camera ID */ - .power = smartbot_cam_power, - .reset = smartbot_cam_reset, - .board_info = &smartbot_i2c_devices[0], - .i2c_adapter_id = 0, -}; - -static struct platform_device smartbot_camera[] = { - { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &base_iclink, - }, - }, -}; - -static struct platform_device *smartbot_cameras[] __initdata = { - &smartbot_camera[0], -}; - -static int __init smartbot_cam_init(void) -{ - int ret = gpio_request(CAM_RST_B, "cam-reset"); - if (ret) - return ret; - gpio_direction_output(CAM_RST_B, 1); - ret = gpio_request(CAM_POWER, "cam-standby"); - if (ret) - return ret; - gpio_direction_output(CAM_POWER, 0); - - return 0; -} - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -#if defined(CONFIG_USB_ULPI) - -static int smartbot_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data otg_host_pdata __initdata = { - .init = smartbot_otg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static int __init smartbot_otg_host_init(void) -{ - struct platform_device *pdev; - - otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (!otg_host_pdata.otg) - return -ENODEV; - - pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} -#else -static inline int smartbot_otg_host_init(void) { return 0; } -#endif - -#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void smartbot_resets_init(void) -{ - if (!gpio_request(POWER_EN, "power-enable")) { - gpio_direction_output(POWER_EN, 0); - gpio_export(POWER_EN, false); - } - - if (!gpio_request(DSPIC_RST_B, "dspic-rst")) { - gpio_direction_output(DSPIC_RST_B, 0); - gpio_export(DSPIC_RST_B, false); - } - - if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 0); - gpio_export(TRSLAT_RST_B, false); - } - - if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) { - gpio_direction_output(TRSLAT_SRC_CHOICE, 0); - gpio_export(TRSLAT_SRC_CHOICE, false); - } -} -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_smartbot_init(int board) -{ - printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), - "smartbot"); - - imx31_add_imx_uart1(&uart_pdata); - - switch (board) { - case MX31SMARTBOT: - imx31_add_fsl_usb2_udc(&usb_pdata); - break; - case MX31EYEBOT: - smartbot_otg_host_init(); - break; - default: - printk(KERN_WARNING "Unknown board %d, USB OTG not initialized", - board); - } - - smartbot_resets_init(); - - smartbot_cam_init(); - platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras)); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/mx51_efika.c b/ANDROID_3.4.5/arch/arm/mach-imx/mx51_efika.c deleted file mode 100644 index ec6ca91b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/mx51_efika.c +++ /dev/null @@ -1,632 +0,0 @@ -/* - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/consumer.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <mach/ulpi.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "efika.h" -#include "cpu_op-mx51.h" - -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 - -#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) -#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27) - -#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) -#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) - -#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) - -static iomux_v3_cfg_t mx51efika_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - - /* SD/MMC WP/CD */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - MX51_PAD_GPIO1_7__SD2_WP, - MX51_PAD_GPIO1_8__SD2_CD, - - /* spi */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - MX51_PAD_CSPI1_RDY__ECSPI1_RDY, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_GPIO1_6__GPIO1_6, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - /* USB HUB RESET */ - MX51_PAD_GPIO1_5__GPIO1_5, - - /* WLAN */ - MX51_PAD_EIM_A22__GPIO2_16, - MX51_PAD_EIM_A16__GPIO2_10, - - /* USB PHY RESET */ - MX51_PAD_EIM_D27__GPIO2_9, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* This function is board specific as the bit mask for the plldiv will also - * be different for other Freescale SoCs, thus a common bitmask is not - * possible and cannot get place in /plat-mxc/ehci.c. - */ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; - u32 v; - void __iomem *usb_base; - void __iomem *socregs_base; - - mxc_iomux_v3_setup_pad(usbh1gpio); - gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); - gpio_direction_output(EFIKAMX_USBH1_STP, 0); - msleep(1); - gpio_set_value(EFIKAMX_USBH1_STP, 1); - msleep(1); - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* The clock for the USBH1 ULPI port will come externally */ - /* from the PHY. */ - v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, - socregs_base + MX51_USB_CTRL_1_OFFSET); - - iounmap(usb_base); - - gpio_free(EFIKAMX_USBH1_STP); - mxc_iomux_v3_setup_pad(usbh1stp); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); -} - -static struct mxc_usbh_platform_data usbh1_config __initdata = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void mx51_efika_hubreset(void) -{ - gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst"); - gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); - msleep(1); - gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); - msleep(1); - gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); -} - -static void __init mx51_efika_usb(void) -{ - mx51_efika_hubreset(); - - /* pulling it low, means no USB at all... */ - gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset"); - gpio_direction_output(EFIKA_USB_PHY_RESET, 0); - msleep(1); - gpio_set_value(EFIKA_USB_PHY_RESET, 1); - - usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - - imx51_add_mxc_ehci_otg(&dr_utmi_config); - if (usbh1_config.otg) - imx51_add_mxc_ehci_hs(1, &usbh1_config); -} - -static struct mtd_partition mx51_efika_spi_nor_partitions[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_256K, - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - }, -}; - -static struct flash_platform_data mx51_efika_spi_flash_data = { - .name = "spi_flash", - .parts = mx51_efika_spi_nor_partitions, - .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions), - .type = "sst25vf032b", -}; - -static struct regulator_consumer_supply sw1_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_consumer_supply vdig_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDA", "1-000a"), - REGULATOR_SUPPLY("VDDD", "1-000a"), -}; - -static struct regulator_consumer_supply vvideo_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDIO", "1-000a"), -}; - -static struct regulator_consumer_supply vsd_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"), - REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"), -}; - -static struct regulator_consumer_supply pwgt1_consumer[] = { - { - .supply = "pwgt1", - } -}; - -static struct regulator_consumer_supply pwgt2_consumer[] = { - { - .supply = "pwgt2", - } -}; - -static struct regulator_consumer_supply coincell_consumer[] = { - { - .supply = "coincell", - } -}; - -static struct regulator_init_data sw1_init = { - .constraints = { - .name = "SW1", - .min_uV = 600000, - .max_uV = 1375000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .valid_modes_mask = 0, - .always_on = 1, - .boot_on = 1, - .state_mem = { - .uV = 850000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), - .consumer_supplies = sw1_consumers, -}; - -static struct regulator_init_data sw2_init = { - .constraints = { - .name = "SW2", - .min_uV = 900000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - .state_mem = { - .uV = 950000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - } -}; - -static struct regulator_init_data sw3_init = { - .constraints = { - .name = "SW3", - .min_uV = 1100000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw4_init = { - .constraints = { - .name = "SW4", - .min_uV = 1100000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data viohi_init = { - .constraints = { - .name = "VIOHI", - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vusb_init = { - .constraints = { - .name = "VUSB", - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data swbst_init = { - .constraints = { - .name = "SWBST", - } -}; - -static struct regulator_init_data vdig_init = { - .constraints = { - .name = "VDIG", - .min_uV = 1050000, - .max_uV = 1800000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), - .consumer_supplies = vdig_consumers, -}; - -static struct regulator_init_data vpll_init = { - .constraints = { - .name = "VPLL", - .min_uV = 1050000, - .max_uV = 1800000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vusb2_init = { - .constraints = { - .name = "VUSB2", - .min_uV = 2400000, - .max_uV = 2775000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vvideo_init = { - .constraints = { - .name = "VVIDEO", - .min_uV = 2775000, - .max_uV = 2775000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), - .consumer_supplies = vvideo_consumers, -}; - -static struct regulator_init_data vaudio_init = { - .constraints = { - .name = "VAUDIO", - .min_uV = 2300000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - } -}; - -static struct regulator_init_data vsd_init = { - .constraints = { - .name = "VSD", - .min_uV = 1800000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), - .consumer_supplies = vsd_consumers, -}; - -static struct regulator_init_data vcam_init = { - .constraints = { - .name = "VCAM", - .min_uV = 2500000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, - .boot_on = 1, - } -}; - -static struct regulator_init_data vgen1_init = { - .constraints = { - .name = "VGEN1", - .min_uV = 1200000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vgen2_init = { - .constraints = { - .name = "VGEN2", - .min_uV = 1200000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vgen3_init = { - .constraints = { - .name = "VGEN3", - .min_uV = 1800000, - .max_uV = 2900000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data gpo1_init = { - .constraints = { - .name = "GPO1", - } -}; - -static struct regulator_init_data gpo2_init = { - .constraints = { - .name = "GPO2", - } -}; - -static struct regulator_init_data gpo3_init = { - .constraints = { - .name = "GPO3", - } -}; - -static struct regulator_init_data gpo4_init = { - .constraints = { - .name = "GPO4", - } -}; - -static struct regulator_init_data pwgt1_init = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer), - .consumer_supplies = pwgt1_consumer, -}; - -static struct regulator_init_data pwgt2_init = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer), - .consumer_supplies = pwgt2_consumer, -}; - -static struct regulator_init_data vcoincell_init = { - .constraints = { - .name = "COINCELL", - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(coincell_consumer), - .consumer_supplies = coincell_consumer, -}; - -static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { - { .id = MC13892_SW1, .init_data = &sw1_init }, - { .id = MC13892_SW2, .init_data = &sw2_init }, - { .id = MC13892_SW3, .init_data = &sw3_init }, - { .id = MC13892_SW4, .init_data = &sw4_init }, - { .id = MC13892_SWBST, .init_data = &swbst_init }, - { .id = MC13892_VIOHI, .init_data = &viohi_init }, - { .id = MC13892_VPLL, .init_data = &vpll_init }, - { .id = MC13892_VDIG, .init_data = &vdig_init }, - { .id = MC13892_VSD, .init_data = &vsd_init }, - { .id = MC13892_VUSB2, .init_data = &vusb2_init }, - { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, - { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, - { .id = MC13892_VCAM, .init_data = &vcam_init }, - { .id = MC13892_VGEN1, .init_data = &vgen1_init }, - { .id = MC13892_VGEN2, .init_data = &vgen2_init }, - { .id = MC13892_VGEN3, .init_data = &vgen3_init }, - { .id = MC13892_VUSB, .init_data = &vusb_init }, - { .id = MC13892_GPO1, .init_data = &gpo1_init }, - { .id = MC13892_GPO2, .init_data = &gpo2_init }, - { .id = MC13892_GPO3, .init_data = &gpo3_init }, - { .id = MC13892_GPO4, .init_data = &gpo4_init }, - { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, - { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, - { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, -}; - -static struct mc13xxx_platform_data mx51_efika_mc13892_data = { - .flags = MC13XXX_USE_RTC, - .regulators = { - .num_regulators = ARRAY_SIZE(mx51_efika_regulators), - .regulators = mx51_efika_regulators, - }, -}; - -static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &mx51_efika_spi_flash_data, - .irq = -1, - }, - { - .modalias = "mc13892", - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &mx51_efika_mc13892_data, - .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC), - }, -}; - -static int mx51_efika_spi_cs[] = { - EFIKAMX_SPI_CS0, - EFIKAMX_SPI_CS1, -}; - -static const struct spi_imx_master mx51_efika_spi_pdata __initconst = { - .chipselect = mx51_efika_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs), -}; - -void __init efika_board_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, - ARRAY_SIZE(mx51efika_pads)); - imx51_add_imx_uart(0, &uart_pdata); - mx51_efika_usb(); - - /* FIXME: comes from original code. check this. */ - if (mx51_revision() < IMX_CHIP_REVISION_2_0) - sw2_init.constraints.state_mem.uV = 1100000; - else if (mx51_revision() == IMX_CHIP_REVISION_2_0) { - sw2_init.constraints.state_mem.uV = 1250000; - sw1_init.constraints.state_mem.uV = 1000000; - } - if (machine_is_mx51_efikasb()) - vgen1_init.constraints.max_uV = 1200000; - - gpio_request(EFIKAMX_PMIC, "pmic irq"); - gpio_direction_input(EFIKAMX_PMIC); - spi_register_board_info(mx51_efika_spi_board_info, - ARRAY_SIZE(mx51_efika_spi_board_info)); - imx51_add_ecspi(0, &mx51_efika_spi_pdata); - - imx51_add_pata_imx(); - -#if defined(CONFIG_CPU_FREQ_IMX) - get_cpu_op = mx51_get_cpu_op; -#endif -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/pcm037.h b/ANDROID_3.4.5/arch/arm/mach-imx/pcm037.h deleted file mode 100644 index d6929721..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/pcm037.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __PCM037_H__ -#define __PCM037_H__ - -enum pcm037_board_variant { - PCM037_PCM970, - PCM037_EET, -}; - -extern enum pcm037_board_variant pcm037_variant(void); - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/pcm970-baseboard.c b/ANDROID_3.4.5/arch/arm/mach-imx/pcm970-baseboard.c deleted file mode 100644 index 99afbc3f..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/pcm970-baseboard.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/can/platform/sja1000.h> - -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/iomux-mx27.h> -#include <mach/hardware.h> - -#include "devices-imx27.h" - -static const int pcm970_pins[] __initconst = { - /* SDHC */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* - * it seems the data line misses a pullup, so we must enable - * the internal pullup as a local workaround - */ - PD17_PF_I2C_DATA | GPIO_PUEN, - PD18_PF_I2C_CLK, - /* Camera */ - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, -}; - -static int pcm970_sdhc2_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_PORTC + 28); -} - -static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) -{ - int ret; - - ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING, - "imx-mmc-detect", data); - if (ret) - return ret; - - ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); - if (ret) { - free_irq(IRQ_GPIOC(29), data); - return ret; - } - - gpio_direction_input(GPIO_PORTC + 28); - - return 0; -} - -static void pcm970_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(IRQ_GPIOC(29), data); - gpio_free(GPIO_PORTC + 28); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .get_ro = pcm970_sdhc2_get_ro, - .init = pcm970_sdhc2_init, - .exit = pcm970_sdhc2_exit, -}; - -static struct imx_fb_videomode pcm970_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 7, - .left_margin = 5, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - }, - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock not inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pcr = 0xF00080C0, - .bpp = 16, - }, { - .mode = { - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - }, - /* - * - HSYNC active low (1 << 22) - * - VSYNC active low (1 << 23) - * - clk notenabled while idle - * - clock not inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19), - .bpp = 32, - }, -}; - -static const struct imx_fb_platform_data pcm038_fb_data __initconst = { - .mode = pcm970_modes, - .num_modes = ARRAY_SIZE(pcm970_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static struct resource pcm970_sja1000_resources[] = { - { - .start = MX27_CS4_BASE_ADDR, - .end = MX27_CS4_BASE_ADDR + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_GPIOE(19), - .end = IRQ_GPIOE(19), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct sja1000_platform_data pcm970_sja1000_platform_data = { - .osc_freq = 16000000, - .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, - .cdr = CDR_CBP, -}; - -static struct platform_device pcm970_sja1000 = { - .name = "sja1000_platform", - .dev = { - .platform_data = &pcm970_sja1000_platform_data, - }, - .resource = pcm970_sja1000_resources, - .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), -}; - -/* - * system init for baseboard usage. Will be called by pcm038 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init pcm970_baseboard_init(void) -{ - mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), - "PCM970"); - - imx27_add_imx_fb(&pcm038_fb_data); - mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); - imx27_add_mxc_mmc(1, &sdhc_pdata); - platform_device_register(&pcm970_sja1000); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/platsmp.c b/ANDROID_3.4.5/arch/arm/mach-imx/platsmp.c deleted file mode 100644 index ab98c6fe..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/platsmp.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/smp.h> -#include <asm/page.h> -#include <asm/smp_scu.h> -#include <asm/hardware/gic.h> -#include <asm/mach/map.h> -#include <mach/common.h> -#include <mach/hardware.h> - -static void __iomem *scu_base; - -static struct map_desc scu_io_desc __initdata = { - /* .virtual and .pfn are run-time assigned */ - .length = SZ_4K, - .type = MT_DEVICE, -}; - -void __init imx_scu_map_io(void) -{ - unsigned long base; - - /* Get SCU base */ - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); - - scu_io_desc.virtual = IMX_IO_P2V(base); - scu_io_desc.pfn = __phys_to_pfn(base); - iotable_init(&scu_io_desc, 1); - - scu_base = IMX_IO_ADDRESS(base); -} - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - imx_set_cpu_jump(cpu, v7_secondary_startup); - imx_enable_cpu(cpu, true); - return 0; -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -void __init smp_init_cpus(void) -{ - int i, ncores; - - ncores = scu_get_core_count(scu_base); - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); -} - -void imx_smp_prepare(void) -{ - scu_enable(scu_base); -} - -void __init platform_smp_prepare_cpus(unsigned int max_cpus) -{ - imx_smp_prepare(); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx27.c b/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx27.c deleted file mode 100644 index 6fcffa7d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx27.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * i.MX27 Power Management Routines - * - * Based on Freescale's BSP - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License. - */ - -#include <linux/kernel.h> -#include <linux/suspend.h> -#include <linux/io.h> -#include <mach/hardware.h> - -static int mx27_suspend_enter(suspend_state_t state) -{ - u32 cscr; - switch (state) { - case PM_SUSPEND_MEM: - /* Clear MPEN and SPEN to disable MPLL/SPLL */ - cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); - cscr &= 0xFFFFFFFC; - __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); - /* Executes WFI */ - cpu_do_idle(); - break; - - default: - return -EINVAL; - } - return 0; -} - -static const struct platform_suspend_ops mx27_suspend_ops = { - .enter = mx27_suspend_enter, - .valid = suspend_valid_only_mem, -}; - -static int __init mx27_pm_init(void) -{ - if (!cpu_is_mx27()) - return 0; - - suspend_set_ops(&mx27_suspend_ops); - return 0; -} - -device_initcall(mx27_pm_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx3.c b/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx3.c deleted file mode 100644 index b3752439..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx3.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/io.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/devices-common.h> -#include "crmregs-imx3.h" - -/* - * Set cpu low power mode before WFI instruction. This function is called - * mx3 because it can be used for mx31 and mx35. - * Currently only WAIT_MODE is supported. - */ -void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode) -{ - int reg = __raw_readl(MXC_CCM_CCMR); - reg &= ~MXC_CCM_CCMR_LPM_MASK; - - switch (mode) { - case MX3_WAIT: - if (cpu_is_mx35()) - reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; - __raw_writel(reg, MXC_CCM_CCMR); - break; - default: - pr_err("Unknown cpu power mode: %d\n", mode); - return; - } -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx5.c b/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx5.c deleted file mode 100644 index e26a9cb0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx5.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/suspend.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/err.h> -#include <asm/cacheflush.h> -#include <asm/tlbflush.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include "crm-regs-imx5.h" - -static struct clk *gpc_dvfs_clk; - -/* - * set cpu low power mode before WFI instruction. This function is called - * mx5 because it can be used for mx50, mx51, and mx53. - */ -void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) -{ - u32 plat_lpc, arm_srpgcr, ccm_clpcr; - u32 empgc0, empgc1; - int stop_mode = 0; - - /* always allow platform to issue a deep sleep mode request */ - plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & - ~(MXC_CORTEXA8_PLAT_LPC_DSM); - ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); - arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); - - switch (mode) { - case WAIT_CLOCKED: - break; - case WAIT_UNCLOCKED: - ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; - break; - case WAIT_UNCLOCKED_POWER_OFF: - case STOP_POWER_OFF: - plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM - | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; - if (mode == WAIT_UNCLOCKED_POWER_OFF) { - ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; - ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; - ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; - stop_mode = 0; - } else { - ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; - ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; - ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; - ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; - stop_mode = 1; - } - arm_srpgcr |= MXC_SRPGCR_PCR; - break; - case STOP_POWER_ON: - ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; - break; - default: - printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); - return; - } - - __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); - __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); - __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); - - /* Enable NEON SRPG for all but MX50TO1.0. */ - if (mx50_revision() != IMX_CHIP_REVISION_1_0) - __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); - - if (stop_mode) { - empgc0 |= MXC_SRPGCR_PCR; - empgc1 |= MXC_SRPGCR_PCR; - - __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); - } -} - -static int mx5_suspend_prepare(void) -{ - return clk_prepare_enable(gpc_dvfs_clk); -} - -static int mx5_suspend_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - mx5_cpu_lp_set(STOP_POWER_OFF); - break; - case PM_SUSPEND_STANDBY: - mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - break; - default: - return -EINVAL; - } - - if (state == PM_SUSPEND_MEM) { - local_flush_tlb_all(); - flush_cache_all(); - - /*clear the EMPGC0/1 bits */ - __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); - } - cpu_do_idle(); - return 0; -} - -static void mx5_suspend_finish(void) -{ - clk_disable_unprepare(gpc_dvfs_clk); -} - -static int mx5_pm_valid(suspend_state_t state) -{ - return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); -} - -static const struct platform_suspend_ops mx5_suspend_ops = { - .valid = mx5_pm_valid, - .prepare = mx5_suspend_prepare, - .enter = mx5_suspend_enter, - .finish = mx5_suspend_finish, -}; - -static int __init mx5_pm_init(void) -{ - if (!cpu_is_mx51() && !cpu_is_mx53()) - return 0; - - if (gpc_dvfs_clk == NULL) - gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); - - if (!IS_ERR(gpc_dvfs_clk)) { - if (cpu_is_mx51()) - suspend_set_ops(&mx5_suspend_ops); - } else - return -EPERM; - - return 0; -} -device_initcall(mx5_pm_init); diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx6q.c b/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx6q.c deleted file mode 100644 index f7b0c2b1..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/pm-imx6q.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/suspend.h> -#include <asm/cacheflush.h> -#include <asm/proc-fns.h> -#include <asm/suspend.h> -#include <asm/hardware/cache-l2x0.h> -#include <mach/common.h> -#include <mach/hardware.h> - -extern unsigned long phys_l2x0_saved_regs; - -static int imx6q_suspend_finish(unsigned long val) -{ - cpu_do_idle(); - return 0; -} - -static int imx6q_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - imx6q_set_lpm(STOP_POWER_OFF); - imx_gpc_pre_suspend(); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Zzz ... */ - cpu_suspend(0, imx6q_suspend_finish); - imx_smp_prepare(); - imx_gpc_post_resume(); - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct platform_suspend_ops imx6q_pm_ops = { - .enter = imx6q_pm_enter, - .valid = suspend_valid_only_mem, -}; - -void __init imx6q_pm_init(void) -{ - /* - * The l2x0 core code provides an infrastucture to save and restore - * l2x0 registers across suspend/resume cycle. But because imx6q - * retains L2 content during suspend and needs to resume L2 before - * MMU is enabled, it can only utilize register saving support and - * have to take care of restoring on its own. So we save physical - * address of the data structure used by l2x0 core to save registers, - * and later restore the necessary ones in imx6q resume entry. - */ -#ifdef CONFIG_CACHE_L2X0 - phys_l2x0_saved_regs = __pa(&l2x0_saved_regs); -#endif - - suspend_set_ops(&imx6q_pm_ops); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-imx/src.c b/ANDROID_3.4.5/arch/arm/mach-imx/src.c deleted file mode 100644 index e15f1555..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-imx/src.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/smp.h> -#include <asm/smp_plat.h> - -#define SRC_SCR 0x000 -#define SRC_GPR1 0x020 -#define BP_SRC_SCR_WARM_RESET_ENABLE 0 -#define BP_SRC_SCR_CORE1_RST 14 -#define BP_SRC_SCR_CORE1_ENABLE 22 - -static void __iomem *src_base; - -void imx_enable_cpu(int cpu, bool enable) -{ - u32 mask, val; - - cpu = cpu_logical_map(cpu); - mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); - val = readl_relaxed(src_base + SRC_SCR); - val = enable ? val | mask : val & ~mask; - writel_relaxed(val, src_base + SRC_SCR); -} - -void imx_set_cpu_jump(int cpu, void *jump_addr) -{ - cpu = cpu_logical_map(cpu); - writel_relaxed(virt_to_phys(jump_addr), - src_base + SRC_GPR1 + cpu * 8); -} - -void imx_src_prepare_restart(void) -{ - u32 val; - - /* clear enable bits of secondary cores */ - val = readl_relaxed(src_base + SRC_SCR); - val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); - writel_relaxed(val, src_base + SRC_SCR); - - /* clear persistent entry register of primary core */ - writel_relaxed(0, src_base + SRC_GPR1); -} - -void __init imx_src_init(void) -{ - struct device_node *np; - u32 val; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); - src_base = of_iomap(np, 0); - WARN_ON(!src_base); - - /* - * force warm reset sources to generate cold reset - * for a more reliable restart - */ - val = readl_relaxed(src_base + SRC_SCR); - val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); - writel_relaxed(val, src_base + SRC_SCR); -} |