dirty fix to merging

7 files changed, 1496 insertions, 0 deletions

diff --git a/drivers/video/wmt/hw/wmt-cec-reg.h b/drivers/video/wmt/hw/wmt-cec-reg.h
new file mode 100644
index 00000000..e93939fd
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-cec-reg.h
@@ -0,0 +1,169 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-cec-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_CEC_REG_H
+#define WMT_CEC_REG_H
+
+#define WMT_FTBLK_CEC
+
+#define CEC_BASE_ADDR			(LVDS_BASE_ADDR + 0x100)
+#define CEC_BASE2_ADDR			(LVDS_BASE_ADDR + 0x200)
+
+#define REG_CEC_BEGIN			(CEC_BASE_ADDR + 0x0)
+#define REG_CEC_ENABLE			(CEC_BASE_ADDR + 0x0)
+#define REG_CEC_ENCODE_NUMBER		(CEC_BASE_ADDR + 0x4)
+#define REG_CEC_ENCODE_HEADER		(CEC_BASE_ADDR + 0x8)
+#define REG_CEC_ENCODE_DATA		(CEC_BASE_ADDR + 0xC) /* Data1(0x0C) - Data15(0x44) */
+#define REG_CEC_DECODE_RESET		(CEC_BASE_ADDR + 0x48)
+#define REG_CEC_DECODE_START		(CEC_BASE_ADDR + 0x4C)
+#define REG_CEC_DECODE_HEADER		(CEC_BASE_ADDR + 0x50)
+#define REG_CEC_DECODE_DATA		(CEC_BASE_ADDR + 0x54) /* Data1(0x54) - Data15(0x8C) */
+#define REG_CEC_WR_START_SET0		(CEC_BASE_ADDR + 0x90) /* val * CEC_CLK = 3.7 ms */
+#define REG_CEC_WR_START_SET1		(CEC_BASE_ADDR + 0x94) /* val * CEC_CLK = 4.5 ms */
+#define REG_CEC_WR_LOGIC0_SET0		(CEC_BASE_ADDR + 0x98) /* val * CEC_CLK = 0.6 ms */
+#define REG_CEC_WR_LOGIC0_SET1		(CEC_BASE_ADDR + 0x9C) /* val * CEC_CLK = 2.4 ms */
+#define REG_CEC_WR_LOGIC1_SET0		(CEC_BASE_ADDR + 0xA0) /* val * CEC_CLK = 1.5 ms */
+#define REG_CEC_WR_LOGIC1_SET1		(CEC_BASE_ADDR + 0xA4) /* val * CEC_CLK = 2.4 ms */
+#define REG_CEC_RD_START_L_SET0		(CEC_BASE_ADDR + 0xA8) /* val * CEC_CLK = 3.5 ms */
+#define REG_CEC_RD_START_R_SET0		(CEC_BASE_ADDR + 0xAC) /* val * CEC_CLK = 3.9 ms */
+#define REG_CEC_RD_START_L_SET1		(CEC_BASE_ADDR + 0xB0) /* val * CEC_CLK = 4.3 ms */
+#define REG_CEC_RD_START_R_SET1		(CEC_BASE_ADDR + 0xB4) /* val * CEC_CLK = 4.7 ms */
+#define REG_CEC_RD_LOGIC0_L_SET0	(CEC_BASE_ADDR + 0xB8) /* val * CEC_CLK = 1.3 ms */
+#define REG_CEC_RD_LOGIC0_R_SET0	(CEC_BASE_ADDR + 0xBC) /* val * CEC_CLK = 1.7 ms */
+#define REG_CEC_RD_LOGIC0_L_SET1	(CEC_BASE_ADDR + 0xC0) /* val * CEC_CLK = 2.05 ms */
+#define REG_CEC_RD_LOGIC0_R_SET1	(CEC_BASE_ADDR + 0xC4) /* val * CEC_CLK = 2.75 ms */
+#define REG_CEC_RD_LOGIC1_L_SET0	(CEC_BASE_ADDR + 0xC8) /* val * CEC_CLK = 0.4 ms */
+#define REG_CEC_RD_LOGIC1_R_SET0	(CEC_BASE_ADDR + 0xCC) /* val * CEC_CLK = 0.8 ms */
+#define REG_CEC_RD_LOGIC1_L_SET1	(CEC_BASE_ADDR + 0xD0) /* val * CEC_CLK = 2.05 ms */
+#define REG_CEC_RD_LOGIC1_R_SET1	(CEC_BASE_ADDR + 0xD4) /* val * CEC_CLK = 2.75 ms */
+#define REG_CEC_PHYSICAL_ADDR		(CEC_BASE_ADDR + 0xD8)
+#define REG_CEC_LOGICAL_ADDR		(CEC_BASE_ADDR + 0xDC)
+#define REG_CEC_WR_RETRY		(CEC_BASE_ADDR + 0xE0)
+#define REG_CEC_FREE_3X			(CEC_BASE_ADDR + 0xE4)
+#define REG_CEC_WR_SET0_ERROR		(CEC_BASE_ADDR + 0xE8) /* val * CEC_CLK = 2.25 ms */
+#define REG_CEC_WR_SET1_ERROR		(CEC_BASE_ADDR + 0xEC)
+#define REG_CEC_REJECT			(CEC_BASE_ADDR + 0xF0)
+#define REG_CEC_RD_L_SET0_ERROR		(CEC_BASE_ADDR + 0xF4) /* val * CEC_CLK = 1.82 ms */
+#define REG_CEC_RD_R_SET1_ERROR		(CEC_BASE_ADDR + 0xF8) /* val * CEC_CLK = 2.38 ms */
+#define REG_CEC_RD_L_ERROR		(CEC_BASE_ADDR + 0xFC) /* val * CEC_CLK = 2.87 ms */
+
+#define REG_CEC_RX_TRIG_RANGE		(CEC_BASE2_ADDR + 0x00)
+#define REG_CEC_RX_SAMPLE_L_RANGE	(CEC_BASE2_ADDR + 0x04) /* val * CEC_CLK = 0.85 ms */
+#define REG_CEC_RX_SAMPLE_R_RANGE	(CEC_BASE2_ADDR + 0x08) /* val * CEC_CLK = 1.25 ms */
+#define REG_CEC_COMP_DISABLE		(CEC_BASE2_ADDR + 0x0C)
+#define REG_CEC_ERR_HANDLE_DISABLE  	(CEC_BASE2_ADDR + 0x10)
+#define REG_CEC_STATUS			(CEC_BASE2_ADDR + 0x14)
+#define REG_CEC_INT_ENABLE		(CEC_BASE2_ADDR + 0x18)
+#define REG_CEC_DECODE_FULL_DISABLE 	(CEC_BASE2_ADDR + 0x1C)
+#define REG_CEC_STATUS4_DISABLE		(CEC_BASE2_ADDR + 0x20)
+#define REG_CEC_RD_ENCODE_ENABLE	(CEC_BASE2_ADDR + 0x24)
+#define REG_CEC_DIS_ARB_CHECK		(CEC_BASE2_ADDR + 0x28)
+#define REG_CEC_END			(CEC_BASE2_ADDR + 0x28)
+
+/* REG_CEC_ENABLE,0x0 */
+#define CEC_WR_START			REG_CEC_ENABLE, BIT0, 0
+
+/* REG_CEC_ENCODE_NUMBER,0x4 */
+#define CEC_WR_NUM			REG_CEC_ENCODE_NUMBER, 0xFF, 0x0
+
+/* REG_CEC_ENCODE_HEADER,0x8 */
+#define CEC_WR_HEADER_ACK		REG_CEC_ENCODE_HEADER, BIT0, 0
+#define CEC_WR_HEADER_EOM		REG_CEC_ENCODE_HEADER, BIT1, 1
+#define CEC_WR_HEADER_DATA		REG_CEC_ENCODE_HEADER, 0xFF0, 4
+
+/* REG_CEC_ENCODE_DATA,Data1(0x0C) - Data15(0x44) */
+#define CEC_WR_DATA_ACK			REG_CEC_ENCODE_DATA, BIT0, 0
+#define CEC_WR_DATA_EOM			REG_CEC_ENCODE_DATA, BIT1, 1
+#define CEC_WR_DATA			REG_CEC_ENCODE_DATA, 0xFF0, 4
+
+/* REG_CEC_DECODE_RESET,0x48 */
+#define CEC_FINISH_RESET		REG_CEC_DECODE_RESET, BIT0, 0
+
+/* REG_CEC_DECODE_START,0x4C */
+#define CEC_RD_START			REG_CEC_DECODE_START, BIT0, 0
+#define CEC_RD_ALL_ACK			REG_CEC_DECODE_START, BIT1, 1
+#define CEC_RD_FINISH			REG_CEC_DECODE_START, BIT2, 2
+
+/* REG_CEC_DECODE_HEADER,0x50 */
+#define CEC_RD_HEADER_ACK		REG_CEC_DECODE_HEADER, BIT0, 0
+#define CEC_RD_HEADER_EOM		REG_CEC_DECODE_HEADER, BIT1, 1
+#define CEC_RD_HEADER_DATA		REG_CEC_DECODE_HEADER, 0xFF0, 4
+
+/* REG_CEC_DECODE_DATA,Data1(0x54) - Data15(0x8C) */
+#define CEC_RD_DATA_ACK			REG_CEC_DECODE_DATA, BIT0, 0
+#define CEC_RD_DATA_EOM			REG_CEC_DECODE_DATA, BIT1, 1
+#define CEC_RD_DATA			REG_CEC_DECODE_DATA, 0xFF0, 4
+
+/* REG_CEC_LOGICAL_ADDR,0xDC */
+#define CEC_LOGICAL_ADDR1		REG_CEC_LOGICAL_ADDR, 0xF, 0
+#define CEC_LOGICAL_ADDR2		REG_CEC_LOGICAL_ADDR, 0xF0, 4
+#define CEC_LOGICAL_ADDR3		REG_CEC_LOGICAL_ADDR, 0xF00, 8
+#define CEC_LOGICAL_ADDR4		REG_CEC_LOGICAL_ADDR, 0xF000, 12
+#define CEC_LOGICAL_ADDR5		REG_CEC_LOGICAL_ADDR, 0xF0000, 16
+#define CEC_ADDR_VALID1			REG_CEC_LOGICAL_ADDR, BIT24, 24
+#define CEC_ADDR_VALID2			REG_CEC_LOGICAL_ADDR, BIT25, 25
+#define CEC_ADDR_VALID3			REG_CEC_LOGICAL_ADDR, BIT26, 26
+#define CEC_ADDR_VALID4			REG_CEC_LOGICAL_ADDR, BIT27, 27
+#define CEC_ADDR_VALID5			REG_CEC_LOGICAL_ADDR, BIT28, 28
+
+/* REG_CEC_WR_RETRY,0xE0 */
+#define CEC_WR_RETRY			REG_CEC_WR_RETRY, 0xF, 0
+
+/* REG_CEC_FREE_3X,0xE4 */
+#define CEC_FREE_3X			REG_CEC_FREE_3X, 0xF, 0
+#define CEC_FREE_5X			REG_CEC_FREE_3X, 0xF00, 8
+#define CEC_FREE_7X			REG_CEC_FREE_3X, 0xF0000, 16
+
+/* REG_CEC_REJECT,0xF0 */
+#define CEC_REJECT_NEXT_DECODE		REG_CEC_REJECT, BIT0, 0 /*read enable*/
+
+/* REG_CEC_COMP_DISABLE,0x0C */
+#define CEC_COMP_DISABLE		REG_CEC_COMP_DISABLE, BIT0, 0
+
+/* REG_CEC_ERR_HANDLE_DISABLE,0x10 */
+#define CEC_ERR_HANDLE_DISABLE  	REG_CEC_ERR_HANDLE_DISABLE, BIT0, 0
+#define CEC_NO_ACK_DISABLE		REG_CEC_ERR_HANDLE_DISABLE, BIT1, 1
+
+/* REG_CEC_STATUS,0x14 */
+#define CEC_R1_ENCODE_OK		REG_CEC_STATUS, BIT0, 0 /* write finish */
+#define CEC_R1_DECODE_OK		REG_CEC_STATUS, BIT1, 1 /* read finish */
+#define CEC_R1_ERROR			REG_CEC_STATUS, BIT2, 2 /* read error */
+#define CEC_R1_ARB_FAIL			REG_CEC_STATUS, BIT3, 3 /* wr arb fail */
+#define CEC_R1_NO_ACK			REG_CEC_STATUS, BIT4, 4 /* wr no ack */
+
+/* REG_CEC_DECODE_FULL_DISABLE,0x1C */
+#define CEC_DECODE_FULL_DISABLE 	REG_CEC_DECODE_FULL_DISABLE, BIT0, 0
+
+/* REG_CEC_STATUS4_DISABLE,0x20 */
+#define CEC_STATUS4_START_DISABLE 	REG_CEC_STATUS4_DISABLE, BIT0, 0
+#define CEC_STATUS4_LOGIC0_DISABLE 	REG_CEC_STATUS4_DISABLE, BIT1, 1
+#define CEC_STATUS4_LOGIC1_DISABLE 	REG_CEC_STATUS4_DISABLE, BIT2, 2
+
+/* REG_CEC_RD_ENCODE_ENABLE,0x24 */
+#define CEC_RD_ENCODE_ENABLE	 	REG_CEC_RD_ENCODE_ENABLE, BIT0, 0 /* 1 : read self write and all dest data */
+
+/* REG_CEC_DIS_ARB_CHECK,0x28 */
+#define CEC_ARB_CHECK_DISABLE		REG_CEC_DIS_ARB_CHECK, BIT0, 0 /* 1 : disable arbitration check */
+
+#endif /* WMT_CEC_REG_H */
+
diff --git a/drivers/video/wmt/hw/wmt-govrh-reg.h b/drivers/video/wmt/hw/wmt-govrh-reg.h
new file mode 100644
index 00000000..4e2e2341
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-govrh-reg.h
@@ -0,0 +1,362 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-govrh-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_GOVRH_REG_H
+#define WMT_GOVRH_REG_H
+
+/* feature */
+#define WMT_FTBLK_GOVRH
+#ifndef CONFIG_UBOOT
+#define WMT_FTBLK_GOVRH_CURSOR
+#endif
+#define WMT_FTBLK_GOVRH2
+
+#define GOVRH_FRAMEBUF_ALIGN	128
+
+struct govrh_regs {
+	/* base1 */
+	unsigned int cur_addr; /* 0x00 */
+	unsigned int cur_width;
+	unsigned int cur_fb_width;
+	unsigned int cur_vcrop;
+	unsigned int cur_hcrop; /* 0x10 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int start : 11;
+			unsigned int reserved : 5;
+			unsigned int end : 11;
+		} b;
+	} cur_hcoord; /* 0x14 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int start : 11;
+			unsigned int reserved : 5;
+			unsigned int end : 11;
+		} b;
+	} cur_vcoord; /* 0x18 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable : 1;
+			unsigned int reserved : 7;
+			unsigned int out_field : 1;	/* 0:frame,1-field */
+		} b;
+	} cur_status; /* 0x1C */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int colkey : 24;
+			unsigned int enable : 1;
+			unsigned int invert : 1;
+			unsigned int reserved : 2;
+			unsigned int alpha : 1;
+		} b;
+	} cur_color_key; /* 0x20 */
+
+	unsigned int reserved[3];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int rgb : 1;
+			unsigned int yuv422 : 1;
+		} b;
+	} dvo_pix; /* 0x30 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int delay : 14;
+			unsigned int inv : 1;
+		} b;
+	} dvo_dly_sel; /* 0x34 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int cur_enable : 1;
+			unsigned int mem_enable : 1;
+			unsigned int reserved : 7;
+			unsigned int err_sts : 1;
+			unsigned int reserved2 : 6;
+			unsigned int cur_sts : 1;
+			unsigned int mem_sts : 1;
+		} b;
+	} interrupt; /* 0x38 */
+
+	unsigned int dvo_blank_data;
+	unsigned int dirpath; /* 0x40 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int v : 8;
+			unsigned int u : 8;
+			unsigned int y : 8;
+		} b;
+	} saturation; /* 0x44 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable : 1; 
+			unsigned int format : 1; /* 0:YCbCr, 1:RGB */
+		} b;
+	} saturation_enable; /* 0x48 */
+
+	unsigned int reserved2[13];
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable : 1;
+			unsigned int reserved : 7;
+			unsigned int h264 : 1;
+		} b;
+	} mif; /* 0x80 */
+
+	unsigned int colfmt; /* 0x84, 0:422,1:420 */
+	unsigned int srcfmt; /* 0x88, 0:frame,1:field */
+	unsigned int dstfmt; /* 0x8C, 0:frame,1:field */
+	unsigned int ysa; /* 0x90 */
+	unsigned int csa;
+	unsigned int pixwid;
+	unsigned int bufwid;
+	unsigned int vcrop; /* 0xA0 */
+	unsigned int hcrop;
+	unsigned int fhi;
+	unsigned int colfmt2; /* 0xAC, 1-444,other refer 0x84 */
+	unsigned int ysa2;	/* 0xB0 */
+	unsigned int csa2;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int req_num : 8;	/* Y & RGB */
+			unsigned int req_num_c : 8;	/* C */
+			unsigned int frame_enable : 1;
+		} b;
+	} mif_frame_mode; /* 0xB8 */
+
+	unsigned int reserved3[10];
+	union {
+		unsigned int val;
+		struct {
+			unsigned int update : 1;
+			unsigned int reserved : 7;
+			unsigned int level : 1;	/* 0:level 1, 1:level2 */
+		} b;
+	} sts; /* 0xE4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int fixed : 1;	/* 0-top, 1-bottom */
+			unsigned int enable : 1;
+		} b;
+	} swfld; /* 0xE8 */
+
+	unsigned int reserved4[5];
+	/* base2 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable : 1;
+			unsigned int reserved : 7;
+			unsigned int mode : 1; /* 0-frame,1-field */
+		} b;
+	} tg_enable; /* 0x100 */
+
+	unsigned int read_cyc;
+	unsigned int h_allpxl;
+	unsigned int v_allln;
+	unsigned int actln_bg; /* 0x110 */
+	unsigned int actln_end;
+	unsigned int actpx_bg;
+	unsigned int actpx_end;
+	unsigned int vbie_line; /* 0x120 */
+	unsigned int pvbi_line;
+	unsigned int hdmi_vbisw;
+	unsigned int hdmi_hsynw;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int offset : 12;
+			unsigned int reserved : 4;
+			unsigned int field_invert : 1;
+		} b;
+	} vsync_offset; /* 0x130 */
+
+	unsigned int field_status; /* 0x134, 1-BOTTOM,0-TOP */
+	unsigned int reserved5[1]; /* 0x138 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode : 3;	/* 011-frame packing progressive format,111-frame packing interlace format */
+			unsigned int inv_filed_polar : 1;
+			unsigned int blank_value : 16;
+			unsigned int reserved : 11;
+			unsigned int addr_sel : 1;	/* in frame packing interlace mode */
+		} b;
+	} hdmi_3d; /* 0x13C */
+
+	unsigned int reserved5_2[2];
+	union {
+		unsigned int val;
+		struct {
+			unsigned int outwidth : 1;	/* 0-24bit,1-12bit */
+			unsigned int hsync_polar : 1;	/* 0-active high,1-active low */
+			unsigned int enable : 1;
+			unsigned int vsync_polar : 1;	/* 0-active high,1-active low */
+			unsigned int reserved : 4;
+			unsigned int rgb_swap : 2;	/* 0-RGB[7:0],1-RGB[0:7],2-BGR[7:0],3-BGR[0:7] */
+			unsigned int reserved2 : 6;
+			unsigned int blk_dis : 1;	/* 0-Blank Data,1-Embeded sync CCIR656 */
+		} b;
+	} dvo_set; /* 0x148 */
+
+	unsigned int reserved6;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable : 1;
+			unsigned int reserved1 : 7;
+			unsigned int mode : 1;
+			unsigned int reserved2 : 7;
+			unsigned int inversion : 1;
+		} b;
+	} cb_enable; /* 0x150 */
+
+	unsigned int reserved7;
+	unsigned int h_allpxl2;
+	unsigned int v_allln2;
+	unsigned int actln_bg2;	/* 0x160 */
+	unsigned int actln_end2;
+	unsigned int actpx_bg2;
+	unsigned int actpx_end2;
+	unsigned int vbie_line2; /* 0x170 */
+	unsigned int pvbi_line2;
+	unsigned int hdmi_vbisw2;
+	unsigned int hdmi_hsynw2;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int outwidth : 1;	/* 0-24bit,1-12bit */
+			unsigned int hsync_polar : 1;	/* 0-active high,1-active low */
+			unsigned int enable : 1;
+			unsigned int vsync_polar : 1;	/* 0-active high,1-active low */
+		} b;
+	} lvds_ctrl; /* 0x180 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pix : 2;	/* 0-YUV444,1-RGB,2-YUV422,3-RGB */
+		} b;
+	} lvds_ctrl2; /* 0x184 */
+
+	unsigned int reserved_dac[12];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int praf : 8;
+			unsigned int pbaf : 8;
+			unsigned int yaf : 8;
+		} b;
+	} contrast; /* 0x1B8 */
+
+	unsigned int brightness;
+	unsigned int dmacsc_coef0; /* 0x1C0 */
+	unsigned int dmacsc_coef1;
+	unsigned int dmacsc_coef2;
+	unsigned int dmacsc_coef3;
+	unsigned int dmacsc_coef4; /* 0x1D0 */
+	unsigned int reserved8;
+	unsigned int dmacsc_coef5;
+	unsigned int dmacsc_coef6;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode : 1;	/* 1: YUV2RGB, 0: RGB2YUV */
+			unsigned int clamp : 1;	/* 0:Y,1:Y-16 */
+		} b;
+	} csc_mode; /* 0x1E0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int dvo : 1;
+			unsigned int vga : 1;
+			unsigned int reserved1 : 1;
+			unsigned int dac_clkinv : 1;
+			unsigned int blank_zero : 1;
+			unsigned int disp : 1;
+			unsigned int lvds : 1;
+			unsigned int hdmi : 1;
+			unsigned int rgb_mode : 2; /* 0-YUV, 1-RGB24, 2-1555, 3-565 */
+		} b;
+	} yuv2rgb; /* 0x1E4 */
+
+	unsigned int h264_input_en;	/* 0x1E8 */
+	unsigned int reserved9;
+	unsigned int lvds_clkinv; 	/* 0x1F0 */
+	unsigned int hscale_up;		/* 0x1F4 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode : 3;	/* 0:888,1:555,2:666,3:565,4:original */
+			unsigned int reserved : 5;
+			unsigned int ldi : 1;	/* 0:shift right,1:shift left */
+		} b;
+	} igs_mode; /* 0x1F8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode : 3;	/* 0:888,1:555,2:666,3:565,4:original */
+			unsigned int reserved : 5;
+			unsigned int ldi : 1;	/* 0:shift right,1:shift left */
+		} b;
+	} igs_mode2; /* 0x1FC */
+};
+
+/* GOVRH */
+#define REG_GOVRH_BASE1_BEGIN		(GOVRH_BASE1_ADDR+0x00)
+#define REG_GOVRH_YSA			(GOVRH_BASE1_ADDR+0x90)
+#define REG_GOVRH_CSA			(GOVRH_BASE1_ADDR+0x94)
+#define REG_GOVRH_BASE1_END		(GOVRH_BASE1_ADDR+0xe8)
+#define REG_GOVRH_BASE2_BEGIN		(GOVRH_BASE2_ADDR+0x00)
+#define REG_GOVRH_BASE2_END		(GOVRH_BASE2_ADDR+0xFC)
+
+/* GOVRH2 */
+#define REG_GOVRH2_BASE1_BEGIN		(GOVRH2_BASE1_ADDR+0x00)
+#define REG_GOVRH2_YSA			(GOVRH2_BASE1_ADDR+0x90)
+#define REG_GOVRH2_CSA			(GOVRH2_BASE1_ADDR+0x94)
+#define REG_GOVRH2_BASE1_END		(GOVRH2_BASE1_ADDR+0xe8)
+#define REG_GOVRH2_BASE2_BEGIN		(GOVRH2_BASE2_ADDR+0x00)
+#define REG_GOVRH2_BASE2_END		(GOVRH2_BASE2_ADDR+0xFC)
+
+#endif /* WMT_GOVRH_REG_H */
diff --git a/drivers/video/wmt/hw/wmt-hdmi-reg.h b/drivers/video/wmt/hw/wmt-hdmi-reg.h
new file mode 100644
index 00000000..919d6ab3
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-hdmi-reg.h
@@ -0,0 +1,266 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-hdmi-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_HDMI_REG_H
+#define WMT_HDMI_REG_H
+
+#define WMT_FTBLK_HDMI
+
+#define HDMI_BASE_ADDR			(HDMI_TRANSMITTE_BASE_ADDR + 0xC000)
+
+/* HDMI registers */
+#define REG_HDMI_BEGIN			(HDMI_BASE_ADDR + 0x100)
+#define REG_HDMI_CTRL			(HDMI_BASE_ADDR + 0x120)
+#define REG_HDMI_I2C_CTRL		(HDMI_BASE_ADDR + 0x124)
+#define REG_HDMI_I2C_CTRL2		(HDMI_BASE_ADDR + 0x128)
+#define REG_HDMI_GENERAL_CTRL		(HDMI_BASE_ADDR + 0x280)
+#define REG_HDMI_INFOFRAME_CTRL		(HDMI_BASE_ADDR + 0x284)
+#define REG_HDMI_AUD_INSERT_CTRL	(HDMI_BASE_ADDR + 0x294)
+#define REG_HDMI_AUD_RATIO		(HDMI_BASE_ADDR + 0x29c)
+#define REG_HDMI_AUD_ENABLE		(HDMI_BASE_ADDR + 0x2a0)
+#define REG_HDMI_AUD_MODE		(HDMI_BASE_ADDR + 0x2ac)
+#define REG_HDMI_AUD_CHAN_STATUS0	(HDMI_BASE_ADDR + 0x390)
+#define REG_HDMI_AUD_CHAN_STATUS1	(HDMI_BASE_ADDR + 0x394)
+#define REG_HDMI_AUD_CHAN_STATUS2	(HDMI_BASE_ADDR + 0x398)
+#define REG_HDMI_AUD_CHAN_STATUS3	(HDMI_BASE_ADDR + 0x39c)
+#define REG_HDMI_AUD_CHAN_STATUS4	(HDMI_BASE_ADDR + 0x3a0)
+#define REG_HDMI_AUD_CHAN_STATUS5	(HDMI_BASE_ADDR + 0x3a4)
+#define REG_HDMI_AUD_SAMPLE_RATE1	(HDMI_BASE_ADDR + 0x3a8)
+#define REG_HDMI_AUD_SAMPLE_RATE2	(HDMI_BASE_ADDR + 0x3ac)
+
+/* HDMI info WR FIFO 0x3c0 - 0x3e0 */
+#define REG_HDMI_WR_FIFO_ADDR		(HDMI_BASE_ADDR + 0x3c0)
+#define REG_HDMI_FIFO_CTRL		(HDMI_BASE_ADDR + 0x3e4)
+#define REG_HDMI_CHANNEL_TEST		(HDMI_BASE_ADDR + 0x3e8)
+#define REG_HDMI_HOTPLUG_DETECT		(HDMI_BASE_ADDR + 0x3ec)
+#define REG_HDMI_HOTPLUG_DEBOUNCE	(HDMI_BASE_ADDR + 0x3f0)
+#define REG_HDMI_TMDS_CTRL 		(HDMI_BASE_ADDR + 0x3f8)
+
+/* HDMI info RD FIFO 0x400 - 0x420 */
+#define REG_HDMI_RD_FIFO_ADDR		(HDMI_BASE_ADDR + 0x400)
+
+#define REG_HDMI_END			(HDMI_BASE_ADDR + 0x420)
+
+/* REG_HDMI_CTRL,0x120 */
+#define HDMI_EEPROM_RESET		REG_HDMI_CTRL, BIT0, 0
+#define HDMI_ENCODE_ENABLE		REG_HDMI_CTRL, BIT1, 1
+#define HDMI_HDEN			REG_HDMI_CTRL, BIT2, 2
+#define HDMI_EESS_ENABLE		REG_HDMI_CTRL, BIT3, 3
+#define HDMI_VERIFY_PJ_ENABLE		REG_HDMI_CTRL, BIT4, 4
+#define HDMI_I2C_ENABLE			REG_HDMI_CTRL, BIT5, 5
+#define HDMI_AUTH_TEST_KEY		REG_HDMI_CTRL, BIT6, 6
+#define HDMI_CIPHER_1_1			REG_HDMI_CTRL, BIT8, 8
+#define HDMI_PREAMBLE			REG_HDMI_CTRL, 0xF000, 12
+#define HDMI_ENCODE_WINDOW		REG_HDMI_CTRL, 0x700000, 20
+
+/* REG_HDMI_I2C_CTRL,0x124 */
+#define HDMI_FORCE_EXIT_FSM		REG_HDMI_I2C_CTRL, BIT7, 7
+#define HDMI_KEY_READ_WORD		REG_HDMI_I2C_CTRL, 0xFF00, 8
+#define HDMI_I2C_SW_RESET		REG_HDMI_I2C_CTRL, 0x8000, 15
+#define HDMI_I2C_CLK_DIVIDER		REG_HDMI_I2C_CTRL, 0xFFFF0000, 16
+
+/* REG_HDMI_I2C_CTRL2,0x128 */
+#define HDMI_WR_DATA			REG_HDMI_I2C_CTRL2, 0xFF, 0
+#define HDMI_RD_DATA			REG_HDMI_I2C_CTRL2, 0xFF00, 8
+#define HDMI_SW_START_REQ		REG_HDMI_I2C_CTRL2, BIT16, 16
+#define HDMI_SW_STOP_REQ		REG_HDMI_I2C_CTRL2, BIT17, 17
+#define HDMI_WR_DATA_AVAIL		REG_HDMI_I2C_CTRL2, BIT18, 18
+#define HDMI_I2C_STATUS			REG_HDMI_I2C_CTRL2, BIT19, 19 /* 0-not using, 1-in using */
+#define HDMI_CP_KEY_REQ			REG_HDMI_I2C_CTRL2, BIT20, 20
+#define HDMI_CP_KEY_READ		REG_HDMI_I2C_CTRL2, BIT21, 21
+#define HDMI_CP_KEY_LAST		REG_HDMI_I2C_CTRL2, BIT22, 22
+#define HDMI_CP_SRC_SEL			REG_HDMI_I2C_CTRL2, BIT24, 24
+#define HDMI_SW_READ			REG_HDMI_I2C_CTRL2, BIT25, 25
+#define HDMI_SW_I2C_REQ			REG_HDMI_I2C_CTRL2, BIT26, 26
+#define HDMI_KSV_LIST_AVAIL		REG_HDMI_I2C_CTRL2, BIT27, 27
+#define HDMI_KSV_VERIFY_DONE		REG_HDMI_I2C_CTRL2, BIT28, 28
+
+/* REG_HDMI_GENERAL_CTRL,0x280 */
+#define HDMI_RESET			REG_HDMI_GENERAL_CTRL, BIT0, 0
+#define HDMI_ENABLE			REG_HDMI_GENERAL_CTRL, BIT1, 1
+#define HDMI_DVI_MODE_ENABLE		REG_HDMI_GENERAL_CTRL, BIT6, 6
+#define HDMI_OUTPUT_FORMAT		REG_HDMI_GENERAL_CTRL, 0x180, 7	/* 0-RGB,1-YUV444,2-YUV422 */
+#define HDMI_CONVERT_YUV422		REG_HDMI_GENERAL_CTRL, BIT9, 9
+#define HDMI_HSYNC_LOW_ACTIVE		REG_HDMI_GENERAL_CTRL, BIT10, 10 /* 0-active high,1-active low */
+#define HDMI_DBG_BUS_SELECT		REG_HDMI_GENERAL_CTRL, BIT11, 11 /* 0-before,1-after */
+#define HDMI_VSYNC_LOW_ACTIVE		REG_HDMI_GENERAL_CTRL, BIT13, 13 /* 0-active high,1-active low */
+#define HDMI_CP_DELAY			REG_HDMI_GENERAL_CTRL, 0x7F0000, 16 /* delay for CP after HSYNC raising edge */
+#define HDMI_VSYNC_384_ENABLE		REG_HDMI_GENERAL_CTRL, BIT24, 24
+#define HDMI_VSYNC_385_507_ENABLE	REG_HDMI_GENERAL_CTRL, BIT25, 25
+#define HDMI_VSYNC_650_ENABLE		REG_HDMI_GENERAL_CTRL, BIT26, 26
+#define HDMI_STATE_MACHINE_STATUS	REG_HDMI_GENERAL_CTRL, 0xF8000000, 27
+
+/* REG_HDMI_INFOFRAME_CTRL,0x284 */
+#define HDMI_INFOFRAME_SELECT		REG_HDMI_INFOFRAME_CTRL, BIT0, 0 /* 0-fifo1,1-fifo2 */
+#define HDMI_INFOFRAME_FIFO1_RDY	REG_HDMI_INFOFRAME_CTRL, BIT1, 1 /* Info frame FIFO 1 ready */
+#define HDMI_INFOFRAME_FIFO2_RDY	REG_HDMI_INFOFRAME_CTRL, BIT2, 2 /* Info frame FIFO 2 ready */
+#define HDMI_INFOFRAME_FIFO1_ADDR	REG_HDMI_INFOFRAME_CTRL, 0xF0, 4 /* Info frame FIFO 1 start address */
+#define HDMI_INFOFRAME_FIFO1_LEN	REG_HDMI_INFOFRAME_CTRL, 0x1F00, 8 /* Info frame FIFO 1 length */
+#define HDMI_INFOFRAME_FIFO2_ADDR	REG_HDMI_INFOFRAME_CTRL, 0xF0000, 16 /* Info frame FIFO 2 start address */
+#define HDMI_INFOFRAME_FIFO2_LEN	REG_HDMI_INFOFRAME_CTRL, 0x1F00000, 20 /* Info frame FIFO 2 length */
+#define HDMI_HORIZ_BLANK_MAX_PCK	REG_HDMI_INFOFRAME_CTRL, 0x70000000, 28 /* Max packets that insert during HSYNC */
+
+/* REG_HDMI_AUD_INSERT_CTRL,0x294 */
+#define HDMI_AUD_PCK_INSERT_RESET	REG_HDMI_AUD_INSERT_CTRL, BIT0, 0
+#define HDMI_AUD_PCK_INSERT_ENABLE	REG_HDMI_AUD_INSERT_CTRL, BIT1, 1
+#define HDMI_AVMUTE_SET_ENABLE		REG_HDMI_AUD_INSERT_CTRL, BIT2, 2
+#define HDMI_AVMUTE_CLR_ENABLE		REG_HDMI_AUD_INSERT_CTRL, BIT3, 3
+#define HDMI_AUD_INSERT_DELAY		REG_HDMI_AUD_INSERT_CTRL, 0xFFF0, 4
+#define HDMI_AUD_PIXEL_REPETITION	REG_HDMI_AUD_INSERT_CTRL, 0xC0000000, 30 /* 0-none,1-2 times,2-4 times */
+
+/* REG_HDMI_AUD_RATIO,0x29c */
+#define HDMI_AUD_ACR_RATIO		REG_HDMI_AUD_RATIO, 0x0FFFFF00, 8
+#define HDMI_AUD_ACR_ENABLE		REG_HDMI_AUD_RATIO, BIT28, 28
+#define HDMI_AUD_MUTE			REG_HDMI_AUD_RATIO, BIT29, 29
+
+/* REG_HDMI_AUD_ENABLE,0x2a0 */
+#define HDMI_AUD_ENABLE			REG_HDMI_AUD_ENABLE, BIT0, 0
+
+/* REG_HDMI_AUD_MODE,0x2ac */
+#define HDMI_AUD_SUB_PACKET		REG_HDMI_AUD_MODE, 0xF, 0
+#define HDMI_AUD_SPFLAT			REG_HDMI_AUD_MODE, 0xF0, 4
+#define HDMI_AUD_2CH_ECO		REG_HDMI_AUD_MODE, BIT8, 8
+#define HDMI_AUD_LAYOUT			REG_HDMI_AUD_MODE, BIT10, 10 /* 0-2 channel,1-8 channel */
+#define HDMI_AUD_PWR_SAVING		REG_HDMI_AUD_MODE, BIT11, 11 /* 0-normal, 1-power saving */
+
+/* REG_HDMI_AUD_CHAN_STATUS0,0x390 */
+/* REG_HDMI_AUD_CHAN_STATUS1,0x394 */
+/* REG_HDMI_AUD_CHAN_STATUS2,0x398 */
+/* REG_HDMI_AUD_CHAN_STATUS3,0x39c */
+/* REG_HDMI_AUD_CHAN_STATUS4,0x3a0 */
+/* REG_HDMI_AUD_CHAN_STATUS5,0x3a4 */
+
+/* REG_HDMI_AUD_SAMPLE_RATE1,0x3a8 */
+#define HDMI_AUD_N_20BITS		REG_HDMI_AUD_SAMPLE_RATE1, 0xFFFFF, 0
+#define HDMI_AUD_CTS_LOW_12BITS		REG_HDMI_AUD_SAMPLE_RATE1, 0xFFF00000, 20
+
+/* REG_HDMI_AUD_SAMPLE_RATE2,0x3ac */
+#define HDMI_AUD_CTS_HI_8BITS		REG_HDMI_AUD_SAMPLE_RATE2, 0xFF, 0
+#define HDMI_AUD_AIPCLK_RATE		REG_HDMI_AUD_SAMPLE_RATE2, 0x30000000, 28 /* 0-N/2,1-N,2-N/4,3-N*2 */
+#define HDMI_AUD_CTS_SELECT		REG_HDMI_AUD_SAMPLE_RATE2, BIT30, 30 /* 0-auto, 1-fixed from register */
+
+/* 0x3c0 - 0x3e0 : Info frame FIFO data */
+
+/* REG_HDMI_FIFO_CTRL,0x3e4 */
+#define HDMI_INFOFRAME_WR_STROBE	REG_HDMI_FIFO_CTRL, BIT0, 0
+#define HDMI_INFOFRAME_RD_STROBE	REG_HDMI_FIFO_CTRL, BIT1, 1
+#define HDMI_INFOFRAME_FIFO_ADDR	REG_HDMI_FIFO_CTRL, 0xFF00, 8
+
+/* REG_HDMI_CHANNEL_TEST,0x3e8 */
+#define HDMI_CH1_TEST_MODE_ENABLE	REG_HDMI_CHANNEL_TEST, BIT26, 26
+#define HDMI_CH1_TEST_DATA		REG_HDMI_CHANNEL_TEST, 0x3FF0000, 16
+#define HDMI_CH0_TEST_MODE_ENABLE	REG_HDMI_CHANNEL_TEST, BIT10, 10
+#define HDMI_CH0_TEST_DATA		REG_HDMI_CHANNEL_TEST, 0x3FF, 0
+
+/* REG_HDMI_HOTPLUG_DETECT,0x3ec */
+#define HDMI_HOTPLUG_IN			REG_HDMI_HOTPLUG_DETECT, BIT31, 31 /* 0-plug out,1-plug in */
+#define HDMI_HOTPLUG_OUT_STS		REG_HDMI_HOTPLUG_DETECT, BIT25, 25
+#define HDMI_HOTPLUG_IN_STS		REG_HDMI_HOTPLUG_DETECT, BIT24, 24
+#define HDMI_HOTPLUG_OUT_INT		REG_HDMI_HOTPLUG_DETECT, BIT17, 17
+#define HDMI_HOTPLUG_IN_INT		REG_HDMI_HOTPLUG_DETECT, BIT16, 16
+#define HDMI_CH2_TEST_MODE_ENABLE	REG_HDMI_HOTPLUG_DETECT, BIT10, 10
+#define HDMI_CH2_TEST_DATA		REG_HDMI_HOTPLUG_DETECT, 0x3FF, 0
+
+/* REG_HDMI_HOTPLUG_DEBOUNCE,0x3f0 */
+#define HDMI_DEBOUNCE_DETECT		REG_HDMI_HOTPLUG_DEBOUNCE, 0x1FF0000, 16
+#define HDMI_DEBOUNCE_SAMPLE		REG_HDMI_HOTPLUG_DEBOUNCE, 0xFF, 0
+
+/* REG_HDMI_TMDS_CTRL,0x3f8 */
+#define HDMI_CLOCK_SELECT		REG_HDMI_TMDS_CTRL, BIT16, 16 /* 0-clk 1x, 1-clk 2x */
+#define HDMI_INFOFRAME_SRAM_ENABLE	REG_HDMI_TMDS_CTRL, BIT10, 10
+#define HDMI_TMDS_TST_FORMAT		REG_HDMI_TMDS_CTRL, BIT1, 1
+#define HDMI_TMDS_TST_ENABLE		REG_HDMI_TMDS_CTRL, BIT0, 0
+
+/* 0x400 - 0x420 : HDMI info frame FIFO data (RO) */
+
+#define REG_HDMI2_BEGIN			(HDMI_BASE2_ADDR + 0x00)
+#define REG_HDMI_STATUS			(HDMI_BASE2_ADDR + 0x00)
+#define REG_HDMI_TEST			(HDMI_BASE2_ADDR + 0x04)
+#define REG_HDMI_LEVEL			(HDMI_BASE2_ADDR + 0x08)
+#define REG_HDMI_IGS			(HDMI_BASE2_ADDR + 0x0C)
+#define REG_HDMI_SET			(HDMI_BASE2_ADDR + 0x10)
+#define REG_HDMI_SET2			(HDMI_BASE2_ADDR + 0x14)
+#define REG_HDMI_DETECT			(HDMI_BASE2_ADDR + 0x18)
+#define REG_HDMI_TEST2			(HDMI_BASE2_ADDR + 0x1C)
+#define REG_HDMI_TEST3			(HDMI_BASE2_ADDR + 0x20)
+#define REG_HDMI_DFTSET2		(HDMI_BASE2_ADDR + 0x24)
+#define REG_HDMI2_END			(HDMI_BASE2_ADDR + 0x28)
+
+/* REG_HDMI_STATUS,0x00 */
+#define HDMI_INTERNAL_LDO		REG_HDMI_STATUS, 0x80000, 19
+#define HDMI_TEST			REG_HDMI_STATUS, 0xF00, 8
+#define HDMI_DUAL_CHANNEL		REG_HDMI_STATUS, BIT4, 4
+#define HDMI_INV_CLK			REG_HDMI_STATUS, BIT0, 0
+
+/* REG_HDMI_TEST,0x04 */
+#define HDMI_PLL_R_F			REG_HDMI_TEST, BIT18, 18
+#define HDMI_PLL_CPSET			REG_HDMI_TEST, 0x30000, 16
+#define HDMI_PLLCK_DLY			REG_HDMI_TEST, 0x7000, 12
+#define HDMI_TRE_EN			REG_HDMI_TEST, 0x600, 9
+#define HDMI_PD				REG_HDMI_TEST, BIT8, 8
+#define HDMI_VBG_SEL			REG_HDMI_TEST, 0xC, 2
+#define HDMI_DRV_PDMODE			REG_HDMI_TEST, BIT0, 0
+
+/* REG_HDMI_LEVEL,0x08 */
+#define HDMI_REG_LEVEL			REG_HDMI_LEVEL, BIT8, 8
+#define HDMI_REG_UPDATE			REG_HDMI_LEVEL, BIT0, 0
+
+/* REG_HDMI_IGS,0x0C */
+#define HDMI_LDI_SHIFT_LEFT		REG_HDMI_IGS, BIT8, 8 /* 0-shift right,1-shift left */
+#define HDMI_IGS_BPP_TYPE		REG_HDMI_IGS, 0x7, 0 /* 0-888,1-555,2-666,3-565 */
+
+/* REG_HDMI_SET,0x10 */
+#define HDMI_VSYNC_POLAR_LO		REG_HDMI_SET, BIT3, 3 /* 0-active high,1-active low */
+#define HDMI_DVO_ENABLE			REG_HDMI_SET, BIT2, 2
+#define HDMI_HSYNC_POLAR_LO		REG_HDMI_SET, BIT1, 1 /* 0-active high,1-active low */
+#define HDMI_OUT_DATA_12		REG_HDMI_SET, BIT0, 0 /* 0-24bit,1-12bit */
+
+/* REG_HDMI_SET2,0x14 */
+#define HDMI_COLFMT_YUV422		REG_HDMI_SET2, BIT1, 1 /* 0-RGB or YUV444,1-YUV422 */
+#define HDMI_COLFMT_RGB			REG_HDMI_SET2, BIT0, 0
+
+/* REG_HDMI_DETECT,0x18 */
+#define HDMI_RSEN			REG_HDMI_DETECT, BIT8, 8
+#define HDMI_PLL_READY			REG_HDMI_DETECT, BIT0, 0
+
+/* REG_HDMI_TEST2,0x1C */
+#define HDMI_PLL_TSYNC			REG_HDMI_TEST2, BIT0, 0
+#define HDMI_TP2S_TYPE			REG_HDMI_TEST2, BIT1, 1
+#define HDMI_DIV_SEL			REG_HDMI_TEST2, 0xC, 2
+#define HDMI_PD_V2I			REG_HDMI_TEST2, BIT4, 4
+#define HDMI_VCO_SX			REG_HDMI_TEST2, BIT5, 5
+#define HDMI_VCO_MODE			REG_HDMI_TEST2, BIT6, 6
+#define HDMI_VSREF_SEL			REG_HDMI_TEST2, 0x300, 8
+#define HDMI_MODE			REG_HDMI_TEST2, BIT10, 10
+#define HDMI_PD_L2HA			REG_HDMI_TEST2, BIT11, 11
+#define HDMI_PD_L2HB			REG_HDMI_TEST2, BIT12, 12
+#define HDMI_L2HA_HSEN			REG_HDMI_TEST2, BIT13, 13
+#define HDMI_RESA_EN			REG_HDMI_TEST2, BIT14, 14
+#define HDMI_RESA_S			REG_HDMI_TEST2, BIT15, 15
+#define HDMI_PLL_LPFS			REG_HDMI_TEST2, 0x30000, 16
+
+/* REG_HDMI_DFTSET2,0x24 */
+#define HDMI_RESET_PLL			REG_HDMI_DFTSET2, BIT16, 16
+
+#endif /* WMT_HDMI_REG_H */
+
diff --git a/drivers/video/wmt/hw/wmt-lvds-reg.h b/drivers/video/wmt/hw/wmt-lvds-reg.h
new file mode 100644
index 00000000..d258d6e8
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-lvds-reg.h
@@ -0,0 +1,92 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-lvds-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_LVDS_REG_H
+#define WMT_LVDS_REG_H
+
+#define WMT_FTBLK_LVDS
+
+#define REG_LVDS_BEGIN		(LVDS_BASE_ADDR + 0x00)
+#define REG_LVDS_STATUS		(LVDS_BASE_ADDR + 0x00)
+#define REG_LVDS_TEST		(LVDS_BASE_ADDR + 0x04)
+#define REG_LVDS_LEVEL		(LVDS_BASE_ADDR + 0x08)
+#define REG_LVDS_IGS		(LVDS_BASE_ADDR + 0x0C)
+#define REG_LVDS_SET		(LVDS_BASE_ADDR + 0x10)
+#define REG_LVDS_SET2		(LVDS_BASE_ADDR + 0x14)
+#define REG_LVDS_DETECT		(LVDS_BASE_ADDR + 0x18)
+#define REG_LVDS_TEST2		(LVDS_BASE_ADDR + 0x1C)
+#define REG_LVDS_END		(LVDS_BASE_ADDR + 0x1C)
+
+/* REG_LVDS_STATUS,0x00 */
+#define LVDS_TEST		REG_LVDS_STATUS, 0xF00, 8
+#define LVDS_DUAL_CHANNEL	REG_LVDS_STATUS, BIT4, 4
+#define LVDS_INV_CLK		REG_LVDS_STATUS, BIT0, 0
+
+/* REG_LVDS_TEST,0x04 */
+#define LVDS_PLL_R_F		REG_LVDS_TEST, BIT18, 18
+#define LVDS_PLL_CPSET		REG_LVDS_TEST, 0x30000, 16
+#define LVDS_PLLCK_DLY		REG_LVDS_TEST, 0x7000, 12
+#define LVDS_TRE_EN		REG_LVDS_TEST, 0x600, 9
+#define LVDS_PD			REG_LVDS_TEST, BIT8, 8
+#define LVDS_VBG_SEL		REG_LVDS_TEST, 0xC, 2
+#define LVDS_DRV_PDMODE		REG_LVDS_TEST, BIT0, 0
+
+/* REG_LVDS_LEVEL,0x08 */
+#define LVDS_REG_LEVEL		REG_LVDS_LEVEL, BIT8, 8
+#define LVDS_REG_UPDATE		REG_LVDS_LEVEL, BIT0, 0
+
+/* REG_LVDS_IGS,0x0C */
+#define LVDS_LDI_SHIFT_LEFT	REG_LVDS_IGS, BIT8, 8 /* 0-shift right,1-shift left */
+#define LVDS_IGS_BPP_TYPE	REG_LVDS_IGS, 0x7, 0 /* 0-888,1-555,2-666,3-565 */
+
+/* REG_LVDS_SET,0x10 */
+#define LVDS_VSYNC_POLAR_LO	REG_LVDS_SET, BIT3, 3 /* 0-active high,1-active low */
+#define LVDS_DVO_ENABLE		REG_LVDS_SET, BIT2, 2
+#define LVDS_HSYNC_POLAR_LO	REG_LVDS_SET, BIT1, 1 /* 0-active high,1-active low */
+#define LVDS_OUT_DATA_12	REG_LVDS_SET, BIT0, 0 /* 0-24bit,1-12bit */
+
+/* REG_LVDS_SET2,0x14 */
+#define LVDS_COLFMT_YUV422	REG_LVDS_SET2, BIT1, 1 /* 0-RGB or YUV444,1-YUV422 */
+#define LVDS_COLFMT_RGB		REG_LVDS_SET2, BIT0, 0
+
+/* REG_LVDS_DETECT,0x18 */
+#define LVDS_RSEN		REG_LVDS_DETECT, BIT8, 8
+#define LVDS_PLL_READY		REG_LVDS_DETECT, BIT0, 0
+
+/* REG_LVDS_TEST2,0x1C */
+#define LVDS_PLL_TSYNC		REG_LVDS_TEST2, BIT0, 0
+#define LVDS_TP2S_TYPE		REG_LVDS_TEST2, BIT1, 1
+#define LVDS_DIV_SEL		REG_LVDS_TEST2, 0xC, 2
+#define LVDS_PD_V2I		REG_LVDS_TEST2, BIT4, 4
+#define LVDS_VCO_SX		REG_LVDS_TEST2, BIT5, 5
+#define LVDS_VCO_MODE		REG_LVDS_TEST2, BIT6, 6
+#define LVDS_VSREF_SEL		REG_LVDS_TEST2, 0x300, 8
+#define LVDS_MODE		REG_LVDS_TEST2, BIT10, 10
+#define LVDS_PD_L2HA		REG_LVDS_TEST2, BIT11, 11
+#define LVDS_PD_L2HB		REG_LVDS_TEST2, BIT12, 12
+#define LVDS_L2HA_HSEN		REG_LVDS_TEST2, BIT13, 13
+#define LVDS_RESA_EN		REG_LVDS_TEST2, BIT14, 14
+#define LVDS_RESA_S		REG_LVDS_TEST2, BIT15, 15
+#define LVDS_PLL_LPFS		REG_LVDS_TEST2, 0x30000, 16
+
+#endif /* WMT_LVDS_REG_H */
diff --git a/drivers/video/wmt/hw/wmt-scl-reg.h b/drivers/video/wmt/hw/wmt-scl-reg.h
new file mode 100644
index 00000000..cabb75a7
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-scl-reg.h
@@ -0,0 +1,374 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-scl-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_SCL_REG_H
+#define WMT_SCL_REG_H
+
+/* feature */
+#define WMT_FTBLK_SCL
+
+/* constant */
+#define WMT_SCL_RCYC_MIN	0	/* 1T */
+#define WMT_SCL_H_DIV_MAX	8192
+#define WMT_SCL_V_DIV_MAX	8192
+#define WMT_SCL_FB_WIDTH_MAX	8192
+
+#define WMT_SCL_SCALE_DST_H_MAX	1920 	/* bypass no limit */
+
+/* registers */
+#define REG_SCL_BASE1_BEGIN	(SCL_BASE_ADDR + 0x00)
+#define REG_SCL_EN		(SCL_BASE_ADDR + 0x00)
+#define REG_SCL_UPD		(SCL_BASE_ADDR + 0x04)
+#define REG_SCL_SEL		(SCL_BASE_ADDR + 0x08)
+#define REG_SCL_HXWIDTH		(SCL_BASE_ADDR + 0x3c)
+#define REG_SCLR2_CTL		(SCL_BASE_ADDR + 0x40)
+#define REG_SCLR2_YSA		(SCL_BASE_ADDR + 0x44)
+#define REG_SCLR2_CSA		(SCL_BASE_ADDR + 0x48)
+#define REG_SCLR2_H_SIZE	(SCL_BASE_ADDR + 0x4C)
+#define REG_SCLR2_CROP		(SCL_BASE_ADDR + 0x50)
+#define REG_ALFA_MD		(SCL_BASE_ADDR + 0x54)
+#define REG_ALFA_FXD		(SCL_BASE_ADDR + 0x58)
+#define REG_ALFA_COLORKEY	(SCL_BASE_ADDR + 0x5C)
+#define REG_ALFA_COLORKEY_RGB	(SCL_BASE_ADDR + 0x60)
+#define REG_SCL_VXWIDTH		(SCL_BASE_ADDR + 0x70)
+#define REG_SCL_SCLUP_EN	(SCL_BASE_ADDR + 0x74)
+
+#define REG_SCL_VSCALE1		(SCL_BASE_ADDR + 0x78)
+#define REG_SCL_VSCALE2		(SCL_BASE_ADDR + 0x7c)
+#define REG_SCL_VSCALE3		(SCL_BASE_ADDR + 0x80)
+#define REG_SCL_HSCALE1		(SCL_BASE_ADDR + 0x84)
+#define REG_SCL_HSCALE2		(SCL_BASE_ADDR + 0x88)
+#define REG_SCL_HSCALE3		(SCL_BASE_ADDR + 0x8c)
+#define REG_SCLR_REQ_NUM	(SCL_BASE_ADDR + 0x90)
+#define REG_SCL_SCLDW		(SCL_BASE_ADDR + 0x94)
+#define REG_SCL_426_SW		(SCL_BASE_ADDR + 0x98)
+#define REG_SCL_VBYPASS		(SCL_BASE_ADDR + 0x9C)
+/* SCL_TG */
+#define REG_SCL_TG_CTL		(SCL_BASE_ADDR + 0xa0)
+#define REG_SCL_TG_TOTAL	(SCL_BASE_ADDR + 0xa4)
+#define REG_SCL_TG_V_ACTIVE	(SCL_BASE_ADDR + 0xa8)
+#define REG_SCL_TG_H_ACTIVE	(SCL_BASE_ADDR + 0xac)
+#define REG_SCL_TG_VBI		(SCL_BASE_ADDR + 0xb0)
+#define REG_SCL_TG_WATCHDOG	(SCL_BASE_ADDR + 0xb4)
+#define REG_SCL_TG_STS		(SCL_BASE_ADDR + 0xb8)
+#define REG_SCL_TG_GOVW		(SCL_BASE_ADDR + 0xbc)
+/* SCLR */
+#define REG_SCLR_CTL		(SCL_BASE_ADDR + 0xc0)
+#define REG_SCLR_YSA		(SCL_BASE_ADDR + 0xc4)
+#define REG_SCLR_CSA		(SCL_BASE_ADDR + 0xc8)
+#define REG_SCLR_H_SIZE		(SCL_BASE_ADDR + 0xcc)
+#define REG_SCLR_CROP		(SCL_BASE_ADDR + 0xd0)
+#define REG_SCLR_FIFO_CTL	(SCL_BASE_ADDR + 0xd4)
+/* SCLW */
+#define REG_SCLW_CTL		(SCL_BASE_ADDR + 0xe0)
+#define REG_SCLW_YSA		(SCL_BASE_ADDR + 0xe4)
+#define REG_SCLW_CSA		(SCL_BASE_ADDR + 0xe8)
+#define REG_SCLW_Y_TIME		(SCL_BASE_ADDR + 0xec)
+#define REG_SCLW_C_TIME		(SCL_BASE_ADDR + 0xf0)
+#define REG_SCLW_FF_CTL		(SCL_BASE_ADDR + 0xf4)
+#define REG_SCLW_INT		(SCL_BASE_ADDR + 0xf8)
+#define REG_SCL_TRUE_BILINEAR	(SCL_BASE_ADDR + 0xfc)
+
+#define REG_SCL_BASE1_END	(SCL_BASE_ADDR + 0xFC)
+
+/* SCL444 CSC */
+#define REG_SCL_BASE2_BEGIN	(SCL_BASE2_ADDR + 0x00)
+#define REG_SCL_CSC_CTL		(SCL_BASE2_ADDR + 0x00)
+#define REG_SCL_CSC1		(SCL_BASE2_ADDR + 0x04)
+#define REG_SCL_CSC2		(SCL_BASE2_ADDR + 0x08)
+#define REG_SCL_CSC3		(SCL_BASE2_ADDR + 0x0c)
+#define REG_SCL_CSC4		(SCL_BASE2_ADDR + 0x10)
+#define REG_SCL_CSC5		(SCL_BASE2_ADDR + 0x14)
+#define REG_SCL_CSC6		(SCL_BASE2_ADDR + 0x18)
+#define REG_SCL_ARGB_ALPHA	(SCL_BASE2_ADDR + 0x1C)
+#define REG_SCL_IGS		(SCL_BASE2_ADDR + 0x20)
+#define REG_SCL_R2_CSC		(SCL_BASE2_ADDR + 0x24)
+#define REG_SCL_R2_CSC1		(SCL_BASE2_ADDR + 0x28)
+#define REG_SCL_R2_CSC2		(SCL_BASE2_ADDR + 0x2C)
+#define REG_SCL_R2_CSC3		(SCL_BASE2_ADDR + 0x30)
+#define REG_SCL_R2_CSC4		(SCL_BASE2_ADDR + 0x34)
+#define REG_SCL_R2_CSC5		(SCL_BASE2_ADDR + 0x38)
+#define REG_SCL_R2_CSC6		(SCL_BASE2_ADDR + 0x3C)
+#define REG_SCL_RECURSIVE_MODE	(SCL_BASE2_ADDR + 0xA0)
+#define REG_SCL_FIELD_MODE	(SCL_BASE2_ADDR + 0xC0)
+#define REG_SCL_DBLK_THRESHOLD	(SCL_BASE2_ADDR + 0xC4)
+#define REG_SCL_FIELD_FLICKER	(SCL_BASE2_ADDR + 0xC8)
+#define REG_SCL_FRAME_FLICKER	(SCL_BASE2_ADDR + 0xCC)
+#define REG_SCL_READCYC_1T	(SCL_BASE2_ADDR + 0xD0)
+#define REG_SCL_BASE2_END	(SCL_BASE2_ADDR + 0xE0)
+
+/* REG_SCL_EN,0x00 */
+#define SCL_ALU_ENABLE		REG_SCL_EN, BIT0, 0
+
+/* REG_SCL_UPD,0x04 */
+#define SCL_REG_UPDATE		REG_SCL_UPD, BIT0, 0
+
+/* REG_SCL_SEL,0x08 */
+#define SCL_REG_LEVEL		REG_SCL_SEL, BIT0, 0
+
+/* REG_SCL_HXWIDTH,0x3c */
+#define SCL_HXWIDTH		REG_SCL_HXWIDTH, 0x1FFF, 0
+
+/* REG_SCLR2_CTL,0x40 */
+#define SCL_R2_MIF_EN		REG_SCLR2_CTL, BIT0, 0
+#define SCL_R2_RGB_MODE		REG_SCLR2_CTL, 0x30, 4	 /* 0-YUV,1-RGB565,3-RGB32 */
+#define SCL_R2_420C_FMT		REG_SCLR2_CTL, BIT8, 8	 /* 0-frame,1-field */
+#define SCL_R2_VFMT		REG_SCLR2_CTL, 0xE00, 9	 /* 0-YUV422,1-YUV420,2-YUV444,4-RGB32 */
+#define SCL_R2_H264_FMT		REG_SCLR2_CTL, BIT12, 12 /* 0-MPEG,1-H264 */
+#define SCL_R2_IOFMT		REG_SCLR2_CTL, BIT16, 16 /* 0-frame,1-field */
+#define SCL_R2_COLOR_EN		REG_SCLR2_CTL, BIT24, 24 /* 0-disable,1-enable */
+#define SCL_R2_COLOR_WIDE	REG_SCLR2_CTL, BIT25, 25 /* 0-Normal,1-Wider */
+#define SCL_R2_COLOR_INV	REG_SCLR2_CTL, BIT26, 26 /* 0-Normal,1-Opposite color */
+
+/* REG_SCLR2_YSA,0x44 */
+/* REG_SCLR2_CSA,0x48 */
+
+/* REG_SCLR2_H_SIZE,0x4C */
+#define SCL_R2_FBW		REG_SCLR2_H_SIZE, 0x1FFF, 0 /* frame buffer width pixel */
+#define SCL_R2_LNSIZE		REG_SCLR2_H_SIZE, 0x1FFF0000, 16 /* line width pixel */
+
+/* REG_SCLR2_CROP,0x50 */
+#define SCL_R2_HCROP		REG_SCLR2_CROP, 0x1FFF, 0
+#define SCL_R2_VCROP		REG_SCLR2_CROP, 0x1FFF0000, 16
+
+/* REG_ALFA_MD,0x54 */
+#define SCL_ALPHA_SRC		REG_ALFA_MD, 0x3, 0	/* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */
+#define SCL_ALPHA_DST		REG_ALFA_MD, 0x300, 8 	/* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */
+#define SCL_ALPHA_SWAP		REG_ALFA_MD, 0x10000, 16 /* 0-(alpha,1-alpha),1:(1-alpha,alpha) */
+
+/* REG_ALFA_FXD,0x58 */
+#define SCL_ALPHA_SRC_FIXED	REG_ALFA_FXD, 0xFF, 0
+#define SCL_ALPHA_DST_FIXED	REG_ALFA_FXD, 0xFF00, 8
+
+/* REG_ALFA_COLORKEY,0x5C */
+#define SCL_ALPHA_COLORKEY_ENABLE REG_ALFA_COLORKEY, BIT0, 0
+#define SCL_ALPHA_COLORKEY_FROM	REG_ALFA_COLORKEY, BIT8, 8	/* 0-RMIF1,1-RMIF2 */
+#define SCL_ALPHA_COLORKEY_COMP	REG_ALFA_COLORKEY, 0x30000, 16	/* 0-888,1-777,2-666,3-555 */
+#define SCL_ALPHA_COLORKEY_MODE	REG_ALFA_COLORKEY, 0x7000000, 24 /* (Non-Hit,Hit):0/1-(alpha,alpha),
+									2-(alpha,pix1),3-(pix1,alpha),4-(alpha,pix2),
+									5-(pix2,alpha),6-(pix1,pix2),7-(pix2,pix1) */
+
+/* REG_ALFA_COLORKEY_RGB,0x60 */
+#define SCL_ALPHA_COLORKEY_R	REG_ALFA_COLORKEY_RGB, 0xFF, 0
+#define SCL_ALPHA_COLORKEY_G	REG_ALFA_COLORKEY_RGB, 0xFF00, 8
+#define SCL_ALPHA_COLORKEY_B	REG_ALFA_COLORKEY_RGB, 0xFF0000, 16
+
+/* REG_SCL_VXWIDTH,0x70 */
+#define SCL_VXWIDTH		REG_SCL_VXWIDTH, 0x1FFF, 0
+#define SCL_DST_VXWIDTH		REG_SCL_VXWIDTH, 0x1FFF0000, 16
+
+/* REG_SCL_SCLUP_EN,0x74 */
+#define SCL_VSCLUP_ENABLE	REG_SCL_SCLUP_EN, BIT16, 16
+#define SCL_HSCLUP_ENABLE	REG_SCL_SCLUP_EN, BIT0, 0
+
+/* REG_SCL_VSCALE1,0x78 */
+#define SCL_V_SUBSTEP		REG_SCL_VSCALE1, 0x1FFF0000, 16
+#define SCL_V_THR		REG_SCL_VSCALE1, 0x1FFF, 0
+
+/* REG_SCL_VSCALE2,0x7c */
+#define SCL_V_STEP		REG_SCL_VSCALE2, 0x1FFF0000, 16
+#define SCL_V_I_SUBSTEPCNT	REG_SCL_VSCALE2, 0x1FFF, 0
+
+/* REG_SCL_VSCALE3,0x80 */
+#define SCL_V_I_STEPCNT		REG_SCL_VSCALE3, 0x1FFFF, 0
+
+/* REG_SCL_HSCALE1,0x84 */
+#define SCL_H_SUBSTEP		REG_SCL_HSCALE1, 0x1FFF0000, 16
+#define SCL_H_THR		REG_SCL_HSCALE1, 0x1FFF, 0
+
+/* REG_SCL_HSCALE2,0x88 */
+#define SCL_H_STEP		REG_SCL_HSCALE2, 0x1FFF0000, 16
+#define SCL_H_I_SUBSTEPCNT	REG_SCL_HSCALE2, 0x1FFF, 0
+
+/* REG_SCL_HSCALE3,0x8c */
+#define SCL_H_I_STEPCNT		REG_SCL_HSCALE3, 0x1FFFF, 0
+
+/* REG_SCLR_REQ_NUM,0x90 */
+#define SCL_R_C_REQ_NUM		REG_SCLR_REQ_NUM, 0xFF, 0
+#define SCL_R_Y_REQ_NUM		REG_SCLR_REQ_NUM, 0xFF00, 8
+
+/* REG_SCL_SCLDW,0x94 */
+#define SCL_SCLDW_METHOD	REG_SCL_SCLDW, BIT0, 0	/* (VPU path, scale dn) 0 - bilinear mode, quality better */
+
+/* REG_SCL_426_SW,0x98 */
+#define SCL_426_SW		REG_SCL_426_SW, BIT0, 0	/* 1-follow 426, 0-437 */
+
+/* REG_SCL_VBYPASS,0x9C */
+#define SCL_VBYPASS		REG_SCL_VBYPASS, BIT0, 0
+
+/* SCL_TG */
+/* REG_SCL_TG_CTL,0xa0 */
+#define SCL_ONESHOT_ENABLE	REG_SCL_TG_CTL, BIT24, 24 /* sacling complete will set SCL tg enable to 0 */
+#define SCL_TG_RDCYC		REG_SCL_TG_CTL, 0xFF0000, 16
+#define SCL_TG_WATCHDOG_ENABLE	REG_SCL_TG_CTL, BIT8, 8
+#define SCL_TG_ERR_OFF		REG_SCL_TG_CTL, BIT4, 4	/* disable TG_EN whtn tg timeout */
+#define SCL_TG_ENABLE		REG_SCL_TG_CTL, BIT0, 0
+
+/* REG_SCL_TG_TOTAL,0xa4 */
+#define SCL_TG_V_ALLLINE	REG_SCL_TG_TOTAL, 0x1FFF0000, 16
+#define SCL_TG_H_ALLPIXEL	REG_SCL_TG_TOTAL, 0x1FFF, 0
+
+/* REG_SCL_TG_V_ACTIVE,0xa8 */
+#define SCL_TG_V_ACTEND		REG_SCL_TG_V_ACTIVE, 0x1FFF0000, 16
+#define SCL_TG_V_ACTBG		REG_SCL_TG_V_ACTIVE, 0xFF, 0
+ 
+/* REG_SCL_TG_H_ACTIVE,0xac */
+#define SCL_TG_H_ACTEND		REG_SCL_TG_H_ACTIVE, 0x1FFF0000, 16
+#define SCL_TG_H_ACTBG		REG_SCL_TG_H_ACTIVE, 0x3FF, 0
+
+/* REG_SCL_TG_VBI,0xb0 */
+#define SCL_TG_PVBI		REG_SCL_TG_VBI, 0x1F00, 8
+#define SCL_TG_VBIE		REG_SCL_TG_VBI, 0x7F, 0
+
+/* REG_SCL_TG_WATCHDOG,0xb4 */
+#define SCL_TG_WATCHDOG_VALUE	REG_SCL_TG_WATCHDOG, 0xFFFFFFFF, 0
+
+/* REG_SCL_TG_STS,0xb8 */
+#define SCL_INTSTS_TGERR	REG_SCL_TG_STS, BIT0, 0
+
+/* REG_SCL_TG_GOVW,0xbc */
+#define SCL_TG_GOVWTG_ENABLE	REG_SCL_TG_GOVW, BIT0, 0
+
+/* SCLR */
+/* REG_SCL_MIF_CTL,0xc0 */
+#define SCLR_COLBAR_INVERSION	REG_SCLR_CTL, BIT26, 26
+#define SCLR_COLBAR_MODE	REG_SCLR_CTL, BIT25, 25
+#define SCLR_COLBAR_ENABLE	REG_SCLR_CTL, BIT24, 24
+#define SCLR_TAR_DISP_FMT	REG_SCLR_CTL, BIT16, 16	/*0:Frame, 1:Field */
+#define SCLR_MEDIAFMT_H264	REG_SCLR_CTL, BIT12, 12	/*0:MPEG, 1:H264 */
+#define SCLR_COLFMT_RGB		REG_SCLR_CTL, BIT11, 11	/*0:YCbCr, 1:RGB32 */
+#define SCLR_COLFMT_YUV		REG_SCLR_CTL, 0x600, 9	/*0:422,1:420,2:444*/
+#define SCLR_SRC_DISP_FMT	REG_SCLR_CTL, BIT8, 8	/*420C 0:Frame, 1:Field */
+#define SCLR_RGB_MODE		REG_SCLR_CTL, 0x30, 4	/*0:YC,1:RGB565,3:RGB32 */
+#define SCLR_MIF_ENABLE		REG_SCLR_CTL, BIT0, 0	/*0:Disable, 1:Enable */
+
+/* REG_SCLR_YSA,0xc4 */
+
+/* REG_SCLR_CSA,0xc8 */
+
+/* REG_SCLR_H_SIZE,0xcc */
+#define SCLR_YPXLWID		REG_SCLR_H_SIZE, 0x1FFF0000, 16
+#define SCLR_YBUFWID		REG_SCLR_H_SIZE, 0x1FFF, 0
+
+/* REG_SCLR_CROP,0xd0 */
+#define SCLR_VCROP		REG_SCLR_CROP, 0x1FFF0000, 16
+#define SCLR_HCROP		REG_SCLR_CROP, 0x1FFF, 0
+
+/* REG_SCLR_FIFO_CTL,0xd4 (W:0xf4) */
+#define SCLR_INTSTS_R2MIFERR	REG_SCLR_FIFO_CTL, BIT9, 9
+#define SCLR_INTSTS_R1MIFERR	REG_SCLR_FIFO_CTL, BIT8, 8
+#define SCLR_FIFO_THR		REG_SCLR_FIFO_CTL, 0xF, 0
+
+/* SCL_W */
+/* REG_SCLW_CTL,0xe0 */
+#define SCLW_COLFMT_RGB		REG_SCLW_CTL, BIT9, 9 /* 0-YC,1-RGB32 */
+#define SCLW_COLFMT_YUV		REG_SCLW_CTL, BIT8, 8 /* 0-444,1-422 */
+#define SCLW_MIF_ENABLE		REG_SCLW_CTL, BIT0, 0
+
+/* REG_SCLW_YSA,0xe4 */
+
+/* REG_SCLW_CSA,0xe8 */
+
+/* REG_SCLW_Y_TIME,0xec */
+#define SCLW_YPXLWID		REG_SCLW_Y_TIME, 0x1FFF0000, 16
+#define SCLW_YBUFWID		REG_SCLW_Y_TIME, 0x1FFF, 0
+
+/* REG_SCLW_C_TIME,0xf0 */
+#define SCLW_CPXLWID		REG_SCLW_C_TIME, 0xFFF0000, 16
+#define SCLW_CBUFWID		REG_SCLW_C_TIME, 0x1FFF, 0
+
+/* REG_SCLW_FF_CTL,0xf4 (R:0xd4) */
+#define SCLW_INTSTS_MIFRGBERR	REG_SCLW_FF_CTL, BIT16, 16
+#define SCLW_INTSTS_MIFYERR	REG_SCLW_FF_CTL, BIT8, 8
+#define SCLW_INTSTS_MIFCERR	REG_SCLW_FF_CTL, BIT0, 0
+
+/* REG_SCLW_INT,0xf8 */
+#define SCLW_INT_TGERR_ENABLE	REG_SCLW_INT, BIT16, 16
+#define SCLW_INT_R1MIF_ENABLE	REG_SCLW_INT, BIT9, 9
+#define SCLW_INT_R2MIF_ENABLE	REG_SCLW_INT, BIT8, 8
+#define SCLW_INT_WMIFRGB_ENABLE	REG_SCLW_INT, BIT2, 2
+#define SCLW_INT_WMIFYERR_ENABLE REG_SCLW_INT, BIT1, 1
+#define SCLW_INT_WMIFCERR_ENABLE REG_SCLW_INT, BIT0, 0
+
+/* REG_SCL_TRUE_BILINEAR,0xfc */
+#define SCL_BILINEAR_H		REG_SCL_TRUE_BILINEAR, BIT0, 0
+#define SCL_BILINEAR_V		REG_SCL_TRUE_BILINEAR, BIT8, 8
+
+/* SCL Base2 */
+/* REG_SCL_CSC_CTL,0x00 */
+#define SCL_CSC_ENABLE		REG_SCL_CSC_CTL, BIT16, 16
+#define SCL_CSC_CLAMP_ENABLE	REG_SCL_CSC_CTL, BIT8, 8 /* clamp to 16-235 */
+#define SCL_CSC_MODE		REG_SCL_CSC_CTL, BIT0, 0 /* 0-RGB2YC,1-YC2RGB */
+
+/* REG_SCL_CSC1,0x04 */
+/* REG_SCL_CSC2,0x08 */
+/* REG_SCL_CSC3,0x0c */
+/* REG_SCL_CSC4,0x10 */
+/* REG_SCL_CSC5,0x14 */
+/* REG_SCL_CSC6,0x18 */
+
+/* REG_SCL_ARGB_ALPHA,0x1C */
+#define SCL_FIXED_ALPHA_ENABLE	REG_SCL_ARGB_ALPHA, BIT0, 0
+#define SCL_FIXED_ALPHA_DATA	REG_SCL_ARGB_ALPHA, 0xFF00, 8
+
+/* REG_SCL_IGS,0x20 */
+#define SCL_IGS_MODE		REG_SCL_IGS, 0x3, 0 /* 0-888,1-555,2-666,3-565 */
+
+/* REG_SCL_R2_CSC,0x24 */
+#define SCL_R2_CSC_MODE		REG_SCL_R2_CSC, BIT0, 0	/* 0-CCIR/ITU-601 */
+#define SCL_R2_CSC_CLAMP_EN	REG_SCL_R2_CSC, BIT8, 8	/* 0-direct,1-16-235 */
+#define SCL_R2_CSC_EN		REG_SCL_R2_CSC, BIT16, 16
+
+/* REG_SCL_R2_CSC1,0x28 */
+/* REG_SCL_R2_CSC2,0x2C */
+/* REG_SCL_R2_CSC3,0x30 */
+/* REG_SCL_R2_CSC4,0x34 */
+/* REG_SCL_R2_CSC5,0x38 */
+/* REG_SCL_R2_CSC6,0x3C */
+
+/* REG_SCL_RECURSIVE_MODE,0xA0 */
+#define SCL_RECURSIVE_H		REG_SCL_RECURSIVE_MODE, BIT0, 0
+#define SCL_RECURSIVE_V		REG_SCL_RECURSIVE_MODE, BIT8, 8
+
+/* REG_SCL_FIELD_MODE,0xC0 */
+#define SCL_DEBLOCK_ENABLE	REG_SCL_FIELD_MODE, BIT0, 0
+#define SCL_FIELD_DEFLICKER	REG_SCL_FIELD_MODE, BIT1, 1
+#define SCL_FRAME_DEFLICKER	REG_SCL_FIELD_MODE, BIT2, 2
+
+/* REG_SCL_DBLK_THRESHOLD,0xC4 */
+#define SCL_1ST_LAYER_BOUNDARY	REG_SCL_DBLK_THRESHOLD, 0xFF, 0
+#define SCL_2ND_LAYER_BOUNDARY	REG_SCL_DBLK_THRESHOLD, 0xFF00, 8
+
+/* REG_SCL_FIELD_FLICKER,0xC8 */
+#define SCL_FIELD_FILTER_CONDITION	REG_SCL_FIELD_FLICKER, BIT0, 0	/* 0-up or down,1-up and down */
+#define SCL_FIELD_FILTER_Y_THD		REG_SCL_FIELD_FLICKER, 0xFF00, 8
+#define SCL_FIELD_FILTER_C_THD		REG_SCL_FIELD_FLICKER, 0xFF0000, 16
+
+/* REG_SCL_FRAME_FLICKER,0xCC */
+#define SCL_FRAME_FILTER_RGB		REG_SCL_FRAME_FLICKER, BIT0, 0 	/* 0-Y,1-RGB */
+#define SCL_FRAME_FILTER_SAMPLER	REG_SCL_FRAME_FLICKER, 0x1F00, 8 /* 2^x */
+#define SCL_FR_FILTER_SCENE_CHG_THD	REG_SCL_FRAME_FLICKER, 0xFF0000, 16
+
+/* REG_SCL_READCYC_1T,0xD0 */
+#define SCL_READCYC_1T		REG_SCL_READCYC_1T,BIT0,0
+#endif /* WMT_SCL_REG_H */
diff --git a/drivers/video/wmt/hw/wmt-vpp-hw.h b/drivers/video/wmt/hw/wmt-vpp-hw.h
new file mode 100644
index 00000000..b3d3a7ad
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-vpp-hw.h
@@ -0,0 +1,135 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-vpp-hw.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_VPP_HW_H
+#define WMT_VPP_HW_H
+
+/*-------------------- EXPORTED PRIVATE CONSTANTS ----------------------------*/
+/*
+* Product ID / Project ID
+* 84xx series: 8420/3300, 8430/3357, 8435/3437
+* 85xx series: 8500/3400, 8510/3426, 8520/3429
+*/
+/* 84xx series, (1-100) with VDU & DSP */
+#define VIA_PID_8420	10	/* 3300 */
+#define VIA_PID_8430	12	/* 3357 */
+#define WMT_PID_8435	14	/* 3437 */
+#define WMT_PID_8440	16	/* 3451 */
+#define WMT_PID_8425	18	/* 3429 */
+#define WMT_PID_8710	20	/* 3445 */
+#define WMT_PID_8950	22	/* 3481 */
+#define WMT_PID_8980	24	/* 3498 */
+
+/* 85xx series, (101-200) */
+#define VIA_PID_8500	110	/* 3400 */
+#define WMT_PID_8505	111
+#define WMT_PID_8510	112	/* 3426* */
+
+#define WMT_PID_8950_A	1
+
+/* current pid */
+#define WMT_CUR_PID	WMT_PID_8980
+#define WMT_SUB_PID	0
+
+/* #define WMT_SUB_PID	WMT_PID_8505 */
+#ifndef WMT_SUB_PID
+	#define WMT_SUB_PID	0
+#endif
+
+/* VPP interrupt map to irq */
+#define VPP_IRQ_SCL_FINISH	IRQ_VPP_IRQ0
+#define VPP_IRQ_SCL		IRQ_VPP_IRQ1
+#define VPP_IRQ_SCL444_TG	IRQ_VPP_IRQ2
+#define VPP_IRQ_VPPM		IRQ_VPP_IRQ3
+#define VPP_IRQ_GOVW_TG		IRQ_VPP_IRQ4
+#define VPP_IRQ_GOVW		IRQ_VPP_IRQ5
+#define VPP_IRQ_GOVM		IRQ_VPP_IRQ6
+#define VPP_IRQ_GE		IRQ_VPP_IRQ7
+#define VPP_IRQ_GOVRH_TG	IRQ_VPP_IRQ8	/* PVBI or VBIS or VBIE */
+#define VPP_IRQ_DVO		IRQ_VPP_IRQ9
+#define VPP_IRQ_VID		IRQ_VPP_IRQ10
+#define VPP_IRQ_GOVR		IRQ_VPP_IRQ11	/* underrun & mif */
+#define VPP_IRQ_GOVRSD_TG	IRQ_VPP_IRQ12
+#define VPP_IRQ_VPU		IRQ_VPP_IRQ13
+#define VPP_IRQ_VPU_TG		IRQ_VPP_IRQ14
+#define VPP_IRQ_HDMI_CP		IRQ_VPP_IRQ15
+#define VPP_IRQ_HDMI_HPDH	IRQ_VPP_IRQ16
+#define VPP_IRQ_HDMI_HPDL	IRQ_VPP_IRQ17
+#define VPP_IRQ_GOVR_0		IRQ_VPP_IRQ18
+#define VPP_IRQ_GOVR_2		IRQ_VPP_IRQ19
+#define VPP_IRQ_CEC		IRQ_VPP_IRQ20
+#define VPP_IRQ_GOVR2_0		IRQ_VPP_IRQ21
+#define VPP_IRQ_GOVR2		IRQ_VPP_IRQ22
+#define VPP_IRQ_GOVR2_2		IRQ_VPP_IRQ23
+#define VPP_IRQ_DVO2		IRQ_VPP_IRQ24
+#define VPP_IRQ_GOVR2_TG	IRQ_VPP_IRQ25
+
+/* DVI I2C */
+#define VPP_DVI_I2C_BIT		0x80 /* use sw id that can vary */
+#define VPP_DVI_I2C_SW_BIT 	0x10 /* hw or sw i2c */
+#define VPP_DVI_I2C_ID_MASK 	0x1F
+#define VPP_DVI_I2C_ID 		(VPP_DVI_I2C_BIT + 0x1)
+#define VPP_DVI_EDID_ID 	(VPP_DVI_I2C_SW_BIT + 0x1) /* DVO EDID use sw i2c bus 1 */
+
+/* vout */
+#define VPP_VOUT_INFO_NUM 	2 /* linux fb or govr number */
+
+#define VPP_VOUT_NUM 		2
+#define VPP_VOUT_ALL 		0xFFFFFFFF
+#define VPP_VOUT_NUM_HDMI 	0
+#define VPP_VOUT_NUM_LVDS 	1
+#define VPP_VOUT_NUM_DVI 	1
+
+#define WMT_FTBLK_VOUT_DVI
+#define WMT_FTBLK_VOUT_HDMI
+#define WMT_FTBLK_VOUT_LVDS
+
+/* hw parameter */
+#define VPP_VOINT_NO 		0  /* DVO external board interrupt use GPIOxx */
+#define VPP_UBOOT_COLFMT 	VDO_COL_FMT_RGB_565
+#define VPP_FB_ADDR_ALIGN 	64
+#define VPP_FB_WIDTH_ALIGN 	64   /* hw should 4 byte align,android
+	framework 8 byte align modify by aksenxu VPU need 64bytes alignment
+	you need modify FramebufferNativeWindow::FramebufferNativeWindow
+	in android framework together */
+#define VPP_GOVR_DVO_DELAY_24 	0x4036
+#define VPP_GOVR_DVO_DELAY_12 	0x120
+
+/*-------------------- DEPENDENCY -------------------------------------*/
+#ifdef __KERNEL__
+#ifndef CONFIG_WMT_HDMI
+#undef WMT_FTBLK_VOUT_HDMI
+#endif
+#endif
+
+#include "wmt-vpp-reg.h"
+#include "wmt-govrh-reg.h"
+#include "wmt-lvds-reg.h"
+#ifdef WMT_FTBLK_VOUT_HDMI
+#include "wmt-hdmi-reg.h"
+#endif
+#ifndef CFG_LOADER
+#include "wmt-scl-reg.h"
+#include "wmt-cec-reg.h"
+#endif
+#endif /* WMT_VPP_HW_H */
diff --git a/drivers/video/wmt/hw/wmt-vpp-reg.h b/drivers/video/wmt/hw/wmt-vpp-reg.h
new file mode 100644
index 00000000..ffd02b87
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-vpp-reg.h
@@ -0,0 +1,98 @@
+/*++
+ * linux/drivers/video/wmt/register/wm8710/wmt-vpp-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_VPP_REG_H
+#define WMT_VPP_REG_H
+
+#define REG_VPP_BEGIN		(VPP_BASE_ADDR + 0x00)
+#define REG_VPP_INTSTS		(VPP_BASE_ADDR + 0x04)
+#define REG_VPP_INTEN		(VPP_BASE_ADDR + 0x08)
+#define REG_VPP_WATCH_SEL	(VPP_BASE_ADDR + 0x0c)
+#define REG_VPP_SWRST1_SEL	(VPP_BASE_ADDR + 0x10)
+#define REG_VPP_SWRST2_SEL	(VPP_BASE_ADDR + 0x14)
+#define REG_VPP_DAC_SEL		(VPP_BASE_ADDR + 0x18)
+#define REG_VPP_SWRST3_SEL	(VPP_BASE_ADDR + 0x1C)
+#define REG_VPP_SSCG		(VPP_BASE_ADDR + 0x20)
+#define REG_VPP_END		(VPP_BASE_ADDR + 0x28)
+
+/* REG_VPP_INTSTS,0x04 */
+#define VPP_GE_INTSTS_TG	REG_VPP_INTSTS, BIT20, 20
+#define VPP_SCL_INTSTS_VBIE	REG_VPP_INTSTS, BIT18, 18
+#define VPP_SCL_INTSTS_VBIS	REG_VPP_INTSTS, BIT17, 17
+#define VPP_SCL_INTSTS_PVBI	REG_VPP_INTSTS, BIT16, 16
+#define VPP_SCL_INTSTS		REG_VPP_INTSTS, 0x70000, 16
+#define VPP_GOVRH2_INTSTS_VBIE	REG_VPP_INTSTS, BIT14, 14
+#define VPP_GOVRH2_INTSTS_VBIS	REG_VPP_INTSTS, BIT13, 13
+#define VPP_GOVRH2_INTSTS_PVBI	REG_VPP_INTSTS, BIT12, 12
+#define VPP_GOVRH2_INTSTS	REG_VPP_INTSTS, 0x7000, 12
+#define VPP_GOVRH_INTSTS_VBIE	REG_VPP_INTSTS, BIT10, 10
+#define VPP_GOVRH_INTSTS_VBIS	REG_VPP_INTSTS, BIT9, 9
+#define VPP_GOVRH_INTSTS_PVBI	REG_VPP_INTSTS, BIT8, 8
+#define VPP_GOVRH_INTSTS	REG_VPP_INTSTS, 0x700, 8
+
+/* REG_VPP_INTEN,0x08 */
+#define VPP_GE_INTEN_TG		REG_VPP_INTEN, BIT20, 20
+#define VPP_SCL_INTEN_VBIE	REG_VPP_INTEN, BIT18, 18
+#define VPP_SCL_INTEN_VBIS	REG_VPP_INTEN, BIT17, 17
+#define VPP_SCL_INTEN_PVBI	REG_VPP_INTEN, BIT16, 16
+#define VPP_SCL_INTEN		REG_VPP_INTEN, 0x70000, 16
+#define VPP_GOVRH2_INTEN_VBIE	REG_VPP_INTEN, BIT14, 14
+#define VPP_GOVRH2_INTEN_VBIS	REG_VPP_INTEN, BIT13, 13
+#define VPP_GOVRH2_INTEN_PVBI	REG_VPP_INTEN, BIT12, 12
+#define VPP_GOVRH2_INTEN	REG_VPP_INTEN, 0x7000, 12
+#define VPP_GOVRH_INTEN_VBIE	REG_VPP_INTEN, BIT10, 10
+#define VPP_GOVRH_INTEN_VBIS	REG_VPP_INTEN, BIT9, 9
+#define VPP_GOVRH_INTEN_PVBI	REG_VPP_INTEN, BIT8, 8
+#define VPP_GOVRH_INTEN		REG_VPP_INTEN, 0x700, 8
+
+/* REG_VPP_WATCH_SEL,0x0c */
+#define VPP_WATCH_SEL		REG_VPP_WATCH_SEL, 0x1F, 0
+
+/* REG_VPP_SWRST1_SEL,0x10 */
+#define VPP_GE_RST		REG_VPP_SWRST1_SEL, BIT16, 16
+#define VPP_VID_RST		REG_VPP_SWRST1_SEL, BIT8, 8
+#define VPP_SCL_RST		REG_VPP_SWRST1_SEL, BIT0, 0
+
+/* REG_VPP_SWRST2_SEL,0x14 */
+#define VPP_CEC_RST		REG_VPP_SWRST2_SEL, BIT12,12
+#define VPP_DVO2_RST		REG_VPP_SWRST2_SEL, BIT9, 9
+#define VPP_DVO_RST		REG_VPP_SWRST2_SEL, BIT8, 8
+#define VPP_LVDS_RST		REG_VPP_SWRST2_SEL, BIT4, 4
+#define VPP_GOVRH_RST		REG_VPP_SWRST2_SEL, BIT0, 0
+
+/* REG_VPP_DAC_SEL,0x18 */
+#define VPP_DAC_SEL		REG_VPP_DAC_SEL, BIT0, 0
+#define VPP_DAC_SEL_TV		1
+#define VPP_DAC_SEL_VGA		0
+
+/* REG_VPP_SWRST3_SEL,0x1C */
+#define VPP_HDMI_RST		REG_VPP_SWRST3_SEL, BIT0, 0
+#define VPP_DDC_RST		REG_VPP_SWRST3_SEL, BIT8, 8
+#define VPP_HDMI2_RST		REG_VPP_SWRST3_SEL, BIT16, 16
+
+/* REG_VPP_SSCG,0x20 */
+#define VPP_SSCG_DISABLE	REG_VPP_SSCG, BIT0, 0
+#define VPP_CSI_ACT_LANE_SELECT	REG_VPP_SSCG, BIT8, 8 /* 0-Active lane 0/1, 1-Active lane 2/3 */
+
+#endif /* WMT_VPP_REG_H */
+