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author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
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committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /arch/unicore32/mm/Kconfig | |
parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
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Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'arch/unicore32/mm/Kconfig')
-rw-r--r-- | arch/unicore32/mm/Kconfig | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/unicore32/mm/Kconfig b/arch/unicore32/mm/Kconfig new file mode 100644 index 00000000..5f77fb3c --- /dev/null +++ b/arch/unicore32/mm/Kconfig @@ -0,0 +1,50 @@ +comment "Processor Type" + +# Select CPU types depending on the architecture selected. This selects +# which CPUs we support in the kernel image, and the compiler instruction +# optimiser behaviour. + +config CPU_UCV2 + def_bool y + +comment "Processor Features" + +config CPU_ICACHE_DISABLE + bool "Disable I-Cache (I-bit)" + help + Say Y here to disable the processor instruction cache. Unless + you have a reason not to or are unsure, say N. + +config CPU_DCACHE_DISABLE + bool "Disable D-Cache (D-bit)" + help + Say Y here to disable the processor data cache. Unless + you have a reason not to or are unsure, say N. + +config CPU_DCACHE_WRITETHROUGH + bool "Force write through D-cache" + help + Say Y here to use the data cache in writethrough mode. Unless you + specifically require this or are unsure, say N. + +config CPU_DCACHE_LINE_DISABLE + bool "Disable D-cache line ops" + default y + help + Say Y here to disable the data cache line operations. + +config CPU_TLB_SINGLE_ENTRY_DISABLE + bool "Disable TLB single entry ops" + default y + help + Say Y here to disable the TLB single entry operations. + +config SWIOTLB + def_bool y + +config IOMMU_HELPER + def_bool SWIOTLB + +config NEED_SG_DMA_LENGTH + def_bool SWIOTLB + |