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author | Srikant Patnaik | 2015-01-13 15:08:24 +0530 |
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committer | Srikant Patnaik | 2015-01-13 15:08:24 +0530 |
commit | 97327692361306d1e6259021bc425e32832fdb50 (patch) | |
tree | fe9088f3248ec61e24f404f21b9793cb644b7f01 /arch/sh/cchips | |
parent | 2d05a8f663478a44e088d122e0d62109bbc801d0 (diff) | |
parent | a3a8b90b61e21be3dde9101c4e86c881e0f06210 (diff) | |
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dirty fix to merging
Diffstat (limited to 'arch/sh/cchips')
-rw-r--r-- | arch/sh/cchips/Kconfig | 45 | ||||
-rw-r--r-- | arch/sh/cchips/hd6446x/Makefile | 3 | ||||
-rw-r--r-- | arch/sh/cchips/hd6446x/hd64461.c | 126 |
3 files changed, 174 insertions, 0 deletions
diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig new file mode 100644 index 00000000..a5ab2ecc --- /dev/null +++ b/arch/sh/cchips/Kconfig @@ -0,0 +1,45 @@ +menu "Companion Chips" + +config HD6446X_SERIES + bool + +choice + prompt "HD6446x options" + depends on HD6446X_SERIES + default HD64461 + +config HD64461 + bool "Hitachi HD64461 companion chip support" + ---help--- + The Hitachi HD64461 provides an interface for + the SH7709 CPU, supporting a LCD controller, + CRT color controller, IrDA up to 4 Mbps, and a + PCMCIA controller supporting 2 slots. + + More information is available at + <http://semiconductor.hitachi.com/windowsce/superh/sld013.htm>. + + Say Y if you want support for the HD64461. + Otherwise, say N. + +endchoice + +# These will also be split into the Kconfig's below +config HD64461_IRQ + int "HD64461 IRQ" + depends on HD64461 + default "36" + help + The default setting of the HD64461 IRQ is 36. + + Do not change this unless you know what you are doing. + +config HD64461_ENABLER + bool "HD64461 PCMCIA enabler" + depends on HD64461 + help + Say Y here if you want to enable PCMCIA support + via the HD64461 companion chip. + Otherwise, say N. + +endmenu diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile new file mode 100644 index 00000000..59c34833 --- /dev/null +++ b/arch/sh/cchips/hd6446x/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_HD64461) += hd64461.o + +ccflags-y := -Werror diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c new file mode 100644 index 00000000..eb4ea4d4 --- /dev/null +++ b/arch/sh/cchips/hd6446x/hd64461.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2000 YAEGASHI Takeshi + * Hitachi HD64461 companion chip support + */ + +#include <linux/sched.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <asm/irq.h> +#include <asm/hd64461.h> + +/* This belongs in cpu specific */ +#define INTC_ICR1 0xA4140010UL + +static void hd64461_mask_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + unsigned short nimr; + unsigned short mask = 1 << (irq - HD64461_IRQBASE); + + nimr = __raw_readw(HD64461_NIMR); + nimr |= mask; + __raw_writew(nimr, HD64461_NIMR); +} + +static void hd64461_unmask_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + unsigned short nimr; + unsigned short mask = 1 << (irq - HD64461_IRQBASE); + + nimr = __raw_readw(HD64461_NIMR); + nimr &= ~mask; + __raw_writew(nimr, HD64461_NIMR); +} + +static void hd64461_mask_and_ack_irq(struct irq_data *data) +{ + hd64461_mask_irq(data); + +#ifdef CONFIG_HD64461_ENABLER + if (data->irq == HD64461_IRQBASE + 13) + __raw_writeb(0x00, HD64461_PCC1CSCR); +#endif +} + +static struct irq_chip hd64461_irq_chip = { + .name = "HD64461-IRQ", + .irq_mask = hd64461_mask_irq, + .irq_mask_ack = hd64461_mask_and_ack_irq, + .irq_unmask = hd64461_unmask_irq, +}; + +static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + unsigned short intv = __raw_readw(HD64461_NIRR); + unsigned int ext_irq = HD64461_IRQBASE; + + intv &= (1 << HD64461_IRQ_NUM) - 1; + + for (; intv; intv >>= 1, ext_irq++) { + if (!(intv & 1)) + continue; + + generic_handle_irq(ext_irq); + } +} + +int __init setup_hd64461(void) +{ + int i, nid = cpu_to_node(boot_cpu_data); + + if (!MACH_HD64461) + return 0; + + printk(KERN_INFO + "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n", + HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE, + HD64461_IRQBASE + 15); + +/* Should be at processor specific part.. */ +#if defined(CONFIG_CPU_SUBTYPE_SH7709) + __raw_writew(0x2240, INTC_ICR1); +#endif + __raw_writew(0xffff, HD64461_NIMR); + + /* IRQ 80 -> 95 belongs to HD64461 */ + for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) { + unsigned int irq; + + irq = create_irq_nr(i, nid); + if (unlikely(irq == 0)) { + pr_err("%s: failed hooking irq %d for HD64461\n", + __func__, i); + return -EBUSY; + } + + if (unlikely(irq != i)) { + pr_err("%s: got irq %d but wanted %d, bailing.\n", + __func__, irq, i); + destroy_irq(irq); + return -EINVAL; + } + + irq_set_chip_and_handler(i, &hd64461_irq_chip, + handle_level_irq); + } + + irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); + irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); + +#ifdef CONFIG_HD64461_ENABLER + printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); + __raw_writeb(0x4c, HD64461_PCC1CSCIER); + __raw_writeb(0x00, HD64461_PCC1CSCR); +#endif + + return 0; +} + +module_init(setup_hd64461); |