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author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
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committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /arch/sh/boards/mach-se/7722/irq.c | |
parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
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Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'arch/sh/boards/mach-se/7722/irq.c')
-rw-r--r-- | arch/sh/boards/mach-se/7722/irq.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c new file mode 100644 index 00000000..aac92f21 --- /dev/null +++ b/arch/sh/boards/mach-se/7722/irq.c @@ -0,0 +1,83 @@ +/* + * linux/arch/sh/boards/se/7722/irq.c + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7722 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <asm/irq.h> +#include <asm/io.h> +#include <mach-se/mach/se7722.h> + +unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, }; + +static void disable_se7722_irq(struct irq_data *data) +{ + unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); + __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK); +} + +static void enable_se7722_irq(struct irq_data *data) +{ + unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data); + __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK); +} + +static struct irq_chip se7722_irq_chip __read_mostly = { + .name = "SE7722-FPGA", + .irq_mask = disable_se7722_irq, + .irq_unmask = enable_se7722_irq, +}; + +static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + unsigned short intv = __raw_readw(IRQ01_STS); + unsigned int ext_irq = 0; + + intv &= (1 << SE7722_FPGA_IRQ_NR) - 1; + + for (; intv; intv >>= 1, ext_irq++) { + if (!(intv & 1)) + continue; + + generic_handle_irq(se7722_fpga_irq[ext_irq]); + } +} + +/* + * Initialize IRQ setting + */ +void __init init_se7722_IRQ(void) +{ + int i, irq; + + __raw_writew(0, IRQ01_MASK); /* disable all irqs */ + __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ + + for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { + irq = create_irq(); + if (irq < 0) + return; + se7722_fpga_irq[i] = irq; + + irq_set_chip_and_handler_name(se7722_fpga_irq[i], + &se7722_irq_chip, + handle_level_irq, + "level"); + + irq_set_chip_data(se7722_fpga_irq[i], (void *)i); + } + + irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux); + irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + + irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux); + irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); +} |