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| author | Srikant Patnaik | 2015-01-13 15:08:24 +0530 |
|---|---|---|
| committer | Srikant Patnaik | 2015-01-13 15:08:24 +0530 |
| commit | 97327692361306d1e6259021bc425e32832fdb50 (patch) | |
| tree | fe9088f3248ec61e24f404f21b9793cb644b7f01 /arch/m68k/platform/520x/config.c | |
| parent | 2d05a8f663478a44e088d122e0d62109bbc801d0 (diff) | |
| parent | a3a8b90b61e21be3dde9101c4e86c881e0f06210 (diff) | |
| download | FOSSEE-netbook-kernel-source-97327692361306d1e6259021bc425e32832fdb50.tar.gz FOSSEE-netbook-kernel-source-97327692361306d1e6259021bc425e32832fdb50.tar.bz2 FOSSEE-netbook-kernel-source-97327692361306d1e6259021bc425e32832fdb50.zip | |
dirty fix to merging
Diffstat (limited to 'arch/m68k/platform/520x/config.c')
| -rw-r--r-- | arch/m68k/platform/520x/config.c | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c new file mode 100644 index 00000000..09df4b89 --- /dev/null +++ b/arch/m68k/platform/520x/config.c @@ -0,0 +1,87 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/520x/config.c + * + * Copyright (C) 2005, Freescale (www.freescale.com) + * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com) + * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/init.h> +#include <linux/io.h> +#include <asm/machdep.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> +#include <asm/mcfuart.h> + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + +static void __init m520x_qspi_init(void) +{ + u16 par; + /* setup Port QS for QSPI with gpio CS control */ + writeb(0x3f, MCF_GPIO_PAR_QSPI); + /* make U1CTS and U2RTS gpio for cs_control */ + par = readw(MCF_GPIO_PAR_UART); + par &= 0x00ff; + writew(par, MCF_GPIO_PAR_UART); +} + +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ + +/***************************************************************************/ + +static void __init m520x_uarts_init(void) +{ + u16 par; + u8 par2; + + /* UART0 and UART1 GPIO pin setup */ + par = readw(MCF_GPIO_PAR_UART); + par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0; + par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1; + writew(par, MCF_GPIO_PAR_UART); + + /* UART1 GPIO pin setup */ + par2 = readb(MCF_GPIO_PAR_FECI2C); + par2 &= ~0x0F; + par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | + MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; + writeb(par2, MCF_GPIO_PAR_FECI2C); +} + +/***************************************************************************/ + +static void __init m520x_fec_init(void) +{ + u8 v; + + /* Set multi-function pins to ethernet mode */ + v = readb(MCF_GPIO_PAR_FEC); + writeb(v | 0xf0, MCF_GPIO_PAR_FEC); + + v = readb(MCF_GPIO_PAR_FECI2C); + writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + m520x_uarts_init(); + m520x_fec_init(); +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + m520x_qspi_init(); +#endif +} + +/***************************************************************************/ |