diff options
| author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
|---|---|---|
| committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
| commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
| tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /arch/blackfin/include/asm/cplbinit.h | |
| parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
| download | FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.gz FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.bz2 FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.zip | |
Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'arch/blackfin/include/asm/cplbinit.h')
| -rw-r--r-- | arch/blackfin/include/asm/cplbinit.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h new file mode 100644 index 00000000..f315c83a --- /dev/null +++ b/arch/blackfin/include/asm/cplbinit.h @@ -0,0 +1,66 @@ +/* + * Common CPLB definitions for CPLB init + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_CPLBINIT_H__ +#define __ASM_CPLBINIT_H__ + +#include <asm/blackfin.h> +#include <asm/cplb.h> +#include <linux/threads.h> + +#ifdef CONFIG_CPLB_SWITCH_TAB_L1 +# define PDT_ATTR __attribute__((l1_data)) +#else +# define PDT_ATTR +#endif + +struct cplb_entry { + unsigned long data, addr; +}; + +struct cplb_boundary { + unsigned long eaddr; /* End of this region. */ + unsigned long data; /* CPLB data value. */ +}; + +extern struct cplb_boundary dcplb_bounds[]; +extern struct cplb_boundary icplb_bounds[]; +extern int dcplb_nr_bounds, icplb_nr_bounds; + +extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; +extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; +extern int first_switched_icplb; +extern int first_switched_dcplb; + +extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[]; +extern int nr_dcplb_prot[], nr_cplb_flush[]; + +#ifdef CONFIG_MPU + +extern int first_mask_dcplb; + +extern int page_mask_order; +extern int page_mask_nelts; + +extern unsigned long *current_rwx_mask[NR_CPUS]; + +extern void flush_switched_cplbs(unsigned int); +extern void set_mask_dcplbs(unsigned long *, unsigned int); + +extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); + +#endif /* CONFIG_MPU */ + +extern void bfin_icache_init(struct cplb_entry *icplb_tbl); +extern void bfin_dcache_init(struct cplb_entry *icplb_tbl); + +#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) +extern void generate_cplb_tables_all(void); +extern void generate_cplb_tables_cpu(unsigned int cpu); +#endif +#endif |