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authorSrikant Patnaik2015-01-13 15:08:24 +0530
committerSrikant Patnaik2015-01-13 15:08:24 +0530
commit97327692361306d1e6259021bc425e32832fdb50 (patch)
treefe9088f3248ec61e24f404f21b9793cb644b7f01 /arch/arm/plat-orion/include/plat/pcie.h
parent2d05a8f663478a44e088d122e0d62109bbc801d0 (diff)
parenta3a8b90b61e21be3dde9101c4e86c881e0f06210 (diff)
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dirty fix to merging
Diffstat (limited to 'arch/arm/plat-orion/include/plat/pcie.h')
-rw-r--r--arch/arm/plat-orion/include/plat/pcie.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h
new file mode 100644
index 00000000..fe5b9e86
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/pcie.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/plat-orion/include/plat/pcie.h
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PCIE_H
+#define __PLAT_PCIE_H
+
+struct pci_bus;
+
+u32 orion_pcie_dev_id(void __iomem *base);
+u32 orion_pcie_rev(void __iomem *base);
+int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_x4_mode(void __iomem *base);
+int orion_pcie_get_local_bus_nr(void __iomem *base);
+void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
+void orion_pcie_reset(void __iomem *base);
+void orion_pcie_setup(void __iomem *base);
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val);
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 val);
+
+
+#endif