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author | Srikant Patnaik | 2015-01-13 15:08:24 +0530 |
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committer | Srikant Patnaik | 2015-01-13 15:08:24 +0530 |
commit | 97327692361306d1e6259021bc425e32832fdb50 (patch) | |
tree | fe9088f3248ec61e24f404f21b9793cb644b7f01 /arch/arm/mach-omap2/clock44xx.h | |
parent | 2d05a8f663478a44e088d122e0d62109bbc801d0 (diff) | |
parent | a3a8b90b61e21be3dde9101c4e86c881e0f06210 (diff) | |
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dirty fix to merging
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock44xx.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h new file mode 100644 index 00000000..287a46f7 --- /dev/null +++ b/arch/arm/mach-omap2/clock44xx.h @@ -0,0 +1,20 @@ +/* + * OMAP4 clock function prototypes and macros + * + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H + +/* + * OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is + * set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM + * vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters") + */ +#define OMAP4430_REGM4XEN_MULT 4 + +int omap4xxx_clk_init(void); + +#endif |