Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

10 files changed, 0 insertions, 1529 deletions

diff --git a/ANDROID_3.4.5/include/linux/amba/bus.h b/ANDROID_3.4.5/include/linux/amba/bus.h
deleted file mode 100644
index 8d54f794..00000000
--- a/ANDROID_3.4.5/include/linux/amba/bus.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- *  linux/include/amba/bus.h
- *
- *  This device type deals with ARM PrimeCells and anything else that
- *  presents a proper CID (0xB105F00D) at the end of the I/O register
- *  region or that is derived from a PrimeCell.
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_AMBA_H
-#define ASMARM_AMBA_H
-
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/mod_devicetable.h>
-#include <linux/err.h>
-#include <linux/resource.h>
-#include <linux/regulator/consumer.h>
-
-#define AMBA_NR_IRQS	2
-#define AMBA_CID	0xb105f00d
-
-struct clk;
-
-struct amba_device {
-	struct device		dev;
-	struct resource		res;
-	struct clk		*pclk;
-	u64			dma_mask;
-	unsigned int		periphid;
-	unsigned int		irq[AMBA_NR_IRQS];
-};
-
-struct amba_driver {
-	struct device_driver	drv;
-	int			(*probe)(struct amba_device *, const struct amba_id *);
-	int			(*remove)(struct amba_device *);
-	void			(*shutdown)(struct amba_device *);
-	int			(*suspend)(struct amba_device *, pm_message_t);
-	int			(*resume)(struct amba_device *);
-	const struct amba_id	*id_table;
-};
-
-enum amba_vendor {
-	AMBA_VENDOR_ARM = 0x41,
-	AMBA_VENDOR_ST = 0x80,
-};
-
-extern struct bus_type amba_bustype;
-
-#define to_amba_device(d)	container_of(d, struct amba_device, dev)
-
-#define amba_get_drvdata(d)	dev_get_drvdata(&d->dev)
-#define amba_set_drvdata(d,p)	dev_set_drvdata(&d->dev, p)
-
-int amba_driver_register(struct amba_driver *);
-void amba_driver_unregister(struct amba_driver *);
-struct amba_device *amba_device_alloc(const char *, resource_size_t, size_t);
-void amba_device_put(struct amba_device *);
-int amba_device_add(struct amba_device *, struct resource *);
-int amba_device_register(struct amba_device *, struct resource *);
-void amba_device_unregister(struct amba_device *);
-struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
-int amba_request_regions(struct amba_device *, const char *);
-void amba_release_regions(struct amba_device *);
-
-#define amba_pclk_enable(d)	\
-	(IS_ERR((d)->pclk) ? 0 : clk_enable((d)->pclk))
-
-#define amba_pclk_disable(d)	\
-	do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0)
-
-/* Some drivers don't use the struct amba_device */
-#define AMBA_CONFIG_BITS(a) (((a) >> 24) & 0xff)
-#define AMBA_REV_BITS(a) (((a) >> 20) & 0x0f)
-#define AMBA_MANF_BITS(a) (((a) >> 12) & 0xff)
-#define AMBA_PART_BITS(a) ((a) & 0xfff)
-
-#define amba_config(d)	AMBA_CONFIG_BITS((d)->periphid)
-#define amba_rev(d)	AMBA_REV_BITS((d)->periphid)
-#define amba_manf(d)	AMBA_MANF_BITS((d)->periphid)
-#define amba_part(d)	AMBA_PART_BITS((d)->periphid)
-
-#define __AMBA_DEV(busid, data, mask)				\
-	{							\
-		.coherent_dma_mask = mask,			\
-		.init_name = busid,				\
-		.platform_data = data,				\
-	}
-
-/*
- * APB devices do not themselves have the ability to address memory,
- * so DMA masks should be zero (much like USB peripheral devices.)
- * The DMA controller DMA masks should be used instead (much like
- * USB host controllers in conventional PCs.)
- */
-#define AMBA_APB_DEVICE(name, busid, id, base, irqs, data)	\
-struct amba_device name##_device = {				\
-	.dev = __AMBA_DEV(busid, data, 0),			\
-	.res = DEFINE_RES_MEM(base, SZ_4K),			\
-	.irq = irqs,						\
-	.periphid = id,						\
-}
-
-/*
- * AHB devices are DMA capable, so set their DMA masks
- */
-#define AMBA_AHB_DEVICE(name, busid, id, base, irqs, data)	\
-struct amba_device name##_device = {				\
-	.dev = __AMBA_DEV(busid, data, ~0ULL),			\
-	.res = DEFINE_RES_MEM(base, SZ_4K),			\
-	.dma_mask = ~0ULL,					\
-	.irq = irqs,						\
-	.periphid = id,						\
-}
-
-/*
- * module_amba_driver() - Helper macro for drivers that don't do anything
- * special in module init/exit.  This eliminates a lot of boilerplate.  Each
- * module may only use this macro once, and calling it replaces module_init()
- * and module_exit()
- */
-#define module_amba_driver(__amba_drv) \
-	module_driver(__amba_drv, amba_driver_register, amba_driver_unregister)
-
-#endif
diff --git a/ANDROID_3.4.5/include/linux/amba/clcd.h b/ANDROID_3.4.5/include/linux/amba/clcd.h
deleted file mode 100644
index e82e3ee2..00000000
--- a/ANDROID_3.4.5/include/linux/amba/clcd.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
- *
- * David A Rusling
- *
- * Copyright (C) 2001 ARM Limited
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-#include <linux/fb.h>
-
-/*
- * CLCD Controller Internal Register addresses
- */
-#define CLCD_TIM0		0x00000000
-#define CLCD_TIM1 		0x00000004
-#define CLCD_TIM2 		0x00000008
-#define CLCD_TIM3 		0x0000000c
-#define CLCD_UBAS 		0x00000010
-#define CLCD_LBAS 		0x00000014
-
-#define CLCD_PL110_IENB		0x00000018
-#define CLCD_PL110_CNTL		0x0000001c
-#define CLCD_PL110_STAT		0x00000020
-#define CLCD_PL110_INTR 	0x00000024
-#define CLCD_PL110_UCUR		0x00000028
-#define CLCD_PL110_LCUR		0x0000002C
-
-#define CLCD_PL111_CNTL		0x00000018
-#define CLCD_PL111_IENB		0x0000001c
-#define CLCD_PL111_RIS		0x00000020
-#define CLCD_PL111_MIS		0x00000024
-#define CLCD_PL111_ICR		0x00000028
-#define CLCD_PL111_UCUR		0x0000002c
-#define CLCD_PL111_LCUR		0x00000030
-
-#define CLCD_PALL 		0x00000200
-#define CLCD_PALETTE		0x00000200
-
-#define TIM2_CLKSEL		(1 << 5)
-#define TIM2_IVS		(1 << 11)
-#define TIM2_IHS		(1 << 12)
-#define TIM2_IPC		(1 << 13)
-#define TIM2_IOE		(1 << 14)
-#define TIM2_BCD		(1 << 26)
-
-#define CNTL_LCDEN		(1 << 0)
-#define CNTL_LCDBPP1		(0 << 1)
-#define CNTL_LCDBPP2		(1 << 1)
-#define CNTL_LCDBPP4		(2 << 1)
-#define CNTL_LCDBPP8		(3 << 1)
-#define CNTL_LCDBPP16		(4 << 1)
-#define CNTL_LCDBPP16_565	(6 << 1)
-#define CNTL_LCDBPP16_444	(7 << 1)
-#define CNTL_LCDBPP24		(5 << 1)
-#define CNTL_LCDBW		(1 << 4)
-#define CNTL_LCDTFT		(1 << 5)
-#define CNTL_LCDMONO8		(1 << 6)
-#define CNTL_LCDDUAL		(1 << 7)
-#define CNTL_BGR		(1 << 8)
-#define CNTL_BEBO		(1 << 9)
-#define CNTL_BEPO		(1 << 10)
-#define CNTL_LCDPWR		(1 << 11)
-#define CNTL_LCDVCOMP(x)	((x) << 12)
-#define CNTL_LDMAFIFOTIME	(1 << 15)
-#define CNTL_WATERMARK		(1 << 16)
-
-enum {
-	/* individual formats */
-	CLCD_CAP_RGB444		= (1 << 0),
-	CLCD_CAP_RGB5551	= (1 << 1),
-	CLCD_CAP_RGB565		= (1 << 2),
-	CLCD_CAP_RGB888		= (1 << 3),
-	CLCD_CAP_BGR444		= (1 << 4),
-	CLCD_CAP_BGR5551	= (1 << 5),
-	CLCD_CAP_BGR565		= (1 << 6),
-	CLCD_CAP_BGR888		= (1 << 7),
-
-	/* connection layouts */
-	CLCD_CAP_444		= CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
-	CLCD_CAP_5551		= CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
-	CLCD_CAP_565		= CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
-	CLCD_CAP_888		= CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
-
-	/* red/blue ordering */
-	CLCD_CAP_RGB		= CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
-				  CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
-	CLCD_CAP_BGR		= CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
-				  CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
-
-	CLCD_CAP_ALL		= CLCD_CAP_BGR | CLCD_CAP_RGB,
-};
-
-struct clcd_panel {
-	struct fb_videomode	mode;
-	signed short		width;	/* width in mm */
-	signed short		height;	/* height in mm */
-	u32			tim2;
-	u32			tim3;
-	u32			cntl;
-	u32			caps;
-	unsigned int		bpp:8,
-				fixedtimings:1,
-				grayscale:1;
-	unsigned int		connector;
-};
-
-struct clcd_regs {
-	u32			tim0;
-	u32			tim1;
-	u32			tim2;
-	u32			tim3;
-	u32			cntl;
-	unsigned long		pixclock;
-};
-
-struct clcd_fb;
-
-/*
- * the board-type specific routines
- */
-struct clcd_board {
-	const char *name;
-
-	/*
-	 * Optional.  Hardware capability flags.
-	 */
-	u32	caps;
-
-	/*
-	 * Optional.  Check whether the var structure is acceptable
-	 * for this display.
-	 */
-	int	(*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
-
-	/*
-	 * Compulsory.  Decode fb->fb.var into regs->*.  In the case of
-	 * fixed timing, set regs->* to the register values required.
-	 */
-	void	(*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
-
-	/*
-	 * Optional.  Disable any extra display hardware.
-	 */
-	void	(*disable)(struct clcd_fb *);
-
-	/*
-	 * Optional.  Enable any extra display hardware.
-	 */
-	void	(*enable)(struct clcd_fb *);
-
-	/*
-	 * Setup platform specific parts of CLCD driver
-	 */
-	int	(*setup)(struct clcd_fb *);
-
-	/*
-	 * mmap the framebuffer memory
-	 */
-	int	(*mmap)(struct clcd_fb *, struct vm_area_struct *);
-
-	/*
-	 * Remove platform specific parts of CLCD driver
-	 */
-	void	(*remove)(struct clcd_fb *);
-};
-
-struct amba_device;
-struct clk;
-
-/* this data structure describes each frame buffer device we find */
-struct clcd_fb {
-	struct fb_info		fb;
-	struct amba_device	*dev;
-	struct clk		*clk;
-	struct clcd_panel	*panel;
-	struct clcd_board	*board;
-	void			*board_data;
-	void __iomem		*regs;
-	u16			off_ienb;
-	u16			off_cntl;
-	u32			clcd_cntl;
-	u32			cmap[16];
-	bool			clk_enabled;
-};
-
-static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
-{
-	struct fb_var_screeninfo *var = &fb->fb.var;
-	u32 val, cpl;
-
-	/*
-	 * Program the CLCD controller registers and start the CLCD
-	 */
-	val = ((var->xres / 16) - 1) << 2;
-	val |= (var->hsync_len - 1) << 8;
-	val |= (var->right_margin - 1) << 16;
-	val |= (var->left_margin - 1) << 24;
-	regs->tim0 = val;
-
-	val = var->yres;
-	if (fb->panel->cntl & CNTL_LCDDUAL)
-		val /= 2;
-	val -= 1;
-	val |= (var->vsync_len - 1) << 10;
-	val |= var->lower_margin << 16;
-	val |= var->upper_margin << 24;
-	regs->tim1 = val;
-
-	val = fb->panel->tim2;
-	val |= var->sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
-	val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
-
-	cpl = var->xres_virtual;
-	if (fb->panel->cntl & CNTL_LCDTFT)	  /* TFT */
-		/* / 1 */;
-	else if (!var->grayscale)		  /* STN color */
-		cpl = cpl * 8 / 3;
-	else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
-		cpl /= 8;
-	else					  /* STN monochrome, 4bit */
-		cpl /= 4;
-
-	regs->tim2 = val | ((cpl - 1) << 16);
-
-	regs->tim3 = fb->panel->tim3;
-
-	val = fb->panel->cntl;
-	if (var->grayscale)
-		val |= CNTL_LCDBW;
-
-	if (fb->panel->caps && fb->board->caps &&
-	    var->bits_per_pixel >= 16) {
-		/*
-		 * if board and panel supply capabilities, we can support
-		 * changing BGR/RGB depending on supplied parameters
-		 */
-		if (var->red.offset == 0)
-			val &= ~CNTL_BGR;
-		else
-			val |= CNTL_BGR;
-	}
-
-	switch (var->bits_per_pixel) {
-	case 1:
-		val |= CNTL_LCDBPP1;
-		break;
-	case 2:
-		val |= CNTL_LCDBPP2;
-		break;
-	case 4:
-		val |= CNTL_LCDBPP4;
-		break;
-	case 8:
-		val |= CNTL_LCDBPP8;
-		break;
-	case 16:
-		/*
-		 * PL110 cannot choose between 5551 and 565 modes in its
-		 * control register.  It is possible to use 565 with
-		 * custom external wiring.
-		 */
-		if (amba_part(fb->dev) == 0x110 ||
-		    var->green.length == 5)
-			val |= CNTL_LCDBPP16;
-		else if (var->green.length == 6)
-			val |= CNTL_LCDBPP16_565;
-		else
-			val |= CNTL_LCDBPP16_444;
-		break;
-	case 32:
-		val |= CNTL_LCDBPP24;
-		break;
-	}
-
-	regs->cntl = val;
-	regs->pixclock = var->pixclock;
-}
-
-static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
-{
-	var->xres_virtual = var->xres = (var->xres + 15) & ~15;
-	var->yres_virtual = var->yres = (var->yres + 1) & ~1;
-
-#define CHECK(e,l,h) (var->e < l || var->e > h)
-	if (CHECK(right_margin, (5+1), 256) ||	/* back porch */
-	    CHECK(left_margin, (5+1), 256) ||	/* front porch */
-	    CHECK(hsync_len, (5+1), 256) ||
-	    var->xres > 4096 ||
-	    var->lower_margin > 255 ||		/* back porch */
-	    var->upper_margin > 255 ||		/* front porch */
-	    var->vsync_len > 32 ||
-	    var->yres > 1024)
-		return -EINVAL;
-#undef CHECK
-
-	/* single panel mode: PCD = max(PCD, 1) */
-	/* dual panel mode: PCD = max(PCD, 5) */
-
-	/*
-	 * You can't change the grayscale setting, and
-	 * we can only do non-interlaced video.
-	 */
-	if (var->grayscale != fb->fb.var.grayscale ||
-	    (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
-		return -EINVAL;
-
-#define CHECK(e) (var->e != fb->fb.var.e)
-	if (fb->panel->fixedtimings &&
-	    (CHECK(xres)		||
-	     CHECK(yres)		||
-	     CHECK(bits_per_pixel)	||
-	     CHECK(pixclock)		||
-	     CHECK(left_margin)		||
-	     CHECK(right_margin)	||
-	     CHECK(upper_margin)	||
-	     CHECK(lower_margin)	||
-	     CHECK(hsync_len)		||
-	     CHECK(vsync_len)		||
-	     CHECK(sync)))
-		return -EINVAL;
-#undef CHECK
-
-	var->nonstd = 0;
-	var->accel_flags = 0;
-
-	return 0;
-}
diff --git a/ANDROID_3.4.5/include/linux/amba/kmi.h b/ANDROID_3.4.5/include/linux/amba/kmi.h
deleted file mode 100644
index a39e5be7..00000000
--- a/ANDROID_3.4.5/include/linux/amba/kmi.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware/amba_kmi.h
- *
- *  Internal header file for AMBA KMI ports
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *
- * ---------------------------------------------------------------------------
- *  From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
- *  Reference Manual - ARM DDI 0143B - see http://www.arm.com/
- * ---------------------------------------------------------------------------
- */
-#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
-#define ASM_ARM_HARDWARE_AMBA_KMI_H
-
-/*
- * KMI control register:
- *  KMICR_TYPE       0 = PS2/AT mode, 1 = No line control bit mode
- *  KMICR_RXINTREN   1 = enable RX interrupts
- *  KMICR_TXINTREN   1 = enable TX interrupts
- *  KMICR_EN         1 = enable KMI
- *  KMICR_FD         1 = force KMI data low
- *  KMICR_FC         1 = force KMI clock low
- */
-#define KMICR		(KMI_BASE + 0x00)
-#define KMICR_TYPE		(1 << 5)
-#define KMICR_RXINTREN		(1 << 4)
-#define KMICR_TXINTREN		(1 << 3)
-#define KMICR_EN		(1 << 2)
-#define KMICR_FD		(1 << 1)
-#define KMICR_FC		(1 << 0)
-
-/*
- * KMI status register:
- *  KMISTAT_TXEMPTY  1 = transmitter register empty
- *  KMISTAT_TXBUSY   1 = currently sending data
- *  KMISTAT_RXFULL   1 = receiver register ready to be read
- *  KMISTAT_RXBUSY   1 = currently receiving data
- *  KMISTAT_RXPARITY parity of last databyte received
- *  KMISTAT_IC       current level of KMI clock input
- *  KMISTAT_ID       current level of KMI data input
- */
-#define KMISTAT		(KMI_BASE + 0x04)
-#define KMISTAT_TXEMPTY		(1 << 6)
-#define KMISTAT_TXBUSY		(1 << 5)
-#define KMISTAT_RXFULL		(1 << 4)
-#define KMISTAT_RXBUSY		(1 << 3)
-#define KMISTAT_RXPARITY	(1 << 2)
-#define KMISTAT_IC		(1 << 1)
-#define KMISTAT_ID		(1 << 0)
-
-/*
- * KMI data register
- */
-#define KMIDATA		(KMI_BASE + 0x08)
-
-/*
- * KMI clock divisor: to generate 8MHz internal clock
- *  div = (ref / 8MHz) - 1; 0 <= div <= 15
- */
-#define KMICLKDIV	(KMI_BASE + 0x0c)
-
-/*
- * KMI interrupt register:
- *  KMIIR_TXINTR     1 = transmit interrupt asserted
- *  KMIIR_RXINTR     1 = receive interrupt asserted
- */
-#define KMIIR		(KMI_BASE + 0x10)
-#define KMIIR_TXINTR		(1 << 1)
-#define KMIIR_RXINTR		(1 << 0)
-
-/*
- * The size of the KMI primecell
- */
-#define KMI_SIZE	(0x100)
-
-#endif
diff --git a/ANDROID_3.4.5/include/linux/amba/mmci.h b/ANDROID_3.4.5/include/linux/amba/mmci.h
deleted file mode 100644
index 9d1d9caf..00000000
--- a/ANDROID_3.4.5/include/linux/amba/mmci.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- *  include/linux/amba/mmci.h
- */
-#ifndef AMBA_MMCI_H
-#define AMBA_MMCI_H
-
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-#include <linux/mmc/sdio_func.h>
-
-struct embedded_sdio_data {
-        struct sdio_cis cis;
-        struct sdio_cccr cccr;
-        struct sdio_embedded_func *funcs;
-        int num_funcs;
-};
-
-
-/*
- * These defines is places here due to access is needed from machine
- * configuration files. The ST Micro version does not have ROD and
- * reuse the voltage registers for direction settings.
- */
-#define MCI_ST_DATA2DIREN	(1 << 2)
-#define MCI_ST_CMDDIREN		(1 << 3)
-#define MCI_ST_DATA0DIREN	(1 << 4)
-#define MCI_ST_DATA31DIREN	(1 << 5)
-#define MCI_ST_FBCLKEN		(1 << 7)
-#define MCI_ST_DATA74DIREN	(1 << 8)
-
-/* Just some dummy forwarding */
-struct dma_chan;
-
-/**
- * struct mmci_platform_data - platform configuration for the MMCI
- * (also known as PL180) block.
- * @f_max: the maximum operational frequency for this host in this
- * platform configuration. When this is specified it takes precedence
- * over the module parameter for the same frequency.
- * @ocr_mask: available voltages on the 4 pins from the block, this
- * is ignored if a regulator is used, see the MMC_VDD_* masks in
- * mmc/host.h
- * @ios_handler: a callback function to act on specfic ios changes,
- * used for example to control a levelshifter
- * mask into a value to be binary (or set some other custom bits
- * in MMCIPWR) or:ed and written into the MMCIPWR register of the
- * block.  May also control external power based on the power_mode.
- * @status: if no GPIO read function was given to the block in
- * gpio_wp (below) this function will be called to determine
- * whether a card is present in the MMC slot or not
- * @gpio_wp: read this GPIO pin to see if the card is write protected
- * @gpio_cd: read this GPIO pin to detect card insertion
- * @cd_invert: true if the gpio_cd pin value is active low
- * @capabilities: the capabilities of the block as implemented in
- * this platform, signify anything MMC_CAP_* from mmc/host.h
- * @capabilities2: more capabilities, MMC_CAP2_* from mmc/host.h
- * @sigdir: a bit field indicating for what bits in the MMC bus the host
- * should enable signal direction indication.
- * @dma_filter: function used to select an appropriate RX and TX
- * DMA channel to be used for DMA, if and only if you're deploying the
- * generic DMA engine
- * @dma_rx_param: parameter passed to the DMA allocation
- * filter in order to select an appropriate RX channel. If
- * there is a bidirectional RX+TX channel, then just specify
- * this and leave dma_tx_param set to NULL
- * @dma_tx_param: parameter passed to the DMA allocation
- * filter in order to select an appropriate TX channel. If this
- * is NULL the driver will attempt to use the RX channel as a
- * bidirectional channel
- */
-struct mmci_platform_data {
-	unsigned int f_max;
-	unsigned int ocr_mask;
-	int (*ios_handler)(struct device *, struct mmc_ios *);
-	unsigned int (*status)(struct device *);
-	int	gpio_wp;
-	int	gpio_cd;
-	bool	cd_invert;
-	unsigned long capabilities;
-	unsigned long capabilities2;
-	u32 sigdir;
-	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
-	void *dma_rx_param;
-	void *dma_tx_param;
-	unsigned int status_irq;
-	struct embedded_sdio_data *embedded_sdio;
-	int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
-};
-
-#endif
diff --git a/ANDROID_3.4.5/include/linux/amba/pl022.h b/ANDROID_3.4.5/include/linux/amba/pl022.h
deleted file mode 100644
index 76dd1b19..00000000
--- a/ANDROID_3.4.5/include/linux/amba/pl022.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * include/linux/amba/pl022.h
- *
- * Copyright (C) 2008-2009 ST-Ericsson AB
- * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- *
- * Initial version inspired by:
- *	linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
- * Initial adoption to PL022 by:
- *      Sachin Verma <sachin.verma@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SSP_PL022_H
-#define _SSP_PL022_H
-
-#include <linux/types.h>
-
-/**
- * whether SSP is in loopback mode or not
- */
-enum ssp_loopback {
-	LOOPBACK_DISABLED,
-	LOOPBACK_ENABLED
-};
-
-/**
- * enum ssp_interface - interfaces allowed for this SSP Controller
- * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
- * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
- * interface
- * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
- * interface
- * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
- * &STn8815 only)
- */
-enum ssp_interface {
-	SSP_INTERFACE_MOTOROLA_SPI,
-	SSP_INTERFACE_TI_SYNC_SERIAL,
-	SSP_INTERFACE_NATIONAL_MICROWIRE,
-	SSP_INTERFACE_UNIDIRECTIONAL
-};
-
-/**
- * enum ssp_hierarchy - whether SSP is configured as Master or Slave
- */
-enum ssp_hierarchy {
-	SSP_MASTER,
-	SSP_SLAVE
-};
-
-/**
- * enum ssp_clock_params - clock parameters, to set SSP clock at a
- * desired freq
- */
-struct ssp_clock_params {
-	u8 cpsdvsr; /* value from 2 to 254 (even only!) */
-	u8 scr;	    /* value from 0 to 255 */
-};
-
-/**
- * enum ssp_rx_endian - endianess of Rx FIFO Data
- * this feature is only available in ST versionf of PL022
- */
-enum ssp_rx_endian {
-	SSP_RX_MSB,
-	SSP_RX_LSB
-};
-
-/**
- * enum ssp_tx_endian - endianess of Tx FIFO Data
- */
-enum ssp_tx_endian {
-	SSP_TX_MSB,
-	SSP_TX_LSB
-};
-
-/**
- * enum ssp_data_size - number of bits in one data element
- */
-enum ssp_data_size {
-	SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
-	SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
-	SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
-	SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
-	SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
-	SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
-	SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
-	SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
-	SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
-	SSP_DATA_BITS_31, SSP_DATA_BITS_32
-};
-
-/**
- * enum ssp_mode - SSP mode of operation (Communication modes)
- */
-enum ssp_mode {
-	INTERRUPT_TRANSFER,
-	POLLING_TRANSFER,
-	DMA_TRANSFER
-};
-
-/**
- * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
- * IT: Interrupt fires when _N_ or more elements in RX FIFO.
- */
-enum ssp_rx_level_trig {
-	SSP_RX_1_OR_MORE_ELEM,
-	SSP_RX_4_OR_MORE_ELEM,
-	SSP_RX_8_OR_MORE_ELEM,
-	SSP_RX_16_OR_MORE_ELEM,
-	SSP_RX_32_OR_MORE_ELEM
-};
-
-/**
- * Transmit FIFO watermark level which triggers (IT Interrupt fires
- * when _N_ or more empty locations in TX FIFO)
- */
-enum ssp_tx_level_trig {
-	SSP_TX_1_OR_MORE_EMPTY_LOC,
-	SSP_TX_4_OR_MORE_EMPTY_LOC,
-	SSP_TX_8_OR_MORE_EMPTY_LOC,
-	SSP_TX_16_OR_MORE_EMPTY_LOC,
-	SSP_TX_32_OR_MORE_EMPTY_LOC
-};
-
-/**
- * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
- * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
- * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
- */
-enum ssp_spi_clk_phase {
-	SSP_CLK_FIRST_EDGE,
-	SSP_CLK_SECOND_EDGE
-};
-
-/**
- * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
- * @SSP_CLK_POL_IDLE_LOW: Low inactive level
- * @SSP_CLK_POL_IDLE_HIGH: High inactive level
- */
-enum ssp_spi_clk_pol {
-	SSP_CLK_POL_IDLE_LOW,
-	SSP_CLK_POL_IDLE_HIGH
-};
-
-/**
- * Microwire Conrol Lengths Command size in microwire format
- */
-enum ssp_microwire_ctrl_len {
-	SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
-	SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
-	SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
-	SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
-	SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
-	SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
-	SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
-	SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
-	SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
-	SSP_BITS_31, SSP_BITS_32
-};
-
-/**
- * enum Microwire Wait State
- * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
- * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
- */
-enum ssp_microwire_wait_state {
-	SSP_MWIRE_WAIT_ZERO,
-	SSP_MWIRE_WAIT_ONE
-};
-
-/**
- * enum ssp_duplex - whether Full/Half Duplex on microwire, only
- * available in the ST Micro variant.
- * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
- *     SSPRXD not used
- * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
- *     an input.
- */
-enum ssp_duplex {
-	SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-	SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
-};
-
-/**
- * enum ssp_clkdelay - an optional clock delay on the feedback clock
- * only available in the ST Micro PL023 variant.
- * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
- * slave is sampled directly
- * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
- * a delay of T-dt
- * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
- * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
- * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
- * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
- * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
- * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
- */
-enum ssp_clkdelay {
-	SSP_FEEDBACK_CLK_DELAY_NONE,
-	SSP_FEEDBACK_CLK_DELAY_1T,
-	SSP_FEEDBACK_CLK_DELAY_2T,
-	SSP_FEEDBACK_CLK_DELAY_3T,
-	SSP_FEEDBACK_CLK_DELAY_4T,
-	SSP_FEEDBACK_CLK_DELAY_5T,
-	SSP_FEEDBACK_CLK_DELAY_6T,
-	SSP_FEEDBACK_CLK_DELAY_7T
-};
-
-/**
- * CHIP select/deselect commands
- */
-enum ssp_chip_select {
-	SSP_CHIP_SELECT,
-	SSP_CHIP_DESELECT
-};
-
-
-struct dma_chan;
-/**
- * struct pl022_ssp_master - device.platform_data for SPI controller devices.
- * @num_chipselect: chipselects are used to distinguish individual
- *     SPI slaves, and are numbered from zero to num_chipselects - 1.
- *     each slave has a chipselect signal, but it's common that not
- *     every chipselect is connected to a slave.
- * @enable_dma: if true enables DMA driven transfers.
- * @dma_rx_param: parameter to locate an RX DMA channel.
- * @dma_tx_param: parameter to locate a TX DMA channel.
- * @autosuspend_delay: delay in ms following transfer completion before the
- *     runtime power management system suspends the device. A setting of 0
- *     indicates no delay and the device will be suspended immediately.
- * @rt: indicates the controller should run the message pump with realtime
- *     priority to minimise the transfer latency on the bus.
- */
-struct pl022_ssp_controller {
-	u16 bus_id;
-	u8 num_chipselect;
-	u8 enable_dma:1;
-	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
-	void *dma_rx_param;
-	void *dma_tx_param;
-	int autosuspend_delay;
-	bool rt;
-};
-
-/**
- * struct ssp_config_chip - spi_board_info.controller_data for SPI
- * slave devices, copied to spi_device.controller_data.
- *
- * @lbm: used for test purpose to internally connect RX and TX
- * @iface: Interface type(Motorola, TI, Microwire, Universal)
- * @hierarchy: sets whether interface is master or slave
- * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
- * @clk_freq: Tune freq parameters of SSP(when in master mode)
- * @endian_rx: Endianess of Data in Rx FIFO
- * @endian_tx: Endianess of Data in Tx FIFO
- * @data_size: Width of data element(4 to 32 bits)
- * @com_mode: communication mode: polling, Interrupt or DMA
- * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
- * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
- * @clk_phase: Motorola SPI interface Clock phase
- * @clk_pol: Motorola SPI interface Clock polarity
- * @ctrl_len: Microwire interface: Control length
- * @wait_state: Microwire interface: Wait state
- * @duplex: Microwire interface: Full/Half duplex
- * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
- * before sampling the incoming line
- * @cs_control: function pointer to board-specific function to
- * assert/deassert I/O port to control HW generation of devices chip-select.
- * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph)
- * @dma_config: DMA configuration for SSP controller and peripheral
- */
-struct pl022_config_chip {
-	enum ssp_interface iface;
-	enum ssp_hierarchy hierarchy;
-	bool slave_tx_disable;
-	struct ssp_clock_params clk_freq;
-	enum ssp_mode com_mode;
-	enum ssp_rx_level_trig rx_lev_trig;
-	enum ssp_tx_level_trig tx_lev_trig;
-	enum ssp_microwire_ctrl_len ctrl_len;
-	enum ssp_microwire_wait_state wait_state;
-	enum ssp_duplex duplex;
-	enum ssp_clkdelay clkdelay;
-	void (*cs_control) (u32 control);
-};
-
-#endif /* _SSP_PL022_H */
diff --git a/ANDROID_3.4.5/include/linux/amba/pl061.h b/ANDROID_3.4.5/include/linux/amba/pl061.h
deleted file mode 100644
index fb83c045..00000000
--- a/ANDROID_3.4.5/include/linux/amba/pl061.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <linux/types.h>
-
-/* platform data for the PL061 GPIO driver */
-
-struct pl061_platform_data {
-	/* number of the first GPIO */
-	unsigned	gpio_base;
-
-	/* number of the first IRQ.
-	 * If the IRQ functionality in not desired this must be set to 0.
-	 */
-	unsigned	irq_base;
-
-	u8		directions;	/* startup directions, 1: out, 0: in */
-	u8		values;		/* startup values */
-};
diff --git a/ANDROID_3.4.5/include/linux/amba/pl08x.h b/ANDROID_3.4.5/include/linux/amba/pl08x.h
deleted file mode 100644
index e64ce2cf..00000000
--- a/ANDROID_3.4.5/include/linux/amba/pl08x.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
- *
- * Copyright (C) 2005 ARM Ltd
- * Copyright (C) 2010 ST-Ericsson SA
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * pl08x information required by platform code
- *
- * Please credit ARM.com
- * Documentation: ARM DDI 0196D
- */
-
-#ifndef AMBA_PL08X_H
-#define AMBA_PL08X_H
-
-/* We need sizes of structs from this header */
-#include <linux/dmaengine.h>
-#include <linux/interrupt.h>
-
-struct pl08x_lli;
-struct pl08x_driver_data;
-
-/* Bitmasks for selecting AHB ports for DMA transfers */
-enum {
-	PL08X_AHB1 = (1 << 0),
-	PL08X_AHB2 = (1 << 1)
-};
-
-/**
- * struct pl08x_channel_data - data structure to pass info between
- * platform and PL08x driver regarding channel configuration
- * @bus_id: name of this device channel, not just a device name since
- * devices may have more than one channel e.g. "foo_tx"
- * @min_signal: the minimum DMA signal number to be muxed in for this
- * channel (for platforms supporting muxed signals). If you have
- * static assignments, make sure this is set to the assigned signal
- * number, PL08x have 16 possible signals in number 0 thru 15 so
- * when these are not enough they often get muxed (in hardware)
- * disabling simultaneous use of the same channel for two devices.
- * @max_signal: the maximum DMA signal number to be muxed in for
- * the channel. Set to the same as min_signal for
- * devices with static assignments
- * @muxval: a number usually used to poke into some mux regiser to
- * mux in the signal to this channel
- * @cctl_opt: default options for the channel control register
- * @addr: source/target address in physical memory for this DMA channel,
- * can be the address of a FIFO register for burst requests for example.
- * This can be left undefined if the PrimeCell API is used for configuring
- * this.
- * @circular_buffer: whether the buffer passed in is circular and
- * shall simply be looped round round (like a record baby round
- * round round round)
- * @single: the device connected to this channel will request single DMA
- * transfers, not bursts. (Bursts are default.)
- * @periph_buses: the device connected to this channel is accessible via
- * these buses (use PL08X_AHB1 | PL08X_AHB2).
- */
-struct pl08x_channel_data {
-	char *bus_id;
-	int min_signal;
-	int max_signal;
-	u32 muxval;
-	u32 cctl;
-	dma_addr_t addr;
-	bool circular_buffer;
-	bool single;
-	u8 periph_buses;
-};
-
-/**
- * Struct pl08x_bus_data - information of source or destination
- * busses for a transfer
- * @addr: current address
- * @maxwidth: the maximum width of a transfer on this bus
- * @buswidth: the width of this bus in bytes: 1, 2 or 4
- */
-struct pl08x_bus_data {
-	dma_addr_t addr;
-	u8 maxwidth;
-	u8 buswidth;
-};
-
-/**
- * struct pl08x_phy_chan - holder for the physical channels
- * @id: physical index to this channel
- * @lock: a lock to use when altering an instance of this struct
- * @signal: the physical signal (aka channel) serving this physical channel
- * right now
- * @serving: the virtual channel currently being served by this physical
- * channel
- */
-struct pl08x_phy_chan {
-	unsigned int id;
-	void __iomem *base;
-	spinlock_t lock;
-	int signal;
-	struct pl08x_dma_chan *serving;
-};
-
-/**
- * struct pl08x_sg - structure containing data per sg
- * @src_addr: src address of sg
- * @dst_addr: dst address of sg
- * @len: transfer len in bytes
- * @node: node for txd's dsg_list
- */
-struct pl08x_sg {
-	dma_addr_t src_addr;
-	dma_addr_t dst_addr;
-	size_t len;
-	struct list_head node;
-};
-
-/**
- * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
- * @tx: async tx descriptor
- * @node: node for txd list for channels
- * @dsg_list: list of children sg's
- * @direction: direction of transfer
- * @llis_bus: DMA memory address (physical) start for the LLIs
- * @llis_va: virtual memory address start for the LLIs
- * @cctl: control reg values for current txd
- * @ccfg: config reg values for current txd
- */
-struct pl08x_txd {
-	struct dma_async_tx_descriptor tx;
-	struct list_head node;
-	struct list_head dsg_list;
-	enum dma_transfer_direction direction;
-	dma_addr_t llis_bus;
-	struct pl08x_lli *llis_va;
-	/* Default cctl value for LLIs */
-	u32 cctl;
-	/*
-	 * Settings to be put into the physical channel when we
-	 * trigger this txd.  Other registers are in llis_va[0].
-	 */
-	u32 ccfg;
-};
-
-/**
- * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
- * states
- * @PL08X_CHAN_IDLE: the channel is idle
- * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
- * channel and is running a transfer on it
- * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
- * channel, but the transfer is currently paused
- * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
- * channel to become available (only pertains to memcpy channels)
- */
-enum pl08x_dma_chan_state {
-	PL08X_CHAN_IDLE,
-	PL08X_CHAN_RUNNING,
-	PL08X_CHAN_PAUSED,
-	PL08X_CHAN_WAITING,
-};
-
-/**
- * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
- * @chan: wrappped abstract channel
- * @phychan: the physical channel utilized by this channel, if there is one
- * @phychan_hold: if non-zero, hold on to the physical channel even if we
- * have no pending entries
- * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
- * @name: name of channel
- * @cd: channel platform data
- * @runtime_addr: address for RX/TX according to the runtime config
- * @runtime_direction: current direction of this channel according to
- * runtime config
- * @pend_list: queued transactions pending on this channel
- * @at: active transaction on this channel
- * @lock: a lock for this channel data
- * @host: a pointer to the host (internal use)
- * @state: whether the channel is idle, paused, running etc
- * @slave: whether this channel is a device (slave) or for memcpy
- * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
- * channels. Fill with 'true' if peripheral should be flow controller. Direction
- * will be selected at Runtime.
- * @waiting: a TX descriptor on this channel which is waiting for a physical
- * channel to become available
- */
-struct pl08x_dma_chan {
-	struct dma_chan chan;
-	struct pl08x_phy_chan *phychan;
-	int phychan_hold;
-	struct tasklet_struct tasklet;
-	char *name;
-	const struct pl08x_channel_data *cd;
-	dma_addr_t src_addr;
-	dma_addr_t dst_addr;
-	u32 src_cctl;
-	u32 dst_cctl;
-	enum dma_transfer_direction runtime_direction;
-	struct list_head pend_list;
-	struct pl08x_txd *at;
-	spinlock_t lock;
-	struct pl08x_driver_data *host;
-	enum pl08x_dma_chan_state state;
-	bool slave;
-	bool device_fc;
-	struct pl08x_txd *waiting;
-};
-
-/**
- * struct pl08x_platform_data - the platform configuration for the PL08x
- * PrimeCells.
- * @slave_channels: the channels defined for the different devices on the
- * platform, all inclusive, including multiplexed channels. The available
- * physical channels will be multiplexed around these signals as they are
- * requested, just enumerate all possible channels.
- * @get_signal: request a physical signal to be used for a DMA transfer
- * immediately: if there is some multiplexing or similar blocking the use
- * of the channel the transfer can be denied by returning less than zero,
- * else it returns the allocated signal number
- * @put_signal: indicate to the platform that this physical signal is not
- * running any DMA transfer and multiplexing can be recycled
- * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
- * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
- */
-struct pl08x_platform_data {
-	const struct pl08x_channel_data *slave_channels;
-	unsigned int num_slave_channels;
-	struct pl08x_channel_data memcpy_channel;
-	int (*get_signal)(struct pl08x_dma_chan *);
-	void (*put_signal)(struct pl08x_dma_chan *);
-	u8 lli_buses;
-	u8 mem_buses;
-};
-
-#ifdef CONFIG_AMBA_PL08X
-bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
-#else
-static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
-{
-	return false;
-}
-#endif
-
-#endif	/* AMBA_PL08X_H */
diff --git a/ANDROID_3.4.5/include/linux/amba/pl093.h b/ANDROID_3.4.5/include/linux/amba/pl093.h
deleted file mode 100644
index 2983e367..00000000
--- a/ANDROID_3.4.5/include/linux/amba/pl093.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* linux/amba/pl093.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * AMBA PL093 SSMC (synchronous static memory controller)
- *  See DDI0236.pdf (r0p4) for more details
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define SMB_BANK(x)	((x) * 0x20) /* each bank control set is 0x20 apart */
-
-/* Offsets for SMBxxxxRy registers */
-
-#define SMBIDCYR	(0x00)
-#define SMBWSTRDR	(0x04)
-#define SMBWSTWRR	(0x08)
-#define SMBWSTOENR	(0x0C)
-#define SMBWSTWENR	(0x10)
-#define SMBCR		(0x14)
-#define SMBSR		(0x18)
-#define SMBWSTBRDR	(0x1C)
-
-/* Masks for SMB registers */
-#define IDCY_MASK	(0xf)
-#define WSTRD_MASK	(0xf)
-#define WSTWR_MASK	(0xf)
-#define WSTOEN_MASK	(0xf)
-#define WSTWEN_MASK	(0xf)
-
-/* Notes from datasheet:
- *	WSTOEN <= WSTRD
- *	WSTWEN <= WSTWR
- *
- * WSTOEN is not used with nWAIT
- */
-
-/* SMBCR bit definitions */
-#define SMBCR_BIWRITEEN		(1 << 21)
-#define SMBCR_ADDRVALIDWRITEEN	(1 << 20)
-#define SMBCR_SYNCWRITE		(1 << 17)
-#define SMBCR_BMWRITE		(1 << 16)
-#define SMBCR_WRAPREAD		(1 << 14)
-#define SMBCR_BIREADEN		(1 << 13)
-#define SMBCR_ADDRVALIDREADEN	(1 << 12)
-#define SMBCR_SYNCREAD		(1 << 9)
-#define SMBCR_BMREAD		(1 << 8)
-#define SMBCR_SMBLSPOL		(1 << 6)
-#define SMBCR_WP		(1 << 3)
-#define SMBCR_WAITEN		(1 << 2)
-#define SMBCR_WAITPOL		(1 << 1)
-#define SMBCR_RBLE		(1 << 0)
-
-#define SMBCR_BURSTLENWRITE_MASK	(3 << 18)
-#define SMBCR_BURSTLENWRITE_4		(0 << 18)
-#define SMBCR_BURSTLENWRITE_8		(1 << 18)
-#define SMBCR_BURSTLENWRITE_RESERVED	(2 << 18)
-#define SMBCR_BURSTLENWRITE_CONTINUOUS	(3 << 18)
-
-#define SMBCR_BURSTLENREAD_MASK		(3 << 10)
-#define SMBCR_BURSTLENREAD_4		(0 << 10)
-#define SMBCR_BURSTLENREAD_8		(1 << 10)
-#define SMBCR_BURSTLENREAD_16		(2 << 10)
-#define SMBCR_BURSTLENREAD_CONTINUOUS	(3 << 10)
-
-#define SMBCR_MW_MASK			(3 << 4)
-#define SMBCR_MW_8BIT			(0 << 4)
-#define SMBCR_MW_16BIT			(1 << 4)
-#define SMBCR_MW_M32BIT			(2 << 4)
-
-/* SSMC status registers */
-#define SSMCCSR		(0x200)
-#define SSMCCR		(0x204)
-#define SSMCITCR	(0x208)
-#define SSMCITIP	(0x20C)
-#define SSMCITIOP	(0x210)
diff --git a/ANDROID_3.4.5/include/linux/amba/pl330.h b/ANDROID_3.4.5/include/linux/amba/pl330.h
deleted file mode 100644
index fe93758e..00000000
--- a/ANDROID_3.4.5/include/linux/amba/pl330.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* linux/include/linux/amba/pl330.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *	Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef	__AMBA_PL330_H_
-#define	__AMBA_PL330_H_
-
-#include <linux/dmaengine.h>
-
-struct dma_pl330_platdata {
-	/*
-	 * Number of valid peripherals connected to DMAC.
-	 * This may be different from the value read from
-	 * CR0, as the PL330 implementation might have 'holes'
-	 * in the peri list or the peri could also be reached
-	 * from another DMAC which the platform prefers.
-	 */
-	u8 nr_valid_peri;
-	/* Array of valid peripherals */
-	u8 *peri_id;
-	/* Operational capabilities */
-	dma_cap_mask_t cap_mask;
-	/* Bytes to allocate for MC buffer */
-	unsigned mcbuf_sz;
-};
-
-extern bool pl330_filter(struct dma_chan *chan, void *param);
-#endif	/* __AMBA_PL330_H_ */
diff --git a/ANDROID_3.4.5/include/linux/amba/serial.h b/ANDROID_3.4.5/include/linux/amba/serial.h
deleted file mode 100644
index d117b29d..00000000
--- a/ANDROID_3.4.5/include/linux/amba/serial.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- *  linux/include/asm-arm/hardware/serial_amba.h
- *
- *  Internal header file for AMBA serial ports
- *
- *  Copyright (C) ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
-#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
-
-#include <linux/types.h>
-
-/* -------------------------------------------------------------------------------
- *  From AMBA UART (PL010) Block Specification
- * -------------------------------------------------------------------------------
- *  UART Register Offsets.
- */
-#define UART01x_DR		0x00	/* Data read or written from the interface. */
-#define UART01x_RSR		0x04	/* Receive status register (Read). */
-#define UART01x_ECR		0x04	/* Error clear register (Write). */
-#define UART010_LCRH		0x08	/* Line control register, high byte. */
-#define ST_UART011_DMAWM	0x08    /* DMA watermark configure register. */
-#define UART010_LCRM		0x0C	/* Line control register, middle byte. */
-#define ST_UART011_TIMEOUT	0x0C    /* Timeout period register. */
-#define UART010_LCRL		0x10	/* Line control register, low byte. */
-#define UART010_CR		0x14	/* Control register. */
-#define UART01x_FR		0x18	/* Flag register (Read only). */
-#define UART010_IIR		0x1C	/* Interrupt indentification register (Read). */
-#define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
-#define ST_UART011_LCRH_RX	0x1C    /* Rx line control register. */
-#define UART01x_ILPR		0x20	/* IrDA low power counter register. */
-#define UART011_IBRD		0x24	/* Integer baud rate divisor register. */
-#define UART011_FBRD		0x28	/* Fractional baud rate divisor register. */
-#define UART011_LCRH		0x2c	/* Line control register. */
-#define ST_UART011_LCRH_TX	0x2c    /* Tx Line control register. */
-#define UART011_CR		0x30	/* Control register. */
-#define UART011_IFLS		0x34	/* Interrupt fifo level select. */
-#define UART011_IMSC		0x38	/* Interrupt mask. */
-#define UART011_RIS		0x3c	/* Raw interrupt status. */
-#define UART011_MIS		0x40	/* Masked interrupt status. */
-#define UART011_ICR		0x44	/* Interrupt clear register. */
-#define UART011_DMACR		0x48	/* DMA control register. */
-#define ST_UART011_XFCR		0x50	/* XON/XOFF control register. */
-#define ST_UART011_XON1		0x54	/* XON1 register. */
-#define ST_UART011_XON2		0x58	/* XON2 register. */
-#define ST_UART011_XOFF1	0x5C	/* XON1 register. */
-#define ST_UART011_XOFF2	0x60	/* XON2 register. */
-#define ST_UART011_ITCR		0x80	/* Integration test control register. */
-#define ST_UART011_ITIP		0x84	/* Integration test input register. */
-#define ST_UART011_ABCR		0x100	/* Autobaud control register. */
-#define ST_UART011_ABIMSC	0x15C	/* Autobaud interrupt mask/clear register. */
-
-#define UART011_DR_OE		(1 << 11)
-#define UART011_DR_BE		(1 << 10)
-#define UART011_DR_PE		(1 << 9)
-#define UART011_DR_FE		(1 << 8)
-
-#define UART01x_RSR_OE 		0x08
-#define UART01x_RSR_BE 		0x04
-#define UART01x_RSR_PE 		0x02
-#define UART01x_RSR_FE 		0x01
-
-#define UART011_FR_RI		0x100
-#define UART011_FR_TXFE		0x080
-#define UART011_FR_RXFF		0x040
-#define UART01x_FR_TXFF		0x020
-#define UART01x_FR_RXFE		0x010
-#define UART01x_FR_BUSY		0x008
-#define UART01x_FR_DCD 		0x004
-#define UART01x_FR_DSR 		0x002
-#define UART01x_FR_CTS 		0x001
-#define UART01x_FR_TMSK		(UART01x_FR_TXFF + UART01x_FR_BUSY)
-
-#define UART011_CR_CTSEN	0x8000	/* CTS hardware flow control */
-#define UART011_CR_RTSEN	0x4000	/* RTS hardware flow control */
-#define UART011_CR_OUT2		0x2000	/* OUT2 */
-#define UART011_CR_OUT1		0x1000	/* OUT1 */
-#define UART011_CR_RTS		0x0800	/* RTS */
-#define UART011_CR_DTR		0x0400	/* DTR */
-#define UART011_CR_RXE		0x0200	/* receive enable */
-#define UART011_CR_TXE		0x0100	/* transmit enable */
-#define UART011_CR_LBE		0x0080	/* loopback enable */
-#define UART010_CR_RTIE		0x0040
-#define UART010_CR_TIE 		0x0020
-#define UART010_CR_RIE 		0x0010
-#define UART010_CR_MSIE		0x0008
-#define ST_UART011_CR_OVSFACT	0x0008	/* Oversampling factor */
-#define UART01x_CR_IIRLP	0x0004	/* SIR low power mode */
-#define UART01x_CR_SIREN	0x0002	/* SIR enable */
-#define UART01x_CR_UARTEN	0x0001	/* UART enable */
- 
-#define UART011_LCRH_SPS	0x80
-#define UART01x_LCRH_WLEN_8	0x60
-#define UART01x_LCRH_WLEN_7	0x40
-#define UART01x_LCRH_WLEN_6	0x20
-#define UART01x_LCRH_WLEN_5	0x00
-#define UART01x_LCRH_FEN	0x10
-#define UART01x_LCRH_STP2	0x08
-#define UART01x_LCRH_EPS	0x04
-#define UART01x_LCRH_PEN	0x02
-#define UART01x_LCRH_BRK	0x01
-
-#define ST_UART011_DMAWM_RX_1	(0 << 3)
-#define ST_UART011_DMAWM_RX_2	(1 << 3)
-#define ST_UART011_DMAWM_RX_4	(2 << 3)
-#define ST_UART011_DMAWM_RX_8	(3 << 3)
-#define ST_UART011_DMAWM_RX_16	(4 << 3)
-#define ST_UART011_DMAWM_RX_32	(5 << 3)
-#define ST_UART011_DMAWM_RX_48	(6 << 3)
-#define ST_UART011_DMAWM_TX_1	0
-#define ST_UART011_DMAWM_TX_2	1
-#define ST_UART011_DMAWM_TX_4	2
-#define ST_UART011_DMAWM_TX_8	3
-#define ST_UART011_DMAWM_TX_16	4
-#define ST_UART011_DMAWM_TX_32	5
-#define ST_UART011_DMAWM_TX_48	6
-
-#define UART010_IIR_RTIS	0x08
-#define UART010_IIR_TIS		0x04
-#define UART010_IIR_RIS		0x02
-#define UART010_IIR_MIS		0x01
-
-#define UART011_IFLS_RX1_8	(0 << 3)
-#define UART011_IFLS_RX2_8	(1 << 3)
-#define UART011_IFLS_RX4_8	(2 << 3)
-#define UART011_IFLS_RX6_8	(3 << 3)
-#define UART011_IFLS_RX7_8	(4 << 3)
-#define UART011_IFLS_TX1_8	(0 << 0)
-#define UART011_IFLS_TX2_8	(1 << 0)
-#define UART011_IFLS_TX4_8	(2 << 0)
-#define UART011_IFLS_TX6_8	(3 << 0)
-#define UART011_IFLS_TX7_8	(4 << 0)
-/* special values for ST vendor with deeper fifo */
-#define UART011_IFLS_RX_HALF	(5 << 3)
-#define UART011_IFLS_TX_HALF	(5 << 0)
-
-#define UART011_OEIM		(1 << 10)	/* overrun error interrupt mask */
-#define UART011_BEIM		(1 << 9)	/* break error interrupt mask */
-#define UART011_PEIM		(1 << 8)	/* parity error interrupt mask */
-#define UART011_FEIM		(1 << 7)	/* framing error interrupt mask */
-#define UART011_RTIM		(1 << 6)	/* receive timeout interrupt mask */
-#define UART011_TXIM		(1 << 5)	/* transmit interrupt mask */
-#define UART011_RXIM		(1 << 4)	/* receive interrupt mask */
-#define UART011_DSRMIM		(1 << 3)	/* DSR interrupt mask */
-#define UART011_DCDMIM		(1 << 2)	/* DCD interrupt mask */
-#define UART011_CTSMIM		(1 << 1)	/* CTS interrupt mask */
-#define UART011_RIMIM		(1 << 0)	/* RI interrupt mask */
-
-#define UART011_OEIS		(1 << 10)	/* overrun error interrupt status */
-#define UART011_BEIS		(1 << 9)	/* break error interrupt status */
-#define UART011_PEIS		(1 << 8)	/* parity error interrupt status */
-#define UART011_FEIS		(1 << 7)	/* framing error interrupt status */
-#define UART011_RTIS		(1 << 6)	/* receive timeout interrupt status */
-#define UART011_TXIS		(1 << 5)	/* transmit interrupt status */
-#define UART011_RXIS		(1 << 4)	/* receive interrupt status */
-#define UART011_DSRMIS		(1 << 3)	/* DSR interrupt status */
-#define UART011_DCDMIS		(1 << 2)	/* DCD interrupt status */
-#define UART011_CTSMIS		(1 << 1)	/* CTS interrupt status */
-#define UART011_RIMIS		(1 << 0)	/* RI interrupt status */
-
-#define UART011_OEIC		(1 << 10)	/* overrun error interrupt clear */
-#define UART011_BEIC		(1 << 9)	/* break error interrupt clear */
-#define UART011_PEIC		(1 << 8)	/* parity error interrupt clear */
-#define UART011_FEIC		(1 << 7)	/* framing error interrupt clear */
-#define UART011_RTIC		(1 << 6)	/* receive timeout interrupt clear */
-#define UART011_TXIC		(1 << 5)	/* transmit interrupt clear */
-#define UART011_RXIC		(1 << 4)	/* receive interrupt clear */
-#define UART011_DSRMIC		(1 << 3)	/* DSR interrupt clear */
-#define UART011_DCDMIC		(1 << 2)	/* DCD interrupt clear */
-#define UART011_CTSMIC		(1 << 1)	/* CTS interrupt clear */
-#define UART011_RIMIC		(1 << 0)	/* RI interrupt clear */
-
-#define UART011_DMAONERR	(1 << 2)	/* disable dma on error */
-#define UART011_TXDMAE		(1 << 1)	/* enable transmit dma */
-#define UART011_RXDMAE		(1 << 0)	/* enable receive dma */
-
-#define UART01x_RSR_ANY		(UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
-#define UART01x_FR_MODEM_ANY	(UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
-
-#ifndef __ASSEMBLY__
-struct amba_device; /* in uncompress this is included but amba/bus.h is not */
-struct amba_pl010_data {
-	void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
-};
-
-struct dma_chan;
-struct amba_pl011_data {
-	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
-	void *dma_rx_param;
-	void *dma_tx_param;
-        void (*init) (void);
-	void (*exit) (void);
-	void (*reset) (void);
-};
-#endif
-
-#endif